1target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" 2target triple = "thumbv7-apple-ios0" 3 4; RUN: opt -S -instcombine < %s | FileCheck %s 5 6define <4 x i32> @mulByZero(<4 x i16> %x) nounwind readnone ssp { 7entry: 8 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind 9 ret <4 x i32> %a 10; CHECK: entry: 11; CHECK-NEXT: ret <4 x i32> zeroinitializer 12} 13 14define <4 x i32> @mulByOne(<4 x i16> %x) nounwind readnone ssp { 15entry: 16 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind 17 ret <4 x i32> %a 18; CHECK: entry: 19; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32> 20; CHECK-NEXT: ret <4 x i32> %a 21} 22 23define <4 x i32> @constantMul() nounwind readnone ssp { 24entry: 25 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind 26 ret <4 x i32> %a 27; CHECK: entry: 28; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6> 29} 30 31define <4 x i32> @constantMulS() nounwind readnone ssp { 32entry: 33 %b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind 34 ret <4 x i32> %b 35; CHECK: entry: 36; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 37} 38 39define <4 x i32> @constantMulU() nounwind readnone ssp { 40entry: 41 %b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind 42 ret <4 x i32> %b 43; CHECK: entry: 44; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 45} 46 47define <4 x i32> @complex1(<4 x i16> %x) nounwind readnone ssp { 48entry: 49 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind 50 %b = add <4 x i32> zeroinitializer, %a 51 ret <4 x i32> %b 52; CHECK: entry: 53; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]] 54; CHECK-NEXT: ret <4 x i32> %a 55} 56 57define <4 x i32> @complex2(<4 x i32> %x) nounwind readnone ssp { 58entry: 59 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind 60 %b = add <4 x i32> %x, %a 61 ret <4 x i32> %b 62; CHECK: entry: 63; CHECK-NEXT: %b = add <4 x i32> %x, <i32 6, i32 6, i32 6, i32 6> 64; CHECK-NEXT: ret <4 x i32> %b 65} 66 67declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone 68declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone 69 70; CHECK: attributes #0 = { nounwind readnone ssp } 71; CHECK: attributes #1 = { nounwind readnone } 72; CHECK: attributes [[NUW]] = { nounwind } 73