1; This test makes sure that urem instructions are properly eliminated.
2;
3; RUN: opt < %s -instcombine -S | FileCheck %s
4; END.
5
6define i32 @test1(i32 %A) {
7; CHECK-LABEL: @test1(
8; CHECK-NEXT: ret i32 0
9	%B = srem i32 %A, 1	; ISA constant 0
10	ret i32 %B
11}
12
13define i32 @test2(i32 %A) {	; 0 % X = 0, we don't need to preserve traps
14; CHECK-LABEL: @test2(
15; CHECK-NEXT: ret i32 0
16	%B = srem i32 0, %A
17	ret i32 %B
18}
19
20define i32 @test3(i32 %A) {
21; CHECK-LABEL: @test3(
22; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
23; CHECK-NEXT: ret i32 [[AND]]
24	%B = urem i32 %A, 8
25	ret i32 %B
26}
27
28define i1 @test3a(i32 %A) {
29; CHECK-LABEL: @test3a(
30; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
31; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
32; CHECK-NEXT: ret i1 [[CMP]]
33	%B = srem i32 %A, -8
34	%C = icmp ne i32 %B, 0
35	ret i1 %C
36}
37
38define i32 @test4(i32 %X, i1 %C) {
39; CHECK-LABEL: @test4(
40; CHECK-NEXT: [[SEL:%.*]] = select i1 %C, i32 0, i32 7
41; CHECK-NEXT: [[AND:%.*]] = and i32 [[SEL]], %X
42	%V = select i1 %C, i32 1, i32 8
43	%R = urem i32 %X, %V
44	ret i32 %R
45}
46
47define i32 @test5(i32 %X, i8 %B) {
48; CHECK-LABEL: @test5(
49; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 %B to i32
50; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 32, [[ZEXT]]
51; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
52; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %X
53; CHECK-NEXT: ret i32 [[AND]]
54	%shift.upgrd.1 = zext i8 %B to i32
55	%Amt = shl i32 32, %shift.upgrd.1
56	%V = urem i32 %X, %Amt
57	ret i32 %V
58}
59
60define i32 @test6(i32 %A) {
61; CHECK-LABEL: @test6(
62; CHECK-NEXT: ret i32 undef
63	%B = srem i32 %A, 0	;; undef
64	ret i32 %B
65}
66
67define i32 @test7(i32 %A) {
68; CHECK-LABEL: @test7(
69; CHECK-NEXT: ret i32 0
70	%B = mul i32 %A, 8
71	%C = srem i32 %B, 4
72	ret i32 %C
73}
74
75define i32 @test8(i32 %A) {
76; CHECK-LABEL: @test8(
77; CHECK-NEXT: ret i32 0
78	%B = shl i32 %A, 4
79	%C = srem i32 %B, 8
80	ret i32 %C
81}
82
83define i32 @test9(i32 %A) {
84; CHECK-LABEL: @test9(
85; CHECK-NEXT: ret i32 0
86	%B = mul i32 %A, 64
87	%C = urem i32 %B, 32
88	ret i32 %C
89}
90
91define i32 @test10(i8 %c) {
92; CHECK-LABEL: @test10(
93; CHECK-NEXT: ret i32 0
94	%tmp.1 = zext i8 %c to i32
95	%tmp.2 = mul i32 %tmp.1, 4
96	%tmp.3 = sext i32 %tmp.2 to i64
97	%tmp.5 = urem i64 %tmp.3, 4
98	%tmp.6 = trunc i64 %tmp.5 to i32
99	ret i32 %tmp.6
100}
101
102define i32 @test11(i32 %i) {
103; CHECK-LABEL: @test11(
104; CHECK-NEXT: ret i32 0
105	%tmp.1 = and i32 %i, -2
106	%tmp.3 = mul i32 %tmp.1, 2
107	%tmp.5 = urem i32 %tmp.3, 4
108	ret i32 %tmp.5
109}
110
111define i32 @test12(i32 %i) {
112; CHECK-LABEL: @test12(
113; CHECK-NEXT: ret i32 0
114	%tmp.1 = and i32 %i, -4
115	%tmp.5 = srem i32 %tmp.1, 2
116	ret i32 %tmp.5
117}
118
119define i32 @test13(i32 %i) {
120; CHECK-LABEL: @test13(
121; CHECK-NEXT: ret i32 0
122	%x = srem i32 %i, %i
123	ret i32 %x
124}
125
126define i64 @test14(i64 %x, i32 %y) {
127; CHECK-LABEL: @test14(
128; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
129; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
130; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[ZEXT]], -1
131; CHECK-NEXT: [[AND:%.*]] = and i64 [[ADD]], %x
132; CHECK-NEXT: ret i64 [[AND]]
133	%shl = shl i32 1, %y
134	%zext = zext i32 %shl to i64
135	%urem = urem i64 %x, %zext
136	ret i64 %urem
137}
138
139define i64 @test15(i32 %x, i32 %y) {
140; CHECK-LABEL: @test15(
141; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
142; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
143; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %x
144; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[AND]] to i64
145; CHECK-NEXT: ret i64 [[ZEXT]]
146	%shl = shl i32 1, %y
147	%zext0 = zext i32 %shl to i64
148	%zext1 = zext i32 %x to i64
149	%urem = urem i64 %zext1, %zext0
150	ret i64 %urem
151}
152
153define i32 @test16(i32 %x, i32 %y) {
154; CHECK-LABEL: @test16(
155; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %y, 11
156; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 4
157; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], 3
158; CHECK-NEXT: [[REM:%.*]] = and i32 [[OR]], %x
159; CHECK-NEXT: ret i32 [[REM]]
160	%shr = lshr i32 %y, 11
161	%and = and i32 %shr, 4
162	%add = add i32 %and, 4
163	%rem = urem i32 %x, %add
164	ret i32 %rem
165}
166
167define i32 @test17(i32 %X) {
168; CHECK-LABEL: @test17(
169; CHECK-NEXT: icmp ne i32 %X, 1
170; CHECK-NEXT: zext i1
171; CHECK-NEXT: ret
172  %A = urem i32 1, %X
173  ret i32 %A
174}
175
176define i32 @test18(i16 %x, i32 %y) {
177; CHECK: @test18
178; CHECK-NEXT: [[AND:%.*]] = and i16 %x, 4
179; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[AND]] to i32
180; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i32 [[EXT]], 3
181; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], 63
182; CHECK-NEXT: [[REM:%.*]] = and i32 [[XOR]], %y
183; CHECK-NEXT: ret i32 [[REM]]
184	%1 = and i16 %x, 4
185	%2 = icmp ne i16 %1, 0
186	%3 = select i1 %2, i32 32, i32 64
187	%4 = urem i32 %y, %3
188	ret i32 %4
189}
190
191define i32 @test19(i32 %x, i32 %y) {
192; CHECK: @test19
193; CHECK-NEXT: [[SHL1:%.*]] = shl i32 1, %x
194; CHECK-NEXT: [[SHL2:%.*]] = shl i32 1, %y
195; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL1]], [[SHL2]]
196; CHECK-NEXT: [[ADD:%.*]] = add i32 [[AND]], [[SHL1]]
197; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], -1
198; CHECK-NEXT: [[REM:%.*]] = and i32 [[SUB]], %y
199; CHECK-NEXT: ret i32 [[REM]]
200	%A = shl i32 1, %x
201	%B = shl i32 1, %y
202	%C = and i32 %A, %B
203	%D = add i32 %C, %A
204	%E = urem i32 %y, %D
205	ret i32 %E
206}
207
208define <2 x i64> @test20(<2 x i64> %X, <2 x i1> %C) {
209; CHECK-LABEL: @test20(
210; CHECK-NEXT: select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> zeroinitializer
211; CHECK-NEXT: ret <2 x i64>
212	%V = select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> <i64 8, i64 9>
213	%R = urem <2 x i64> %V, <i64 2, i64 3>
214	ret <2 x i64> %R
215}
216