1; RUN: opt -S -loop-vectorize -force-vector-width=4 -force-vector-interleave=1  < %s |  FileCheck %s
2target datalayout = "e-p:32:32:32-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f16:16:16-f32:32:32-f64:32:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
3
4
5; We can vectorize this code because if the address computation would wrap then
6; a load from 0 would take place which is undefined behaviour in address space 0
7; according to LLVM IR semantics.
8
9; PR16592
10
11; CHECK-LABEL: @safe(
12; CHECK: <4 x float>
13
14define void @safe(float* %A, float* %B, float %K) {
15entry:
16  br label %"<bb 3>"
17
18"<bb 3>":
19  %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]
20  %pp3 = getelementptr float* %A, i32 %i_15
21  %D.1396_10 = load float* %pp3, align 4
22  %pp24 = getelementptr float* %B, i32 %i_15
23  %D.1398_15 = load float* %pp24, align 4
24  %D.1399_17 = fadd float %D.1398_15, %K
25  %D.1400_18 = fmul float %D.1396_10, %D.1399_17
26  store float %D.1400_18, float* %pp3, align 4
27  %i_19 = add nsw i32 %i_15, 1
28  %exitcond = icmp ne i32 %i_19, 64
29  br i1 %exitcond, label %"<bb 3>", label %return
30
31return:
32  ret void
33}
34
35; In a non-default address space we don't have this rule.
36
37; CHECK-LABEL: @notsafe(
38; CHECK-NOT: <4 x float>
39
40define void @notsafe(float addrspace(5) * %A, float* %B, float %K) {
41entry:
42  br label %"<bb 3>"
43
44"<bb 3>":
45  %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]
46  %pp3 = getelementptr float addrspace(5) * %A, i32 %i_15
47  %D.1396_10 = load float addrspace(5) * %pp3, align 4
48  %pp24 = getelementptr float* %B, i32 %i_15
49  %D.1398_15 = load float* %pp24, align 4
50  %D.1399_17 = fadd float %D.1398_15, %K
51  %D.1400_18 = fmul float %D.1396_10, %D.1399_17
52  store float %D.1400_18, float addrspace(5) * %pp3, align 4
53  %i_19 = add nsw i32 %i_15, 1
54  %exitcond = icmp ne i32 %i_19, 64
55  br i1 %exitcond, label %"<bb 3>", label %return
56
57return:
58  ret void
59}
60
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62