1diff -rNU3 dist.orig/bfd/ChangeLog dist/bfd/ChangeLog 2--- dist.orig/bfd/ChangeLog 2013-03-25 10:08:08.000000000 +0100 3+++ dist/bfd/ChangeLog 2015-10-18 13:11:12.000000000 +0200 4@@ -1,3 +1,8 @@ 5+2013-12-14 Alan Modra <amodra@gmail.com> 6+ 7+ * elflink.c (_bfd_elf_merge_symbol): If merging a new weak 8+ symbol that will be skipped, we don't have a new definition. 9+ 10 2013-03-25 Tristan Gingold <gingold@adacore.com> 11 12 * configure.in: Bump version to 2.23.2 13diff -rNU3 dist.orig/bfd/Makefile.am dist/bfd/Makefile.am 14--- dist.orig/bfd/Makefile.am 2013-03-25 10:08:05.000000000 +0100 15+++ dist/bfd/Makefile.am 2015-10-18 13:11:13.000000000 +0200 16@@ -897,6 +897,18 @@ 17 sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new 18 mv -f elf64-ia64.new elf64-ia64.c 19 20+elf32-riscv.c : elfnn-riscv.c 21+ rm -f elf32-riscv.c 22+ echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new 23+ sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new 24+ mv -f elf32-riscv.new elf32-riscv.c 25+ 26+elf64-riscv.c : elfnn-riscv.c 27+ rm -f elf64-riscv.c 28+ echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new 29+ sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new 30+ mv -f elf64-riscv.new elf64-riscv.c 31+ 32 peigen.c : peXXigen.c 33 rm -f peigen.c 34 sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new 35diff -rNU3 dist.orig/bfd/Makefile.in dist/bfd/Makefile.in 36--- dist.orig/bfd/Makefile.in 2013-03-25 10:08:08.000000000 +0100 37+++ dist/bfd/Makefile.in 2015-10-18 13:11:13.000000000 +0200 38@@ -419,7 +419,7 @@ 39 cpu-mt.lo \ 40 cpu-ns32k.lo \ 41 cpu-openrisc.lo \ 42- cpu-or32.lo \ 43+ cpu-or1k.lo \ 44 cpu-pdp11.lo \ 45 cpu-pj.lo \ 46 cpu-plugin.lo \ 47@@ -500,7 +500,7 @@ 48 cpu-mt.c \ 49 cpu-ns32k.c \ 50 cpu-openrisc.c \ 51- cpu-or32.c \ 52+ cpu-or1k.c \ 53 cpu-pdp11.c \ 54 cpu-pj.c \ 55 cpu-plugin.c \ 56@@ -559,7 +559,7 @@ 57 coff-m68k.lo \ 58 coff-m88k.lo \ 59 coff-mips.lo \ 60- coff-or32.lo \ 61+ coff-or1k.lo \ 62 coff-rs6000.lo \ 63 coff-sh.lo \ 64 coff-sparc.lo \ 65@@ -627,7 +627,7 @@ 66 elf32-msp430.lo \ 67 elf32-mt.lo \ 68 elf32-openrisc.lo \ 69- elf32-or32.lo \ 70+ elf32-or1k.lo \ 71 elf32-pj.lo \ 72 elf32-ppc.lo \ 73 elf32-rl78.lo \ 74@@ -747,7 +747,7 @@ 75 coff-m68k.c \ 76 coff-m88k.c \ 77 coff-mips.c \ 78- coff-or32.c \ 79+ coff-or1k.c \ 80 coff-rs6000.c \ 81 coff-sh.c \ 82 coff-sparc.c \ 83@@ -815,7 +815,7 @@ 84 elf32-msp430.c \ 85 elf32-mt.c \ 86 elf32-openrisc.c \ 87- elf32-or32.c \ 88+ elf32-or1k.c \ 89 elf32-pj.c \ 90 elf32-ppc.c \ 91 elf32-rl78.c \ 92@@ -1253,7 +1253,7 @@ 93 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-m68k.Plo@am__quote@ 94 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-m88k.Plo@am__quote@ 95 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-mips.Plo@am__quote@ 96-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-or32.Plo@am__quote@ 97+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-or1k.Plo@am__quote@ 98 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-rs6000.Plo@am__quote@ 99 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-sh.Plo@am__quote@ 100 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-sparc.Plo@am__quote@ 101@@ -1323,7 +1323,7 @@ 102 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mt.Plo@am__quote@ 103 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ns32k.Plo@am__quote@ 104 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-openrisc.Plo@am__quote@ 105-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-or32.Plo@am__quote@ 106+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-or1k.Plo@am__quote@ 107 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pdp11.Plo@am__quote@ 108 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pj.Plo@am__quote@ 109 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@ 110@@ -1408,7 +1408,7 @@ 111 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-msp430.Plo@am__quote@ 112 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mt.Plo@am__quote@ 113 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-openrisc.Plo@am__quote@ 114-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or32.Plo@am__quote@ 115+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or1k.Plo@am__quote@ 116 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@ 117 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@ 118 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rl78.Plo@am__quote@ 119@@ -1967,6 +1967,18 @@ 120 sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new 121 mv -f elf64-ia64.new elf64-ia64.c 122 123+elf32-riscv.c : elfnn-riscv.c 124+ rm -f elf32-riscv.c 125+ echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new 126+ sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new 127+ mv -f elf32-riscv.new elf32-riscv.c 128+ 129+elf64-riscv.c : elfnn-riscv.c 130+ rm -f elf64-riscv.c 131+ echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new 132+ sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new 133+ mv -f elf64-riscv.new elf64-riscv.c 134+ 135 peigen.c : peXXigen.c 136 rm -f peigen.c 137 sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new 138diff -rNU3 dist.orig/bfd/aoutx.h dist/bfd/aoutx.h 139--- dist.orig/bfd/aoutx.h 2012-05-01 18:07:33.000000000 +0200 140+++ dist/bfd/aoutx.h 2015-10-18 13:11:12.000000000 +0200 141@@ -762,7 +762,7 @@ 142 break; 143 144 case bfd_arch_arm: 145- if (machine == 0) 146+ if (machine == 0 || machine == 5) 147 arch_flags = M_ARM; 148 break; 149 150diff -rNU3 dist.orig/bfd/archive.c dist/bfd/archive.c 151--- dist.orig/bfd/archive.c 2013-03-25 09:06:19.000000000 +0100 152+++ dist/bfd/archive.c 2015-10-18 13:11:12.000000000 +0200 153@@ -157,6 +157,9 @@ 154 #define ar_maxnamelen(abfd) ((abfd)->xvec->ar_max_namelen) 155 156 #define arch_eltdata(bfd) ((struct areltdata *) ((bfd)->arelt_data)) 157+ 158+static const char * normalize (bfd *, const char *); 159+ 160 #define arch_hdr(bfd) ((struct ar_hdr *) arch_eltdata (bfd)->arch_header) 161 162 /* True iff NAME designated a BSD 4.4 extended name. */ 163@@ -760,7 +763,9 @@ 164 /* Pad to an even boundary... 165 Note that last_file->origin can be odd in the case of 166 BSD-4.4-style element with a long odd size. */ 167- filestart += filestart % 2; 168+ if (!strncmp(arch_hdr (last_file)->ar_name, "#1/", 3)) 169+ size += strlen(normalize(last_file, last_file->filename)); 170+ filestart += size % 2; 171 } 172 173 return _bfd_get_elt_at_filepos (archive, filestart); 174@@ -2180,11 +2185,22 @@ 175 current = current->archive_next) 176 { 177 char buffer[DEFAULT_BUFFERSIZE]; 178- bfd_size_type remaining = arelt_size (current); 179+ bfd_size_type saved_size = arelt_size (current); 180+ bfd_size_type remaining = saved_size; 181+ struct ar_hdr *hdr = arch_hdr (current); 182 183 /* Write ar header. */ 184 if (!_bfd_write_ar_hdr (arch, current)) 185- return FALSE; 186+ return FALSE; 187+ /* Write filename if it is a 4.4BSD extended file, and add to size. */ 188+ if (!strncmp (hdr->ar_name, "#1/", 3)) 189+ { 190+ const char *normal = normalize (current, current->filename); 191+ unsigned int thislen = strlen (normal); 192+ if (bfd_write (normal, 1, thislen, arch) != thislen) 193+ return FALSE; 194+ saved_size += thislen; 195+ } 196 if (bfd_is_thin_archive (arch)) 197 continue; 198 if (bfd_seek (current, (file_ptr) 0, SEEK_SET) != 0) 199@@ -2457,11 +2473,19 @@ 200 { 201 do 202 { 203+#if 1 204+ bfd_size_type size = arelt_size (current); 205+ if (!strncmp(arch_hdr (current)->ar_name, "#1/", 3)) 206+ size += strlen(normalize(current, current->filename)); 207+ firstreal += size + sizeof (struct ar_hdr); 208+ firstreal += size % 2; 209+#else 210 struct areltdata *ared = arch_eltdata (current); 211 212 firstreal += (ared->parsed_size + ared->extra_size 213 + sizeof (struct ar_hdr)); 214 firstreal += firstreal % 2; 215+#endif 216 current = current->archive_next; 217 } 218 while (current != map[count].u.abfd); 219diff -rNU3 dist.orig/bfd/archures.c dist/bfd/archures.c 220--- dist.orig/bfd/archures.c 2012-09-04 14:53:41.000000000 +0200 221+++ dist/bfd/archures.c 2015-10-18 13:11:12.000000000 +0200 222@@ -123,7 +123,7 @@ 223 .#define bfd_mach_i960_jx 7 224 .#define bfd_mach_i960_hx 8 225 . 226-. bfd_arch_or32, {* OpenRISC 32 *} 227+. bfd_arch_or1k, {* OpenRISC 32 *} 228 . 229 . bfd_arch_sparc, {* SPARC *} 230 .#define bfd_mach_sparc 1 231@@ -245,6 +245,9 @@ 232 .#define bfd_mach_ppc_e6500 5007 233 .#define bfd_mach_ppc_titan 83 234 .#define bfd_mach_ppc_vle 84 235+. bfd_arch_riscv, {* RISC-V *} 236+.#define bfd_mach_riscv32 132 237+.#define bfd_mach_riscv64 164 238 . bfd_arch_rs6000, {* IBM RS/6000 *} 239 .#define bfd_mach_rs6k 6000 240 .#define bfd_mach_rs6k_rs1 6001 241@@ -556,12 +559,13 @@ 242 extern const bfd_arch_info_type bfd_mt_arch; 243 extern const bfd_arch_info_type bfd_ns32k_arch; 244 extern const bfd_arch_info_type bfd_openrisc_arch; 245-extern const bfd_arch_info_type bfd_or32_arch; 246+extern const bfd_arch_info_type bfd_or1k_arch; 247 extern const bfd_arch_info_type bfd_pdp11_arch; 248 extern const bfd_arch_info_type bfd_pj_arch; 249 extern const bfd_arch_info_type bfd_plugin_arch; 250 extern const bfd_arch_info_type bfd_powerpc_archs[]; 251 #define bfd_powerpc_arch bfd_powerpc_archs[0] 252+extern const bfd_arch_info_type bfd_riscv_arch; 253 extern const bfd_arch_info_type bfd_rs6000_arch; 254 extern const bfd_arch_info_type bfd_rl78_arch; 255 extern const bfd_arch_info_type bfd_rx_arch; 256@@ -642,9 +646,10 @@ 257 &bfd_mt_arch, 258 &bfd_ns32k_arch, 259 &bfd_openrisc_arch, 260- &bfd_or32_arch, 261+ &bfd_or1k_arch, 262 &bfd_pdp11_arch, 263 &bfd_powerpc_arch, 264+ &bfd_riscv_arch, 265 &bfd_rs6000_arch, 266 &bfd_rl78_arch, 267 &bfd_rx_arch, 268diff -rNU3 dist.orig/bfd/bfd-in2.h dist/bfd/bfd-in2.h 269--- dist.orig/bfd/bfd-in2.h 2012-09-04 14:53:41.000000000 +0200 270+++ dist/bfd/bfd-in2.h 2015-10-18 13:11:12.000000000 +0200 271@@ -1852,7 +1852,9 @@ 272 #define bfd_mach_i960_jx 7 273 #define bfd_mach_i960_hx 8 274 275- bfd_arch_or32, /* OpenRISC 32 */ 276+ bfd_arch_or1k, /* OpenRISC 1000 */ 277+#define bfd_mach_or1k 1 278+#define bfd_mach_or1knd 2 279 280 bfd_arch_sparc, /* SPARC */ 281 #define bfd_mach_sparc 1 282@@ -1974,6 +1976,9 @@ 283 #define bfd_mach_ppc_e6500 5007 284 #define bfd_mach_ppc_titan 83 285 #define bfd_mach_ppc_vle 84 286+ bfd_arch_riscv, /* RISC-V */ 287+#define bfd_mach_riscv32 132 288+#define bfd_mach_riscv64 164 289 bfd_arch_rs6000, /* IBM RS/6000 */ 290 #define bfd_mach_rs6k 6000 291 #define bfd_mach_rs6k_rs1 6001 292@@ -4803,9 +4808,66 @@ 293 BFD_RELOC_860_HIGOT, 294 BFD_RELOC_860_HIGOTOFF, 295 296-/* OpenRISC Relocations. */ 297- BFD_RELOC_OPENRISC_ABS_26, 298- BFD_RELOC_OPENRISC_REL_26, 299+/* OpenRISC 1000 Relocations. */ 300+ BFD_RELOC_OR1K_REL_26, 301+ BFD_RELOC_OR1K_GOTPC_HI16, 302+ BFD_RELOC_OR1K_GOTPC_LO16, 303+ BFD_RELOC_OR1K_GOT16, 304+ BFD_RELOC_OR1K_PLT26, 305+ BFD_RELOC_OR1K_GOTOFF_HI16, 306+ BFD_RELOC_OR1K_GOTOFF_LO16, 307+ BFD_RELOC_OR1K_COPY, 308+ BFD_RELOC_OR1K_GLOB_DAT, 309+ BFD_RELOC_OR1K_JMP_SLOT, 310+ BFD_RELOC_OR1K_RELATIVE, 311+ BFD_RELOC_OR1K_TLS_GD_HI16, 312+ BFD_RELOC_OR1K_TLS_GD_LO16, 313+ BFD_RELOC_OR1K_TLS_LDM_HI16, 314+ BFD_RELOC_OR1K_TLS_LDM_LO16, 315+ BFD_RELOC_OR1K_TLS_LDO_HI16, 316+ BFD_RELOC_OR1K_TLS_LDO_LO16, 317+ BFD_RELOC_OR1K_TLS_IE_HI16, 318+ BFD_RELOC_OR1K_TLS_IE_LO16, 319+ BFD_RELOC_OR1K_TLS_LE_HI16, 320+ BFD_RELOC_OR1K_TLS_LE_LO16, 321+ BFD_RELOC_OR1K_TLS_TPOFF, 322+ BFD_RELOC_OR1K_TLS_DTPOFF, 323+ BFD_RELOC_OR1K_TLS_DTPMOD, 324+ 325+/* RISC-V relocations. */ 326+ BFD_RELOC_RISCV_HI20, 327+ BFD_RELOC_RISCV_PCREL_HI20, 328+ BFD_RELOC_RISCV_PCREL_LO12_I, 329+ BFD_RELOC_RISCV_PCREL_LO12_S, 330+ BFD_RELOC_RISCV_LO12_I, 331+ BFD_RELOC_RISCV_LO12_S, 332+ BFD_RELOC_RISCV_GPREL12_I, 333+ BFD_RELOC_RISCV_GPREL12_S, 334+ BFD_RELOC_RISCV_TPREL_HI20, 335+ BFD_RELOC_RISCV_TPREL_LO12_I, 336+ BFD_RELOC_RISCV_TPREL_LO12_S, 337+ BFD_RELOC_RISCV_TPREL_ADD, 338+ BFD_RELOC_RISCV_CALL, 339+ BFD_RELOC_RISCV_CALL_PLT, 340+ BFD_RELOC_RISCV_ADD8, 341+ BFD_RELOC_RISCV_ADD16, 342+ BFD_RELOC_RISCV_ADD32, 343+ BFD_RELOC_RISCV_ADD64, 344+ BFD_RELOC_RISCV_SUB8, 345+ BFD_RELOC_RISCV_SUB16, 346+ BFD_RELOC_RISCV_SUB32, 347+ BFD_RELOC_RISCV_SUB64, 348+ BFD_RELOC_RISCV_GOT_HI20, 349+ BFD_RELOC_RISCV_TLS_GOT_HI20, 350+ BFD_RELOC_RISCV_TLS_GD_HI20, 351+ BFD_RELOC_RISCV_JMP, 352+ BFD_RELOC_RISCV_TLS_DTPMOD32, 353+ BFD_RELOC_RISCV_TLS_DTPREL32, 354+ BFD_RELOC_RISCV_TLS_DTPMOD64, 355+ BFD_RELOC_RISCV_TLS_DTPREL64, 356+ BFD_RELOC_RISCV_TLS_TPREL32, 357+ BFD_RELOC_RISCV_TLS_TPREL64, 358+ BFD_RELOC_RISCV_ALIGN, 359 360 /* H8 elf Relocations. */ 361 BFD_RELOC_H8_DIR16A8, 362@@ -5788,6 +5850,11 @@ 363 /* This BFD has been created by the linker and doesn't correspond 364 to any input file. */ 365 #define BFD_LINKER_CREATED 0x2000 366+ /* This may be set before writing out a BFD to request that it 367+ be written using values for UIDs, GIDs, timestamps, etc. that 368+ will be consistent from run to run. */ 369+#define BFD_DETERMINISTIC_OUTPUT 0x4000 370+ 371 372 /* This may be set before writing out a BFD to request that it 373 be written using values for UIDs, GIDs, timestamps, etc. that 374diff -rNU3 dist.orig/bfd/coff-alpha.c dist/bfd/coff-alpha.c 375--- dist.orig/bfd/coff-alpha.c 2012-07-13 16:22:42.000000000 +0200 376+++ dist/bfd/coff-alpha.c 2015-10-18 13:11:12.000000000 +0200 377@@ -642,7 +642,9 @@ 378 case ALPHA_R_OP_STORE: 379 /* The STORE reloc needs the size and offset fields. We store 380 them in the addend. */ 381+#if 0 382 BFD_ASSERT (intern->r_offset <= 256); 383+#endif 384 rptr->addend = (intern->r_offset << 8) + intern->r_size; 385 break; 386 387diff -rNU3 dist.orig/bfd/coff-or32.c dist/bfd/coff-or32.c 388--- dist.orig/bfd/coff-or32.c 2012-07-13 16:22:43.000000000 +0200 389+++ dist/bfd/coff-or32.c 1970-01-01 01:00:00.000000000 +0100 390@@ -1,629 +0,0 @@ 391-/* BFD back-end for OpenRISC 1000 COFF binaries. 392- Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2011, 2012 393- Free Software Foundation, Inc. 394- Contributed by Ivan Guzvinec <ivang@opencores.org> 395- 396- This file is part of BFD, the Binary File Descriptor library. 397- 398- This program is free software; you can redistribute it and/or modify 399- it under the terms of the GNU General Public License as published by 400- the Free Software Foundation; either version 3 of the License, or 401- (at your option) any later version. 402- 403- This program is distributed in the hope that it will be useful, 404- but WITHOUT ANY WARRANTY; without even the implied warranty of 405- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 406- GNU General Public License for more details. 407- 408- You should have received a copy of the GNU General Public License 409- along with this program; if not, write to the Free Software 410- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 411- MA 02110-1301, USA. */ 412- 413-#define OR32 1 414- 415-#include "sysdep.h" 416-#include "bfd.h" 417-#include "libbfd.h" 418-#include "coff/or32.h" 419-#include "coff/internal.h" 420-#include "libcoff.h" 421- 422-static bfd_reloc_status_type or32_reloc 423- (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); 424- 425-#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2) 426- 427-#define INSERT_HWORD(WORD,HWORD) \ 428- (((WORD) & 0xffff0000) | ((HWORD)& 0x0000ffff)) 429-#define EXTRACT_HWORD(WORD) \ 430- ((WORD) & 0x0000ffff) 431-#define SIGN_EXTEND_HWORD(HWORD) \ 432- ((HWORD) & 0x8000 ? (HWORD)|(~0xffffL) : (HWORD)) 433- 434-#define INSERT_JUMPTARG(WORD,JT) \ 435- (((WORD) & 0xfc000000) | ((JT)& 0x03ffffff)) 436-#define EXTRACT_JUMPTARG(WORD) \ 437- ((WORD) & 0x03ffffff) 438-#define SIGN_EXTEND_JUMPTARG(JT) \ 439- ((JT) & 0x04000000 ? (JT)|(~0x03ffffffL) : (JT)) 440- 441-/* Provided the symbol, returns the value reffed. */ 442- 443-static long 444-get_symbol_value (asymbol *symbol) 445-{ 446- long relocation = 0; 447- 448- if (bfd_is_com_section (symbol->section)) 449- relocation = 0; 450- else 451- relocation = symbol->value + 452- symbol->section->output_section->vma + 453- symbol->section->output_offset; 454- 455- return relocation; 456-} 457- 458-/* This function is in charge of performing all the or32 relocations. */ 459- 460-static bfd_reloc_status_type 461-or32_reloc (bfd *abfd, 462- arelent *reloc_entry, 463- asymbol *symbol_in, 464- void * data, 465- asection *input_section, 466- bfd *output_bfd, 467- char **error_message) 468-{ 469- /* The consth relocation comes in two parts, we have to remember 470- the state between calls, in these variables. */ 471- static bfd_boolean part1_consth_active = FALSE; 472- static unsigned long part1_consth_value; 473- 474- unsigned long insn; 475- unsigned long sym_value; 476- unsigned long unsigned_value; 477- unsigned short r_type; 478- long signed_value; 479- 480- unsigned long addr = reloc_entry->address ; /*+ input_section->vma*/ 481- bfd_byte *hit_data =addr + (bfd_byte *)(data); 482- 483- r_type = reloc_entry->howto->type; 484- 485- if (output_bfd) 486- { 487- /* Partial linking - do nothing. */ 488- reloc_entry->address += input_section->output_offset; 489- return bfd_reloc_ok; 490- } 491- 492- if (symbol_in != NULL 493- && bfd_is_und_section (symbol_in->section)) 494- { 495- /* Keep the state machine happy in case we're called again. */ 496- if (r_type == R_IHIHALF) 497- { 498- part1_consth_active = TRUE; 499- part1_consth_value = 0; 500- } 501- 502- return bfd_reloc_undefined; 503- } 504- 505- if ((part1_consth_active) && (r_type != R_IHCONST)) 506- { 507- part1_consth_active = FALSE; 508- *error_message = (char *) "Missing IHCONST"; 509- 510- return bfd_reloc_dangerous; 511- } 512- 513- sym_value = get_symbol_value (symbol_in); 514- 515- switch (r_type) 516- { 517- case R_IREL: 518- insn = bfd_get_32(abfd, hit_data); 519- 520- /* Take the value in the field and sign extend it. */ 521- signed_value = EXTRACT_JUMPTARG (insn); 522- signed_value = SIGN_EXTEND_JUMPTARG (signed_value); 523- signed_value <<= 2; 524- 525- /* See the note on the R_IREL reloc in coff_or32_relocate_section. */ 526- if (signed_value == - (long) reloc_entry->address) 527- signed_value = 0; 528- 529- signed_value += sym_value + reloc_entry->addend; 530- /* Relative jmp/call, so subtract from the value the 531- address of the place we're coming from. */ 532- signed_value -= (reloc_entry->address 533- + input_section->output_section->vma 534- + input_section->output_offset); 535- if (signed_value > 0x7ffffff || signed_value < -0x8000000) 536- return bfd_reloc_overflow; 537- 538- signed_value >>= 2; 539- insn = INSERT_JUMPTARG (insn, signed_value); 540- bfd_put_32 (abfd, insn, hit_data); 541- break; 542- 543- case R_ILOHALF: 544- insn = bfd_get_32 (abfd, hit_data); 545- unsigned_value = EXTRACT_HWORD (insn); 546- unsigned_value += sym_value + reloc_entry->addend; 547- insn = INSERT_HWORD (insn, unsigned_value); 548- bfd_put_32 (abfd, insn, hit_data); 549- break; 550- 551- case R_IHIHALF: 552- insn = bfd_get_32 (abfd, hit_data); 553- 554- /* consth, part 1 555- Just get the symbol value that is referenced. */ 556- part1_consth_active = TRUE; 557- part1_consth_value = sym_value + reloc_entry->addend; 558- 559- /* Don't modify insn until R_IHCONST. */ 560- break; 561- 562- case R_IHCONST: 563- insn = bfd_get_32 (abfd, hit_data); 564- 565- /* consth, part 2 566- Now relocate the reference. */ 567- if (! part1_consth_active) 568- { 569- *error_message = (char *) "Missing IHIHALF"; 570- return bfd_reloc_dangerous; 571- } 572- 573- /* sym_ptr_ptr = r_symndx, in coff_slurp_reloc_table() */ 574- unsigned_value = 0; /*EXTRACT_HWORD(insn) << 16;*/ 575- unsigned_value += reloc_entry->addend; /* r_symndx */ 576- unsigned_value += part1_consth_value; 577- unsigned_value = unsigned_value >> 16; 578- insn = INSERT_HWORD (insn, unsigned_value); 579- part1_consth_active = FALSE; 580- bfd_put_32 (abfd, insn, hit_data); 581- break; 582- 583- case R_BYTE: 584- insn = bfd_get_8 (abfd, hit_data); 585- unsigned_value = insn + sym_value + reloc_entry->addend; 586- if (unsigned_value & 0xffffff00) 587- return bfd_reloc_overflow; 588- bfd_put_8 (abfd, unsigned_value, hit_data); 589- break; 590- 591- case R_HWORD: 592- insn = bfd_get_16 (abfd, hit_data); 593- unsigned_value = insn + sym_value + reloc_entry->addend; 594- if (unsigned_value & 0xffff0000) 595- return bfd_reloc_overflow; 596- bfd_put_16 (abfd, insn, hit_data); 597- break; 598- 599- case R_WORD: 600- insn = bfd_get_32 (abfd, hit_data); 601- insn += sym_value + reloc_entry->addend; 602- bfd_put_32 (abfd, insn, hit_data); 603- break; 604- 605- default: 606- *error_message = _("Unrecognized reloc"); 607- return bfd_reloc_dangerous; 608- } 609- 610- return bfd_reloc_ok; 611-} 612- 613-/* type rightshift 614- size 615- bitsize 616- pc-relative 617- bitpos 618- absolute 619- complain_on_overflow 620- special_function 621- relocation name 622- partial_inplace 623- src_mask 624-*/ 625- 626-/* FIXME: I'm not real sure about this table. */ 627-static reloc_howto_type howto_table[] = 628-{ 629- { R_ABS, 0, 3, 32, FALSE, 0, complain_overflow_bitfield, or32_reloc, "ABS", TRUE, 0xffffffff,0xffffffff, FALSE }, 630- EMPTY_HOWTO (1), 631- EMPTY_HOWTO (2), 632- EMPTY_HOWTO (3), 633- EMPTY_HOWTO (4), 634- EMPTY_HOWTO (5), 635- EMPTY_HOWTO (6), 636- EMPTY_HOWTO (7), 637- EMPTY_HOWTO (8), 638- EMPTY_HOWTO (9), 639- EMPTY_HOWTO (10), 640- EMPTY_HOWTO (11), 641- EMPTY_HOWTO (12), 642- EMPTY_HOWTO (13), 643- EMPTY_HOWTO (14), 644- EMPTY_HOWTO (15), 645- EMPTY_HOWTO (16), 646- EMPTY_HOWTO (17), 647- EMPTY_HOWTO (18), 648- EMPTY_HOWTO (19), 649- EMPTY_HOWTO (20), 650- EMPTY_HOWTO (21), 651- EMPTY_HOWTO (22), 652- EMPTY_HOWTO (23), 653- { R_IREL, 0, 3, 32, TRUE, 0, complain_overflow_signed, or32_reloc, "IREL", TRUE, 0xffffffff,0xffffffff, FALSE }, 654- { R_IABS, 0, 3, 32, FALSE, 0, complain_overflow_bitfield, or32_reloc, "IABS", TRUE, 0xffffffff,0xffffffff, FALSE }, 655- { R_ILOHALF, 0, 3, 16, TRUE, 0, complain_overflow_signed, or32_reloc, "ILOHALF", TRUE, 0x0000ffff,0x0000ffff, FALSE }, 656- { R_IHIHALF, 0, 3, 16, TRUE, 16,complain_overflow_signed, or32_reloc, "IHIHALF", TRUE, 0xffff0000,0xffff0000, FALSE }, 657- { R_IHCONST, 0, 3, 16, TRUE, 0, complain_overflow_signed, or32_reloc, "IHCONST", TRUE, 0xffff0000,0xffff0000, FALSE }, 658- { R_BYTE, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, or32_reloc, "BYTE", TRUE, 0x000000ff,0x000000ff, FALSE }, 659- { R_HWORD, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, or32_reloc, "HWORD", TRUE, 0x0000ffff,0x0000ffff, FALSE }, 660- { R_WORD, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, or32_reloc, "WORD", TRUE, 0xffffffff,0xffffffff, FALSE }, 661-}; 662- 663-#define BADMAG(x) OR32BADMAG (x) 664- 665-#define RELOC_PROCESSING(relent, reloc, symbols, abfd, section) \ 666- reloc_processing (relent, reloc, symbols, abfd, section) 667- 668-static void 669-reloc_processing (arelent *relent, 670- struct internal_reloc *reloc, 671- asymbol **symbols, 672- bfd *abfd, 673- asection *section) 674-{ 675- static bfd_vma ihihalf_vaddr = (bfd_vma) -1; 676- 677- relent->address = reloc->r_vaddr; 678- relent->howto = howto_table + reloc->r_type; 679- 680- if (reloc->r_type == R_IHCONST) 681- { 682- /* The address of an R_IHCONST should always be the address of 683- the immediately preceding R_IHIHALF. relocs generated by gas 684- are correct, but relocs generated by High C are different (I 685- can't figure out what the address means for High C). We can 686- handle both gas and High C by ignoring the address here, and 687- simply reusing the address saved for R_IHIHALF. */ 688- if (ihihalf_vaddr == (bfd_vma) -1) 689- abort (); 690- 691- relent->address = ihihalf_vaddr; 692- ihihalf_vaddr = (bfd_vma) -1; 693- relent->addend = reloc->r_symndx; 694- relent->sym_ptr_ptr= bfd_abs_section_ptr->symbol_ptr_ptr; 695- } 696- else 697- { 698- relent->sym_ptr_ptr = symbols + obj_convert (abfd)[reloc->r_symndx]; 699- relent->addend = 0; 700- relent->address-= section->vma; 701- 702- if (reloc->r_type == R_IHIHALF) 703- ihihalf_vaddr = relent->address; 704- else if (ihihalf_vaddr != (bfd_vma) -1) 705- abort (); 706- } 707-} 708- 709-/* The reloc processing routine for the optimized COFF linker. */ 710- 711-static bfd_boolean 712-coff_or32_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, 713- struct bfd_link_info *info, 714- bfd *input_bfd, 715- asection *input_section, 716- bfd_byte *contents, 717- struct internal_reloc *relocs, 718- struct internal_syment *syms, 719- asection **sections) 720-{ 721- struct internal_reloc *rel; 722- struct internal_reloc *relend; 723- bfd_boolean hihalf; 724- bfd_vma hihalf_val; 725- 726- /* If we are performing a relocatable link, we don't need to do a 727- thing. The caller will take care of adjusting the reloc 728- addresses and symbol indices. */ 729- if (info->relocatable) 730- return TRUE; 731- 732- hihalf = FALSE; 733- hihalf_val = 0; 734- 735- rel = relocs; 736- relend = rel + input_section->reloc_count; 737- 738- for (; rel < relend; rel++) 739- { 740- long symndx; 741- bfd_byte *loc; 742- struct coff_link_hash_entry *h; 743- struct internal_syment *sym; 744- asection *sec; 745- bfd_vma val; 746- bfd_boolean overflow; 747- unsigned long insn; 748- long signed_value; 749- unsigned long unsigned_value; 750- bfd_reloc_status_type rstat; 751- 752- symndx = rel->r_symndx; 753- loc = contents + rel->r_vaddr - input_section->vma; 754- 755- if (symndx == -1 || rel->r_type == R_IHCONST) 756- h = NULL; 757- else 758- h = obj_coff_sym_hashes (input_bfd)[symndx]; 759- 760- sym = NULL; 761- sec = NULL; 762- val = 0; 763- 764- /* An R_IHCONST reloc does not have a symbol. Instead, the 765- symbol index is an addend. R_IHCONST is always used in 766- conjunction with R_IHHALF. */ 767- if (rel->r_type != R_IHCONST) 768- { 769- if (h == NULL) 770- { 771- if (symndx == -1) 772- sec = bfd_abs_section_ptr; 773- else 774- { 775- sym = syms + symndx; 776- sec = sections[symndx]; 777- val = (sec->output_section->vma 778- + sec->output_offset 779- + sym->n_value 780- - sec->vma); 781- } 782- } 783- else 784- { 785- if (h->root.type == bfd_link_hash_defined 786- || h->root.type == bfd_link_hash_defweak) 787- { 788- sec = h->root.u.def.section; 789- val = (h->root.u.def.value 790- + sec->output_section->vma 791- + sec->output_offset); 792- } 793- else 794- { 795- if (! ((*info->callbacks->undefined_symbol) 796- (info, h->root.root.string, input_bfd, input_section, 797- rel->r_vaddr - input_section->vma, TRUE))) 798- return FALSE; 799- } 800- } 801- 802- if (hihalf) 803- { 804- if (! ((*info->callbacks->reloc_dangerous) 805- (info, "missing IHCONST reloc", input_bfd, 806- input_section, rel->r_vaddr - input_section->vma))) 807- return FALSE; 808- hihalf = FALSE; 809- } 810- } 811- 812- overflow = FALSE; 813- 814- switch (rel->r_type) 815- { 816- default: 817- bfd_set_error (bfd_error_bad_value); 818- return FALSE; 819- 820- case R_IREL: 821- insn = bfd_get_32 (input_bfd, loc); 822- 823- /* Extract the addend. */ 824- signed_value = EXTRACT_JUMPTARG (insn); 825- signed_value = SIGN_EXTEND_JUMPTARG (signed_value); 826- signed_value <<= 2; 827- 828- /* Determine the destination of the jump. */ 829- signed_value += val; 830- 831- /* Make the destination PC relative. */ 832- signed_value -= (input_section->output_section->vma 833- + input_section->output_offset 834- + (rel->r_vaddr - input_section->vma)); 835- if (signed_value > 0x7ffffff || signed_value < - 0x8000000) 836- { 837- overflow = TRUE; 838- signed_value = 0; 839- } 840- 841- /* Put the adjusted value back into the instruction. */ 842- signed_value >>= 2; 843- insn = INSERT_JUMPTARG(insn, signed_value); 844- 845- bfd_put_32 (input_bfd, (bfd_vma) insn, loc); 846- break; 847- 848- case R_ILOHALF: 849- insn = bfd_get_32 (input_bfd, loc); 850- unsigned_value = EXTRACT_HWORD (insn); 851- unsigned_value += val; 852- insn = INSERT_HWORD (insn, unsigned_value); 853- bfd_put_32 (input_bfd, insn, loc); 854- break; 855- 856- case R_IHIHALF: 857- /* Save the value for the R_IHCONST reloc. */ 858- hihalf = TRUE; 859- hihalf_val = val; 860- break; 861- 862- case R_IHCONST: 863- if (! hihalf) 864- { 865- if (! ((*info->callbacks->reloc_dangerous) 866- (info, "missing IHIHALF reloc", input_bfd, 867- input_section, rel->r_vaddr - input_section->vma))) 868- return FALSE; 869- hihalf_val = 0; 870- } 871- 872- insn = bfd_get_32 (input_bfd, loc); 873- unsigned_value = rel->r_symndx + hihalf_val; 874- unsigned_value >>= 16; 875- insn = INSERT_HWORD (insn, unsigned_value); 876- bfd_put_32 (input_bfd, (bfd_vma) insn, loc); 877- 878- hihalf = FALSE; 879- break; 880- 881- case R_BYTE: 882- case R_HWORD: 883- case R_WORD: 884- rstat = _bfd_relocate_contents (howto_table + rel->r_type, 885- input_bfd, val, loc); 886- if (rstat == bfd_reloc_overflow) 887- overflow = TRUE; 888- else if (rstat != bfd_reloc_ok) 889- abort (); 890- break; 891- } 892- 893- if (overflow) 894- { 895- const char *name; 896- char buf[SYMNMLEN + 1]; 897- 898- if (symndx == -1) 899- name = "*ABS*"; 900- else if (h != NULL) 901- name = NULL; 902- else if (sym == NULL) 903- name = "*unknown*"; 904- else if (sym->_n._n_n._n_zeroes == 0 905- && sym->_n._n_n._n_offset != 0) 906- name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset; 907- else 908- { 909- strncpy (buf, sym->_n._n_name, SYMNMLEN); 910- buf[SYMNMLEN] = '\0'; 911- name = buf; 912- } 913- 914- if (! ((*info->callbacks->reloc_overflow) 915- (info, (h ? &h->root : NULL), name, 916- howto_table[rel->r_type].name, (bfd_vma) 0, input_bfd, 917- input_section, rel->r_vaddr - input_section->vma))) 918- return FALSE; 919- } 920- } 921- 922- return TRUE; 923-} 924- 925-#define coff_relocate_section coff_or32_relocate_section 926- 927-/* We don't want to change the symndx of a R_IHCONST reloc, since it 928- is actually an addend, not a symbol index at all. */ 929- 930-static bfd_boolean 931-coff_or32_adjust_symndx (bfd *obfd ATTRIBUTE_UNUSED, 932- struct bfd_link_info *info ATTRIBUTE_UNUSED, 933- bfd *ibfd ATTRIBUTE_UNUSED, 934- asection *sec ATTRIBUTE_UNUSED, 935- struct internal_reloc *irel, 936- bfd_boolean *adjustedp) 937-{ 938- if (irel->r_type == R_IHCONST) 939- *adjustedp = TRUE; 940- else 941- *adjustedp = FALSE; 942- return TRUE; 943-} 944- 945-#define coff_adjust_symndx coff_or32_adjust_symndx 946- 947-#ifndef bfd_pe_print_pdata 948-#define bfd_pe_print_pdata NULL 949-#endif 950- 951-#include "coffcode.h" 952- 953-const bfd_target or32coff_big_vec = 954-{ 955- "coff-or32-big", /* Name. */ 956- bfd_target_coff_flavour, 957- BFD_ENDIAN_BIG, /* Data byte order is big. */ 958- BFD_ENDIAN_BIG, /* Header byte order is big. */ 959- 960- (HAS_RELOC | EXEC_P | /* Object flags. */ 961- HAS_LINENO | HAS_DEBUG | 962- HAS_SYMS | HAS_LOCALS | WP_TEXT), 963- 964- (SEC_HAS_CONTENTS | SEC_ALLOC | /* Section flags. */ 965- SEC_LOAD | SEC_RELOC | 966- SEC_READONLY ), 967- '_', /* Leading underscore. */ 968- '/', /* ar_pad_char. */ 969- 15, /* ar_max_namelen. */ 970- 0, /* match priority. */ 971- 972- /* Data. */ 973- bfd_getb64, bfd_getb_signed_64, bfd_putb64, 974- bfd_getb32, bfd_getb_signed_32, bfd_putb32, 975- bfd_getb16, bfd_getb_signed_16, bfd_putb16, 976- 977- /* Headers. */ 978- bfd_getb64, bfd_getb_signed_64, bfd_putb64, 979- bfd_getb32, bfd_getb_signed_32, bfd_putb32, 980- bfd_getb16, bfd_getb_signed_16, bfd_putb16, 981- 982- { 983- _bfd_dummy_target, 984- coff_object_p, 985- bfd_generic_archive_p, 986- _bfd_dummy_target 987- }, 988- { 989- bfd_false, 990- coff_mkobject, 991- _bfd_generic_mkarchive, 992- bfd_false 993- }, 994- { 995- bfd_false, 996- coff_write_object_contents, 997- _bfd_write_archive_contents, 998- bfd_false 999- }, 1000- 1001- BFD_JUMP_TABLE_GENERIC (coff), 1002- BFD_JUMP_TABLE_COPY (coff), 1003- BFD_JUMP_TABLE_CORE (_bfd_nocore), 1004- BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), 1005- BFD_JUMP_TABLE_SYMBOLS (coff), 1006- BFD_JUMP_TABLE_RELOCS (coff), 1007- BFD_JUMP_TABLE_WRITE (coff), 1008- BFD_JUMP_TABLE_LINK (coff), 1009- BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), 1010- 1011- /* Alternative_target. */ 1012-#ifdef TARGET_LITTLE_SYM 1013- & TARGET_LITTLE_SYM, 1014-#else 1015- NULL, 1016-#endif 1017- 1018- COFF_SWAP_TABLE 1019-}; 1020diff -rNU3 dist.orig/bfd/coffcode.h dist/bfd/coffcode.h 1021--- dist.orig/bfd/coffcode.h 2011-09-27 18:03:49.000000000 +0200 1022+++ dist/bfd/coffcode.h 2015-10-18 13:11:12.000000000 +0200 1023@@ -2083,12 +2083,6 @@ 1024 machine = 0; 1025 switch (internal_f->f_magic) 1026 { 1027-#ifdef OR32_MAGIC_BIG 1028- case OR32_MAGIC_BIG: 1029- case OR32_MAGIC_LITTLE: 1030- arch = bfd_arch_or32; 1031- break; 1032-#endif 1033 #ifdef PPCMAGIC 1034 case PPCMAGIC: 1035 arch = bfd_arch_powerpc; 1036@@ -3055,15 +3049,6 @@ 1037 return TRUE; 1038 #endif 1039 1040-#ifdef OR32_MAGIC_BIG 1041- case bfd_arch_or32: 1042- if (bfd_big_endian (abfd)) 1043- * magicp = OR32_MAGIC_BIG; 1044- else 1045- * magicp = OR32_MAGIC_LITTLE; 1046- return TRUE; 1047-#endif 1048- 1049 default: /* Unknown architecture. */ 1050 /* Fall through to "return FALSE" below, to avoid 1051 "statement never reached" errors on the one below. */ 1052diff -rNU3 dist.orig/bfd/config.bfd dist/bfd/config.bfd 1053--- dist.orig/bfd/config.bfd 2012-09-04 16:14:59.000000000 +0200 1054+++ dist/bfd/config.bfd 2015-10-18 13:11:12.000000000 +0200 1055@@ -86,16 +86,18 @@ 1056 i[3-7]86) targ_archs=bfd_i386_arch ;; 1057 i370) targ_archs=bfd_i370_arch ;; 1058 lm32) targ_archs=bfd_lm32_arch ;; 1059+m5200|m5407) targ_archs=bfd_m68k_arch ;; 1060 m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;; 1061 m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;; 1062 m68*) targ_archs=bfd_m68k_arch ;; 1063 m88*) targ_archs=bfd_m88k_arch ;; 1064 microblaze*) targ_archs=bfd_microblaze_arch ;; 1065 mips*) targ_archs=bfd_mips_arch ;; 1066-or32*) targ_archs=bfd_or32_arch ;; 1067+or1k*) targ_archs=bfd_or1k_arch ;; 1068 pdp11*) targ_archs=bfd_pdp11_arch ;; 1069 pj*) targ_archs="bfd_pj_arch bfd_i386_arch";; 1070 powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; 1071+riscv*) targ_archs=bfd_riscv_arch ;; 1072 rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; 1073 s390*) targ_archs=bfd_s390_arch ;; 1074 sh*) targ_archs=bfd_sh_arch ;; 1075@@ -164,6 +166,16 @@ 1076 targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec" 1077 want64=true 1078 ;; 1079+ aarch64-*-netbsd*) 1080+ targ_defvec=bfd_elf64_littleaarch64_vec 1081+ targ_selvecs="bfd_elf64_bigaarch64_vec bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec" 1082+ want64=true 1083+ ;; 1084+ aarch64_be-*-netbsd*) 1085+ targ_defvec=bfd_elf64_bigaarch64_vec 1086+ targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec" 1087+ want64=true 1088+ ;; 1089 alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu) 1090 targ_defvec=bfd_elf64_alpha_freebsd_vec 1091 targ_selvecs="bfd_elf64_alpha_vec ecoffalpha_little_vec" 1092@@ -250,17 +262,17 @@ 1093 targ64_selvecs="bfd_elf32_x86_64_nacl_vec bfd_elf64_x86_64_nacl_vec" 1094 targ_archs="$targ_archs bfd_i386_arch" 1095 ;; 1096- armeb-*-netbsdelf*) 1097+ arm*eb-*-netbsdelf*) 1098 targ_defvec=bfd_elf32_bigarm_vec 1099- targ_selvecs="bfd_elf32_littlearm_vec armnetbsd_vec" 1100+ targ_selvecs="bfd_elf32_littlearm_vec armnetbsd_vec armcoff_little_vec armcoff_big_vec" 1101 ;; 1102- arm-*-netbsdelf*) 1103+ arm*-*-netbsdelf*) 1104 targ_defvec=bfd_elf32_littlearm_vec 1105- targ_selvecs="bfd_elf32_bigarm_vec armnetbsd_vec" 1106+ targ_selvecs="bfd_elf32_bigarm_vec armnetbsd_vec armcoff_little_vec armcoff_big_vec" 1107 ;; 1108 arm-*-netbsd* | arm-*-openbsd*) 1109 targ_defvec=armnetbsd_vec 1110- targ_selvecs="bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec" 1111+ targ_selvecs="bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec armcoff_little_vec armcoff_big_vec" 1112 targ_underscore=yes 1113 targ_cflags=-D__QNXTARGET__ 1114 ;; 1115@@ -574,8 +586,8 @@ 1116 ;; 1117 i[3-7]86-*-netbsdelf* | i[3-7]86-*-netbsd*-gnu* | i[3-7]86-*-knetbsd*-gnu) 1118 targ_defvec=bfd_elf32_i386_vec 1119- targ_selvecs=i386netbsd_vec 1120- targ64_selvecs="bfd_elf64_x86_64_vec bfd_elf64_l1om_vec bfd_elf64_k1om_vec" 1121+ targ_selvecs="i386netbsd_vec i386coff_vec i386pei_vec" 1122+ targ64_selvecs="bfd_elf64_x86_64_vec x86_64pei_vec bfd_elf64_l1om_vec bfd_elf64_k1om_vec" 1123 ;; 1124 i[3-7]86-*-netbsdpe*) 1125 targ_defvec=i386pe_vec 1126@@ -845,12 +857,12 @@ 1127 # targ_selvecs=m68kmach3_vec 1128 # targ_cflags=-DSTAT_FOR_EXEC 1129 ;; 1130- m68*-hp*-netbsd*) 1131+ m68k4k*-*-netbsd*) 1132 targ_defvec=m68k4knetbsd_vec 1133- targ_selvecs="m68knetbsd_vec hp300bsd_vec sunos_big_vec" 1134+ targ_selvecs="m68knetbsd_vec hp300bsd_vec sunos_big_vec bfd_elf32_m68k_vec" 1135 targ_underscore=yes 1136 ;; 1137- m68*-*-netbsdelf*) 1138+ m68*-*-netbsdelf* | m5407-*-netbsdelf*) 1139 targ_defvec=bfd_elf32_m68k_vec 1140 targ_selvecs="m68knetbsd_vec m68k4knetbsd_vec hp300bsd_vec sunos_big_vec" 1141 ;; 1142@@ -923,6 +935,16 @@ 1143 targ_defvec=ecoff_big_vec 1144 targ_selvecs=ecoff_little_vec 1145 ;; 1146+#ifdef BFD64 1147+ mips64*el-*-netbsd*) 1148+ targ_defvec=bfd_elf32_ntradlittlemips_vec 1149+ targ_selvecs="bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec bfd_elf32_ntradbigmips_vec bfd_elf32_tradlittlemips_vec bfd_elf32_tradbigmips_vec" 1150+ ;; 1151+ mips64*-*-netbsd*) 1152+ targ_defvec=bfd_elf32_ntradbigmips_vec 1153+ targ_selvecs="bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec bfd_elf32_ntradlittlemips_vec bfd_elf32_tradlittlemips_vec bfd_elf32_tradbigmips_vec" 1154+ ;; 1155+#endif 1156 mips*el-*-netbsd*) 1157 targ_defvec=bfd_elf32_tradlittlemips_vec 1158 targ_selvecs="bfd_elf32_tradbigmips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec ecoff_little_vec ecoff_big_vec" 1159@@ -1102,17 +1124,16 @@ 1160 targ_underscore=yes 1161 ;; 1162 1163- openrisc-*-elf) 1164- targ_defvec=bfd_elf32_openrisc_vec 1165+ or1k*-*-elf) 1166+ targ_defvec=bfd_elf32_or1k_big_vec 1167 ;; 1168 1169- or32-*-coff) 1170- targ_defvec=or32coff_big_vec 1171- targ_underscore=yes 1172+ or1k*-*-linux*) 1173+ targ_defvec=bfd_elf32_or1k_big_vec 1174 ;; 1175 1176- or32-*-elf) 1177- targ_defvec=bfd_elf32_or32_big_vec 1178+ or1k*-*-netbsd*) 1179+ targ_defvec=bfd_elf32_or1k_big_vec 1180 ;; 1181 1182 pdp11-*-*) 1183@@ -1252,6 +1273,14 @@ 1184 targ_defvec=bfd_elf32_rl78_vec 1185 ;; 1186 1187+#ifdef BFD64 1188+ riscv*-*-*) 1189+ targ_defvec=bfd_elf64_riscv_vec 1190+ targ_selvecs="bfd_elf32_riscv_vec bfd_elf64_riscv_vec" 1191+ want64=true 1192+ ;; 1193+#endif 1194+ 1195 rx-*-elf) 1196 targ_defvec=bfd_elf32_rx_le_vec 1197 targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec bfd_elf32_rx_be_ns_vec" 1198@@ -1347,6 +1376,8 @@ 1199 want64=true 1200 ;; 1201 1202+#endif 1203+ 1204 sh*l*-*-netbsdelf*) 1205 targ_defvec=bfd_elf32_shlnbsd_vec 1206 targ_selvecs="bfd_elf32_shnbsd_vec shcoff_vec shlcoff_vec bfd_elf32_sh64lnbsd_vec bfd_elf32_sh64nbsd_vec bfd_elf64_sh64lnbsd_vec bfd_elf64_sh64nbsd_vec" 1207@@ -1357,8 +1388,6 @@ 1208 targ_selvecs="bfd_elf32_shlnbsd_vec shcoff_vec shlcoff_vec bfd_elf32_sh64lnbsd_vec bfd_elf32_sh64nbsd_vec bfd_elf64_sh64lnbsd_vec bfd_elf64_sh64nbsd_vec" 1209 want64=true 1210 ;; 1211-#endif 1212- 1213 sh*-*-netbsdelf*) 1214 targ_defvec=bfd_elf32_shnbsd_vec 1215 targ_selvecs="bfd_elf32_shlnbsd_vec shcoff_vec shlcoff_vec" 1216@@ -1448,11 +1477,12 @@ 1217 ;; 1218 sparc-*-netbsdelf*) 1219 targ_defvec=bfd_elf32_sparc_vec 1220- targ_selvecs=sparcnetbsd_vec 1221+ targ_selvecs="sparcnetbsd_vec sunos_big_vec" 1222+ want64=true 1223 ;; 1224- sparc-*-netbsdaout* | sparc-*-netbsd*) 1225+ sparc-*-netbsd*) 1226 targ_defvec=sparcnetbsd_vec 1227- targ_selvecs=bfd_elf32_sparc_vec 1228+ targ_selvecs="bfd_elf32_sparc_vec sunos_big_vec" 1229 targ_underscore=yes 1230 ;; 1231 sparc-*-openbsd[0-2].* | sparc-*-openbsd3.[0-1]) 1232@@ -1500,6 +1530,10 @@ 1233 targ_selvecs="bfd_elf32_sparc_vec sparclinux_vec sunos_big_vec" 1234 want64=true 1235 ;; 1236+ sparc64-*-netbsd*) 1237+ targ_defvec=bfd_elf64_sparc_vec 1238+ targ_selvecs="bfd_elf32_sparc_vec sparcnetbsd_vec sunos_big_vec" 1239+ ;; 1240 sparc64-*-elf* | sparc64-*-rtems* ) 1241 targ_defvec=bfd_elf64_sparc_vec 1242 targ_selvecs=bfd_elf32_sparc_vec 1243diff -rNU3 dist.orig/bfd/configure dist/bfd/configure 1244--- dist.orig/bfd/configure 2013-03-25 10:08:07.000000000 +0100 1245+++ dist/bfd/configure 2015-10-18 13:11:12.000000000 +0200 1246@@ -12101,10 +12101,10 @@ 1247 withval=$with_pkgversion; case "$withval" in 1248 yes) as_fn_error "package version not specified" "$LINENO" 5 ;; 1249 no) PKGVERSION= ;; 1250- *) PKGVERSION="($withval) " ;; 1251+ *) PKGVERSION="($withval)\ " ;; 1252 esac 1253 else 1254- PKGVERSION="(GNU Binutils) " 1255+ PKGVERSION="(GNU Binutils)\ " 1256 1257 fi 1258 1259@@ -13861,6 +13861,7 @@ 1260 COREFILE=netbsd-core.lo 1261 ;; 1262 arm-*-riscix) COREFILE=trad-core.lo ;; 1263+ arm*-*-netbsd*) COREFILE=netbsd-core.lo ;; 1264 hppa*-*-hpux*) COREFILE=hpux-core.lo ;; 1265 hppa*-*-hiux*) COREFILE=hpux-core.lo ;; 1266 hppa*-*-mpeix*) COREFILE=hpux-core.lo ;; 1267@@ -13923,7 +13924,7 @@ 1268 COREFILE=trad-core.lo 1269 TRAD_HEADER='"hosts/i860mach3.h"' 1270 ;; 1271- mips-*-netbsd* | mips*-*-openbsd*) 1272+ mips*-*-netbsd* | mips*-*-openbsd*) 1273 COREFILE=netbsd-core.lo 1274 ;; 1275 mips-dec-*) 1276@@ -15278,14 +15279,14 @@ 1277 tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; 1278 bfd_elf32_ntradlittlemips_vec | bfd_elf32_ntradlittlemips_freebsd_vec) 1279 tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; 1280- bfd_elf32_openrisc_vec) tb="$tb elf32-openrisc.lo elf32.lo $elf" ;; 1281- bfd_elf32_or32_big_vec) tb="$tb elf32-or32.lo elf32.lo $elf" ;; 1282+ bfd_elf32_or1k_big_vec) tb="$tb elf32-or1k.lo elf32.lo $elf" ;; 1283 bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; 1284 bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; 1285 bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; 1286 bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; 1287 bfd_elf32_powerpc_freebsd_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; 1288 bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; 1289+ bfd_elf32_riscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;; 1290 bfd_elf32_rl78_vec) tb="$tb elf32-rl78.lo $elf" ;; 1291 bfd_elf32_rx_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; 1292 bfd_elf32_rx_be_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; 1293@@ -15356,6 +15357,7 @@ 1294 bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; 1295 bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; 1296 bfd_elf64_powerpc_freebsd_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; 1297+ bfd_elf64_riscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;; 1298 bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; 1299 bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; 1300 bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; 1301@@ -15447,7 +15449,6 @@ 1302 nlm32_i386_vec) tb="$tb nlm32-i386.lo nlm32.lo nlm.lo" ;; 1303 nlm32_powerpc_vec) tb="$tb nlm32-ppc.lo nlm32.lo nlm.lo" ;; 1304 nlm32_sparc_vec) tb="$tb nlm32-sparc.lo nlm32.lo nlm.lo" ;; 1305- or32coff_big_vec) tb="$tb coff-or32.lo cofflink.lo" ;; 1306 pc532machaout_vec) tb="$tb pc532-mach.lo aout-ns32k.lo" ;; 1307 pc532netbsd_vec) tb="$tb ns32knetbsd.lo aout-ns32k.lo" ;; 1308 pef_vec) tb="$tb pef.lo" ;; 1309diff -rNU3 dist.orig/bfd/configure.host dist/bfd/configure.host 1310--- dist.orig/bfd/configure.host 2010-12-31 12:00:52.000000000 +0100 1311+++ dist/bfd/configure.host 2015-10-18 13:11:12.000000000 +0200 1312@@ -57,6 +57,18 @@ 1313 1314 m68*-hp-hpux*) HDEFINES=-DHOST_HP300HPUX ;; 1315 1316+sparc64*-*-netbsd*) host64=true; HOST_64BIT_TYPE=long ;; 1317+ 1318+x86_64*-*-netbsd*) host64=true; HOST_64BIT_TYPE=long ;; 1319+ 1320+*-*-aix*) HOST_64BIT_TYPE="long long" 1321+ HOST_U_64BIT_TYPE="unsigned long long" 1322+ ;; 1323+ 1324+*-*-solaris*) HOST_64BIT_TYPE="long long" 1325+ HOST_U_64BIT_TYPE="unsigned long long" 1326+ ;; 1327+ 1328 # Some Solaris systems (osol0906 at least) have a libc that doesn't recognise 1329 # the "MS-ANSI" code page name, so we define an override for CP_ACP (sets the 1330 # default code page used by windres/windmc when not specified by a commandline 1331diff -rNU3 dist.orig/bfd/configure.in dist/bfd/configure.in 1332--- dist.orig/bfd/configure.in 2013-03-25 10:08:05.000000000 +0100 1333+++ dist/bfd/configure.in 2015-10-18 13:11:12.000000000 +0200 1334@@ -254,6 +254,7 @@ 1335 COREFILE=netbsd-core.lo 1336 ;; 1337 arm-*-riscix) COREFILE=trad-core.lo ;; 1338+ arm*-*-netbsd*) COREFILE=netbsd-core.lo ;; 1339 hppa*-*-hpux*) COREFILE=hpux-core.lo ;; 1340 hppa*-*-hiux*) COREFILE=hpux-core.lo ;; 1341 hppa*-*-mpeix*) COREFILE=hpux-core.lo ;; 1342@@ -340,7 +341,7 @@ 1343 COREFILE=trad-core.lo 1344 TRAD_HEADER='"hosts/i860mach3.h"' 1345 ;; 1346- mips-*-netbsd* | mips*-*-openbsd*) 1347+ mips*-*-netbsd* | mips*-*-openbsd*) 1348 COREFILE=netbsd-core.lo 1349 ;; 1350 mips-dec-*) 1351@@ -771,7 +772,8 @@ 1352 bfd_elf32_ntradlittlemips_vec | bfd_elf32_ntradlittlemips_freebsd_vec) 1353 tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; 1354 bfd_elf32_openrisc_vec) tb="$tb elf32-openrisc.lo elf32.lo $elf" ;; 1355- bfd_elf32_or32_big_vec) tb="$tb elf32-or32.lo elf32.lo $elf" ;; 1356+ bfd_elf32_or1k_big_vec) tb="$tb elf32-or1k.lo elf32.lo $elf" ;; 1357+ bfd_elf32_riscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;; 1358 bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; 1359 bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; 1360 bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; 1361@@ -835,6 +837,7 @@ 1362 bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;; 1363 bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;; 1364 bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; 1365+ bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; 1366 bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;; 1367 bfd_elf64_hppa_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;; 1368 bfd_elf64_ia64_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;; 1369@@ -844,10 +847,12 @@ 1370 bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;; 1371 bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;; 1372 bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; 1373+ bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; 1374 bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;; 1375 bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; 1376 bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; 1377 bfd_elf64_powerpc_freebsd_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; 1378+ bfd_elf64_riscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;; 1379 bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; 1380 bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; 1381 bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; 1382@@ -939,7 +944,6 @@ 1383 nlm32_i386_vec) tb="$tb nlm32-i386.lo nlm32.lo nlm.lo" ;; 1384 nlm32_powerpc_vec) tb="$tb nlm32-ppc.lo nlm32.lo nlm.lo" ;; 1385 nlm32_sparc_vec) tb="$tb nlm32-sparc.lo nlm32.lo nlm.lo" ;; 1386- or32coff_big_vec) tb="$tb coff-or32.lo cofflink.lo" ;; 1387 pc532machaout_vec) tb="$tb pc532-mach.lo aout-ns32k.lo" ;; 1388 pc532netbsd_vec) tb="$tb ns32knetbsd.lo aout-ns32k.lo" ;; 1389 pef_vec) tb="$tb pef.lo" ;; 1390diff -rNU3 dist.orig/bfd/cpu-or1k.c dist/bfd/cpu-or1k.c 1391--- dist.orig/bfd/cpu-or1k.c 1970-01-01 01:00:00.000000000 +0100 1392+++ dist/bfd/cpu-or1k.c 2015-10-18 13:11:12.000000000 +0200 1393@@ -0,0 +1,61 @@ 1394+/* BFD support for the OpenRISC 1000 architecture. 1395+ Copyright 2002, 2005, 2007 Free Software Foundation, Inc. 1396+ Contributed by Ivan Guzvinec <ivang@opencores.org> 1397+ 1398+ This file is part of BFD, the Binary File Descriptor library. 1399+ 1400+ This program is free software; you can redistribute it and/or modify 1401+ it under the terms of the GNU General Public License as published by 1402+ the Free Software Foundation; either version 3 of the License, or 1403+ (at your option) any later version. 1404+ 1405+ This program is distributed in the hope that it will be useful, 1406+ but WITHOUT ANY WARRANTY; without even the implied warranty of 1407+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1408+ GNU General Public License for more details. 1409+ 1410+ You should have received a copy of the GNU General Public License 1411+ along with this program; if not, write to the Free Software 1412+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 1413+ MA 02110-1301, USA. */ 1414+ 1415+#include "sysdep.h" 1416+#include "bfd.h" 1417+#include "libbfd.h" 1418+ 1419+extern const bfd_arch_info_type bfd_or1knd_arch; 1420+ 1421+const bfd_arch_info_type bfd_or1k_arch = 1422+ { 1423+ 32, /* 32 bits in a word. */ 1424+ 32, /* 32 bits in an address. */ 1425+ 8, /* 8 bits in a byte. */ 1426+ bfd_arch_or1k, 1427+ bfd_mach_or1k, 1428+ "or1k", 1429+ "or1k", 1430+ 4, 1431+ TRUE, /* The one and only. */ 1432+ bfd_default_compatible, 1433+ bfd_default_scan, 1434+ bfd_arch_default_fill, 1435+ &bfd_or1knd_arch, 1436+ }; 1437+ 1438+ 1439+const bfd_arch_info_type bfd_or1knd_arch = 1440+ { 1441+ 32, /* 32 bits in a word. */ 1442+ 32, /* 32 bits in an address. */ 1443+ 8, /* 8 bits in a byte. */ 1444+ bfd_arch_or1k, 1445+ bfd_mach_or1knd, 1446+ "or1knd", 1447+ "or1knd", 1448+ 4, 1449+ TRUE, /* The one and only. */ 1450+ bfd_default_compatible, 1451+ bfd_default_scan, 1452+ bfd_arch_default_fill, 1453+ 0, 1454+ }; 1455diff -rNU3 dist.orig/bfd/cpu-or32.c dist/bfd/cpu-or32.c 1456--- dist.orig/bfd/cpu-or32.c 2012-01-31 18:54:35.000000000 +0100 1457+++ dist/bfd/cpu-or32.c 1970-01-01 01:00:00.000000000 +0100 1458@@ -1,42 +0,0 @@ 1459-/* BFD support for the OpenRISC 1000 architecture. 1460- Copyright 2002, 2005, 2007 Free Software Foundation, Inc. 1461- Contributed by Ivan Guzvinec <ivang@opencores.org> 1462- 1463- This file is part of BFD, the Binary File Descriptor library. 1464- 1465- This program is free software; you can redistribute it and/or modify 1466- it under the terms of the GNU General Public License as published by 1467- the Free Software Foundation; either version 3 of the License, or 1468- (at your option) any later version. 1469- 1470- This program is distributed in the hope that it will be useful, 1471- but WITHOUT ANY WARRANTY; without even the implied warranty of 1472- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1473- GNU General Public License for more details. 1474- 1475- You should have received a copy of the GNU General Public License 1476- along with this program; if not, write to the Free Software 1477- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 1478- MA 02110-1301, USA. */ 1479- 1480-#include "sysdep.h" 1481-#include "bfd.h" 1482-#include "libbfd.h" 1483- 1484-const bfd_arch_info_type bfd_or32_arch = 1485- { 1486- 32, /* 32 bits in a word. */ 1487- 32, /* 32 bits in an address. */ 1488- 8, /* 8 bits in a byte. */ 1489- bfd_arch_or32, 1490- 0, /* Only 1 machine. */ 1491- "or32", 1492- "or32", 1493- 4, 1494- TRUE, /* The one and only. */ 1495- bfd_default_compatible, 1496- bfd_default_scan, 1497- bfd_arch_default_fill, 1498- 0, 1499- }; 1500- 1501diff -rNU3 dist.orig/bfd/cpu-riscv.c dist/bfd/cpu-riscv.c 1502--- dist.orig/bfd/cpu-riscv.c 1970-01-01 01:00:00.000000000 +0100 1503+++ dist/bfd/cpu-riscv.c 2015-10-18 13:11:12.000000000 +0200 1504@@ -0,0 +1,80 @@ 1505+/* BFD backend for RISC-V 1506+ Copyright 2011-2014 Free Software Foundation, Inc. 1507+ 1508+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 1509+ Based on MIPS target. 1510+ 1511+ This file is part of BFD, the Binary File Descriptor library. 1512+ 1513+ This program is free software; you can redistribute it and/or modify 1514+ it under the terms of the GNU General Public License as published by 1515+ the Free Software Foundation; either version 3 of the License, or 1516+ (at your option) any later version. 1517+ 1518+ This program is distributed in the hope that it will be useful, 1519+ but WITHOUT ANY WARRANTY; without even the implied warranty of 1520+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1521+ GNU General Public License for more details. 1522+ 1523+ You should have received a copy of the GNU General Public License 1524+ along with this program; if not, write to the Free Software 1525+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 1526+ MA 02110-1301, USA. */ 1527+ 1528+#include "sysdep.h" 1529+#include "bfd.h" 1530+#include "libbfd.h" 1531+ 1532+static const bfd_arch_info_type *riscv_compatible 1533+ (const bfd_arch_info_type *, const bfd_arch_info_type *); 1534+ 1535+/* The default routine tests bits_per_word, which is wrong on RISC-V, as 1536+ RISC-V word size doesn't correlate with reloc size. */ 1537+ 1538+static const bfd_arch_info_type * 1539+riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b) 1540+{ 1541+ if (a->arch != b->arch) 1542+ return NULL; 1543+ 1544+ /* Machine compatibility is checked in 1545+ _bfd_riscv_elf_merge_private_bfd_data. */ 1546+ 1547+ return a; 1548+} 1549+ 1550+#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ 1551+ { \ 1552+ BITS_WORD, /* bits in a word */ \ 1553+ BITS_ADDR, /* bits in an address */ \ 1554+ 8, /* 8 bits in a byte */ \ 1555+ bfd_arch_riscv, \ 1556+ NUMBER, \ 1557+ "riscv", \ 1558+ PRINT, \ 1559+ 3, \ 1560+ DEFAULT, \ 1561+ riscv_compatible, \ 1562+ bfd_default_scan, \ 1563+ bfd_arch_default_fill, \ 1564+ NEXT, \ 1565+ } 1566+ 1567+enum 1568+{ 1569+ I_riscv64, 1570+ I_riscv32 1571+}; 1572+ 1573+#define NN(index) (&arch_info_struct[(index) + 1]) 1574+ 1575+static const bfd_arch_info_type arch_info_struct[] = 1576+{ 1577+ N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN(I_riscv64)), 1578+ N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0) 1579+}; 1580+ 1581+/* The default architecture is riscv:rv64. */ 1582+ 1583+const bfd_arch_info_type bfd_riscv_arch = 1584+N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]); 1585diff -rNU3 dist.orig/bfd/doc/Makefile.in dist/bfd/doc/Makefile.in 1586--- dist.orig/bfd/doc/Makefile.in 2013-03-25 10:08:08.000000000 +0100 1587+++ dist/bfd/doc/Makefile.in 2015-10-18 13:11:12.000000000 +0200 1588@@ -417,7 +417,9 @@ 1589 clean-libtool: 1590 -rm -rf .libs _libs 1591 1592-bfd.info: bfd.texinfo $(bfd_TEXINFOS) 1593+bfd.info: 1594+ @echo "NOT REBUILDING $@" 1595+NetBSD_DISABLED_bfd.info: bfd.texinfo $(bfd_TEXINFOS) 1596 restore=: && backupdir="$(am__leading_dot)am$$$$" && \ 1597 rm -rf $$backupdir && mkdir $$backupdir && \ 1598 if ($(MAKEINFO) --version) >/dev/null 2>&1; then \ 1599diff -rNU3 dist.orig/bfd/doc/reloc.texi dist/bfd/doc/reloc.texi 1600--- dist.orig/bfd/doc/reloc.texi 2012-11-13 15:19:29.000000000 +0100 1601+++ dist/bfd/doc/reloc.texi 2015-10-18 13:11:12.000000000 +0200 1602@@ -570,6 +570,12 @@ 1603 @deffnx {} BFD_RELOC_68K_TLS_LE8 1604 Relocations used by 68K ELF. 1605 @end deffn 1606+@deffn {} BFD_RELOC_VAX_GLOB_DAT 1607+@deffnx {} BFD_RELOC_VAX_GLOB_REF 1608+@deffnx {} BFD_RELOC_VAX_JMP_SLOT 1609+@deffnx {} BFD_RELOC_VAX_RELATIVE 1610+Relocations used by VAX ELF. 1611+@end deffn 1612 @deffn {} BFD_RELOC_32_BASEREL 1613 @deffnx {} BFD_RELOC_16_BASEREL 1614 @deffnx {} BFD_RELOC_LO16_BASEREL 1615diff -rNU3 dist.orig/bfd/elf-bfd.h dist/bfd/elf-bfd.h 1616--- dist.orig/bfd/elf-bfd.h 2013-03-25 09:06:19.000000000 +0100 1617+++ dist/bfd/elf-bfd.h 2015-10-18 13:11:12.000000000 +0200 1618@@ -420,6 +420,7 @@ 1619 MICROBLAZE_ELF_DATA, 1620 MIPS_ELF_DATA, 1621 MN10300_ELF_DATA, 1622+ OR1K_ELF_DATA, 1623 PPC32_ELF_DATA, 1624 PPC64_ELF_DATA, 1625 S390_ELF_DATA, 1626@@ -432,6 +433,7 @@ 1627 XGATE_ELF_DATA, 1628 TILEGX_ELF_DATA, 1629 TILEPRO_ELF_DATA, 1630+ RISCV_ELF_DATA, 1631 GENERIC_ELF_DATA 1632 }; 1633 1634diff -rNU3 dist.orig/bfd/elf.c dist/bfd/elf.c 1635--- dist.orig/bfd/elf.c 2013-03-25 09:06:19.000000000 +0100 1636+++ dist/bfd/elf.c 2015-10-18 13:11:12.000000000 +0200 1637@@ -8756,6 +8756,23 @@ 1638 return TRUE; 1639 } 1640 1641+ /* On SuperH, PT_GETREGS == mach+3 and PT_GETFPREGS == mach+5. 1642+ There's also old PT___GETREGS40 == mach + 1 for old reg 1643+ structure which lacks GBR. */ 1644+ 1645+ case bfd_arch_sh: 1646+ switch (note->type) 1647+ { 1648+ case NT_NETBSDCORE_FIRSTMACH+3: 1649+ return elfcore_make_note_pseudosection (abfd, ".reg", note); 1650+ 1651+ case NT_NETBSDCORE_FIRSTMACH+5: 1652+ return elfcore_make_note_pseudosection (abfd, ".reg2", note); 1653+ 1654+ default: 1655+ return TRUE; 1656+ } 1657+ 1658 /* On all other arch's, PT_GETREGS == mach+1 and 1659 PT_GETFPREGS == mach+3. */ 1660 1661diff -rNU3 dist.orig/bfd/elf32-arm.c dist/bfd/elf32-arm.c 1662--- dist.orig/bfd/elf32-arm.c 2013-03-25 09:06:19.000000000 +0100 1663+++ dist/bfd/elf32-arm.c 2015-10-18 13:11:12.000000000 +0200 1664@@ -13475,6 +13475,10 @@ 1665 { 1666 struct bfd_link_info *info = (struct bfd_link_info *) inf; 1667 1668+ if (info->warn_shared_textrel) 1669+ (*_bfd_error_handler) 1670+ (_("warning: dynamic relocation to `%s' in readonly section `%s'"), 1671+ h->root.root.string, s->name); 1672 info->flags |= DF_TEXTREL; 1673 1674 /* Not an error, just cut short the traversal. */ 1675@@ -15640,7 +15644,7 @@ 1676 #ifdef __QNXTARGET__ 1677 #define ELF_MAXPAGESIZE 0x1000 1678 #else 1679-#define ELF_MAXPAGESIZE 0x8000 1680+#define ELF_MAXPAGESIZE 0x10000 1681 #endif 1682 #define ELF_MINPAGESIZE 0x1000 1683 #define ELF_COMMONPAGESIZE 0x1000 1684@@ -15769,9 +15773,6 @@ 1685 #undef elf_backend_modify_program_headers 1686 #define elf_backend_modify_program_headers nacl_modify_program_headers 1687 1688-#undef ELF_MAXPAGESIZE 1689-#define ELF_MAXPAGESIZE 0x10000 1690- 1691 #include "elf32-target.h" 1692 1693 /* Reset to defaults. */ 1694diff -rNU3 dist.orig/bfd/elf32-hppa.c dist/bfd/elf32-hppa.c 1695--- dist.orig/bfd/elf32-hppa.c 2012-06-29 16:45:58.000000000 +0200 1696+++ dist/bfd/elf32-hppa.c 2015-10-18 13:11:12.000000000 +0200 1697@@ -2191,6 +2191,10 @@ 1698 { 1699 struct bfd_link_info *info = inf; 1700 1701+ if (info->warn_shared_textrel) 1702+ (*_bfd_error_handler) 1703+ (_("warning: dynamic relocation in readonly section `%s'"), 1704+ eh->root.root.string); 1705 info->flags |= DF_TEXTREL; 1706 1707 /* Not an error, just cut short the traversal. */ 1708diff -rNU3 dist.orig/bfd/elf32-i386.c dist/bfd/elf32-i386.c 1709--- dist.orig/bfd/elf32-i386.c 2013-03-25 09:06:19.000000000 +0100 1710+++ dist/bfd/elf32-i386.c 2015-10-18 13:11:12.000000000 +0200 1711@@ -518,7 +518,7 @@ 1712 /* The name of the dynamic interpreter. This is put in the .interp 1713 section. */ 1714 1715-#define ELF_DYNAMIC_INTERPRETER "/usr/lib/libc.so.1" 1716+#define ELF_DYNAMIC_INTERPRETER "/libexec/ld.elf_so" 1717 1718 /* If ELIMINATE_COPY_RELOCS is non-zero, the linker will try to avoid 1719 copying dynamic variables from a shared lib into an app's dynbss 1720@@ -2552,7 +2552,10 @@ 1721 if (s != NULL && (s->flags & SEC_READONLY) != 0) 1722 { 1723 struct bfd_link_info *info = (struct bfd_link_info *) inf; 1724- 1725+ if (info->warn_shared_textrel) 1726+ (*_bfd_error_handler) 1727+ (_("warning: dynamic relocation in readonly section `%s'"), 1728+ h->root.root.string); 1729 info->flags |= DF_TEXTREL; 1730 1731 if (info->warn_shared_textrel && info->shared) 1732diff -rNU3 dist.orig/bfd/elf32-m68k.c dist/bfd/elf32-m68k.c 1733--- dist.orig/bfd/elf32-m68k.c 2012-07-13 16:22:47.000000000 +0200 1734+++ dist/bfd/elf32-m68k.c 2015-10-18 13:11:12.000000000 +0200 1735@@ -2532,7 +2532,7 @@ 1736 if (ind->got_entry_key != 0) 1737 { 1738 BFD_ASSERT (dir->got_entry_key == 0); 1739- /* Assert that GOTs aren't partioned yet. */ 1740+ /* Assert that GOTs aren't partitioned yet. */ 1741 BFD_ASSERT (ind->glist == NULL); 1742 1743 dir->got_entry_key = ind->got_entry_key; 1744@@ -3104,6 +3104,7 @@ 1745 /* Make sure we know what is going on here. */ 1746 BFD_ASSERT (dynobj != NULL 1747 && (h->needs_plt 1748+ || h->type == STT_GNU_IFUNC 1749 || h->u.weakdef != NULL 1750 || (h->def_dynamic 1751 && h->ref_regular 1752@@ -3112,7 +3113,7 @@ 1753 /* If this is a function, put it in the procedure linkage table. We 1754 will fill in the contents of the procedure linkage table later, 1755 when we know the address of the .got section. */ 1756- if (h->type == STT_FUNC 1757+ if ((h->type == STT_FUNC || h->type == STT_GNU_IFUNC) 1758 || h->needs_plt) 1759 { 1760 if ((h->plt.refcount <= 0 1761diff -rNU3 dist.orig/bfd/elf32-openrisc.c dist/bfd/elf32-openrisc.c 1762--- dist.orig/bfd/elf32-openrisc.c 2012-05-07 05:27:50.000000000 +0200 1763+++ dist/bfd/elf32-openrisc.c 1970-01-01 01:00:00.000000000 +0100 1764@@ -1,566 +0,0 @@ 1765-/* OpenRISC-specific support for 32-bit ELF. 1766- Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2010, 2012 1767- Free Software Foundation, Inc. 1768- Contributed by Johan Rydberg, jrydberg@opencores.org 1769- 1770- This file is part of BFD, the Binary File Descriptor library. 1771- 1772- This program is free software; you can redistribute it and/or modify 1773- it under the terms of the GNU General Public License as published by 1774- the Free Software Foundation; either version 3 of the License, or 1775- (at your option) any later version. 1776- 1777- This program is distributed in the hope that it will be useful, 1778- but WITHOUT ANY WARRANTY; without even the implied warranty of 1779- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1780- GNU General Public License for more details. 1781- 1782- You should have received a copy of the GNU General Public License 1783- along with this program; if not, write to the Free Software 1784- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 1785- MA 02110-1301, USA. */ 1786- 1787-#include "sysdep.h" 1788-#include "bfd.h" 1789-#include "libbfd.h" 1790-#include "elf-bfd.h" 1791-#include "elf/openrisc.h" 1792-#include "libiberty.h" 1793- 1794-static reloc_howto_type openrisc_elf_howto_table[] = 1795-{ 1796- /* This reloc does nothing. */ 1797- HOWTO (R_OPENRISC_NONE, /* type */ 1798- 0, /* rightshift */ 1799- 2, /* size (0 = byte, 1 = short, 2 = long) */ 1800- 32, /* bitsize */ 1801- FALSE, /* pc_relative */ 1802- 0, /* bitpos */ 1803- complain_overflow_bitfield, /* complain_on_overflow */ 1804- bfd_elf_generic_reloc, /* special_function */ 1805- "R_OPENRISC_NONE", /* name */ 1806- FALSE, /* partial_inplace */ 1807- 0, /* src_mask */ 1808- 0, /* dst_mask */ 1809- FALSE), /* pcrel_offset */ 1810- 1811- /* A PC relative 26 bit relocation, right shifted by 2. */ 1812- HOWTO (R_OPENRISC_INSN_REL_26, /* type */ 1813- 2, /* rightshift */ 1814- 2, /* size (0 = byte, 1 = short, 2 = long) */ 1815- 26, /* bitsize */ 1816- TRUE, /* pc_relative */ 1817- 0, /* bitpos */ 1818- complain_overflow_signed, /* complain_on_overflow */ 1819- bfd_elf_generic_reloc, /* special_function */ 1820- "R_OPENRISC_INSN_REL_26", /* name */ 1821- FALSE, /* partial_inplace */ 1822- 0x00000000, /* src_mask */ 1823- 0x03ffffff, /* dst_mask */ 1824- FALSE), /* pcrel_offset */ 1825- 1826- /* A absolute 26 bit relocation, right shifted by 2. */ 1827- HOWTO (R_OPENRISC_INSN_ABS_26, /* type */ 1828- 2, /* rightshift */ 1829- 2, /* size (0 = byte, 1 = short, 2 = long) */ 1830- 26, /* bitsize */ 1831- FALSE, /* pc_relative */ 1832- 0, /* bitpos */ 1833- complain_overflow_signed, /* complain_on_overflow */ 1834- bfd_elf_generic_reloc, /* special_function */ 1835- "R_OPENRISC_INSN_ABS_26", /* name */ 1836- FALSE, /* partial_inplace */ 1837- 0x00000000, /* src_mask */ 1838- 0x03ffffff, /* dst_mask */ 1839- FALSE), /* pcrel_offset */ 1840- 1841- HOWTO (R_OPENRISC_LO_16_IN_INSN, /* type */ 1842- 0, /* rightshift */ 1843- 1, /* size (0 = byte, 1 = short, 2 = long) */ 1844- 16, /* bitsize */ 1845- FALSE, /* pc_relative */ 1846- 0, /* bitpos */ 1847- complain_overflow_dont, /* complain_on_overflow */ 1848- bfd_elf_generic_reloc, /* special_function */ 1849- "R_OPENRISC_LO_16_IN_INSN", /* name */ 1850- FALSE, /* partial_inplace */ 1851- 0, /* src_mask */ 1852- 0x0000ffff, /* dst_mask */ 1853- FALSE), /* pcrel_offset */ 1854- 1855- HOWTO (R_OPENRISC_HI_16_IN_INSN, /* type */ 1856- 16, /* rightshift */ 1857- 1, /* size (0 = byte, 1 = short, 2 = long) */ 1858- 16, /* bitsize */ 1859- FALSE, /* pc_relative */ 1860- 0, /* bitpos */ 1861- complain_overflow_dont, /* complain_on_overflow */ 1862- bfd_elf_generic_reloc, /* special_function */ 1863- "R_OPENRISC_HI_16_IN_INSN", /* name */ 1864- FALSE, /* partial_inplace */ 1865- 0, /* src_mask */ 1866- 0x0000ffff, /* dst_mask */ 1867- FALSE), /* pcrel_offset */ 1868- 1869- /* An 8 bit absolute relocation. */ 1870- HOWTO (R_OPENRISC_8, /* type */ 1871- 0, /* rightshift */ 1872- 0, /* size (0 = byte, 1 = short, 2 = long) */ 1873- 8, /* bitsize */ 1874- FALSE, /* pc_relative */ 1875- 0, /* bitpos */ 1876- complain_overflow_bitfield, /* complain_on_overflow */ 1877- bfd_elf_generic_reloc, /* special_function */ 1878- "R_OPENRISC_8", /* name */ 1879- TRUE, /* partial_inplace */ 1880- 0x0000, /* src_mask */ 1881- 0x00ff, /* dst_mask */ 1882- FALSE), /* pcrel_offset */ 1883- 1884- /* A 16 bit absolute relocation. */ 1885- HOWTO (R_OPENRISC_16, /* type */ 1886- 0, /* rightshift */ 1887- 1, /* size (0 = byte, 1 = short, 2 = long) */ 1888- 16, /* bitsize */ 1889- FALSE, /* pc_relative */ 1890- 0, /* bitpos */ 1891- complain_overflow_bitfield, /* complain_on_overflow */ 1892- bfd_elf_generic_reloc, /* special_function */ 1893- "R_OPENRISC_16", /* name */ 1894- TRUE, /* partial_inplace */ 1895- 0x00000000, /* src_mask */ 1896- 0x0000ffff, /* dst_mask */ 1897- FALSE), /* pcrel_offset */ 1898- 1899- /* A 32 bit absolute relocation. */ 1900- HOWTO (R_OPENRISC_32, /* type */ 1901- 0, /* rightshift */ 1902- 2, /* size (0 = byte, 1 = short, 2 = long) */ 1903- 32, /* bitsize */ 1904- FALSE, /* pc_relative */ 1905- 0, /* bitpos */ 1906- complain_overflow_bitfield, /* complain_on_overflow */ 1907- bfd_elf_generic_reloc, /* special_function */ 1908- "R_OPENRISC_32", /* name */ 1909- TRUE, /* partial_inplace */ 1910- 0x00000000, /* src_mask */ 1911- 0xffffffff, /* dst_mask */ 1912- FALSE), /* pcrel_offset */ 1913- 1914- /* GNU extension to record C++ vtable hierarchy. */ 1915- HOWTO (R_OPENRISC_GNU_VTINHERIT, /* type */ 1916- 0, /* rightshift */ 1917- 2, /* size (0 = byte, 1 = short, 2 = long) */ 1918- 0, /* bitsize */ 1919- FALSE, /* pc_relative */ 1920- 0, /* bitpos */ 1921- complain_overflow_dont, /* complain_on_overflow */ 1922- NULL, /* special_function */ 1923- "R_OPENRISC_GNU_VTINHERIT", /* name */ 1924- FALSE, /* partial_inplace */ 1925- 0, /* src_mask */ 1926- 0, /* dst_mask */ 1927- FALSE), /* pcrel_offset */ 1928- 1929- /* GNU extension to record C++ vtable member usage. */ 1930- HOWTO (R_OPENRISC_GNU_VTENTRY, /* type */ 1931- 0, /* rightshift */ 1932- 2, /* size (0 = byte, 1 = short, 2 = long) */ 1933- 0, /* bitsize */ 1934- FALSE, /* pc_relative */ 1935- 0, /* bitpos */ 1936- complain_overflow_dont, /* complain_on_overflow */ 1937- _bfd_elf_rel_vtable_reloc_fn, /* special_function */ 1938- "R_OPENRISC_GNU_VTENTRY", /* name */ 1939- FALSE, /* partial_inplace */ 1940- 0, /* src_mask */ 1941- 0, /* dst_mask */ 1942- FALSE), /* pcrel_offset */ 1943-}; 1944- 1945-/* Map BFD reloc types to OpenRISC ELF reloc types. */ 1946- 1947-struct openrisc_reloc_map 1948-{ 1949- bfd_reloc_code_real_type bfd_reloc_val; 1950- unsigned int openrisc_reloc_val; 1951-}; 1952- 1953-static const struct openrisc_reloc_map openrisc_reloc_map[] = 1954-{ 1955- { BFD_RELOC_NONE, R_OPENRISC_NONE }, 1956- { BFD_RELOC_32, R_OPENRISC_32 }, 1957- { BFD_RELOC_16, R_OPENRISC_16 }, 1958- { BFD_RELOC_8, R_OPENRISC_8 }, 1959- { BFD_RELOC_OPENRISC_REL_26, R_OPENRISC_INSN_REL_26 }, 1960- { BFD_RELOC_OPENRISC_ABS_26, R_OPENRISC_INSN_ABS_26 }, 1961- { BFD_RELOC_HI16, R_OPENRISC_HI_16_IN_INSN }, 1962- { BFD_RELOC_LO16, R_OPENRISC_LO_16_IN_INSN }, 1963- { BFD_RELOC_VTABLE_INHERIT, R_OPENRISC_GNU_VTINHERIT }, 1964- { BFD_RELOC_VTABLE_ENTRY, R_OPENRISC_GNU_VTENTRY } 1965-}; 1966- 1967-static reloc_howto_type * 1968-openrisc_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, 1969- bfd_reloc_code_real_type code) 1970-{ 1971- unsigned int i; 1972- 1973- for (i = ARRAY_SIZE (openrisc_reloc_map); --i;) 1974- if (openrisc_reloc_map[i].bfd_reloc_val == code) 1975- return & openrisc_elf_howto_table[openrisc_reloc_map[i]. 1976- openrisc_reloc_val]; 1977- 1978- return NULL; 1979-} 1980- 1981-static reloc_howto_type * 1982-openrisc_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 1983- const char *r_name) 1984-{ 1985- unsigned int i; 1986- 1987- for (i = 0; 1988- i < (sizeof (openrisc_elf_howto_table) 1989- / sizeof (openrisc_elf_howto_table[0])); 1990- i++) 1991- if (openrisc_elf_howto_table[i].name != NULL 1992- && strcasecmp (openrisc_elf_howto_table[i].name, r_name) == 0) 1993- return &openrisc_elf_howto_table[i]; 1994- 1995- return NULL; 1996-} 1997- 1998-/* Set the howto pointer for an OpenRISC ELF reloc. */ 1999- 2000-static void 2001-openrisc_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, 2002- arelent * cache_ptr, 2003- Elf_Internal_Rela * dst) 2004-{ 2005- unsigned int r_type; 2006- 2007- r_type = ELF32_R_TYPE (dst->r_info); 2008- BFD_ASSERT (r_type < (unsigned int) R_OPENRISC_max); 2009- cache_ptr->howto = & openrisc_elf_howto_table[r_type]; 2010-} 2011- 2012-/* Perform a single relocation. By default we use the standard BFD 2013- routines, but a few relocs, we have to do them ourselves. */ 2014- 2015-static bfd_reloc_status_type 2016-openrisc_final_link_relocate (reloc_howto_type *howto, 2017- bfd *input_bfd, 2018- asection *input_section, 2019- bfd_byte *contents, 2020- Elf_Internal_Rela *rel, 2021- bfd_vma relocation) 2022-{ 2023- bfd_reloc_status_type r = bfd_reloc_ok; 2024- 2025- switch (howto->type) 2026- { 2027- case R_OPENRISC_LO_16_IN_INSN: 2028- relocation &= 0xffff; 2029- r = _bfd_final_link_relocate (howto, input_bfd, input_section, 2030- contents, rel->r_offset, 2031- relocation, rel->r_addend); 2032- break; 2033- 2034- default: 2035- r = _bfd_final_link_relocate (howto, input_bfd, input_section, 2036- contents, rel->r_offset, 2037- relocation, rel->r_addend); 2038- } 2039- 2040- return r; 2041-} 2042- 2043-/* Relocate an OpenRISC ELF section. 2044- 2045- The RELOCATE_SECTION function is called by the new ELF backend linker 2046- to handle the relocations for a section. 2047- 2048- The relocs are always passed as Rela structures; if the section 2049- actually uses Rel structures, the r_addend field will always be 2050- zero. 2051- 2052- This function is responsible for adjusting the section contents as 2053- necessary, and (if using Rela relocs and generating a relocatable 2054- output file) adjusting the reloc addend as necessary. 2055- 2056- This function does not have to worry about setting the reloc 2057- address or the reloc symbol index. 2058- 2059- LOCAL_SYMS is a pointer to the swapped in local symbols. 2060- 2061- LOCAL_SECTIONS is an array giving the section in the input file 2062- corresponding to the st_shndx field of each local symbol. 2063- 2064- The global hash table entry for the global symbols can be found 2065- via elf_sym_hashes (input_bfd). 2066- 2067- When generating relocatable output, this function must handle 2068- STB_LOCAL/STT_SECTION symbols specially. The output symbol is 2069- going to be the section symbol corresponding to the output 2070- section, which means that the addend must be adjusted 2071- accordingly. */ 2072- 2073-static bfd_boolean 2074-openrisc_elf_relocate_section (bfd *output_bfd, 2075- struct bfd_link_info *info, 2076- bfd *input_bfd, 2077- asection *input_section, 2078- bfd_byte *contents, 2079- Elf_Internal_Rela *relocs, 2080- Elf_Internal_Sym *local_syms, 2081- asection **local_sections) 2082-{ 2083- Elf_Internal_Shdr *symtab_hdr; 2084- struct elf_link_hash_entry **sym_hashes; 2085- Elf_Internal_Rela *rel; 2086- Elf_Internal_Rela *relend; 2087- 2088- symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; 2089- sym_hashes = elf_sym_hashes (input_bfd); 2090- relend = relocs + input_section->reloc_count; 2091- 2092- for (rel = relocs; rel < relend; rel++) 2093- { 2094- reloc_howto_type *howto; 2095- unsigned long r_symndx; 2096- Elf_Internal_Sym *sym; 2097- asection *sec; 2098- struct elf_link_hash_entry *h; 2099- bfd_vma relocation; 2100- bfd_reloc_status_type r; 2101- const char *name = NULL; 2102- int r_type; 2103- 2104- r_type = ELF32_R_TYPE (rel->r_info); 2105- r_symndx = ELF32_R_SYM (rel->r_info); 2106- 2107- if (r_type == R_OPENRISC_GNU_VTINHERIT 2108- || r_type == R_OPENRISC_GNU_VTENTRY) 2109- continue; 2110- 2111- if ((unsigned int) r_type > 2112- (sizeof openrisc_elf_howto_table / sizeof (reloc_howto_type))) 2113- abort (); 2114- 2115- howto = openrisc_elf_howto_table + ELF32_R_TYPE (rel->r_info); 2116- h = NULL; 2117- sym = NULL; 2118- sec = NULL; 2119- 2120- if (r_symndx < symtab_hdr->sh_info) 2121- { 2122- sym = local_syms + r_symndx; 2123- sec = local_sections[r_symndx]; 2124- relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); 2125- 2126- name = bfd_elf_string_from_elf_section 2127- (input_bfd, symtab_hdr->sh_link, sym->st_name); 2128- name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; 2129- } 2130- else 2131- { 2132- bfd_boolean unresolved_reloc, warned; 2133- 2134- RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, 2135- r_symndx, symtab_hdr, sym_hashes, 2136- h, sec, relocation, 2137- unresolved_reloc, warned); 2138- } 2139- 2140- if (sec != NULL && discarded_section (sec)) 2141- RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, 2142- rel, 1, relend, howto, 0, contents); 2143- 2144- if (info->relocatable) 2145- continue; 2146- 2147- r = openrisc_final_link_relocate (howto, input_bfd, input_section, 2148- contents, rel, relocation); 2149- 2150- if (r != bfd_reloc_ok) 2151- { 2152- const char *msg = NULL; 2153- 2154- switch (r) 2155- { 2156- case bfd_reloc_overflow: 2157- r = info->callbacks->reloc_overflow 2158- (info, (h ? &h->root : NULL), name, howto->name, 2159- (bfd_vma) 0, input_bfd, input_section, rel->r_offset); 2160- break; 2161- 2162- case bfd_reloc_undefined: 2163- r = info->callbacks->undefined_symbol 2164- (info, name, input_bfd, input_section, rel->r_offset, TRUE); 2165- break; 2166- 2167- case bfd_reloc_outofrange: 2168- msg = _("internal error: out of range error"); 2169- break; 2170- 2171- case bfd_reloc_notsupported: 2172- msg = _("internal error: unsupported relocation error"); 2173- break; 2174- 2175- case bfd_reloc_dangerous: 2176- msg = _("internal error: dangerous relocation"); 2177- break; 2178- 2179- default: 2180- msg = _("internal error: unknown error"); 2181- break; 2182- } 2183- 2184- if (msg) 2185- r = info->callbacks->warning 2186- (info, msg, name, input_bfd, input_section, rel->r_offset); 2187- 2188- if (!r) 2189- return FALSE; 2190- } 2191- } 2192- 2193- return TRUE; 2194-} 2195- 2196-/* Return the section that should be marked against GC for a given 2197- relocation. */ 2198- 2199-static asection * 2200-openrisc_elf_gc_mark_hook (asection *sec, 2201- struct bfd_link_info *info, 2202- Elf_Internal_Rela *rel, 2203- struct elf_link_hash_entry *h, 2204- Elf_Internal_Sym *sym) 2205-{ 2206- if (h != NULL) 2207- switch (ELF32_R_TYPE (rel->r_info)) 2208- { 2209- case R_OPENRISC_GNU_VTINHERIT: 2210- case R_OPENRISC_GNU_VTENTRY: 2211- return NULL; 2212- } 2213- 2214- return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); 2215-} 2216- 2217-/* Look through the relocs for a section during the first phase. 2218- Since we don't do .gots or .plts, we just need to consider the 2219- virtual table relocs for gc. */ 2220- 2221-static bfd_boolean 2222-openrisc_elf_check_relocs (bfd *abfd, 2223- struct bfd_link_info *info, 2224- asection *sec, 2225- const Elf_Internal_Rela *relocs) 2226-{ 2227- Elf_Internal_Shdr *symtab_hdr; 2228- struct elf_link_hash_entry **sym_hashes; 2229- const Elf_Internal_Rela *rel; 2230- const Elf_Internal_Rela *rel_end; 2231- 2232- if (info->relocatable) 2233- return TRUE; 2234- 2235- symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 2236- sym_hashes = elf_sym_hashes (abfd); 2237- 2238- rel_end = relocs + sec->reloc_count; 2239- for (rel = relocs; rel < rel_end; rel++) 2240- { 2241- struct elf_link_hash_entry *h; 2242- unsigned long r_symndx; 2243- 2244- r_symndx = ELF32_R_SYM (rel->r_info); 2245- if (r_symndx < symtab_hdr->sh_info) 2246- h = NULL; 2247- else 2248- { 2249- h = sym_hashes[r_symndx - symtab_hdr->sh_info]; 2250- while (h->root.type == bfd_link_hash_indirect 2251- || h->root.type == bfd_link_hash_warning) 2252- h = (struct elf_link_hash_entry *) h->root.u.i.link; 2253- } 2254- 2255- switch (ELF32_R_TYPE (rel->r_info)) 2256- { 2257- /* This relocation describes the C++ object vtable hierarchy. 2258- Reconstruct it for later use during GC. */ 2259- case R_OPENRISC_GNU_VTINHERIT: 2260- if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) 2261- return FALSE; 2262- break; 2263- 2264- /* This relocation describes which C++ vtable entries are actually 2265- used. Record for later use during GC. */ 2266- case R_OPENRISC_GNU_VTENTRY: 2267- BFD_ASSERT (h != NULL); 2268- if (h != NULL 2269- && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) 2270- return FALSE; 2271- break; 2272- } 2273- } 2274- 2275- return TRUE; 2276-} 2277- 2278-/* Set the right machine number. */ 2279- 2280-static bfd_boolean 2281-openrisc_elf_object_p (bfd *abfd) 2282-{ 2283- bfd_default_set_arch_mach (abfd, bfd_arch_openrisc, 0); 2284- return TRUE; 2285-} 2286- 2287-/* Store the machine number in the flags field. */ 2288- 2289-static void 2290-openrisc_elf_final_write_processing (bfd *abfd, 2291- bfd_boolean linker ATTRIBUTE_UNUSED) 2292-{ 2293- unsigned long val; 2294- 2295- switch (bfd_get_mach (abfd)) 2296- { 2297- default: 2298- val = 0; 2299- break; 2300- } 2301- 2302- elf_elfheader (abfd)->e_flags &= ~0xf; 2303- elf_elfheader (abfd)->e_flags |= val; 2304-} 2305- 2306- 2307-#define ELF_ARCH bfd_arch_openrisc 2308-#define ELF_MACHINE_CODE EM_OPENRISC 2309-#define ELF_MACHINE_ALT1 EM_OPENRISC_OLD 2310-#define ELF_MAXPAGESIZE 0x1000 2311- 2312-#define TARGET_BIG_SYM bfd_elf32_openrisc_vec 2313-#define TARGET_BIG_NAME "elf32-openrisc" 2314- 2315-#define elf_info_to_howto_rel NULL 2316-#define elf_info_to_howto openrisc_info_to_howto_rela 2317-#define elf_backend_relocate_section openrisc_elf_relocate_section 2318-#define elf_backend_gc_mark_hook openrisc_elf_gc_mark_hook 2319-#define elf_backend_check_relocs openrisc_elf_check_relocs 2320- 2321-#define elf_backend_can_gc_sections 1 2322-#define elf_backend_rela_normal 1 2323- 2324-#define bfd_elf32_bfd_reloc_type_lookup openrisc_reloc_type_lookup 2325-#define bfd_elf32_bfd_reloc_name_lookup openrisc_reloc_name_lookup 2326- 2327-#define elf_backend_object_p openrisc_elf_object_p 2328-#define elf_backend_final_write_processing openrisc_elf_final_write_processing 2329- 2330-#include "elf32-target.h" 2331diff -rNU3 dist.orig/bfd/elf32-or1k.c dist/bfd/elf32-or1k.c 2332--- dist.orig/bfd/elf32-or1k.c 1970-01-01 01:00:00.000000000 +0100 2333+++ dist/bfd/elf32-or1k.c 2015-10-18 13:11:12.000000000 +0200 2334@@ -0,0 +1,2852 @@ 2335+/* Or1k-specific support for 32-bit ELF. 2336+ Copyright 2001-2014 Free Software Foundation, Inc. 2337+ Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 2338+ 2339+ PIC parts added by Stefan Kristiansson, stefan.kristiansson@saunalahti.fi, 2340+ largely based on elf32-m32r.c and elf32-microblaze.c. 2341+ 2342+ This file is part of BFD, the Binary File Descriptor library. 2343+ 2344+ This program is free software; you can redistribute it and/or modify 2345+ it under the terms of the GNU General Public License as published by 2346+ the Free Software Foundation; either version 3 of the License, or 2347+ (at your option) any later version. 2348+ 2349+ This program is distributed in the hope that it will be useful, 2350+ but WITHOUT ANY WARRANTY; without even the implied warranty of 2351+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2352+ GNU General Public License for more details. 2353+ 2354+ You should have received a copy of the GNU General Public License 2355+ along with this program; if not, see <http://www.gnu.org/licenses/>. */ 2356+ 2357+#include "sysdep.h" 2358+#include "bfd.h" 2359+#include "libbfd.h" 2360+#include "elf-bfd.h" 2361+#include "elf/or1k.h" 2362+#include "libiberty.h" 2363+ 2364+#define PLT_ENTRY_SIZE 20 2365+ 2366+#define PLT0_ENTRY_WORD0 0x19800000 /* l.movhi r12, 0 <- hi(.got+4) */ 2367+#define PLT0_ENTRY_WORD1 0xa98c0000 /* l.ori r12, r12, 0 <- lo(.got+4) */ 2368+#define PLT0_ENTRY_WORD2 0x85ec0004 /* l.lwz r15, 4(r12) <- *(.got+8)*/ 2369+#define PLT0_ENTRY_WORD3 0x44007800 /* l.jr r15 */ 2370+#define PLT0_ENTRY_WORD4 0x858c0000 /* l.lwz r12, 0(r12) */ 2371+ 2372+#define PLT0_PIC_ENTRY_WORD0 0x85900004 /* l.lwz r12, 4(r16) */ 2373+#define PLT0_PIC_ENTRY_WORD1 0x85f00008 /* l.lwz r15, 8(r16) */ 2374+#define PLT0_PIC_ENTRY_WORD2 0x44007800 /* l.jr r15 */ 2375+#define PLT0_PIC_ENTRY_WORD3 0x15000000 /* l.nop */ 2376+#define PLT0_PIC_ENTRY_WORD4 0x15000000 /* l.nop */ 2377+ 2378+#define PLT_ENTRY_WORD0 0x19800000 /* l.movhi r12, 0 <- hi(got idx addr) */ 2379+#define PLT_ENTRY_WORD1 0xa98c0000 /* l.ori r12, r12, 0 <- lo(got idx addr) */ 2380+#define PLT_ENTRY_WORD2 0x858c0000 /* l.lwz r12, 0(r12) */ 2381+#define PLT_ENTRY_WORD3 0x44006000 /* l.jr r12 */ 2382+#define PLT_ENTRY_WORD4 0xa9600000 /* l.ori r11, r0, 0 <- reloc offset */ 2383+ 2384+#define PLT_PIC_ENTRY_WORD0 0x85900000 /* l.lwz r12, 0(r16) <- index in got */ 2385+#define PLT_PIC_ENTRY_WORD1 0xa9600000 /* l.ori r11, r0, 0 <- reloc offset */ 2386+#define PLT_PIC_ENTRY_WORD2 0x44006000 /* l.jr r12 */ 2387+#define PLT_PIC_ENTRY_WORD3 0x15000000 /* l.nop */ 2388+#define PLT_PIC_ENTRY_WORD4 0x15000000 /* l.nop */ 2389+ 2390+#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1" 2391+ 2392+static reloc_howto_type or1k_elf_howto_table[] = 2393+{ 2394+ /* This reloc does nothing. */ 2395+ HOWTO (R_OR1K_NONE, /* type */ 2396+ 0, /* rightshift */ 2397+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2398+ 32, /* bitsize */ 2399+ FALSE, /* pc_relative */ 2400+ 0, /* bitpos */ 2401+ complain_overflow_dont, /* complain_on_overflow */ 2402+ bfd_elf_generic_reloc, /* special_function */ 2403+ "R_OR1K_NONE", /* name */ 2404+ FALSE, /* partial_inplace */ 2405+ 0, /* src_mask */ 2406+ 0, /* dst_mask */ 2407+ FALSE), /* pcrel_offset */ 2408+ 2409+ HOWTO (R_OR1K_32, 2410+ 0, /* rightshift */ 2411+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2412+ 32, /* bitsize */ 2413+ FALSE, /* pc_relative */ 2414+ 0, /* bitpos */ 2415+ complain_overflow_unsigned, /* complain_on_overflow */ 2416+ bfd_elf_generic_reloc, /* special_function */ 2417+ "R_OR1K_32", /* name */ 2418+ FALSE, /* partial_inplace */ 2419+ 0, /* src_mask */ 2420+ 0xffffffff, /* dst_mask */ 2421+ FALSE), /* pcrel_offset */ 2422+ 2423+ HOWTO (R_OR1K_16, 2424+ 0, /* rightshift */ 2425+ 1, /* size (0 = byte, 1 = short, 2 = long) */ 2426+ 16, /* bitsize */ 2427+ FALSE, /* pc_relative */ 2428+ 0, /* bitpos */ 2429+ complain_overflow_unsigned, /* complain_on_overflow */ 2430+ bfd_elf_generic_reloc, /* special_function */ 2431+ "R_OR1K_16", /* name */ 2432+ FALSE, /* partial_inplace */ 2433+ 0, /* src_mask */ 2434+ 0xffff, /* dst_mask */ 2435+ FALSE), /* pcrel_offset */ 2436+ 2437+ HOWTO (R_OR1K_8, 2438+ 0, /* rightshift */ 2439+ 0, /* size (0 = byte, 1 = short, 2 = long) */ 2440+ 8, /* bitsize */ 2441+ FALSE, /* pc_relative */ 2442+ 0, /* bitpos */ 2443+ complain_overflow_unsigned, /* complain_on_overflow */ 2444+ bfd_elf_generic_reloc, /* special_function */ 2445+ "R_OR1K_8", /* name */ 2446+ FALSE, /* partial_inplace */ 2447+ 0, /* src_mask */ 2448+ 0xff, /* dst_mask */ 2449+ FALSE), /* pcrel_offset */ 2450+ 2451+ HOWTO (R_OR1K_LO_16_IN_INSN, /* type */ 2452+ 0, /* rightshift */ 2453+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2454+ 16, /* bitsize */ 2455+ FALSE, /* pc_relative */ 2456+ 0, /* bitpos */ 2457+ complain_overflow_dont, /* complain_on_overflow */ 2458+ bfd_elf_generic_reloc, /* special_function */ 2459+ "R_OR1K_LO_16_IN_INSN", /* name */ 2460+ FALSE, /* partial_inplace */ 2461+ 0, /* src_mask */ 2462+ 0x0000ffff, /* dst_mask */ 2463+ FALSE), /* pcrel_offset */ 2464+ 2465+ HOWTO (R_OR1K_HI_16_IN_INSN, /* type */ 2466+ 16, /* rightshift */ 2467+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2468+ 16, /* bitsize */ 2469+ FALSE, /* pc_relative */ 2470+ 0, /* bitpos */ 2471+ complain_overflow_dont, /* complain_on_overflow */ 2472+ bfd_elf_generic_reloc, /* special_function */ 2473+ "R_OR1K_HI_16_IN_INSN", /* name */ 2474+ FALSE, /* partial_inplace */ 2475+ 0, /* src_mask */ 2476+ 0x0000ffff, /* dst_mask */ 2477+ FALSE), /* pcrel_offset */ 2478+ 2479+ /* A PC relative 26 bit relocation, right shifted by 2. */ 2480+ HOWTO (R_OR1K_INSN_REL_26, /* type */ 2481+ 2, /* rightshift */ 2482+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2483+ 26, /* bitsize */ 2484+ TRUE, /* pc_relative */ 2485+ 0, /* bitpos */ 2486+ complain_overflow_signed, /* complain_on_overflow */ 2487+ bfd_elf_generic_reloc, /* special_function */ 2488+ "R_OR1K_INSN_REL_26", /* name */ 2489+ FALSE, /* partial_inplace */ 2490+ 0, /* src_mask */ 2491+ 0x03ffffff, /* dst_mask */ 2492+ TRUE), /* pcrel_offset */ 2493+ 2494+ /* GNU extension to record C++ vtable hierarchy. */ 2495+ HOWTO (R_OR1K_GNU_VTINHERIT, /* type */ 2496+ 0, /* rightshift */ 2497+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2498+ 0, /* bitsize */ 2499+ FALSE, /* pc_relative */ 2500+ 0, /* bitpos */ 2501+ complain_overflow_dont, /* complain_on_overflow */ 2502+ NULL, /* special_function */ 2503+ "R_OR1K_GNU_VTINHERIT", /* name */ 2504+ FALSE, /* partial_inplace */ 2505+ 0, /* src_mask */ 2506+ 0, /* dst_mask */ 2507+ FALSE), /* pcrel_offset */ 2508+ 2509+ /* GNU extension to record C++ vtable member usage. */ 2510+ HOWTO (R_OR1K_GNU_VTENTRY, /* type */ 2511+ 0, /* rightshift */ 2512+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2513+ 0, /* bitsize */ 2514+ FALSE, /* pc_relative */ 2515+ 0, /* bitpos */ 2516+ complain_overflow_dont, /* complain_on_overflow */ 2517+ _bfd_elf_rel_vtable_reloc_fn, /* special_function */ 2518+ "R_OR1K_GNU_VTENTRY", /* name */ 2519+ FALSE, /* partial_inplace */ 2520+ 0, /* src_mask */ 2521+ 0, /* dst_mask */ 2522+ FALSE), /* pcrel_offset */ 2523+ 2524+ HOWTO (R_OR1K_32_PCREL, 2525+ 0, /* rightshift */ 2526+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2527+ 32, /* bitsize */ 2528+ TRUE, /* pc_relative */ 2529+ 0, /* bitpos */ 2530+ complain_overflow_signed, /* complain_on_overflow */ 2531+ bfd_elf_generic_reloc, /* special_function */ 2532+ "R_OR1K_32_PCREL", /* name */ 2533+ FALSE, /* partial_inplace */ 2534+ 0, /* src_mask */ 2535+ 0xffffffff, /* dst_mask */ 2536+ FALSE), /* pcrel_offset */ 2537+ 2538+ HOWTO (R_OR1K_16_PCREL, 2539+ 0, /* rightshift */ 2540+ 1, /* size (0 = byte, 1 = short, 2 = long) */ 2541+ 16, /* bitsize */ 2542+ TRUE, /* pc_relative */ 2543+ 0, /* bitpos */ 2544+ complain_overflow_signed, /* complain_on_overflow */ 2545+ bfd_elf_generic_reloc, /* special_function */ 2546+ "R_OR1K_16_PCREL", /* name */ 2547+ FALSE, /* partial_inplace */ 2548+ 0, /* src_mask */ 2549+ 0xffff, /* dst_mask */ 2550+ FALSE), /* pcrel_offset */ 2551+ 2552+ HOWTO (R_OR1K_8_PCREL, 2553+ 0, /* rightshift */ 2554+ 0, /* size (0 = byte, 1 = short, 2 = long) */ 2555+ 8, /* bitsize */ 2556+ TRUE, /* pc_relative */ 2557+ 0, /* bitpos */ 2558+ complain_overflow_signed, /* complain_on_overflow */ 2559+ bfd_elf_generic_reloc, /* special_function */ 2560+ "R_OR1K_8_PCREL", /* name */ 2561+ FALSE, /* partial_inplace */ 2562+ 0, /* src_mask */ 2563+ 0xff, /* dst_mask */ 2564+ FALSE), /* pcrel_offset */ 2565+ 2566+ HOWTO (R_OR1K_GOTPC_HI16, /* Type. */ 2567+ 16, /* Rightshift. */ 2568+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ 2569+ 16, /* Bitsize. */ 2570+ TRUE, /* PC_relative. */ 2571+ 0, /* Bitpos. */ 2572+ complain_overflow_dont, /* Complain on overflow. */ 2573+ bfd_elf_generic_reloc, /* Special Function. */ 2574+ "R_OR1K_GOTPC_HI16", /* Name. */ 2575+ FALSE, /* Partial Inplace. */ 2576+ 0, /* Source Mask. */ 2577+ 0xffff, /* Dest Mask. */ 2578+ TRUE), /* PC relative offset? */ 2579+ 2580+ HOWTO (R_OR1K_GOTPC_LO16, /* Type. */ 2581+ 0, /* Rightshift. */ 2582+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ 2583+ 16, /* Bitsize. */ 2584+ TRUE, /* PC_relative. */ 2585+ 0, /* Bitpos. */ 2586+ complain_overflow_dont, /* Complain on overflow. */ 2587+ bfd_elf_generic_reloc, /* Special Function. */ 2588+ "R_OR1K_GOTPC_LO16", /* Name. */ 2589+ FALSE, /* Partial Inplace. */ 2590+ 0, /* Source Mask. */ 2591+ 0xffff, /* Dest Mask. */ 2592+ TRUE), /* PC relative offset? */ 2593+ 2594+ HOWTO (R_OR1K_GOT16, /* type */ 2595+ 0, /* rightshift */ 2596+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2597+ 16, /* bitsize */ 2598+ FALSE, /* pc_relative */ 2599+ 0, /* bitpos */ 2600+ complain_overflow_signed, /* complain_on_overflow */ 2601+ bfd_elf_generic_reloc, /* special_function */ 2602+ "R_OR1K_GOT16", /* name */ 2603+ FALSE, /* partial_inplace */ 2604+ 0, /* src_mask */ 2605+ 0xffff, /* dst_mask */ 2606+ FALSE), /* pcrel_offset */ 2607+ 2608+ /* A 26 bit PLT relocation. Shifted by 2. */ 2609+ HOWTO (R_OR1K_PLT26, /* Type. */ 2610+ 2, /* Rightshift. */ 2611+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ 2612+ 26, /* Bitsize. */ 2613+ TRUE, /* PC_relative. */ 2614+ 0, /* Bitpos. */ 2615+ complain_overflow_dont, /* Complain on overflow. */ 2616+ bfd_elf_generic_reloc,/* Special Function. */ 2617+ "R_OR1K_PLT26", /* Name. */ 2618+ FALSE, /* Partial Inplace. */ 2619+ 0, /* Source Mask. */ 2620+ 0x03ffffff, /* Dest Mask. */ 2621+ TRUE), /* PC relative offset? */ 2622+ 2623+ HOWTO (R_OR1K_GOTOFF_HI16, /* type */ 2624+ 16, /* rightshift */ 2625+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2626+ 16, /* bitsize */ 2627+ FALSE, /* pc_relative */ 2628+ 0, /* bitpos */ 2629+ complain_overflow_dont, /* complain_on_overflow */ 2630+ bfd_elf_generic_reloc, /* special_function */ 2631+ "R_OR1K_GOTOFF_HI16", /* name */ 2632+ FALSE, /* partial_inplace */ 2633+ 0x0, /* src_mask */ 2634+ 0xffff, /* dst_mask */ 2635+ FALSE), /* pcrel_offset */ 2636+ 2637+ HOWTO (R_OR1K_GOTOFF_LO16, /* type */ 2638+ 0, /* rightshift */ 2639+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2640+ 16, /* bitsize */ 2641+ FALSE, /* pc_relative */ 2642+ 0, /* bitpos */ 2643+ complain_overflow_dont, /* complain_on_overflow */ 2644+ bfd_elf_generic_reloc, /* special_function */ 2645+ "R_OR1K_GOTOFF_LO16", /* name */ 2646+ FALSE, /* partial_inplace */ 2647+ 0x0, /* src_mask */ 2648+ 0xffff, /* dst_mask */ 2649+ FALSE), /* pcrel_offset */ 2650+ 2651+ HOWTO (R_OR1K_COPY, /* type */ 2652+ 0, /* rightshift */ 2653+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2654+ 32, /* bitsize */ 2655+ FALSE, /* pc_relative */ 2656+ 0, /* bitpos */ 2657+ complain_overflow_bitfield, /* complain_on_overflow */ 2658+ bfd_elf_generic_reloc, /* special_function */ 2659+ "R_OR1K_COPY", /* name */ 2660+ FALSE, /* partial_inplace */ 2661+ 0xffffffff, /* src_mask */ 2662+ 0xffffffff, /* dst_mask */ 2663+ FALSE), /* pcrel_offset */ 2664+ 2665+ HOWTO (R_OR1K_GLOB_DAT, /* type */ 2666+ 0, /* rightshift */ 2667+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2668+ 32, /* bitsize */ 2669+ FALSE, /* pc_relative */ 2670+ 0, /* bitpos */ 2671+ complain_overflow_bitfield, /* complain_on_overflow */ 2672+ bfd_elf_generic_reloc, /* special_function */ 2673+ "R_OR1K_GLOB_DAT", /* name */ 2674+ FALSE, /* partial_inplace */ 2675+ 0xffffffff, /* src_mask */ 2676+ 0xffffffff, /* dst_mask */ 2677+ FALSE), /* pcrel_offset */ 2678+ 2679+ HOWTO (R_OR1K_JMP_SLOT, /* type */ 2680+ 0, /* rightshift */ 2681+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2682+ 32, /* bitsize */ 2683+ FALSE, /* pc_relative */ 2684+ 0, /* bitpos */ 2685+ complain_overflow_bitfield, /* complain_on_overflow */ 2686+ bfd_elf_generic_reloc, /* special_function */ 2687+ "R_OR1K_JMP_SLOT", /* name */ 2688+ FALSE, /* partial_inplace */ 2689+ 0xffffffff, /* src_mask */ 2690+ 0xffffffff, /* dst_mask */ 2691+ FALSE), /* pcrel_offset */ 2692+ 2693+ HOWTO (R_OR1K_RELATIVE, /* type */ 2694+ 0, /* rightshift */ 2695+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2696+ 32, /* bitsize */ 2697+ FALSE, /* pc_relative */ 2698+ 0, /* bitpos */ 2699+ complain_overflow_bitfield, /* complain_on_overflow */ 2700+ bfd_elf_generic_reloc, /* special_function */ 2701+ "R_OR1K_RELATIVE", /* name */ 2702+ FALSE, /* partial_inplace */ 2703+ 0xffffffff, /* src_mask */ 2704+ 0xffffffff, /* dst_mask */ 2705+ FALSE), /* pcrel_offset */ 2706+ 2707+ HOWTO (R_OR1K_TLS_GD_HI16, /* type */ 2708+ 16, /* rightshift */ 2709+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2710+ 16, /* bitsize */ 2711+ FALSE, /* pc_relative */ 2712+ 0, /* bitpos */ 2713+ complain_overflow_dont, /* complain_on_overflow */ 2714+ bfd_elf_generic_reloc, /* special_function */ 2715+ "R_OR1K_TLS_GD_HI16", /* name */ 2716+ FALSE, /* partial_inplace */ 2717+ 0x0, /* src_mask */ 2718+ 0xffff, /* dst_mask */ 2719+ FALSE), /* pcrel_offset */ 2720+ 2721+ HOWTO (R_OR1K_TLS_GD_LO16, /* type */ 2722+ 0, /* rightshift */ 2723+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2724+ 16, /* bitsize */ 2725+ FALSE, /* pc_relative */ 2726+ 0, /* bitpos */ 2727+ complain_overflow_dont, /* complain_on_overflow */ 2728+ bfd_elf_generic_reloc, /* special_function */ 2729+ "R_OR1K_TLS_GD_LO16", /* name */ 2730+ FALSE, /* partial_inplace */ 2731+ 0x0, /* src_mask */ 2732+ 0xffff, /* dst_mask */ 2733+ FALSE), /* pcrel_offset */ 2734+ 2735+ HOWTO (R_OR1K_TLS_LDM_HI16, /* type */ 2736+ 16, /* rightshift */ 2737+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2738+ 16, /* bitsize */ 2739+ FALSE, /* pc_relative */ 2740+ 0, /* bitpos */ 2741+ complain_overflow_dont, /* complain_on_overflow */ 2742+ bfd_elf_generic_reloc, /* special_function */ 2743+ "R_OR1K_TLS_LDM_HI16", /* name */ 2744+ FALSE, /* partial_inplace */ 2745+ 0x0, /* src_mask */ 2746+ 0xffff, /* dst_mask */ 2747+ FALSE), /* pcrel_offset */ 2748+ 2749+ HOWTO (R_OR1K_TLS_LDM_LO16, /* type */ 2750+ 0, /* rightshift */ 2751+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2752+ 16, /* bitsize */ 2753+ FALSE, /* pc_relative */ 2754+ 0, /* bitpos */ 2755+ complain_overflow_dont, /* complain_on_overflow */ 2756+ bfd_elf_generic_reloc, /* special_function */ 2757+ "R_OR1K_TLS_LDM_LO16", /* name */ 2758+ FALSE, /* partial_inplace */ 2759+ 0x0, /* src_mask */ 2760+ 0xffff, /* dst_mask */ 2761+ FALSE), /* pcrel_offset */ 2762+ 2763+ HOWTO (R_OR1K_TLS_LDO_HI16, /* type */ 2764+ 16, /* rightshift */ 2765+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2766+ 16, /* bitsize */ 2767+ FALSE, /* pc_relative */ 2768+ 0, /* bitpos */ 2769+ complain_overflow_dont, /* complain_on_overflow */ 2770+ bfd_elf_generic_reloc, /* special_function */ 2771+ "R_OR1K_TLS_LDO_HI16", /* name */ 2772+ FALSE, /* partial_inplace */ 2773+ 0x0, /* src_mask */ 2774+ 0xffff, /* dst_mask */ 2775+ FALSE), /* pcrel_offset */ 2776+ 2777+ HOWTO (R_OR1K_TLS_LDO_LO16, /* type */ 2778+ 0, /* rightshift */ 2779+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2780+ 16, /* bitsize */ 2781+ FALSE, /* pc_relative */ 2782+ 0, /* bitpos */ 2783+ complain_overflow_dont, /* complain_on_overflow */ 2784+ bfd_elf_generic_reloc, /* special_function */ 2785+ "R_OR1K_TLS_LDO_LO16", /* name */ 2786+ FALSE, /* partial_inplace */ 2787+ 0x0, /* src_mask */ 2788+ 0xffff, /* dst_mask */ 2789+ FALSE), /* pcrel_offset */ 2790+ 2791+ HOWTO (R_OR1K_TLS_IE_HI16, /* type */ 2792+ 16, /* rightshift */ 2793+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2794+ 16, /* bitsize */ 2795+ FALSE, /* pc_relative */ 2796+ 0, /* bitpos */ 2797+ complain_overflow_dont, /* complain_on_overflow */ 2798+ bfd_elf_generic_reloc, /* special_function */ 2799+ "R_OR1K_TLS_IE_HI16", /* name */ 2800+ FALSE, /* partial_inplace */ 2801+ 0x0, /* src_mask */ 2802+ 0xffff, /* dst_mask */ 2803+ FALSE), /* pcrel_offset */ 2804+ 2805+ HOWTO (R_OR1K_TLS_IE_LO16, /* type */ 2806+ 0, /* rightshift */ 2807+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2808+ 16, /* bitsize */ 2809+ FALSE, /* pc_relative */ 2810+ 0, /* bitpos */ 2811+ complain_overflow_dont, /* complain_on_overflow */ 2812+ bfd_elf_generic_reloc, /* special_function */ 2813+ "R_OR1K_TLS_IE_LO16", /* name */ 2814+ FALSE, /* partial_inplace */ 2815+ 0x0, /* src_mask */ 2816+ 0xffff, /* dst_mask */ 2817+ FALSE), /* pcrel_offset */ 2818+ 2819+ HOWTO (R_OR1K_TLS_LE_HI16, /* type */ 2820+ 16, /* rightshift */ 2821+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2822+ 16, /* bitsize */ 2823+ FALSE, /* pc_relative */ 2824+ 0, /* bitpos */ 2825+ complain_overflow_dont, /* complain_on_overflow */ 2826+ bfd_elf_generic_reloc, /* special_function */ 2827+ "R_OR1K_TLS_LE_HI16", /* name */ 2828+ FALSE, /* partial_inplace */ 2829+ 0x0, /* src_mask */ 2830+ 0xffff, /* dst_mask */ 2831+ FALSE), /* pcrel_offset */ 2832+ 2833+ HOWTO (R_OR1K_TLS_LE_LO16, /* type */ 2834+ 0, /* rightshift */ 2835+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 2836+ 16, /* bitsize */ 2837+ FALSE, /* pc_relative */ 2838+ 0, /* bitpos */ 2839+ complain_overflow_dont, /* complain_on_overflow */ 2840+ bfd_elf_generic_reloc, /* special_function */ 2841+ "R_OR1K_TLS_LE_LO16", /* name */ 2842+ FALSE, /* partial_inplace */ 2843+ 0x0, /* src_mask */ 2844+ 0xffff, /* dst_mask */ 2845+ FALSE), /* pcrel_offset */ 2846+ 2847+}; 2848+ 2849+/* Map BFD reloc types to Or1k ELF reloc types. */ 2850+ 2851+struct or1k_reloc_map 2852+{ 2853+ bfd_reloc_code_real_type bfd_reloc_val; 2854+ unsigned int or1k_reloc_val; 2855+}; 2856+ 2857+static const struct or1k_reloc_map or1k_reloc_map[] = 2858+{ 2859+ { BFD_RELOC_NONE, R_OR1K_NONE }, 2860+ { BFD_RELOC_32, R_OR1K_32 }, 2861+ { BFD_RELOC_16, R_OR1K_16 }, 2862+ { BFD_RELOC_8, R_OR1K_8 }, 2863+ { BFD_RELOC_LO16, R_OR1K_LO_16_IN_INSN }, 2864+ { BFD_RELOC_HI16, R_OR1K_HI_16_IN_INSN }, 2865+ { BFD_RELOC_OR1K_REL_26, R_OR1K_INSN_REL_26 }, 2866+ { BFD_RELOC_VTABLE_ENTRY, R_OR1K_GNU_VTENTRY }, 2867+ { BFD_RELOC_VTABLE_INHERIT, R_OR1K_GNU_VTINHERIT }, 2868+ { BFD_RELOC_32_PCREL, R_OR1K_32_PCREL }, 2869+ { BFD_RELOC_16_PCREL, R_OR1K_16_PCREL }, 2870+ { BFD_RELOC_8_PCREL, R_OR1K_8_PCREL }, 2871+ { BFD_RELOC_OR1K_GOTPC_HI16, R_OR1K_GOTPC_HI16 }, 2872+ { BFD_RELOC_OR1K_GOTPC_LO16, R_OR1K_GOTPC_LO16 }, 2873+ { BFD_RELOC_OR1K_GOT16, R_OR1K_GOT16 }, 2874+ { BFD_RELOC_OR1K_PLT26, R_OR1K_PLT26 }, 2875+ { BFD_RELOC_OR1K_GOTOFF_HI16, R_OR1K_GOTOFF_HI16 }, 2876+ { BFD_RELOC_OR1K_GOTOFF_LO16, R_OR1K_GOTOFF_LO16 }, 2877+ { BFD_RELOC_OR1K_GLOB_DAT, R_OR1K_GLOB_DAT }, 2878+ { BFD_RELOC_OR1K_COPY, R_OR1K_COPY }, 2879+ { BFD_RELOC_OR1K_JMP_SLOT, R_OR1K_JMP_SLOT }, 2880+ { BFD_RELOC_OR1K_RELATIVE, R_OR1K_RELATIVE }, 2881+ { BFD_RELOC_OR1K_TLS_GD_HI16, R_OR1K_TLS_GD_HI16 }, 2882+ { BFD_RELOC_OR1K_TLS_GD_LO16, R_OR1K_TLS_GD_LO16 }, 2883+ { BFD_RELOC_OR1K_TLS_LDM_HI16, R_OR1K_TLS_LDM_HI16 }, 2884+ { BFD_RELOC_OR1K_TLS_LDM_LO16, R_OR1K_TLS_LDM_LO16 }, 2885+ { BFD_RELOC_OR1K_TLS_LDO_HI16, R_OR1K_TLS_LDO_HI16 }, 2886+ { BFD_RELOC_OR1K_TLS_LDO_LO16, R_OR1K_TLS_LDO_LO16 }, 2887+ { BFD_RELOC_OR1K_TLS_IE_HI16, R_OR1K_TLS_IE_HI16 }, 2888+ { BFD_RELOC_OR1K_TLS_IE_LO16, R_OR1K_TLS_IE_LO16 }, 2889+ { BFD_RELOC_OR1K_TLS_LE_HI16, R_OR1K_TLS_LE_HI16 }, 2890+ { BFD_RELOC_OR1K_TLS_LE_LO16, R_OR1K_TLS_LE_LO16 }, 2891+}; 2892+ 2893+/* The linker needs to keep track of the number of relocs that it 2894+ decides to copy as dynamic relocs in check_relocs for each symbol. 2895+ This is so that it can later discard them if they are found to be 2896+ unnecessary. We store the information in a field extending the 2897+ regular ELF linker hash table. */ 2898+ 2899+struct elf_or1k_dyn_relocs 2900+{ 2901+ struct elf_or1k_dyn_relocs *next; 2902+ 2903+ /* The input section of the reloc. */ 2904+ asection *sec; 2905+ 2906+ /* Total number of relocs copied for the input section. */ 2907+ bfd_size_type count; 2908+ 2909+ /* Number of pc-relative relocs copied for the input section. */ 2910+ bfd_size_type pc_count; 2911+}; 2912+ 2913+#define TLS_UNKNOWN 0 2914+#define TLS_NONE 1 2915+#define TLS_GD 2 2916+#define TLS_LD 3 2917+#define TLS_IE 4 2918+#define TLS_LE 5 2919+ 2920+/* ELF linker hash entry. */ 2921+struct elf_or1k_link_hash_entry 2922+{ 2923+ struct elf_link_hash_entry root; 2924+ 2925+ /* Track dynamic relocs copied for this symbol. */ 2926+ struct elf_or1k_dyn_relocs *dyn_relocs; 2927+ 2928+ /* Track type of TLS access. */ 2929+ unsigned char tls_type; 2930+}; 2931+ 2932+/* ELF object data. */ 2933+struct elf_or1k_obj_tdata 2934+{ 2935+ struct elf_obj_tdata root; 2936+ 2937+ /* tls_type for each local got entry. */ 2938+ unsigned char *local_tls_type; 2939+}; 2940+ 2941+#define elf_or1k_tdata(abfd) \ 2942+ ((struct elf_or1k_obj_tdata *) (abfd)->tdata.any) 2943+ 2944+#define elf_or1k_local_tls_type(abfd) \ 2945+ (elf_or1k_tdata (abfd)->local_tls_type) 2946+ 2947+/* ELF linker hash table. */ 2948+struct elf_or1k_link_hash_table 2949+{ 2950+ struct elf_link_hash_table root; 2951+ 2952+ /* Short-cuts to get to dynamic linker sections. */ 2953+ asection *sgot; 2954+ asection *sgotplt; 2955+ asection *srelgot; 2956+ asection *splt; 2957+ asection *srelplt; 2958+ asection *sdynbss; 2959+ asection *srelbss; 2960+ 2961+ /* Small local sym to section mapping cache. */ 2962+ struct sym_cache sym_sec; 2963+}; 2964+ 2965+/* Get the ELF linker hash table from a link_info structure. */ 2966+#define or1k_elf_hash_table(p) \ 2967+ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \ 2968+ == OR1K_ELF_DATA ? ((struct elf_or1k_link_hash_table *) ((p)->hash)) : NULL) 2969+ 2970+static bfd_boolean 2971+elf_or1k_mkobject (bfd *abfd) 2972+{ 2973+ return bfd_elf_allocate_object (abfd, sizeof (struct elf_or1k_obj_tdata), 2974+ OR1K_ELF_DATA); 2975+} 2976+ 2977+/* Create an entry in an or1k ELF linker hash table. */ 2978+ 2979+static struct bfd_hash_entry * 2980+or1k_elf_link_hash_newfunc (struct bfd_hash_entry *entry, 2981+ struct bfd_hash_table *table, 2982+ const char *string) 2983+{ 2984+ struct elf_or1k_link_hash_entry *ret = 2985+ (struct elf_or1k_link_hash_entry *) entry; 2986+ 2987+ /* Allocate the structure if it has not already been allocated by a 2988+ subclass. */ 2989+ if (ret == NULL) 2990+ ret = bfd_hash_allocate (table, 2991+ sizeof (struct elf_or1k_link_hash_entry)); 2992+ if (ret == NULL) 2993+ return NULL; 2994+ 2995+ /* Call the allocation method of the superclass. */ 2996+ ret = ((struct elf_or1k_link_hash_entry *) 2997+ _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret, 2998+ table, string)); 2999+ if (ret != NULL) 3000+ { 3001+ struct elf_or1k_link_hash_entry *eh; 3002+ 3003+ eh = (struct elf_or1k_link_hash_entry *) ret; 3004+ eh->dyn_relocs = NULL; 3005+ eh->tls_type = TLS_UNKNOWN; 3006+ } 3007+ 3008+ return (struct bfd_hash_entry *) ret; 3009+} 3010+ 3011+/* Create an or1k ELF linker hash table. */ 3012+ 3013+static struct bfd_link_hash_table * 3014+or1k_elf_link_hash_table_create (bfd *abfd) 3015+{ 3016+ struct elf_or1k_link_hash_table *ret; 3017+ bfd_size_type amt = sizeof (struct elf_or1k_link_hash_table); 3018+ 3019+ ret = bfd_zmalloc (amt); 3020+ if (ret == NULL) 3021+ return NULL; 3022+ 3023+ if (!_bfd_elf_link_hash_table_init (&ret->root, abfd, 3024+ or1k_elf_link_hash_newfunc, 3025+ sizeof (struct elf_or1k_link_hash_entry), 3026+ OR1K_ELF_DATA)) 3027+ { 3028+ free (ret); 3029+ return NULL; 3030+ } 3031+ 3032+ return &ret->root.root; 3033+} 3034+ 3035+static reloc_howto_type * 3036+or1k_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, 3037+ bfd_reloc_code_real_type code) 3038+{ 3039+ unsigned int i; 3040+ 3041+ for (i = ARRAY_SIZE (or1k_reloc_map); --i;) 3042+ if (or1k_reloc_map[i].bfd_reloc_val == code) 3043+ return & or1k_elf_howto_table[or1k_reloc_map[i].or1k_reloc_val]; 3044+ 3045+ return NULL; 3046+} 3047+ 3048+static reloc_howto_type * 3049+or1k_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 3050+ const char *r_name) 3051+{ 3052+ unsigned int i; 3053+ 3054+ for (i = 0; 3055+ i < (sizeof (or1k_elf_howto_table) 3056+ / sizeof (or1k_elf_howto_table[0])); 3057+ i++) 3058+ if (or1k_elf_howto_table[i].name != NULL 3059+ && strcasecmp (or1k_elf_howto_table[i].name, r_name) == 0) 3060+ return &or1k_elf_howto_table[i]; 3061+ 3062+ return NULL; 3063+} 3064+ 3065+/* Set the howto pointer for an Or1k ELF reloc. */ 3066+ 3067+static void 3068+or1k_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, 3069+ arelent * cache_ptr, 3070+ Elf_Internal_Rela * dst) 3071+{ 3072+ unsigned int r_type; 3073+ 3074+ r_type = ELF32_R_TYPE (dst->r_info); 3075+ BFD_ASSERT (r_type < (unsigned int) R_OR1K_max); 3076+ cache_ptr->howto = & or1k_elf_howto_table[r_type]; 3077+} 3078+ 3079+ 3080+/* Return the relocation value for @tpoff relocations.. */ 3081+static bfd_vma 3082+tpoff (struct bfd_link_info *info, bfd_vma address) 3083+{ 3084+ /* If tls_sec is NULL, we should have signalled an error already. */ 3085+ if (elf_hash_table (info)->tls_sec == NULL) 3086+ return 0; 3087+ 3088+ /* The thread pointer on or1k stores the address after the TCB where 3089+ the data is, just compute the difference. No need to compensate 3090+ for the size of TCB. */ 3091+ return (address - elf_hash_table (info)->tls_sec->vma); 3092+} 3093+ 3094+/* Relocate an Or1k ELF section. 3095+ 3096+ The RELOCATE_SECTION function is called by the new ELF backend linker 3097+ to handle the relocations for a section. 3098+ 3099+ The relocs are always passed as Rela structures; if the section 3100+ actually uses Rel structures, the r_addend field will always be 3101+ zero. 3102+ 3103+ This function is responsible for adjusting the section contents as 3104+ necessary, and (if using Rela relocs and generating a relocatable 3105+ output file) adjusting the reloc addend as necessary. 3106+ 3107+ This function does not have to worry about setting the reloc 3108+ address or the reloc symbol index. 3109+ 3110+ LOCAL_SYMS is a pointer to the swapped in local symbols. 3111+ 3112+ LOCAL_SECTIONS is an array giving the section in the input file 3113+ corresponding to the st_shndx field of each local symbol. 3114+ 3115+ The global hash table entry for the global symbols can be found 3116+ via elf_sym_hashes (input_bfd). 3117+ 3118+ When generating relocatable output, this function must handle 3119+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is 3120+ going to be the section symbol corresponding to the output 3121+ section, which means that the addend must be adjusted 3122+ accordingly. */ 3123+ 3124+static bfd_boolean 3125+or1k_elf_relocate_section (bfd *output_bfd, 3126+ struct bfd_link_info *info, 3127+ bfd *input_bfd, 3128+ asection *input_section, 3129+ bfd_byte *contents, 3130+ Elf_Internal_Rela *relocs, 3131+ Elf_Internal_Sym *local_syms, 3132+ asection **local_sections) 3133+{ 3134+ Elf_Internal_Shdr *symtab_hdr; 3135+ struct elf_link_hash_entry **sym_hashes; 3136+ Elf_Internal_Rela *rel; 3137+ Elf_Internal_Rela *relend; 3138+ struct elf_or1k_link_hash_table *htab = or1k_elf_hash_table (info); 3139+ bfd *dynobj; 3140+ asection *sreloc; 3141+ bfd_vma *local_got_offsets; 3142+ asection *sgot; 3143+ 3144+ if (htab == NULL) 3145+ return FALSE; 3146+ 3147+ dynobj = htab->root.dynobj; 3148+ local_got_offsets = elf_local_got_offsets (input_bfd); 3149+ 3150+ sreloc = elf_section_data (input_section)->sreloc; 3151+ 3152+ sgot = htab->sgot; 3153+ 3154+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; 3155+ sym_hashes = elf_sym_hashes (input_bfd); 3156+ relend = relocs + input_section->reloc_count; 3157+ 3158+ for (rel = relocs; rel < relend; rel++) 3159+ { 3160+ reloc_howto_type *howto; 3161+ unsigned long r_symndx; 3162+ Elf_Internal_Sym *sym; 3163+ asection *sec; 3164+ struct elf_link_hash_entry *h; 3165+ bfd_vma relocation; 3166+ bfd_reloc_status_type r; 3167+ const char *name = NULL; 3168+ int r_type; 3169+ 3170+ r_type = ELF32_R_TYPE (rel->r_info); 3171+ r_symndx = ELF32_R_SYM (rel->r_info); 3172+ 3173+ if (r_type == R_OR1K_GNU_VTINHERIT 3174+ || r_type == R_OR1K_GNU_VTENTRY) 3175+ continue; 3176+ 3177+ if (r_type < 0 || r_type >= (int) R_OR1K_max) 3178+ { 3179+ bfd_set_error (bfd_error_bad_value); 3180+ return FALSE; 3181+ } 3182+ 3183+ howto = or1k_elf_howto_table + ELF32_R_TYPE (rel->r_info); 3184+ h = NULL; 3185+ sym = NULL; 3186+ sec = NULL; 3187+ 3188+ if (r_symndx < symtab_hdr->sh_info) 3189+ { 3190+ sym = local_syms + r_symndx; 3191+ sec = local_sections[r_symndx]; 3192+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); 3193+ 3194+ name = bfd_elf_string_from_elf_section 3195+ (input_bfd, symtab_hdr->sh_link, sym->st_name); 3196+ name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; 3197+ } 3198+ else 3199+ { 3200+ bfd_boolean unresolved_reloc, warned; 3201+ 3202+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, 3203+ r_symndx, symtab_hdr, sym_hashes, 3204+ h, sec, relocation, 3205+ unresolved_reloc, warned); 3206+ } 3207+ 3208+ if (sec != NULL && discarded_section (sec)) 3209+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, 3210+ rel, 1, relend, howto, 0, contents); 3211+ 3212+ if (info->relocatable) 3213+ continue; 3214+ 3215+ switch (howto->type) 3216+ { 3217+ case R_OR1K_PLT26: 3218+ { 3219+ if (htab->splt != NULL && h != NULL 3220+ && h->plt.offset != (bfd_vma) -1) 3221+ { 3222+ relocation = (htab->splt->output_section->vma 3223+ + htab->splt->output_offset 3224+ + h->plt.offset); 3225+ } 3226+ break; 3227+ } 3228+ 3229+ case R_OR1K_GOT16: 3230+ /* Relocation is to the entry for this symbol in the global 3231+ offset table. */ 3232+ BFD_ASSERT (sgot != NULL); 3233+ if (h != NULL) 3234+ { 3235+ bfd_boolean dyn; 3236+ bfd_vma off; 3237+ 3238+ off = h->got.offset; 3239+ BFD_ASSERT (off != (bfd_vma) -1); 3240+ 3241+ dyn = htab->root.dynamic_sections_created; 3242+ if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h) 3243+ || (info->shared 3244+ && SYMBOL_REFERENCES_LOCAL (info, h))) 3245+ { 3246+ /* This is actually a static link, or it is a 3247+ -Bsymbolic link and the symbol is defined 3248+ locally, or the symbol was forced to be local 3249+ because of a version file. We must initialize 3250+ this entry in the global offset table. Since the 3251+ offset must always be a multiple of 4, we use the 3252+ least significant bit to record whether we have 3253+ initialized it already. 3254+ 3255+ When doing a dynamic link, we create a .rela.got 3256+ relocation entry to initialize the value. This 3257+ is done in the finish_dynamic_symbol routine. */ 3258+ if ((off & 1) != 0) 3259+ off &= ~1; 3260+ else 3261+ { 3262+ /* Write entry in GOT. */ 3263+ bfd_put_32 (output_bfd, relocation, 3264+ sgot->contents + off); 3265+ /* Mark GOT entry as having been written. */ 3266+ h->got.offset |= 1; 3267+ } 3268+ } 3269+ 3270+ relocation = sgot->output_offset + off; 3271+ } 3272+ else 3273+ { 3274+ bfd_vma off; 3275+ bfd_byte *loc; 3276+ 3277+ BFD_ASSERT (local_got_offsets != NULL 3278+ && local_got_offsets[r_symndx] != (bfd_vma) -1); 3279+ 3280+ /* Get offset into GOT table. */ 3281+ off = local_got_offsets[r_symndx]; 3282+ 3283+ /* The offset must always be a multiple of 4. We use 3284+ the least significant bit to record whether we have 3285+ already processed this entry. */ 3286+ if ((off & 1) != 0) 3287+ off &= ~1; 3288+ else 3289+ { 3290+ /* Write entry in GOT. */ 3291+ bfd_put_32 (output_bfd, relocation, sgot->contents + off); 3292+ if (info->shared) 3293+ { 3294+ asection *srelgot; 3295+ Elf_Internal_Rela outrel; 3296+ 3297+ /* We need to generate a R_OR1K_RELATIVE reloc 3298+ for the dynamic linker. */ 3299+ srelgot = bfd_get_section_by_name (dynobj, ".rela.got"); 3300+ BFD_ASSERT (srelgot != NULL); 3301+ 3302+ outrel.r_offset = (sgot->output_section->vma 3303+ + sgot->output_offset 3304+ + off); 3305+ outrel.r_info = ELF32_R_INFO (0, R_OR1K_RELATIVE); 3306+ outrel.r_addend = relocation; 3307+ loc = srelgot->contents; 3308+ loc += srelgot->reloc_count * sizeof (Elf32_External_Rela); 3309+ bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc); 3310+ ++srelgot->reloc_count; 3311+ } 3312+ 3313+ local_got_offsets[r_symndx] |= 1; 3314+ } 3315+ relocation = sgot->output_offset + off; 3316+ } 3317+ 3318+ /* Addend should be zero. */ 3319+ if (rel->r_addend != 0) 3320+ (*_bfd_error_handler) 3321+ (_("internal error: addend should be zero for R_OR1K_GOT16")); 3322+ 3323+ break; 3324+ 3325+ case R_OR1K_GOTOFF_LO16: 3326+ case R_OR1K_GOTOFF_HI16: 3327+ /* Relocation is offset from GOT. */ 3328+ BFD_ASSERT (sgot != NULL); 3329+ relocation -= sgot->output_section->vma; 3330+ break; 3331+ 3332+ case R_OR1K_INSN_REL_26: 3333+ case R_OR1K_HI_16_IN_INSN: 3334+ case R_OR1K_LO_16_IN_INSN: 3335+ case R_OR1K_32: 3336+ /* R_OR1K_16? */ 3337+ { 3338+ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols 3339+ from removed linkonce sections, or sections discarded by 3340+ a linker script. */ 3341+ if (r_symndx == STN_UNDEF 3342+ || (input_section->flags & SEC_ALLOC) == 0) 3343+ break; 3344+ 3345+ if ((info->shared 3346+ && (h == NULL 3347+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 3348+ || h->root.type != bfd_link_hash_undefweak) 3349+ && (howto->type != R_OR1K_INSN_REL_26 3350+ || !SYMBOL_CALLS_LOCAL (info, h))) 3351+ || (!info->shared 3352+ && h != NULL 3353+ && h->dynindx != -1 3354+ && !h->non_got_ref 3355+ && ((h->def_dynamic 3356+ && !h->def_regular) 3357+ || h->root.type == bfd_link_hash_undefweak 3358+ || h->root.type == bfd_link_hash_undefined))) 3359+ { 3360+ Elf_Internal_Rela outrel; 3361+ bfd_byte *loc; 3362+ bfd_boolean skip; 3363+ 3364+ /* When generating a shared object, these relocations 3365+ are copied into the output file to be resolved at run 3366+ time. */ 3367+ 3368+ BFD_ASSERT (sreloc != NULL); 3369+ 3370+ skip = FALSE; 3371+ 3372+ outrel.r_offset = 3373+ _bfd_elf_section_offset (output_bfd, info, input_section, 3374+ rel->r_offset); 3375+ if (outrel.r_offset == (bfd_vma) -1) 3376+ skip = TRUE; 3377+ else if (outrel.r_offset == (bfd_vma) -2) 3378+ skip = TRUE; 3379+ outrel.r_offset += (input_section->output_section->vma 3380+ + input_section->output_offset); 3381+ 3382+ if (skip) 3383+ memset (&outrel, 0, sizeof outrel); 3384+ /* h->dynindx may be -1 if the symbol was marked to 3385+ become local. */ 3386+ else if (h != NULL 3387+ && ((! info->symbolic && h->dynindx != -1) 3388+ || !h->def_regular)) 3389+ { 3390+ BFD_ASSERT (h->dynindx != -1); 3391+ outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); 3392+ outrel.r_addend = rel->r_addend; 3393+ } 3394+ else 3395+ { 3396+ if (r_type == R_OR1K_32) 3397+ { 3398+ outrel.r_info = ELF32_R_INFO (0, R_OR1K_RELATIVE); 3399+ outrel.r_addend = relocation + rel->r_addend; 3400+ } 3401+ else 3402+ { 3403+ BFD_FAIL (); 3404+ (*_bfd_error_handler) 3405+ (_("%B: probably compiled without -fPIC?"), 3406+ input_bfd); 3407+ bfd_set_error (bfd_error_bad_value); 3408+ return FALSE; 3409+ } 3410+ } 3411+ 3412+ loc = sreloc->contents; 3413+ loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela); 3414+ bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); 3415+ break; 3416+ } 3417+ break; 3418+ } 3419+ 3420+ case R_OR1K_TLS_LDM_HI16: 3421+ case R_OR1K_TLS_LDM_LO16: 3422+ case R_OR1K_TLS_LDO_HI16: 3423+ case R_OR1K_TLS_LDO_LO16: 3424+ /* TODO: implement support for local dynamic. */ 3425+ BFD_FAIL (); 3426+ (*_bfd_error_handler) 3427+ (_("%B: support for local dynamic not implemented"), 3428+ input_bfd); 3429+ bfd_set_error (bfd_error_bad_value); 3430+ return FALSE; 3431+ 3432+ 3433+ case R_OR1K_TLS_GD_HI16: 3434+ case R_OR1K_TLS_GD_LO16: 3435+ case R_OR1K_TLS_IE_HI16: 3436+ case R_OR1K_TLS_IE_LO16: 3437+ { 3438+ bfd_vma gotoff; 3439+ Elf_Internal_Rela rela; 3440+ bfd_byte *loc; 3441+ int dynamic; 3442+ 3443+ sreloc = bfd_get_section_by_name (dynobj, ".rela.got"); 3444+ 3445+ /* Mark as TLS related GOT entry by setting 3446+ bit 2 as well as bit 1. */ 3447+ if (h != NULL) 3448+ { 3449+ gotoff = h->got.offset; 3450+ h->got.offset |= 3; 3451+ } 3452+ else 3453+ { 3454+ gotoff = local_got_offsets[r_symndx]; 3455+ local_got_offsets[r_symndx] |= 3; 3456+ } 3457+ 3458+ /* Only process the relocation once. */ 3459+ if (gotoff & 1) 3460+ { 3461+ relocation = sgot->output_offset + (gotoff & ~3); 3462+ break; 3463+ } 3464+ 3465+ BFD_ASSERT (elf_hash_table (info)->hgot == NULL 3466+ || elf_hash_table (info)->hgot->root.u.def.value == 0); 3467+ 3468+ /* Dynamic entries will require relocations. if we do not need 3469+ them we will just use the default R_OR1K_NONE and 3470+ not set anything. */ 3471+ dynamic = info->shared 3472+ || (sec && (sec->flags & SEC_ALLOC) != 0 3473+ && h != NULL 3474+ && (h->root.type == bfd_link_hash_defweak || !h->def_regular)); 3475+ 3476+ /* Shared GD. */ 3477+ if (dynamic && (howto->type == R_OR1K_TLS_GD_HI16 3478+ || howto->type == R_OR1K_TLS_GD_LO16)) 3479+ { 3480+ int i; 3481+ 3482+ /* Add DTPMOD and DTPOFF GOT and rela entries. */ 3483+ for (i = 0; i < 2; ++i) 3484+ { 3485+ rela.r_offset = sgot->output_section->vma + 3486+ sgot->output_offset + gotoff + i*4; 3487+ if (h != NULL && h->dynindx != -1) 3488+ { 3489+ rela.r_info = ELF32_R_INFO (h->dynindx, 3490+ (i == 0 ? R_OR1K_TLS_DTPMOD : R_OR1K_TLS_DTPOFF)); 3491+ rela.r_addend = 0; 3492+ } 3493+ else 3494+ { 3495+ rela.r_info = ELF32_R_INFO (0, 3496+ (i == 0 ? R_OR1K_TLS_DTPMOD : R_OR1K_TLS_DTPOFF)); 3497+ rela.r_addend = tpoff (info, relocation); 3498+ } 3499+ 3500+ loc = sreloc->contents; 3501+ loc += sreloc->reloc_count++ * 3502+ sizeof (Elf32_External_Rela); 3503+ 3504+ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); 3505+ bfd_put_32 (output_bfd, 0, sgot->contents + gotoff + i*4); 3506+ } 3507+ } 3508+ /* Static GD. */ 3509+ else if (howto->type == R_OR1K_TLS_GD_HI16 3510+ || howto->type == R_OR1K_TLS_GD_LO16) 3511+ { 3512+ bfd_put_32 (output_bfd, 1, sgot->contents + gotoff); 3513+ bfd_put_32 (output_bfd, tpoff (info, relocation), 3514+ sgot->contents + gotoff + 4); 3515+ } 3516+ /* Shared IE. */ 3517+ else if (dynamic) 3518+ { 3519+ /* Add TPOFF GOT and rela entries. */ 3520+ rela.r_offset = sgot->output_section->vma + 3521+ sgot->output_offset + gotoff; 3522+ if (h != NULL && h->dynindx != -1) 3523+ { 3524+ rela.r_info = ELF32_R_INFO (h->dynindx, R_OR1K_TLS_TPOFF); 3525+ rela.r_addend = 0; 3526+ } 3527+ else 3528+ { 3529+ rela.r_info = ELF32_R_INFO (0, R_OR1K_TLS_TPOFF); 3530+ rela.r_addend = tpoff (info, relocation); 3531+ } 3532+ 3533+ loc = sreloc->contents; 3534+ loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela); 3535+ 3536+ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); 3537+ bfd_put_32 (output_bfd, 0, sgot->contents + gotoff); 3538+ } 3539+ /* Static IE. */ 3540+ else 3541+ { 3542+ bfd_put_32 (output_bfd, tpoff (info, relocation), 3543+ sgot->contents + gotoff); 3544+ } 3545+ relocation = sgot->output_offset + gotoff; 3546+ break; 3547+ } 3548+ case R_OR1K_TLS_LE_HI16: 3549+ case R_OR1K_TLS_LE_LO16: 3550+ 3551+ /* Relocation is offset from TP. */ 3552+ relocation = tpoff (info, relocation); 3553+ break; 3554+ 3555+ case R_OR1K_TLS_DTPMOD: 3556+ case R_OR1K_TLS_DTPOFF: 3557+ case R_OR1K_TLS_TPOFF: 3558+ /* These are resolved dynamically on load and shouldn't 3559+ be used as linker input. */ 3560+ BFD_FAIL (); 3561+ (*_bfd_error_handler) 3562+ (_("%B: will not resolve runtime TLS relocation"), 3563+ input_bfd); 3564+ bfd_set_error (bfd_error_bad_value); 3565+ return FALSE; 3566+ 3567+ default: 3568+ break; 3569+ } 3570+ r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents, 3571+ rel->r_offset, relocation, rel->r_addend); 3572+ 3573+ if (r != bfd_reloc_ok) 3574+ { 3575+ const char *msg = NULL; 3576+ 3577+ switch (r) 3578+ { 3579+ case bfd_reloc_overflow: 3580+ r = info->callbacks->reloc_overflow 3581+ (info, (h ? &h->root : NULL), name, howto->name, 3582+ (bfd_vma) 0, input_bfd, input_section, rel->r_offset); 3583+ break; 3584+ 3585+ case bfd_reloc_undefined: 3586+ r = info->callbacks->undefined_symbol 3587+ (info, name, input_bfd, input_section, rel->r_offset, TRUE); 3588+ break; 3589+ 3590+ case bfd_reloc_outofrange: 3591+ msg = _("internal error: out of range error"); 3592+ break; 3593+ 3594+ case bfd_reloc_notsupported: 3595+ msg = _("internal error: unsupported relocation error"); 3596+ break; 3597+ 3598+ case bfd_reloc_dangerous: 3599+ msg = _("internal error: dangerous relocation"); 3600+ break; 3601+ 3602+ default: 3603+ msg = _("internal error: unknown error"); 3604+ break; 3605+ } 3606+ 3607+ if (msg) 3608+ r = info->callbacks->warning 3609+ (info, msg, name, input_bfd, input_section, rel->r_offset); 3610+ 3611+ if (!r) 3612+ return FALSE; 3613+ } 3614+ } 3615+ 3616+ return TRUE; 3617+} 3618+ 3619+/* Return the section that should be marked against GC for a given 3620+ relocation. */ 3621+ 3622+static asection * 3623+or1k_elf_gc_mark_hook (asection *sec, 3624+ struct bfd_link_info *info, 3625+ Elf_Internal_Rela *rel, 3626+ struct elf_link_hash_entry *h, 3627+ Elf_Internal_Sym *sym) 3628+{ 3629+ if (h != NULL) 3630+ switch (ELF32_R_TYPE (rel->r_info)) 3631+ { 3632+ case R_OR1K_GNU_VTINHERIT: 3633+ case R_OR1K_GNU_VTENTRY: 3634+ return NULL; 3635+ } 3636+ 3637+ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); 3638+} 3639+ 3640+static bfd_boolean 3641+or1k_elf_gc_sweep_hook (bfd *abfd, 3642+ struct bfd_link_info *info ATTRIBUTE_UNUSED, 3643+ asection *sec, 3644+ const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) 3645+{ 3646+ /* Update the got entry reference counts for the section being removed. */ 3647+ Elf_Internal_Shdr *symtab_hdr; 3648+ struct elf_link_hash_entry **sym_hashes; 3649+ bfd_signed_vma *local_got_refcounts; 3650+ const Elf_Internal_Rela *rel, *relend; 3651+ 3652+ elf_section_data (sec)->local_dynrel = NULL; 3653+ 3654+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 3655+ sym_hashes = elf_sym_hashes (abfd); 3656+ local_got_refcounts = elf_local_got_refcounts (abfd); 3657+ 3658+ relend = relocs + sec->reloc_count; 3659+ for (rel = relocs; rel < relend; rel++) 3660+ { 3661+ unsigned long r_symndx; 3662+ struct elf_link_hash_entry *h = NULL; 3663+ 3664+ r_symndx = ELF32_R_SYM (rel->r_info); 3665+ if (r_symndx >= symtab_hdr->sh_info) 3666+ { 3667+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; 3668+ while (h->root.type == bfd_link_hash_indirect 3669+ || h->root.type == bfd_link_hash_warning) 3670+ h = (struct elf_link_hash_entry *) h->root.u.i.link; 3671+ } 3672+ 3673+ switch (ELF32_R_TYPE (rel->r_info)) 3674+ { 3675+ case R_OR1K_GOT16: 3676+ if (h != NULL) 3677+ { 3678+ if (h->got.refcount > 0) 3679+ h->got.refcount--; 3680+ } 3681+ else 3682+ { 3683+ if (local_got_refcounts && local_got_refcounts[r_symndx] > 0) 3684+ local_got_refcounts[r_symndx]--; 3685+ } 3686+ break; 3687+ 3688+ default: 3689+ break; 3690+ } 3691+ } 3692+ return TRUE; 3693+} 3694+ 3695+/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up 3696+ shortcuts to them in our hash table. */ 3697+ 3698+static bfd_boolean 3699+create_got_section (bfd *dynobj, struct bfd_link_info *info) 3700+{ 3701+ struct elf_or1k_link_hash_table *htab; 3702+ asection *s; 3703+ 3704+ /* This function may be called more than once. */ 3705+ s = bfd_get_section_by_name (dynobj, ".got"); 3706+ if (s != NULL && (s->flags & SEC_LINKER_CREATED) != 0) 3707+ return TRUE; 3708+ 3709+ htab = or1k_elf_hash_table (info); 3710+ if (htab == NULL) 3711+ return FALSE; 3712+ 3713+ if (! _bfd_elf_create_got_section (dynobj, info)) 3714+ return FALSE; 3715+ 3716+ htab->sgot = bfd_get_section_by_name (dynobj, ".got"); 3717+ htab->sgotplt = bfd_get_section_by_name (dynobj, ".got.plt"); 3718+ htab->srelgot = bfd_get_section_by_name (dynobj, ".rela.got"); 3719+ 3720+ if (! htab->sgot || ! htab->sgotplt || ! htab->srelgot) 3721+ abort (); 3722+ 3723+ if (! bfd_set_section_flags (dynobj, htab->srelgot, SEC_ALLOC 3724+ | SEC_LOAD 3725+ | SEC_HAS_CONTENTS 3726+ | SEC_IN_MEMORY 3727+ | SEC_LINKER_CREATED 3728+ | SEC_READONLY) 3729+ || ! bfd_set_section_alignment (dynobj, htab->srelgot, 2)) 3730+ return FALSE; 3731+ 3732+ return TRUE; 3733+} 3734+ 3735+/* Look through the relocs for a section during the first phase. */ 3736+ 3737+static bfd_boolean 3738+or1k_elf_check_relocs (bfd *abfd, 3739+ struct bfd_link_info *info, 3740+ asection *sec, 3741+ const Elf_Internal_Rela *relocs) 3742+{ 3743+ Elf_Internal_Shdr *symtab_hdr; 3744+ struct elf_link_hash_entry **sym_hashes; 3745+ const Elf_Internal_Rela *rel; 3746+ 3747+ const Elf_Internal_Rela *rel_end; 3748+ struct elf_or1k_link_hash_table *htab; 3749+ bfd *dynobj; 3750+ asection *sreloc = NULL; 3751+ 3752+ if (info->relocatable) 3753+ return TRUE; 3754+ 3755+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 3756+ sym_hashes = elf_sym_hashes (abfd); 3757+ 3758+ htab = or1k_elf_hash_table (info); 3759+ if (htab == NULL) 3760+ return FALSE; 3761+ 3762+ dynobj = htab->root.dynobj; 3763+ 3764+ rel_end = relocs + sec->reloc_count; 3765+ for (rel = relocs; rel < rel_end; rel++) 3766+ { 3767+ struct elf_link_hash_entry *h; 3768+ unsigned long r_symndx; 3769+ unsigned char tls_type; 3770+ 3771+ r_symndx = ELF32_R_SYM (rel->r_info); 3772+ if (r_symndx < symtab_hdr->sh_info) 3773+ h = NULL; 3774+ else 3775+ { 3776+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; 3777+ while (h->root.type == bfd_link_hash_indirect 3778+ || h->root.type == bfd_link_hash_warning) 3779+ h = (struct elf_link_hash_entry *) h->root.u.i.link; 3780+ 3781+ /* PR15323, ref flags aren't set for references in the same 3782+ object. */ 3783+ h->root.non_ir_ref = 1; 3784+ } 3785+ 3786+ switch (ELF32_R_TYPE (rel->r_info)) 3787+ { 3788+ case R_OR1K_TLS_GD_HI16: 3789+ case R_OR1K_TLS_GD_LO16: 3790+ tls_type = TLS_GD; 3791+ break; 3792+ case R_OR1K_TLS_LDM_HI16: 3793+ case R_OR1K_TLS_LDM_LO16: 3794+ case R_OR1K_TLS_LDO_HI16: 3795+ case R_OR1K_TLS_LDO_LO16: 3796+ tls_type = TLS_LD; 3797+ break; 3798+ case R_OR1K_TLS_IE_HI16: 3799+ case R_OR1K_TLS_IE_LO16: 3800+ tls_type = TLS_IE; 3801+ break; 3802+ case R_OR1K_TLS_LE_HI16: 3803+ case R_OR1K_TLS_LE_LO16: 3804+ tls_type = TLS_LE; 3805+ break; 3806+ default: 3807+ tls_type = TLS_NONE; 3808+ } 3809+ 3810+ /* Record TLS type. */ 3811+ if (h != NULL) 3812+ ((struct elf_or1k_link_hash_entry *) h)->tls_type = tls_type; 3813+ else 3814+ { 3815+ unsigned char *local_tls_type; 3816+ 3817+ /* This is a TLS type record for a local symbol. */ 3818+ local_tls_type = (unsigned char *) elf_or1k_local_tls_type (abfd); 3819+ if (local_tls_type == NULL) 3820+ { 3821+ bfd_size_type size; 3822+ 3823+ size = symtab_hdr->sh_info; 3824+ local_tls_type = bfd_zalloc (abfd, size); 3825+ if (local_tls_type == NULL) 3826+ return FALSE; 3827+ elf_or1k_local_tls_type (abfd) = local_tls_type; 3828+ } 3829+ local_tls_type[r_symndx] = tls_type; 3830+ } 3831+ 3832+ switch (ELF32_R_TYPE (rel->r_info)) 3833+ { 3834+ /* This relocation describes the C++ object vtable hierarchy. 3835+ Reconstruct it for later use during GC. */ 3836+ case R_OR1K_GNU_VTINHERIT: 3837+ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) 3838+ return FALSE; 3839+ break; 3840+ 3841+ /* This relocation describes which C++ vtable entries are actually 3842+ used. Record for later use during GC. */ 3843+ case R_OR1K_GNU_VTENTRY: 3844+ BFD_ASSERT (h != NULL); 3845+ if (h != NULL 3846+ && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) 3847+ return FALSE; 3848+ break; 3849+ 3850+ /* This relocation requires .plt entry. */ 3851+ case R_OR1K_PLT26: 3852+ if (h != NULL) 3853+ { 3854+ h->needs_plt = 1; 3855+ h->plt.refcount += 1; 3856+ } 3857+ break; 3858+ 3859+ case R_OR1K_GOT16: 3860+ case R_OR1K_GOTOFF_HI16: 3861+ case R_OR1K_GOTOFF_LO16: 3862+ case R_OR1K_TLS_GD_HI16: 3863+ case R_OR1K_TLS_GD_LO16: 3864+ case R_OR1K_TLS_IE_HI16: 3865+ case R_OR1K_TLS_IE_LO16: 3866+ if (htab->sgot == NULL) 3867+ { 3868+ if (dynobj == NULL) 3869+ htab->root.dynobj = dynobj = abfd; 3870+ if (! create_got_section (dynobj, info)) 3871+ return FALSE; 3872+ } 3873+ 3874+ if (ELF32_R_TYPE (rel->r_info) != R_OR1K_GOTOFF_HI16 && 3875+ ELF32_R_TYPE (rel->r_info) != R_OR1K_GOTOFF_LO16) 3876+ { 3877+ if (h != NULL) 3878+ h->got.refcount += 1; 3879+ else 3880+ { 3881+ bfd_signed_vma *local_got_refcounts; 3882+ 3883+ /* This is a global offset table entry for a local symbol. */ 3884+ local_got_refcounts = elf_local_got_refcounts (abfd); 3885+ if (local_got_refcounts == NULL) 3886+ { 3887+ bfd_size_type size; 3888+ 3889+ size = symtab_hdr->sh_info; 3890+ size *= sizeof (bfd_signed_vma); 3891+ local_got_refcounts = bfd_zalloc (abfd, size); 3892+ if (local_got_refcounts == NULL) 3893+ return FALSE; 3894+ elf_local_got_refcounts (abfd) = local_got_refcounts; 3895+ } 3896+ local_got_refcounts[r_symndx] += 1; 3897+ } 3898+ } 3899+ break; 3900+ 3901+ case R_OR1K_INSN_REL_26: 3902+ case R_OR1K_HI_16_IN_INSN: 3903+ case R_OR1K_LO_16_IN_INSN: 3904+ case R_OR1K_32: 3905+ /* R_OR1K_16? */ 3906+ { 3907+ if (h != NULL && !info->shared) 3908+ { 3909+ /* We may need a copy reloc. */ 3910+ h->non_got_ref = 1; 3911+ 3912+ /* We may also need a .plt entry. */ 3913+ h->plt.refcount += 1; 3914+ if (ELF32_R_TYPE (rel->r_info) != R_OR1K_INSN_REL_26) 3915+ h->pointer_equality_needed = 1; 3916+ } 3917+ 3918+ /* If we are creating a shared library, and this is a reloc 3919+ against a global symbol, or a non PC relative reloc 3920+ against a local symbol, then we need to copy the reloc 3921+ into the shared library. However, if we are linking with 3922+ -Bsymbolic, we do not need to copy a reloc against a 3923+ global symbol which is defined in an object we are 3924+ including in the link (i.e., DEF_REGULAR is set). At 3925+ this point we have not seen all the input files, so it is 3926+ possible that DEF_REGULAR is not set now but will be set 3927+ later (it is never cleared). In case of a weak definition, 3928+ DEF_REGULAR may be cleared later by a strong definition in 3929+ a shared library. We account for that possibility below by 3930+ storing information in the relocs_copied field of the hash 3931+ table entry. A similar situation occurs when creating 3932+ shared libraries and symbol visibility changes render the 3933+ symbol local. 3934+ 3935+ If on the other hand, we are creating an executable, we 3936+ may need to keep relocations for symbols satisfied by a 3937+ dynamic library if we manage to avoid copy relocs for the 3938+ symbol. */ 3939+ 3940+ if ((info->shared 3941+ && (sec->flags & SEC_ALLOC) != 0 3942+ && (ELF32_R_TYPE (rel->r_info) != R_OR1K_INSN_REL_26 3943+ || (h != NULL 3944+ && (!SYMBOLIC_BIND (info, h) 3945+ || h->root.type == bfd_link_hash_defweak 3946+ || !h->def_regular)))) 3947+ || (!info->shared 3948+ && (sec->flags & SEC_ALLOC) != 0 3949+ && h != NULL 3950+ && (h->root.type == bfd_link_hash_defweak 3951+ || !h->def_regular))) 3952+ { 3953+ struct elf_or1k_dyn_relocs *p; 3954+ struct elf_or1k_dyn_relocs **head; 3955+ 3956+ /* When creating a shared object, we must copy these 3957+ relocs into the output file. We create a reloc 3958+ section in dynobj and make room for the reloc. */ 3959+ if (sreloc == NULL) 3960+ { 3961+ const char *name; 3962+ unsigned int strndx = elf_elfheader (abfd)->e_shstrndx; 3963+ unsigned int shnam = _bfd_elf_single_rel_hdr (sec)->sh_name; 3964+ 3965+ name = bfd_elf_string_from_elf_section (abfd, strndx, shnam); 3966+ if (name == NULL) 3967+ return FALSE; 3968+ 3969+ if (strncmp (name, ".rela", 5) != 0 3970+ || strcmp (bfd_get_section_name (abfd, sec), 3971+ name + 5) != 0) 3972+ { 3973+ (*_bfd_error_handler) 3974+ (_("%B: bad relocation section name `%s\'"), 3975+ abfd, name); 3976+ } 3977+ 3978+ if (htab->root.dynobj == NULL) 3979+ htab->root.dynobj = abfd; 3980+ dynobj = htab->root.dynobj; 3981+ 3982+ sreloc = bfd_get_section_by_name (dynobj, name); 3983+ if (sreloc == NULL) 3984+ { 3985+ sreloc = _bfd_elf_make_dynamic_reloc_section 3986+ (sec, dynobj, 2, abfd, /*rela?*/ TRUE); 3987+ 3988+ if (sreloc == NULL) 3989+ return FALSE; 3990+ } 3991+ elf_section_data (sec)->sreloc = sreloc; 3992+ } 3993+ 3994+ /* If this is a global symbol, we count the number of 3995+ relocations we need for this symbol. */ 3996+ if (h != NULL) 3997+ head = &((struct elf_or1k_link_hash_entry *) h)->dyn_relocs; 3998+ else 3999+ { 4000+ /* Track dynamic relocs needed for local syms too. 4001+ We really need local syms available to do this 4002+ easily. Oh well. */ 4003+ 4004+ asection *s; 4005+ Elf_Internal_Sym *isym; 4006+ void *vpp; 4007+ 4008+ isym = bfd_sym_from_r_symndx (&htab->sym_sec, 4009+ abfd, r_symndx); 4010+ if (isym == NULL) 4011+ return FALSE; 4012+ 4013+ s = bfd_section_from_elf_index (abfd, isym->st_shndx); 4014+ if (s == NULL) 4015+ return FALSE; 4016+ 4017+ vpp = &elf_section_data (s)->local_dynrel; 4018+ head = (struct elf_or1k_dyn_relocs **) vpp; 4019+ } 4020+ 4021+ p = *head; 4022+ if (p == NULL || p->sec != sec) 4023+ { 4024+ bfd_size_type amt = sizeof *p; 4025+ p = ((struct elf_or1k_dyn_relocs *) 4026+ bfd_alloc (htab->root.dynobj, amt)); 4027+ if (p == NULL) 4028+ return FALSE; 4029+ p->next = *head; 4030+ *head = p; 4031+ p->sec = sec; 4032+ p->count = 0; 4033+ p->pc_count = 0; 4034+ } 4035+ 4036+ p->count += 1; 4037+ if (ELF32_R_TYPE (rel->r_info) == R_OR1K_INSN_REL_26) 4038+ p->pc_count += 1; 4039+ } 4040+ } 4041+ break; 4042+ } 4043+ } 4044+ 4045+ return TRUE; 4046+} 4047+ 4048+/* Finish up the dynamic sections. */ 4049+ 4050+static bfd_boolean 4051+or1k_elf_finish_dynamic_sections (bfd *output_bfd, 4052+ struct bfd_link_info *info) 4053+{ 4054+ bfd *dynobj; 4055+ asection *sdyn, *sgot; 4056+ struct elf_or1k_link_hash_table *htab; 4057+ 4058+ htab = or1k_elf_hash_table (info); 4059+ if (htab == NULL) 4060+ return FALSE; 4061+ 4062+ dynobj = htab->root.dynobj; 4063+ 4064+ sgot = htab->sgotplt; 4065+ sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); 4066+ 4067+ if (htab->root.dynamic_sections_created) 4068+ { 4069+ asection *splt; 4070+ Elf32_External_Dyn *dyncon, *dynconend; 4071+ 4072+ BFD_ASSERT (sgot != NULL && sdyn != NULL); 4073+ 4074+ dyncon = (Elf32_External_Dyn *) sdyn->contents; 4075+ dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size); 4076+ 4077+ for (; dyncon < dynconend; dyncon++) 4078+ { 4079+ Elf_Internal_Dyn dyn; 4080+ asection *s; 4081+ 4082+ bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); 4083+ 4084+ switch (dyn.d_tag) 4085+ { 4086+ default: 4087+ continue; 4088+ 4089+ case DT_PLTGOT: 4090+ s = htab->sgot->output_section; 4091+ BFD_ASSERT (s != NULL); 4092+ dyn.d_un.d_ptr = s->vma; 4093+ break; 4094+ 4095+ case DT_JMPREL: 4096+ s = htab->srelplt->output_section; 4097+ BFD_ASSERT (s != NULL); 4098+ dyn.d_un.d_ptr = s->vma; 4099+ break; 4100+ 4101+ case DT_PLTRELSZ: 4102+ s = htab->srelplt->output_section; 4103+ BFD_ASSERT (s != NULL); 4104+ dyn.d_un.d_val = s->size; 4105+ break; 4106+ 4107+ case DT_RELASZ: 4108+ /* My reading of the SVR4 ABI indicates that the 4109+ procedure linkage table relocs (DT_JMPREL) should be 4110+ included in the overall relocs (DT_RELA). This is 4111+ what Solaris does. However, UnixWare can not handle 4112+ that case. Therefore, we override the DT_RELASZ entry 4113+ here to make it not include the JMPREL relocs. Since 4114+ the linker script arranges for .rela.plt to follow all 4115+ other relocation sections, we don't have to worry 4116+ about changing the DT_RELA entry. */ 4117+ if (htab->srelplt != NULL) 4118+ { 4119+ /* FIXME: this calculation sometimes produces 4120+ wrong result, the problem is that the dyn.d_un.d_val 4121+ is not always correct, needs investigation why 4122+ that happens. In the meantime, reading the 4123+ ".rela.dyn" section by name seems to yield 4124+ correct result. 4125+ 4126+ s = htab->srelplt->output_section; 4127+ dyn.d_un.d_val -= s->size; 4128+ */ 4129+ 4130+ s = bfd_get_section_by_name (output_bfd, ".rela.dyn"); 4131+ dyn.d_un.d_val = s ? s->size : 0; 4132+ } 4133+ break; 4134+ } 4135+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); 4136+ } 4137+ 4138+ 4139+ /* Fill in the first entry in the procedure linkage table. */ 4140+ splt = htab->splt; 4141+ if (splt && splt->size > 0) 4142+ { 4143+ if (info->shared) 4144+ { 4145+ bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD0, 4146+ splt->contents); 4147+ bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD1, 4148+ splt->contents + 4); 4149+ bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD2, 4150+ splt->contents + 8); 4151+ bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD3, 4152+ splt->contents + 12); 4153+ bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD4, 4154+ splt->contents + 16); 4155+ } 4156+ else 4157+ { 4158+ unsigned long addr; 4159+ /* addr = .got + 4 */ 4160+ addr = sgot->output_section->vma + sgot->output_offset + 4; 4161+ bfd_put_32 (output_bfd, 4162+ PLT0_ENTRY_WORD0 | ((addr >> 16) & 0xffff), 4163+ splt->contents); 4164+ bfd_put_32 (output_bfd, 4165+ PLT0_ENTRY_WORD1 | (addr & 0xffff), 4166+ splt->contents + 4); 4167+ bfd_put_32 (output_bfd, PLT0_ENTRY_WORD2, splt->contents + 8); 4168+ bfd_put_32 (output_bfd, PLT0_ENTRY_WORD3, splt->contents + 12); 4169+ bfd_put_32 (output_bfd, PLT0_ENTRY_WORD4, splt->contents + 16); 4170+ } 4171+ 4172+ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; 4173+ } 4174+ } 4175+ 4176+ /* Set the first entry in the global offset table to the address of 4177+ the dynamic section. */ 4178+ if (sgot && sgot->size > 0) 4179+ { 4180+ if (sdyn == NULL) 4181+ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); 4182+ else 4183+ bfd_put_32 (output_bfd, 4184+ sdyn->output_section->vma + sdyn->output_offset, 4185+ sgot->contents); 4186+ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; 4187+ } 4188+ 4189+ if (htab->sgot && htab->sgot->size > 0) 4190+ elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4; 4191+ 4192+ return TRUE; 4193+} 4194+ 4195+/* Finish up dynamic symbol handling. We set the contents of various 4196+ dynamic sections here. */ 4197+ 4198+static bfd_boolean 4199+or1k_elf_finish_dynamic_symbol (bfd *output_bfd, 4200+ struct bfd_link_info *info, 4201+ struct elf_link_hash_entry *h, 4202+ Elf_Internal_Sym *sym) 4203+{ 4204+ struct elf_or1k_link_hash_table *htab; 4205+ bfd_byte *loc; 4206+ 4207+ htab = or1k_elf_hash_table (info); 4208+ if (htab == NULL) 4209+ return FALSE; 4210+ 4211+ if (h->plt.offset != (bfd_vma) -1) 4212+ { 4213+ asection *splt; 4214+ asection *sgot; 4215+ asection *srela; 4216+ 4217+ bfd_vma plt_index; 4218+ bfd_vma got_offset; 4219+ bfd_vma got_addr; 4220+ Elf_Internal_Rela rela; 4221+ 4222+ /* This symbol has an entry in the procedure linkage table. Set 4223+ it up. */ 4224+ BFD_ASSERT (h->dynindx != -1); 4225+ 4226+ splt = htab->splt; 4227+ sgot = htab->sgotplt; 4228+ srela = htab->srelplt; 4229+ BFD_ASSERT (splt != NULL && sgot != NULL && srela != NULL); 4230+ 4231+ /* Get the index in the procedure linkage table which 4232+ corresponds to this symbol. This is the index of this symbol 4233+ in all the symbols for which we are making plt entries. The 4234+ first entry in the procedure linkage table is reserved. */ 4235+ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; 4236+ 4237+ /* Get the offset into the .got table of the entry that 4238+ corresponds to this function. Each .got entry is 4 bytes. 4239+ The first three are reserved. */ 4240+ got_offset = (plt_index + 3) * 4; 4241+ got_addr = got_offset; 4242+ 4243+ /* Fill in the entry in the procedure linkage table. */ 4244+ if (! info->shared) 4245+ { 4246+ got_addr += htab->sgotplt->output_section->vma 4247+ + htab->sgotplt->output_offset; 4248+ bfd_put_32 (output_bfd, PLT_ENTRY_WORD0 | ((got_addr >> 16) & 0xffff), 4249+ splt->contents + h->plt.offset); 4250+ bfd_put_32 (output_bfd, PLT_ENTRY_WORD1 | (got_addr & 0xffff), 4251+ splt->contents + h->plt.offset + 4); 4252+ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD2, 4253+ splt->contents + h->plt.offset + 8); 4254+ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD3, 4255+ splt->contents + h->plt.offset + 12); 4256+ bfd_put_32 (output_bfd, PLT_ENTRY_WORD4 4257+ | plt_index * sizeof (Elf32_External_Rela), 4258+ splt->contents + h->plt.offset + 16); 4259+ } 4260+ else 4261+ { 4262+ bfd_put_32 (output_bfd, PLT_PIC_ENTRY_WORD0 | (got_addr & 0xffff), 4263+ splt->contents + h->plt.offset); 4264+ bfd_put_32 (output_bfd, PLT_PIC_ENTRY_WORD1 4265+ | plt_index * sizeof (Elf32_External_Rela), 4266+ splt->contents + h->plt.offset + 4); 4267+ bfd_put_32 (output_bfd, (bfd_vma) PLT_PIC_ENTRY_WORD2, 4268+ splt->contents + h->plt.offset + 8); 4269+ bfd_put_32 (output_bfd, (bfd_vma) PLT_PIC_ENTRY_WORD3, 4270+ splt->contents + h->plt.offset + 12); 4271+ bfd_put_32 (output_bfd, (bfd_vma) PLT_PIC_ENTRY_WORD4, 4272+ splt->contents + h->plt.offset + 16); 4273+ } 4274+ 4275+ /* Fill in the entry in the global offset table. */ 4276+ bfd_put_32 (output_bfd, 4277+ (splt->output_section->vma 4278+ + splt->output_offset), /* Same offset. */ 4279+ sgot->contents + got_offset); 4280+ 4281+ /* Fill in the entry in the .rela.plt section. */ 4282+ rela.r_offset = (sgot->output_section->vma 4283+ + sgot->output_offset 4284+ + got_offset); 4285+ rela.r_info = ELF32_R_INFO (h->dynindx, R_OR1K_JMP_SLOT); 4286+ rela.r_addend = 0; 4287+ loc = srela->contents; 4288+ loc += plt_index * sizeof (Elf32_External_Rela); 4289+ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); 4290+ 4291+ if (!h->def_regular) 4292+ { 4293+ /* Mark the symbol as undefined, rather than as defined in 4294+ the .plt section. Leave the value alone. */ 4295+ sym->st_shndx = SHN_UNDEF; 4296+ } 4297+ 4298+ } 4299+ 4300+ if (h->got.offset != (bfd_vma) -1 4301+ && (h->got.offset & 2) == 0) /* Homemade TLS check. */ 4302+ { 4303+ asection *sgot; 4304+ asection *srela; 4305+ Elf_Internal_Rela rela; 4306+ 4307+ /* This symbol has an entry in the global offset table. Set it 4308+ up. */ 4309+ sgot = htab->sgot; 4310+ srela = htab->srelgot; 4311+ BFD_ASSERT (sgot != NULL && srela != NULL); 4312+ 4313+ rela.r_offset = (sgot->output_section->vma 4314+ + sgot->output_offset 4315+ + (h->got.offset &~ 1)); 4316+ 4317+ /* If this is a -Bsymbolic link, and the symbol is defined 4318+ locally, we just want to emit a RELATIVE reloc. Likewise if 4319+ the symbol was forced to be local because of a version file. 4320+ The entry in the global offset table will already have been 4321+ initialized in the relocate_section function. */ 4322+ if (info->shared && SYMBOL_REFERENCES_LOCAL (info, h)) 4323+ { 4324+ rela.r_info = ELF32_R_INFO (0, R_OR1K_RELATIVE); 4325+ rela.r_addend = (h->root.u.def.value 4326+ + h->root.u.def.section->output_section->vma 4327+ + h->root.u.def.section->output_offset); 4328+ } 4329+ else 4330+ { 4331+ BFD_ASSERT ((h->got.offset & 1) == 0); 4332+ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset); 4333+ rela.r_info = ELF32_R_INFO (h->dynindx, R_OR1K_GLOB_DAT); 4334+ rela.r_addend = 0; 4335+ } 4336+ 4337+ loc = srela->contents; 4338+ loc += srela->reloc_count * sizeof (Elf32_External_Rela); 4339+ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); 4340+ ++srela->reloc_count; 4341+ } 4342+ 4343+ if (h->needs_copy) 4344+ { 4345+ asection *s; 4346+ Elf_Internal_Rela rela; 4347+ 4348+ /* This symbols needs a copy reloc. Set it up. */ 4349+ BFD_ASSERT (h->dynindx != -1 4350+ && (h->root.type == bfd_link_hash_defined 4351+ || h->root.type == bfd_link_hash_defweak)); 4352+ 4353+ s = bfd_get_section_by_name (h->root.u.def.section->owner, 4354+ ".rela.bss"); 4355+ BFD_ASSERT (s != NULL); 4356+ 4357+ rela.r_offset = (h->root.u.def.value 4358+ + h->root.u.def.section->output_section->vma 4359+ + h->root.u.def.section->output_offset); 4360+ rela.r_info = ELF32_R_INFO (h->dynindx, R_OR1K_COPY); 4361+ rela.r_addend = 0; 4362+ loc = s->contents; 4363+ loc += s->reloc_count * sizeof (Elf32_External_Rela); 4364+ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); 4365+ ++s->reloc_count; 4366+ } 4367+ 4368+ /* Mark some specially defined symbols as absolute. */ 4369+ if (strcmp (h->root.root.string, "_DYNAMIC") == 0 4370+ || h == htab->root.hgot) 4371+ sym->st_shndx = SHN_ABS; 4372+ 4373+ return TRUE; 4374+} 4375+ 4376+static enum elf_reloc_type_class 4377+or1k_elf_reloc_type_class (const Elf_Internal_Rela *rela) 4378+{ 4379+ switch ((int) ELF32_R_TYPE (rela->r_info)) 4380+ { 4381+ case R_OR1K_RELATIVE: return reloc_class_relative; 4382+ case R_OR1K_JMP_SLOT: return reloc_class_plt; 4383+ case R_OR1K_COPY: return reloc_class_copy; 4384+ default: return reloc_class_normal; 4385+ } 4386+} 4387+ 4388+/* Adjust a symbol defined by a dynamic object and referenced by a 4389+ regular object. The current definition is in some section of the 4390+ dynamic object, but we're not including those sections. We have to 4391+ change the definition to something the rest of the link can 4392+ understand. */ 4393+ 4394+static bfd_boolean 4395+or1k_elf_adjust_dynamic_symbol (struct bfd_link_info *info, 4396+ struct elf_link_hash_entry *h) 4397+{ 4398+ struct elf_or1k_link_hash_table *htab; 4399+ struct elf_or1k_link_hash_entry *eh; 4400+ struct elf_or1k_dyn_relocs *p; 4401+ bfd *dynobj; 4402+ asection *s; 4403+ 4404+ dynobj = elf_hash_table (info)->dynobj; 4405+ 4406+ /* Make sure we know what is going on here. */ 4407+ BFD_ASSERT (dynobj != NULL 4408+ && (h->needs_plt 4409+ || h->type == STT_GNU_IFUNC 4410+ || h->u.weakdef != NULL 4411+ || (h->def_dynamic 4412+ && h->ref_regular 4413+ && !h->def_regular))); 4414+ 4415+ /* If this is a function, put it in the procedure linkage table. We 4416+ will fill in the contents of the procedure linkage table later, 4417+ when we know the address of the .got section. */ 4418+ if ((h->type == STT_FUNC || h->type == STT_GNU_IFUNC) 4419+ || h->needs_plt) 4420+ { 4421+ if (! info->shared 4422+ && !h->def_dynamic 4423+ && !h->ref_dynamic 4424+ && h->root.type != bfd_link_hash_undefweak 4425+ && h->root.type != bfd_link_hash_undefined) 4426+ { 4427+ /* This case can occur if we saw a PLT reloc in an input 4428+ file, but the symbol was never referred to by a dynamic 4429+ object. In such a case, we don't actually need to build 4430+ a procedure linkage table, and we can just do a PCREL 4431+ reloc instead. */ 4432+ h->plt.offset = (bfd_vma) -1; 4433+ h->needs_plt = 0; 4434+ } 4435+ 4436+ return TRUE; 4437+ } 4438+ else 4439+ h->plt.offset = (bfd_vma) -1; 4440+ 4441+ /* If this is a weak symbol, and there is a real definition, the 4442+ processor independent code will have arranged for us to see the 4443+ real definition first, and we can just use the same value. */ 4444+ if (h->u.weakdef != NULL) 4445+ { 4446+ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined 4447+ || h->u.weakdef->root.type == bfd_link_hash_defweak); 4448+ h->root.u.def.section = h->u.weakdef->root.u.def.section; 4449+ h->root.u.def.value = h->u.weakdef->root.u.def.value; 4450+ return TRUE; 4451+ } 4452+ 4453+ /* This is a reference to a symbol defined by a dynamic object which 4454+ is not a function. */ 4455+ 4456+ /* If we are creating a shared library, we must presume that the 4457+ only references to the symbol are via the global offset table. 4458+ For such cases we need not do anything here; the relocations will 4459+ be handled correctly by relocate_section. */ 4460+ if (info->shared) 4461+ return TRUE; 4462+ 4463+ /* If there are no references to this symbol that do not use the 4464+ GOT, we don't need to generate a copy reloc. */ 4465+ if (!h->non_got_ref) 4466+ return TRUE; 4467+ 4468+ /* If -z nocopyreloc was given, we won't generate them either. */ 4469+ if (info->nocopyreloc) 4470+ { 4471+ h->non_got_ref = 0; 4472+ return TRUE; 4473+ } 4474+ 4475+ eh = (struct elf_or1k_link_hash_entry *) h; 4476+ for (p = eh->dyn_relocs; p != NULL; p = p->next) 4477+ { 4478+ s = p->sec->output_section; 4479+ if (s != NULL && (s->flags & (SEC_READONLY | SEC_HAS_CONTENTS)) != 0) 4480+ break; 4481+ } 4482+ 4483+ /* If we didn't find any dynamic relocs in sections which needs the 4484+ copy reloc, then we'll be keeping the dynamic relocs and avoiding 4485+ the copy reloc. */ 4486+ if (p == NULL) 4487+ { 4488+ h->non_got_ref = 0; 4489+ return TRUE; 4490+ } 4491+ 4492+ /* We must allocate the symbol in our .dynbss section, which will 4493+ become part of the .bss section of the executable. There will be 4494+ an entry for this symbol in the .dynsym section. The dynamic 4495+ object will contain position independent code, so all references 4496+ from the dynamic object to this symbol will go through the global 4497+ offset table. The dynamic linker will use the .dynsym entry to 4498+ determine the address it must put in the global offset table, so 4499+ both the dynamic object and the regular object will refer to the 4500+ same memory location for the variable. */ 4501+ 4502+ htab = or1k_elf_hash_table (info); 4503+ if (htab == NULL) 4504+ return FALSE; 4505+ 4506+ s = htab->sdynbss; 4507+ BFD_ASSERT (s != NULL); 4508+ 4509+ /* We must generate a R_OR1K_COPY reloc to tell the dynamic linker 4510+ to copy the initial value out of the dynamic object and into the 4511+ runtime process image. We need to remember the offset into the 4512+ .rela.bss section we are going to use. */ 4513+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0) 4514+ { 4515+ asection *srel; 4516+ 4517+ srel = htab->srelbss; 4518+ BFD_ASSERT (srel != NULL); 4519+ srel->size += sizeof (Elf32_External_Rela); 4520+ h->needs_copy = 1; 4521+ } 4522+ 4523+ return _bfd_elf_adjust_dynamic_copy (h, s); 4524+} 4525+ 4526+/* Allocate space in .plt, .got and associated reloc sections for 4527+ dynamic relocs. */ 4528+ 4529+static bfd_boolean 4530+allocate_dynrelocs (struct elf_link_hash_entry *h, void * inf) 4531+{ 4532+ struct bfd_link_info *info; 4533+ struct elf_or1k_link_hash_table *htab; 4534+ struct elf_or1k_link_hash_entry *eh; 4535+ struct elf_or1k_dyn_relocs *p; 4536+ 4537+ if (h->root.type == bfd_link_hash_indirect) 4538+ return TRUE; 4539+ 4540+ info = (struct bfd_link_info *) inf; 4541+ htab = or1k_elf_hash_table (info); 4542+ if (htab == NULL) 4543+ return FALSE; 4544+ 4545+ eh = (struct elf_or1k_link_hash_entry *) h; 4546+ 4547+ if (htab->root.dynamic_sections_created 4548+ && h->plt.refcount > 0) 4549+ { 4550+ /* Make sure this symbol is output as a dynamic symbol. 4551+ Undefined weak syms won't yet be marked as dynamic. */ 4552+ if (h->dynindx == -1 4553+ && !h->forced_local) 4554+ { 4555+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 4556+ return FALSE; 4557+ } 4558+ 4559+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info->shared, h)) 4560+ { 4561+ asection *s = htab->splt; 4562+ 4563+ /* If this is the first .plt entry, make room for the special 4564+ first entry. */ 4565+ if (s->size == 0) 4566+ s->size = PLT_ENTRY_SIZE; 4567+ 4568+ h->plt.offset = s->size; 4569+ 4570+ /* If this symbol is not defined in a regular file, and we are 4571+ not generating a shared library, then set the symbol to this 4572+ location in the .plt. This is required to make function 4573+ pointers compare as equal between the normal executable and 4574+ the shared library. */ 4575+ if (! info->shared 4576+ && !h->def_regular) 4577+ { 4578+ h->root.u.def.section = s; 4579+ h->root.u.def.value = h->plt.offset; 4580+ } 4581+ 4582+ /* Make room for this entry. */ 4583+ s->size += PLT_ENTRY_SIZE; 4584+ 4585+ /* We also need to make an entry in the .got.plt section, which 4586+ will be placed in the .got section by the linker script. */ 4587+ htab->sgotplt->size += 4; 4588+ 4589+ /* We also need to make an entry in the .rel.plt section. */ 4590+ htab->srelplt->size += sizeof (Elf32_External_Rela); 4591+ } 4592+ else 4593+ { 4594+ h->plt.offset = (bfd_vma) -1; 4595+ h->needs_plt = 0; 4596+ } 4597+ } 4598+ else 4599+ { 4600+ h->plt.offset = (bfd_vma) -1; 4601+ h->needs_plt = 0; 4602+ } 4603+ 4604+ if (h->got.refcount > 0) 4605+ { 4606+ asection *s; 4607+ bfd_boolean dyn; 4608+ unsigned char tls_type; 4609+ 4610+ /* Make sure this symbol is output as a dynamic symbol. 4611+ Undefined weak syms won't yet be marked as dynamic. */ 4612+ if (h->dynindx == -1 4613+ && !h->forced_local) 4614+ { 4615+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 4616+ return FALSE; 4617+ } 4618+ 4619+ s = htab->sgot; 4620+ 4621+ h->got.offset = s->size; 4622+ 4623+ tls_type = ((struct elf_or1k_link_hash_entry *) h)->tls_type; 4624+ 4625+ /* TLS GD requires two GOT and two relocs. */ 4626+ if (tls_type == TLS_GD) 4627+ s->size += 8; 4628+ else 4629+ s->size += 4; 4630+ dyn = htab->root.dynamic_sections_created; 4631+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)) 4632+ { 4633+ if (tls_type == TLS_GD) 4634+ htab->srelgot->size += 2 * sizeof (Elf32_External_Rela); 4635+ else 4636+ htab->srelgot->size += sizeof (Elf32_External_Rela); 4637+ } 4638+ } 4639+ else 4640+ h->got.offset = (bfd_vma) -1; 4641+ 4642+ if (eh->dyn_relocs == NULL) 4643+ return TRUE; 4644+ 4645+ /* In the shared -Bsymbolic case, discard space allocated for 4646+ dynamic pc-relative relocs against symbols which turn out to be 4647+ defined in regular objects. For the normal shared case, discard 4648+ space for pc-relative relocs that have become local due to symbol 4649+ visibility changes. */ 4650+ 4651+ if (info->shared) 4652+ { 4653+ if (SYMBOL_CALLS_LOCAL (info, h)) 4654+ { 4655+ struct elf_or1k_dyn_relocs **pp; 4656+ 4657+ for (pp = &eh->dyn_relocs; (p = *pp) != NULL;) 4658+ { 4659+ p->count -= p->pc_count; 4660+ p->pc_count = 0; 4661+ if (p->count == 0) 4662+ *pp = p->next; 4663+ else 4664+ pp = &p->next; 4665+ } 4666+ } 4667+ 4668+ /* Also discard relocs on undefined weak syms with non-default 4669+ visibility. */ 4670+ if (eh->dyn_relocs != NULL 4671+ && h->root.type == bfd_link_hash_undefweak) 4672+ { 4673+ if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT) 4674+ eh->dyn_relocs = NULL; 4675+ 4676+ /* Make sure undefined weak symbols are output as a dynamic 4677+ symbol in PIEs. */ 4678+ else if (h->dynindx == -1 4679+ && !h->forced_local) 4680+ { 4681+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 4682+ return FALSE; 4683+ } 4684+ } 4685+ } 4686+ else 4687+ { 4688+ /* For the non-shared case, discard space for relocs against 4689+ symbols which turn out to need copy relocs or are not 4690+ dynamic. */ 4691+ 4692+ if (!h->non_got_ref 4693+ && ((h->def_dynamic 4694+ && !h->def_regular) 4695+ || (htab->root.dynamic_sections_created 4696+ && (h->root.type == bfd_link_hash_undefweak 4697+ || h->root.type == bfd_link_hash_undefined)))) 4698+ { 4699+ /* Make sure this symbol is output as a dynamic symbol. 4700+ Undefined weak syms won't yet be marked as dynamic. */ 4701+ if (h->dynindx == -1 4702+ && !h->forced_local) 4703+ { 4704+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 4705+ return FALSE; 4706+ } 4707+ 4708+ /* If that succeeded, we know we'll be keeping all the 4709+ relocs. */ 4710+ if (h->dynindx != -1) 4711+ goto keep; 4712+ } 4713+ 4714+ eh->dyn_relocs = NULL; 4715+ 4716+ keep: ; 4717+ } 4718+ 4719+ /* Finally, allocate space. */ 4720+ for (p = eh->dyn_relocs; p != NULL; p = p->next) 4721+ { 4722+ asection *sreloc = elf_section_data (p->sec)->sreloc; 4723+ sreloc->size += p->count * sizeof (Elf32_External_Rela); 4724+ } 4725+ 4726+ return TRUE; 4727+} 4728+ 4729+/* Find any dynamic relocs that apply to read-only sections. */ 4730+ 4731+static bfd_boolean 4732+readonly_dynrelocs (struct elf_link_hash_entry *h, void * inf) 4733+{ 4734+ struct elf_or1k_link_hash_entry *eh; 4735+ struct elf_or1k_dyn_relocs *p; 4736+ 4737+ eh = (struct elf_or1k_link_hash_entry *) h; 4738+ for (p = eh->dyn_relocs; p != NULL; p = p->next) 4739+ { 4740+ asection *s = p->sec->output_section; 4741+ 4742+ if (s != NULL && (s->flags & SEC_READONLY) != 0) 4743+ { 4744+ struct bfd_link_info *info = (struct bfd_link_info *) inf; 4745+ 4746+ info->flags |= DF_TEXTREL; 4747+ 4748+ /* Not an error, just cut short the traversal. */ 4749+ return FALSE; 4750+ } 4751+ } 4752+ return TRUE; 4753+} 4754+ 4755+/* Set the sizes of the dynamic sections. */ 4756+ 4757+static bfd_boolean 4758+or1k_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, 4759+ struct bfd_link_info *info) 4760+{ 4761+ struct elf_or1k_link_hash_table *htab; 4762+ bfd *dynobj; 4763+ asection *s; 4764+ bfd_boolean relocs; 4765+ bfd *ibfd; 4766+ 4767+ htab = or1k_elf_hash_table (info); 4768+ if (htab == NULL) 4769+ return FALSE; 4770+ 4771+ dynobj = htab->root.dynobj; 4772+ BFD_ASSERT (dynobj != NULL); 4773+ 4774+ if (htab->root.dynamic_sections_created) 4775+ { 4776+ /* Set the contents of the .interp section to the interpreter. */ 4777+ if (info->executable) 4778+ { 4779+ s = bfd_get_section_by_name (dynobj, ".interp"); 4780+ BFD_ASSERT (s != NULL); 4781+ s->size = sizeof ELF_DYNAMIC_INTERPRETER; 4782+ s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER; 4783+ } 4784+ } 4785+ 4786+ /* Set up .got offsets for local syms, and space for local dynamic 4787+ relocs. */ 4788+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next) 4789+ { 4790+ bfd_signed_vma *local_got; 4791+ bfd_signed_vma *end_local_got; 4792+ bfd_size_type locsymcount; 4793+ Elf_Internal_Shdr *symtab_hdr; 4794+ unsigned char *local_tls_type; 4795+ asection *srel; 4796+ 4797+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) 4798+ continue; 4799+ 4800+ for (s = ibfd->sections; s != NULL; s = s->next) 4801+ { 4802+ struct elf_or1k_dyn_relocs *p; 4803+ 4804+ for (p = ((struct elf_or1k_dyn_relocs *) 4805+ elf_section_data (s)->local_dynrel); 4806+ p != NULL; 4807+ p = p->next) 4808+ { 4809+ if (! bfd_is_abs_section (p->sec) 4810+ && bfd_is_abs_section (p->sec->output_section)) 4811+ { 4812+ /* Input section has been discarded, either because 4813+ it is a copy of a linkonce section or due to 4814+ linker script /DISCARD/, so we'll be discarding 4815+ the relocs too. */ 4816+ } 4817+ else if (p->count != 0) 4818+ { 4819+ srel = elf_section_data (p->sec)->sreloc; 4820+ srel->size += p->count * sizeof (Elf32_External_Rela); 4821+ if ((p->sec->output_section->flags & SEC_READONLY) != 0) 4822+ info->flags |= DF_TEXTREL; 4823+ } 4824+ } 4825+ } 4826+ 4827+ local_got = elf_local_got_refcounts (ibfd); 4828+ if (!local_got) 4829+ continue; 4830+ 4831+ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; 4832+ locsymcount = symtab_hdr->sh_info; 4833+ end_local_got = local_got + locsymcount; 4834+ s = htab->sgot; 4835+ srel = htab->srelgot; 4836+ local_tls_type = (unsigned char *) elf_or1k_local_tls_type (ibfd); 4837+ for (; local_got < end_local_got; ++local_got) 4838+ { 4839+ if (*local_got > 0) 4840+ { 4841+ *local_got = s->size; 4842+ 4843+ /* TLS GD requires two GOT and two relocs. */ 4844+ if (local_tls_type != NULL && *local_tls_type == TLS_GD) 4845+ s->size += 8; 4846+ else 4847+ s->size += 4; 4848+ if (info->shared) 4849+ { 4850+ if (local_tls_type != NULL && *local_tls_type == TLS_GD) 4851+ srel->size += 2 * sizeof (Elf32_External_Rela); 4852+ else 4853+ srel->size += sizeof (Elf32_External_Rela); 4854+ } 4855+ } 4856+ else 4857+ 4858+ *local_got = (bfd_vma) -1; 4859+ 4860+ if (local_tls_type) 4861+ ++local_tls_type; 4862+ } 4863+ } 4864+ 4865+ /* Allocate global sym .plt and .got entries, and space for global 4866+ sym dynamic relocs. */ 4867+ elf_link_hash_traverse (&htab->root, allocate_dynrelocs, info); 4868+ 4869+ /* We now have determined the sizes of the various dynamic sections. 4870+ Allocate memory for them. */ 4871+ relocs = FALSE; 4872+ for (s = dynobj->sections; s != NULL; s = s->next) 4873+ { 4874+ if ((s->flags & SEC_LINKER_CREATED) == 0) 4875+ continue; 4876+ 4877+ if (s == htab->splt 4878+ || s == htab->sgot 4879+ || s == htab->sgotplt 4880+ || s == htab->sdynbss) 4881+ { 4882+ /* Strip this section if we don't need it; see the 4883+ comment below. */ 4884+ } 4885+ else if (CONST_STRNEQ (bfd_get_section_name (dynobj, s), ".rela")) 4886+ { 4887+ if (s->size != 0 && s != htab->srelplt) 4888+ relocs = TRUE; 4889+ 4890+ /* We use the reloc_count field as a counter if we need 4891+ to copy relocs into the output file. */ 4892+ s->reloc_count = 0; 4893+ } 4894+ else 4895+ /* It's not one of our sections, so don't allocate space. */ 4896+ continue; 4897+ 4898+ if (s->size == 0) 4899+ { 4900+ /* If we don't need this section, strip it from the 4901+ output file. This is mostly to handle .rela.bss and 4902+ .rela.plt. We must create both sections in 4903+ create_dynamic_sections, because they must be created 4904+ before the linker maps input sections to output 4905+ sections. The linker does that before 4906+ adjust_dynamic_symbol is called, and it is that 4907+ function which decides whether anything needs to go 4908+ into these sections. */ 4909+ s->flags |= SEC_EXCLUDE; 4910+ continue; 4911+ } 4912+ 4913+ if ((s->flags & SEC_HAS_CONTENTS) == 0) 4914+ continue; 4915+ 4916+ /* Allocate memory for the section contents. We use bfd_zalloc 4917+ here in case unused entries are not reclaimed before the 4918+ section's contents are written out. This should not happen, 4919+ but this way if it does, we get a R_OR1K_NONE reloc instead 4920+ of garbage. */ 4921+ s->contents = bfd_zalloc (dynobj, s->size); 4922+ 4923+ if (s->contents == NULL) 4924+ return FALSE; 4925+ } 4926+ 4927+ if (htab->root.dynamic_sections_created) 4928+ { 4929+ /* Add some entries to the .dynamic section. We fill in the 4930+ values later, in or1k_elf_finish_dynamic_sections, but we 4931+ must add the entries now so that we get the correct size for 4932+ the .dynamic section. The DT_DEBUG entry is filled in by the 4933+ dynamic linker and used by the debugger. */ 4934+#define add_dynamic_entry(TAG, VAL) \ 4935+ _bfd_elf_add_dynamic_entry (info, TAG, VAL) 4936+ 4937+ if (info->executable) 4938+ { 4939+ if (! add_dynamic_entry (DT_DEBUG, 0)) 4940+ return FALSE; 4941+ } 4942+ 4943+ if (htab->splt->size != 0) 4944+ { 4945+ if (! add_dynamic_entry (DT_PLTGOT, 0) 4946+ || ! add_dynamic_entry (DT_PLTRELSZ, 0) 4947+ || ! add_dynamic_entry (DT_PLTREL, DT_RELA) 4948+ || ! add_dynamic_entry (DT_JMPREL, 0)) 4949+ return FALSE; 4950+ } 4951+ 4952+ if (relocs) 4953+ { 4954+ if (! add_dynamic_entry (DT_RELA, 0) 4955+ || ! add_dynamic_entry (DT_RELASZ, 0) 4956+ || ! add_dynamic_entry (DT_RELAENT, 4957+ sizeof (Elf32_External_Rela))) 4958+ return FALSE; 4959+ 4960+ /* If any dynamic relocs apply to a read-only section, 4961+ then we need a DT_TEXTREL entry. */ 4962+ if ((info->flags & DF_TEXTREL) == 0) 4963+ elf_link_hash_traverse (&htab->root, readonly_dynrelocs, 4964+ info); 4965+ 4966+ if ((info->flags & DF_TEXTREL) != 0) 4967+ { 4968+ if (! add_dynamic_entry (DT_TEXTREL, 0)) 4969+ return FALSE; 4970+ } 4971+ } 4972+ } 4973+ 4974+#undef add_dynamic_entry 4975+ return TRUE; 4976+} 4977+ 4978+/* Create dynamic sections when linking against a dynamic object. */ 4979+ 4980+static bfd_boolean 4981+or1k_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) 4982+{ 4983+ struct elf_or1k_link_hash_table *htab; 4984+ 4985+ htab = or1k_elf_hash_table (info); 4986+ if (htab == NULL) 4987+ return FALSE; 4988+ 4989+ if (!htab->sgot && !create_got_section (dynobj, info)) 4990+ return FALSE; 4991+ 4992+ if (!_bfd_elf_create_dynamic_sections (dynobj, info)) 4993+ return FALSE; 4994+ 4995+ htab->splt = bfd_get_section_by_name (dynobj, ".plt"); 4996+ htab->srelplt = bfd_get_section_by_name (dynobj, ".rela.plt"); 4997+ htab->sdynbss = bfd_get_section_by_name (dynobj, ".dynbss"); 4998+ if (!info->shared) 4999+ htab->srelbss = bfd_get_section_by_name (dynobj, ".rela.bss"); 5000+ 5001+ if (!htab->splt || !htab->srelplt || !htab->sdynbss 5002+ || (!info->shared && !htab->srelbss)) 5003+ abort (); 5004+ 5005+ return TRUE; 5006+} 5007+ 5008+/* Copy the extra info we tack onto an elf_link_hash_entry. */ 5009+ 5010+static void 5011+or1k_elf_copy_indirect_symbol (struct bfd_link_info *info, 5012+ struct elf_link_hash_entry *dir, 5013+ struct elf_link_hash_entry *ind) 5014+{ 5015+ struct elf_or1k_link_hash_entry * edir; 5016+ struct elf_or1k_link_hash_entry * eind; 5017+ 5018+ edir = (struct elf_or1k_link_hash_entry *) dir; 5019+ eind = (struct elf_or1k_link_hash_entry *) ind; 5020+ 5021+ if (eind->dyn_relocs != NULL) 5022+ { 5023+ if (edir->dyn_relocs != NULL) 5024+ { 5025+ struct elf_or1k_dyn_relocs **pp; 5026+ struct elf_or1k_dyn_relocs *p; 5027+ 5028+ /* Add reloc counts against the indirect sym to the direct sym 5029+ list. Merge any entries against the same section. */ 5030+ for (pp = &eind->dyn_relocs; (p = *pp) != NULL;) 5031+ { 5032+ struct elf_or1k_dyn_relocs *q; 5033+ 5034+ for (q = edir->dyn_relocs; q != NULL; q = q->next) 5035+ if (q->sec == p->sec) 5036+ { 5037+ q->pc_count += p->pc_count; 5038+ q->count += p->count; 5039+ *pp = p->next; 5040+ break; 5041+ } 5042+ if (q == NULL) 5043+ pp = &p->next; 5044+ } 5045+ *pp = edir->dyn_relocs; 5046+ } 5047+ 5048+ edir->dyn_relocs = eind->dyn_relocs; 5049+ eind->dyn_relocs = NULL; 5050+ } 5051+ 5052+ if (ind->root.type == bfd_link_hash_indirect) 5053+ { 5054+ if (dir->got.refcount <= 0) 5055+ { 5056+ edir->tls_type = eind->tls_type; 5057+ eind->tls_type = TLS_UNKNOWN; 5058+ } 5059+ } 5060+ 5061+ _bfd_elf_link_hash_copy_indirect (info, dir, ind); 5062+} 5063+ 5064+/* Set the right machine number. */ 5065+ 5066+static bfd_boolean 5067+or1k_elf_object_p (bfd *abfd) 5068+{ 5069+ unsigned long mach = bfd_mach_or1k; 5070+ 5071+ if (elf_elfheader (abfd)->e_flags & EF_OR1K_NODELAY) 5072+ mach = bfd_mach_or1knd; 5073+ 5074+ return bfd_default_set_arch_mach (abfd, bfd_arch_or1k, mach); 5075+} 5076+ 5077+/* Store the machine number in the flags field. */ 5078+ 5079+static void 5080+or1k_elf_final_write_processing (bfd *abfd, 5081+ bfd_boolean linker ATTRIBUTE_UNUSED) 5082+{ 5083+ switch (bfd_get_mach (abfd)) 5084+ { 5085+ default: 5086+ case bfd_mach_or1k: 5087+ break; 5088+ case bfd_mach_or1knd: 5089+ elf_elfheader (abfd)->e_flags |= EF_OR1K_NODELAY; 5090+ break; 5091+ } 5092+} 5093+ 5094+static bfd_boolean 5095+or1k_elf_set_private_flags (bfd *abfd, flagword flags) 5096+{ 5097+ BFD_ASSERT (!elf_flags_init (abfd) 5098+ || elf_elfheader (abfd)->e_flags == flags); 5099+ 5100+ elf_elfheader (abfd)->e_flags = flags; 5101+ elf_flags_init (abfd) = TRUE; 5102+ return TRUE; 5103+} 5104+ 5105+/* Make sure all input files are consistent with respect to 5106+ EF_OR1K_NODELAY flag setting. */ 5107+ 5108+static bfd_boolean 5109+elf32_or1k_merge_private_bfd_data (bfd *ibfd, bfd *obfd) 5110+{ 5111+ flagword out_flags; 5112+ flagword in_flags; 5113+ 5114+ in_flags = elf_elfheader (ibfd)->e_flags; 5115+ out_flags = elf_elfheader (obfd)->e_flags; 5116+ 5117+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour 5118+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour) 5119+ return TRUE; 5120+ 5121+ if (!elf_flags_init (obfd)) 5122+ { 5123+ elf_flags_init (obfd) = TRUE; 5124+ elf_elfheader (obfd)->e_flags = in_flags; 5125+ 5126+ return TRUE; 5127+ } 5128+ 5129+ if (in_flags == out_flags) 5130+ return TRUE; 5131+ 5132+ if ((in_flags & EF_OR1K_NODELAY) != (out_flags & EF_OR1K_NODELAY)) 5133+ { 5134+ (*_bfd_error_handler) 5135+ (_("%B: EF_OR1K_NODELAY flag mismatch with previous modules"), ibfd); 5136+ 5137+ bfd_set_error (bfd_error_bad_value); 5138+ return FALSE; 5139+ } 5140+ 5141+ return TRUE; 5142+ 5143+} 5144+ 5145+#define ELF_ARCH bfd_arch_or1k 5146+#define ELF_MACHINE_CODE EM_OR1K 5147+#define ELF_TARGET_ID OR1K_ELF_DATA 5148+#define ELF_MAXPAGESIZE 0x2000 5149+ 5150+#define TARGET_BIG_SYM bfd_elf32_or1k_big_vec 5151+#define TARGET_BIG_NAME "elf32-or1k" 5152+ 5153+#define elf_info_to_howto_rel NULL 5154+#define elf_info_to_howto or1k_info_to_howto_rela 5155+#define elf_backend_relocate_section or1k_elf_relocate_section 5156+#define elf_backend_gc_mark_hook or1k_elf_gc_mark_hook 5157+#define elf_backend_gc_sweep_hook or1k_elf_gc_sweep_hook 5158+#define elf_backend_check_relocs or1k_elf_check_relocs 5159+#define elf_backend_reloc_type_class or1k_elf_reloc_type_class 5160+#define elf_backend_can_gc_sections 1 5161+#define elf_backend_rela_normal 1 5162+ 5163+#define bfd_elf32_mkobject elf_or1k_mkobject 5164+ 5165+#define bfd_elf32_bfd_merge_private_bfd_data elf32_or1k_merge_private_bfd_data 5166+#define bfd_elf32_bfd_set_private_flags or1k_elf_set_private_flags 5167+#define bfd_elf32_bfd_reloc_type_lookup or1k_reloc_type_lookup 5168+#define bfd_elf32_bfd_reloc_name_lookup or1k_reloc_name_lookup 5169+ 5170+#define elf_backend_object_p or1k_elf_object_p 5171+#define elf_backend_final_write_processing or1k_elf_final_write_processing 5172+#define elf_backend_can_refcount 1 5173+ 5174+#define elf_backend_plt_readonly 1 5175+#define elf_backend_want_got_plt 1 5176+#define elf_backend_want_plt_sym 0 5177+#define elf_backend_got_header_size 12 5178+#define bfd_elf32_bfd_link_hash_table_create or1k_elf_link_hash_table_create 5179+#define elf_backend_copy_indirect_symbol or1k_elf_copy_indirect_symbol 5180+#define elf_backend_create_dynamic_sections or1k_elf_create_dynamic_sections 5181+#define elf_backend_finish_dynamic_sections or1k_elf_finish_dynamic_sections 5182+#define elf_backend_size_dynamic_sections or1k_elf_size_dynamic_sections 5183+#define elf_backend_adjust_dynamic_symbol or1k_elf_adjust_dynamic_symbol 5184+#define elf_backend_finish_dynamic_symbol or1k_elf_finish_dynamic_symbol 5185+ 5186+#include "elf32-target.h" 5187diff -rNU3 dist.orig/bfd/elf32-or32.c dist/bfd/elf32-or32.c 5188--- dist.orig/bfd/elf32-or32.c 2007-07-03 16:26:41.000000000 +0200 5189+++ dist/bfd/elf32-or32.c 1970-01-01 01:00:00.000000000 +0100 5190@@ -1,514 +0,0 @@ 5191-/* OR32-specific support for 32-bit ELF 5192- Copyright 2002, 2004, 2005, 2007 Free Software Foundation, Inc. 5193- Contributed by Ivan Guzvinec <ivang@opencores.org> 5194- 5195- This file is part of BFD, the Binary File Descriptor library. 5196- 5197- This program is free software; you can redistribute it and/or modify 5198- it under the terms of the GNU General Public License as published by 5199- the Free Software Foundation; either version 3 of the License, or 5200- (at your option) any later version. 5201- 5202- This program is distributed in the hope that it will be useful, 5203- but WITHOUT ANY WARRANTY; without even the implied warranty of 5204- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5205- GNU General Public License for more details. 5206- 5207- You should have received a copy of the GNU General Public License 5208- along with this program; if not, write to the Free Software 5209- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 5210- MA 02110-1301, USA. */ 5211- 5212-#include "sysdep.h" 5213-#include "bfd.h" 5214-#include "libbfd.h" 5215-#include "elf-bfd.h" 5216-#include "elf/or32.h" 5217-#include "libiberty.h" 5218- 5219-/* Try to minimize the amount of space occupied by relocation tables 5220- on the ROM (not that the ROM won't be swamped by other ELF overhead). */ 5221-#define USE_REL 1 5222- 5223-/* Set the right machine number for an OR32 ELF file. */ 5224- 5225-static bfd_boolean 5226-or32_elf_object_p (bfd *abfd) 5227-{ 5228- (void) bfd_default_set_arch_mach (abfd, bfd_arch_or32, 0); 5229- return TRUE; 5230-} 5231- 5232-/* The final processing done just before writing out an OR32 ELF object file. 5233- This gets the OR32 architecture right based on the machine number. */ 5234- 5235-static void 5236-or32_elf_final_write_processing (bfd *abfd, 5237- bfd_boolean linker ATTRIBUTE_UNUSED) 5238-{ 5239- elf_elfheader (abfd)->e_flags &=~ EF_OR32_MACH; 5240-} 5241- 5242-static bfd_reloc_status_type 5243-or32_elf_32_reloc (bfd *abfd, 5244- arelent *reloc_entry, 5245- asymbol *symbol, 5246- void * data, 5247- asection *input_section, 5248- bfd *output_bfd, 5249- char **error_message ATTRIBUTE_UNUSED) 5250-{ 5251- if (output_bfd != NULL) 5252- { 5253- unsigned long insn; 5254- bfd_size_type addr = reloc_entry->address; 5255- 5256- reloc_entry->address += input_section->output_offset; 5257- 5258- insn = bfd_get_32 (abfd, (bfd_byte *) data + addr); 5259- insn += symbol->section->output_section->vma; 5260- insn += symbol->section->output_offset; 5261- insn += symbol->value; 5262- bfd_put_32 (abfd, insn, (bfd_byte *) data + addr); 5263- 5264- return bfd_reloc_ok; 5265- } 5266- 5267- return bfd_reloc_continue; 5268-} 5269- 5270-static bfd_reloc_status_type 5271-or32_elf_16_reloc (bfd *abfd, 5272- arelent *reloc_entry, 5273- asymbol *symbol, 5274- void * data, 5275- asection *input_section, 5276- bfd *output_bfd, 5277- char **error_message ATTRIBUTE_UNUSED) 5278-{ 5279- if (output_bfd != NULL) 5280- { 5281- unsigned short insn; 5282- bfd_size_type addr = reloc_entry->address; 5283- 5284- reloc_entry->address += input_section->output_offset; 5285- 5286- insn = bfd_get_16 (abfd, (bfd_byte *) data + addr); 5287- insn += symbol->section->output_section->vma; 5288- insn += symbol->section->output_offset; 5289- insn += symbol->value; 5290- bfd_put_16 (abfd, insn, (bfd_byte *) data + addr); 5291- 5292- return bfd_reloc_ok; 5293- } 5294- 5295- return bfd_reloc_continue; 5296-} 5297- 5298-static bfd_reloc_status_type 5299-or32_elf_8_reloc (bfd *abfd ATTRIBUTE_UNUSED, 5300- arelent *reloc_entry, 5301- asymbol *symbol, 5302- void * data, 5303- asection *input_section, 5304- bfd *output_bfd, 5305- char **error_message ATTRIBUTE_UNUSED) 5306-{ 5307- if (output_bfd != NULL) 5308- { 5309- unsigned char insn; 5310- bfd_size_type addr = reloc_entry->address; 5311- 5312- reloc_entry->address += input_section->output_offset; 5313- 5314- insn = bfd_get_8 (abfd, (bfd_byte *) data + addr); 5315- insn += symbol->section->output_section->vma; 5316- insn += symbol->section->output_offset; 5317- insn += symbol->value; 5318- bfd_put_8 (abfd, insn, (bfd_byte *) data + addr); 5319- 5320- return bfd_reloc_ok; 5321- } 5322- 5323- return bfd_reloc_continue; 5324-} 5325- 5326-/* Do a R_OR32_CONSTH relocation. This has to be done in combination 5327- with a R_OR32_CONST reloc, because there is a carry from the LO16 to 5328- the HI16. Here we just save the information we need; we do the 5329- actual relocation when we see the LO16. OR32 ELF requires that the 5330- LO16 immediately follow the HI16. As a GNU extension, we permit an 5331- arbitrary number of HI16 relocs to be associated with a single LO16 5332- reloc. This extension permits gcc to output the HI and LO relocs 5333- itself. This code is copied from the elf32-mips.c. */ 5334- 5335-struct or32_consth 5336-{ 5337- struct or32_consth *next; 5338- bfd_byte *addr; 5339- bfd_vma addend; 5340-}; 5341- 5342-/* FIXME: This should not be a static variable. */ 5343- 5344-static struct or32_consth *or32_consth_list; 5345- 5346-static bfd_reloc_status_type 5347-or32_elf_consth_reloc (bfd *abfd ATTRIBUTE_UNUSED, 5348- arelent *reloc_entry, 5349- asymbol *symbol, 5350- void * data, 5351- asection *input_section, 5352- bfd *output_bfd, 5353- char **error_message ATTRIBUTE_UNUSED) 5354-{ 5355- bfd_reloc_status_type ret; 5356- bfd_vma relocation; 5357- struct or32_consth *n; 5358- 5359- ret = bfd_reloc_ok; 5360- 5361- if (bfd_is_und_section (symbol->section) 5362- && output_bfd == NULL) 5363- ret = bfd_reloc_undefined; 5364- 5365- if (bfd_is_com_section (symbol->section)) 5366- relocation = 0; 5367- else 5368- relocation = symbol->value; 5369- 5370- relocation += symbol->section->output_section->vma; 5371- relocation += symbol->section->output_offset; 5372- relocation += reloc_entry->addend; 5373- 5374- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) 5375- return bfd_reloc_outofrange; 5376- 5377- /* Save the information, and let LO16 do the actual relocation. */ 5378- n = bfd_malloc (sizeof *n); 5379- if (n == NULL) 5380- return bfd_reloc_outofrange; 5381- n->addr = (bfd_byte *) data + reloc_entry->address; 5382- n->addend = relocation; 5383- n->next = or32_consth_list; 5384- or32_consth_list = n; 5385- 5386- if (output_bfd != NULL) 5387- reloc_entry->address += input_section->output_offset; 5388- 5389- return ret; 5390-} 5391- 5392-/* Do a R_OR32_CONST relocation. This is a straightforward 16 bit 5393- inplace relocation; this function exists in order to do the 5394- R_OR32_CONSTH relocation described above. */ 5395- 5396-static bfd_reloc_status_type 5397-or32_elf_const_reloc (bfd *abfd, 5398- arelent *reloc_entry, 5399- asymbol *symbol, 5400- void * data, 5401- asection *input_section, 5402- bfd *output_bfd, 5403- char **error_message) 5404-{ 5405- if (or32_consth_list != NULL) 5406- { 5407- struct or32_consth *l; 5408- 5409- l = or32_consth_list; 5410- while (l != NULL) 5411- { 5412- unsigned long insn; 5413- unsigned long val; 5414- unsigned long vallo; 5415- struct or32_consth *next; 5416- 5417- /* Do the HI16 relocation. Note that we actually don't need 5418- to know anything about the LO16 itself, except where to 5419- find the low 16 bits of the addend needed by the LO16. */ 5420- insn = bfd_get_32 (abfd, l->addr); 5421- vallo = (bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address) 5422- & 0xffff); 5423- val = ((insn & 0xffff) << 16) + vallo; 5424- val += l->addend; 5425- 5426- insn = (insn &~ 0xffff) | ((val >> 16) & 0xffff); 5427- bfd_put_32 (abfd, insn, l->addr); 5428- 5429- next = l->next; 5430- free (l); 5431- l = next; 5432- } 5433- 5434- or32_consth_list = NULL; 5435- } 5436- 5437- if (output_bfd != NULL) 5438- { 5439- unsigned long insn, tmp; 5440- bfd_size_type addr = reloc_entry->address; 5441- 5442- reloc_entry->address += input_section->output_offset; 5443- 5444- insn = bfd_get_32 (abfd, (bfd_byte *) data + addr); 5445- tmp = insn & 0x0000ffff; 5446- tmp += symbol->section->output_section->vma; 5447- tmp += symbol->section->output_offset; 5448- tmp += symbol->value; 5449- insn = (insn & 0xffff0000) | (tmp & 0x0000ffff); 5450- bfd_put_32 (abfd, insn, (bfd_byte *) data + addr); 5451- 5452- return bfd_reloc_ok; 5453- } 5454- 5455- /* Now do the LO16 reloc in the usual way. */ 5456- return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data, 5457- input_section, output_bfd, error_message); 5458-} 5459- 5460-static bfd_reloc_status_type 5461-or32_elf_jumptarg_reloc (bfd *abfd, 5462- arelent *reloc_entry, 5463- asymbol *symbol ATTRIBUTE_UNUSED, 5464- void * data, 5465- asection *input_section, 5466- bfd *output_bfd, 5467- char **error_message ATTRIBUTE_UNUSED) 5468-{ 5469- if (output_bfd != NULL) 5470- { 5471- unsigned long insn, tmp; 5472- bfd_size_type addr = reloc_entry->address; 5473- 5474- reloc_entry->address += input_section->output_offset; 5475- 5476- insn = bfd_get_32 (abfd, (bfd_byte *) data + addr); 5477- tmp = insn | 0xfc000000; 5478- tmp -= (input_section->output_offset >> 2); 5479- insn = (insn & 0xfc000000) | (tmp & 0x03ffffff); 5480- bfd_put_32 (abfd, insn, (bfd_byte *) data + addr); 5481- 5482- return bfd_reloc_ok; 5483- } 5484- 5485- return bfd_reloc_continue; 5486-} 5487- 5488-static reloc_howto_type elf_or32_howto_table[] = 5489-{ 5490- /* This reloc does nothing. */ 5491- HOWTO (R_OR32_NONE, /* type */ 5492- 0, /* rightshift */ 5493- 2, /* size (0 = byte, 1 = short, 2 = long) */ 5494- 32, /* bitsize */ 5495- FALSE, /* pc_relative */ 5496- 0, /* bitpos */ 5497- complain_overflow_bitfield, /* complain_on_overflow */ 5498- bfd_elf_generic_reloc, /* special_function */ 5499- "R_OR32_NONE", /* name */ 5500- FALSE, /* partial_inplace */ 5501- 0, /* src_mask */ 5502- 0, /* dst_mask */ 5503- FALSE), /* pcrel_offset */ 5504- 5505- /* A standard 32 bit relocation. */ 5506- HOWTO (R_OR32_32, /* type */ 5507- 0, /* rightshift */ 5508- 2, /* size (0 = byte, 1 = short, 2 = long) */ 5509- 32, /* bitsize */ 5510- FALSE, /* pc_relative */ 5511- 0, /* bitpos */ 5512- complain_overflow_bitfield, /* complain_on_overflow */ 5513- or32_elf_32_reloc, /* special_function */ 5514- "R_OR32_32", /* name */ 5515- FALSE, /* partial_inplace */ 5516- 0xffffffff, /* src_mask */ 5517- 0xffffffff, /* dst_mask */ 5518- FALSE), /* pcrel_offset */ 5519- 5520- /* A standard 16 bit relocation. */ 5521- HOWTO (R_OR32_16, /* type */ 5522- 0, /* rightshift */ 5523- 1, /* size (0 = byte, 1 = short, 2 = long) */ 5524- 16, /* bitsize */ 5525- FALSE, /* pc_relative */ 5526- 0, /* bitpos */ 5527- complain_overflow_bitfield, /* complain_on_overflow */ 5528- or32_elf_16_reloc, /* special_function */ 5529- "R_OR32_16", /* name */ 5530- FALSE, /* partial_inplace */ 5531- 0x0000ffff, /* src_mask */ 5532- 0x0000ffff, /* dst_mask */ 5533- FALSE), /* pcrel_offset */ 5534- 5535- /* A standard 8 bit relocation. */ 5536- HOWTO (R_OR32_8, /* type */ 5537- 0, /* rightshift */ 5538- 0, /* size (0 = byte, 1 = short, 2 = long) */ 5539- 8, /* bitsize */ 5540- FALSE, /* pc_relative */ 5541- 0, /* bitpos */ 5542- complain_overflow_bitfield, /* complain_on_overflow */ 5543- or32_elf_8_reloc, /* special_function */ 5544- "R_OR32_8", /* name */ 5545- FALSE, /* partial_inplace */ 5546- 0x000000ff, /* src_mask */ 5547- 0x000000ff, /* dst_mask */ 5548- FALSE), /* pcrel_offset */ 5549- 5550- /* A standard low 16 bit relocation. */ 5551- HOWTO (R_OR32_CONST, /* type */ 5552- 0, /* rightshift */ 5553- 2, /* size (0 = byte, 1 = short, 2 = long) */ 5554- 16, /* bitsize */ 5555- FALSE, /* pc_relative */ 5556- 0, /* bitpos */ 5557- complain_overflow_dont, /* complain_on_overflow */ 5558- or32_elf_const_reloc, /* special_function */ 5559- "R_OR32_CONST", /* name */ 5560- FALSE, /* partial_inplace */ 5561- 0x0000ffff, /* src_mask */ 5562- 0x0000ffff, /* dst_mask */ 5563- FALSE), /* pcrel_offset */ 5564- 5565- /* A standard high 16 bit relocation. */ 5566- HOWTO (R_OR32_CONSTH, /* type */ 5567- 16, /* rightshift */ 5568- 2, /* size (0 = byte, 1 = short, 2 = long) */ 5569- 16, /* bitsize */ 5570- TRUE, /* pc_relative */ 5571- 0, /* bitpos */ 5572- complain_overflow_dont, /* complain_on_overflow */ 5573- or32_elf_consth_reloc, /* special_function */ 5574- "R_OR32_CONSTH", /* name */ 5575- FALSE, /* partial_inplace */ 5576- 0xffff0000, /* src_mask */ 5577- 0x0000ffff, /* dst_mask */ 5578- FALSE), /* pcrel_offset */ 5579- 5580- /* A standard branch relocation. */ 5581- HOWTO (R_OR32_JUMPTARG, /* type */ 5582- 2, /* rightshift */ 5583- 2, /* size (0 = byte, 1 = short, 2 = long) */ 5584- 28, /* bitsize */ 5585- TRUE, /* pc_relative */ 5586- 0, /* bitpos */ 5587- complain_overflow_signed, /* complain_on_overflow */ 5588- or32_elf_jumptarg_reloc,/* special_function */ 5589- "R_OR32_JUMPTARG", /* name */ 5590- FALSE, /* partial_inplace */ 5591- 0, /* src_mask */ 5592- 0x03ffffff, /* dst_mask */ 5593- TRUE), /* pcrel_offset */ 5594- 5595- /* GNU extension to record C++ vtable hierarchy. */ 5596- HOWTO (R_OR32_GNU_VTINHERIT, /* type */ 5597- 0, /* rightshift */ 5598- 2, /* size (0 = byte, 1 = short, 2 = long) */ 5599- 0, /* bitsize */ 5600- FALSE, /* pc_relative */ 5601- 0, /* bitpos */ 5602- complain_overflow_dont, /* complain_on_overflow */ 5603- NULL, /* special_function */ 5604- "R_OR32_GNU_VTINHERIT", /* name */ 5605- FALSE, /* partial_inplace */ 5606- 0, /* src_mask */ 5607- 0, /* dst_mask */ 5608- FALSE), /* pcrel_offset */ 5609- 5610- /* GNU extension to record C++ vtable member usage. */ 5611- HOWTO (R_OR32_GNU_VTENTRY, /* type */ 5612- 0, /* rightshift */ 5613- 2, /* size (0 = byte, 1 = short, 2 = long) */ 5614- 0, /* bitsize */ 5615- FALSE, /* pc_relative */ 5616- 0, /* bitpos */ 5617- complain_overflow_dont, /* complain_on_overflow */ 5618- _bfd_elf_rel_vtable_reloc_fn, /* special_function */ 5619- "R_OR32_GNU_VTENTRY", /* name */ 5620- FALSE, /* partial_inplace */ 5621- 0, /* src_mask */ 5622- 0, /* dst_mask */ 5623- FALSE), /* pcrel_offset */ 5624-}; 5625- 5626-/* Map BFD reloc types to OR32 ELF reloc types. */ 5627- 5628-struct or32_reloc_map 5629-{ 5630- bfd_reloc_code_real_type bfd_reloc_val; 5631- unsigned char elf_reloc_val; 5632-}; 5633- 5634-static const struct or32_reloc_map or32_reloc_map[] = 5635-{ 5636- { BFD_RELOC_NONE, R_OR32_NONE }, 5637- { BFD_RELOC_32, R_OR32_32 }, 5638- { BFD_RELOC_16, R_OR32_16 }, 5639- { BFD_RELOC_8, R_OR32_8 }, 5640- { BFD_RELOC_LO16, R_OR32_CONST }, 5641- { BFD_RELOC_HI16, R_OR32_CONSTH }, 5642- { BFD_RELOC_32_GOT_PCREL, R_OR32_JUMPTARG }, 5643- { BFD_RELOC_VTABLE_INHERIT, R_OR32_GNU_VTINHERIT }, 5644- { BFD_RELOC_VTABLE_ENTRY, R_OR32_GNU_VTENTRY }, 5645-}; 5646- 5647-static reloc_howto_type * 5648-bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, 5649- bfd_reloc_code_real_type code) 5650-{ 5651- unsigned int i; 5652- 5653- for (i = ARRAY_SIZE (or32_reloc_map); i--;) 5654- if (or32_reloc_map[i].bfd_reloc_val == code) 5655- return &elf_or32_howto_table[or32_reloc_map[i].elf_reloc_val]; 5656- 5657- return NULL; 5658-} 5659- 5660-static reloc_howto_type * 5661-bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 5662- const char *r_name) 5663-{ 5664- unsigned int i; 5665- 5666- for (i = 0; 5667- i < sizeof (elf_or32_howto_table) / sizeof (elf_or32_howto_table[0]); 5668- i++) 5669- if (elf_or32_howto_table[i].name != NULL 5670- && strcasecmp (elf_or32_howto_table[i].name, r_name) == 0) 5671- return &elf_or32_howto_table[i]; 5672- 5673- return NULL; 5674-} 5675- 5676-/* Set the howto pointer for an OR32 ELF reloc. */ 5677- 5678-static void 5679-or32_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, 5680- arelent *cache_ptr, 5681- Elf_Internal_Rela *dst) 5682-{ 5683- unsigned int r_type; 5684- 5685- r_type = ELF32_R_TYPE (dst->r_info); 5686- BFD_ASSERT (r_type < (unsigned int) R_OR32_max); 5687- cache_ptr->howto = &elf_or32_howto_table[r_type]; 5688-} 5689- 5690-#define TARGET_LITTLE_SYM bfd_elf32_or32_little_vec 5691-#define TARGET_LITTLE_NAME "elf32-littleor32" 5692-#define TARGET_BIG_SYM bfd_elf32_or32_big_vec 5693-#define TARGET_BIG_NAME "elf32-or32" 5694-#define ELF_ARCH bfd_arch_or32 5695-#define ELF_MACHINE_CODE EM_OR32 5696-#define ELF_MAXPAGESIZE 0x1000 5697- 5698-#define elf_info_to_howto 0 5699-#define elf_info_to_howto_rel or32_info_to_howto_rel 5700-#define elf_backend_object_p or32_elf_object_p 5701-#define elf_backend_final_write_processing \ 5702- or32_elf_final_write_processing 5703- 5704-#include "elf32-target.h" 5705diff -rNU3 dist.orig/bfd/elf32-ppc.c dist/bfd/elf32-ppc.c 5706--- dist.orig/bfd/elf32-ppc.c 2013-03-25 09:06:19.000000000 +0100 5707+++ dist/bfd/elf32-ppc.c 2015-10-18 13:11:12.000000000 +0200 5708@@ -3898,7 +3898,7 @@ 5709 sec->has_tls_get_addr_call = 1; 5710 } 5711 5712- switch (r_type) 5713+ switch ((int)r_type) 5714 { 5715 case R_PPC_TLSGD: 5716 case R_PPC_TLSLD: 5717@@ -7766,7 +7766,7 @@ 5718 howto = NULL; 5719 if (r_type < R_PPC_max) 5720 howto = ppc_elf_howto_table[r_type]; 5721- switch (r_type) 5722+ switch ((int)r_type) 5723 { 5724 default: 5725 info->callbacks->einfo 5726diff -rNU3 dist.orig/bfd/elf32-sh.c dist/bfd/elf32-sh.c 5727--- dist.orig/bfd/elf32-sh.c 2013-03-25 09:06:20.000000000 +0100 5728+++ dist/bfd/elf32-sh.c 2015-10-18 13:11:12.000000000 +0200 5729@@ -2808,6 +2808,7 @@ 5730 /* Make sure we know what is going on here. */ 5731 BFD_ASSERT (htab->root.dynobj != NULL 5732 && (h->needs_plt 5733+ || h->type == STT_GNU_IFUNC 5734 || h->u.weakdef != NULL 5735 || (h->def_dynamic 5736 && h->ref_regular 5737@@ -2816,7 +2817,7 @@ 5738 /* If this is a function, put it in the procedure linkage table. We 5739 will fill in the contents of the procedure linkage table later, 5740 when we know the address of the .got section. */ 5741- if (h->type == STT_FUNC 5742+ if ((h->type == STT_FUNC || h->type == STT_GNU_IFUNC) 5743 || h->needs_plt) 5744 { 5745 if (h->plt.refcount <= 0 5746@@ -3285,6 +3286,10 @@ 5747 { 5748 struct bfd_link_info *info = (struct bfd_link_info *) inf; 5749 5750+ if (info->warn_shared_textrel) 5751+ (*_bfd_error_handler) 5752+ (_("warning: dynamic relocation in readonly section `%s'"), 5753+ h->root.root.string); 5754 info->flags |= DF_TEXTREL; 5755 5756 /* Not an error, just cut short the traversal. */ 5757diff -rNU3 dist.orig/bfd/elf32-vax.c dist/bfd/elf32-vax.c 5758--- dist.orig/bfd/elf32-vax.c 2012-09-04 15:32:53.000000000 +0200 5759+++ dist/bfd/elf32-vax.c 2015-10-18 13:11:13.000000000 +0200 5760@@ -490,6 +490,24 @@ 5761 return TRUE; 5762 } 5763 5764+/* Copy vax-specific data from one module to another */ 5765+static bfd_boolean 5766+elf32_vax_copy_private_bfd_data (bfd *ibfd, bfd *obfd) 5767+{ 5768+ flagword in_flags; 5769+ 5770+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour 5771+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour) 5772+ return TRUE; 5773+ 5774+ in_flags = elf_elfheader (ibfd)->e_flags; 5775+ 5776+ elf_elfheader (obfd)->e_flags = in_flags; 5777+ elf_flags_init (obfd) = TRUE; 5778+ 5779+ return TRUE; 5780+} 5781+ 5782 /* Merge backend specific data from an object file to the output 5783 object file when linking. */ 5784 static bfd_boolean 5785@@ -752,7 +770,13 @@ 5786 return FALSE; 5787 5788 if (sec->flags & SEC_READONLY) 5789- info->flags |= DF_TEXTREL; 5790+ { 5791+ if (info->warn_shared_textrel) 5792+ (*_bfd_error_handler) 5793+ (_("warning: dynamic relocation in readonly section `%s'"), 5794+ sec->name); 5795+ info->flags |= DF_TEXTREL; 5796+ } 5797 } 5798 5799 sreloc->size += sizeof (Elf32_External_Rela); 5800@@ -922,6 +946,7 @@ 5801 /* Make sure we know what is going on here. */ 5802 BFD_ASSERT (dynobj != NULL 5803 && (h->needs_plt 5804+ || h->type == STT_GNU_IFUNC 5805 || h->u.weakdef != NULL 5806 || (h->def_dynamic 5807 && h->ref_regular 5808@@ -930,7 +955,7 @@ 5809 /* If this is a function, put it in the procedure linkage table. We 5810 will fill in the contents of the procedure linkage table later, 5811 when we know the address of the .got section. */ 5812- if (h->type == STT_FUNC 5813+ if ((h->type == STT_FUNC || h->type == STT_GNU_IFUNC) 5814 || h->needs_plt) 5815 { 5816 if (h->plt.refcount <= 0 5817@@ -1186,7 +1211,12 @@ 5818 continue; 5819 5820 /* Allocate memory for the section contents. */ 5821- s->contents = (bfd_byte *) bfd_alloc (dynobj, s->size); 5822+ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. 5823+ Unused entries should be reclaimed before the section's contents 5824+ are written out, but at the moment this does not happen. Thus in 5825+ order to prevent writing out garbage, we initialise the section's 5826+ contents to zero. */ 5827+ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); 5828 if (s->contents == NULL) 5829 return FALSE; 5830 } 5831@@ -1285,6 +1315,7 @@ 5832 5833 if (!elf_hash_table (info)->dynamic_sections_created 5834 || (info->shared && info->symbolic) 5835+ || ELF_ST_VISIBILITY (h->other) != STV_DEFAULT 5836 || h->forced_local) 5837 { 5838 h->got.refcount = 0; 5839@@ -1305,9 +1336,7 @@ 5840 5841 dyn = elf_hash_table (info)->dynamic_sections_created; 5842 /* Allocate space in the .got and .rela.got sections. */ 5843- if (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 5844- && (info->shared 5845- || WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, 0, h))) 5846+ if (info->shared || WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, 0, h)) 5847 { 5848 sgot->size += 4; 5849 srelgot->size += sizeof (Elf32_External_Rela); 5850@@ -1631,9 +1660,9 @@ 5851 { 5852 relocate = TRUE; 5853 outrel.r_info = ELF32_R_INFO (0, R_VAX_RELATIVE); 5854- BFD_ASSERT (bfd_get_signed_32 (input_bfd, 5855- &contents[rel->r_offset]) == 0); 5856- outrel.r_addend = relocation + rel->r_addend; 5857+ outrel.r_addend = bfd_get_signed_32(input_bfd, 5858+ &contents[rel->r_offset]) 5859+ + relocation + rel->r_addend; 5860 } 5861 else 5862 { 5863@@ -1672,6 +1701,9 @@ 5864 } 5865 } 5866 5867+ if (input_section->flags & SEC_CODE) 5868+ info->flags |= DF_TEXTREL; 5869+ 5870 if ((input_section->flags & SEC_CODE) != 0 5871 || (ELF32_R_TYPE (outrel.r_info) != R_VAX_32 5872 && ELF32_R_TYPE (outrel.r_info) != R_VAX_RELATIVE 5873@@ -2051,12 +2083,15 @@ 5874 #define TARGET_LITTLE_SYM bfd_elf32_vax_vec 5875 #define TARGET_LITTLE_NAME "elf32-vax" 5876 #define ELF_MACHINE_CODE EM_VAX 5877-#define ELF_MAXPAGESIZE 0x1000 5878+#define ELF_MAXPAGESIZE 0x10000 5879 5880 #define elf_backend_create_dynamic_sections \ 5881 _bfd_elf_create_dynamic_sections 5882 #define bfd_elf32_bfd_link_hash_table_create \ 5883 elf_vax_link_hash_table_create 5884+#define bfd_elf32_bfd_copy_private_bfd_data \ 5885+ elf32_vax_copy_private_bfd_data 5886+ 5887 #define bfd_elf32_bfd_final_link bfd_elf_gc_common_final_link 5888 5889 #define elf_backend_check_relocs elf_vax_check_relocs 5890diff -rNU3 dist.orig/bfd/elf64-alpha.c dist/bfd/elf64-alpha.c 5891--- dist.orig/bfd/elf64-alpha.c 2012-07-24 23:06:58.000000000 +0200 5892+++ dist/bfd/elf64-alpha.c 2015-10-18 13:11:13.000000000 +0200 5893@@ -100,6 +100,11 @@ 5894 #define PLT_ENTRY_SIZE \ 5895 (elf64_alpha_use_secureplt ? NEW_PLT_ENTRY_SIZE : OLD_PLT_ENTRY_SIZE) 5896 5897+/* ld --traditional-format uses this older format instead. */ 5898+#define OLD_PLT_ENTRY_WORD1 0x279f0000 /* ldah $28, 0($31) */ 5899+#define OLD_PLT_ENTRY_WORD2 0x239c0000 /* lda $28, 0($28) */ 5900+#define OLD_PLT_ENTRY_WORD3 0xc3e00000 /* br $31, plt0 */ 5901+ 5902 #define MAX_GOT_SIZE (64*1024) 5903 5904 #define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so" 5905@@ -4821,6 +4826,32 @@ 5906 plt_index = ((gotent->plt_offset - NEW_PLT_HEADER_SIZE) 5907 / NEW_PLT_ENTRY_SIZE); 5908 } 5909+ else if ((output_bfd->flags & BFD_TRADITIONAL_FORMAT) != 0) 5910+ { 5911+ long hi, lo; 5912+ 5913+ /* decompose the reloc offset for the plt for ldah+lda */ 5914+ hi = plt_index * sizeof(Elf64_External_Rela); 5915+ lo = ((hi & 0xffff) ^ 0x8000) - 0x8000; 5916+ hi = (hi - lo) >> 16; 5917+ 5918+ insn = INSN_ABO (INSN_LDAH, 28, 31, hi); 5919+ bfd_put_32 (output_bfd, insn, 5920+ splt->contents + gotent->plt_offset); 5921+ 5922+ insn = INSN_ABO (INSN_LDA, 28, 28, lo); 5923+ bfd_put_32 (output_bfd, insn, 5924+ splt->contents + gotent->plt_offset + 4); 5925+ 5926+ disp = -(gotent->plt_offset + 12); 5927+ insn = INSN_AD (INSN_BR, 31, disp); 5928+ 5929+ bfd_put_32 (output_bfd, insn, 5930+ splt->contents + gotent->plt_offset + 8); 5931+ 5932+ plt_index = ((gotent->plt_offset - OLD_PLT_HEADER_SIZE) 5933+ / OLD_PLT_ENTRY_SIZE); 5934+ } 5935 else 5936 { 5937 disp = -(gotent->plt_offset + 4); 5938diff -rNU3 dist.orig/bfd/elf64-mips.c dist/bfd/elf64-mips.c 5939--- dist.orig/bfd/elf64-mips.c 2012-09-04 16:13:07.000000000 +0200 5940+++ dist/bfd/elf64-mips.c 2015-10-18 13:11:13.000000000 +0200 5941@@ -123,6 +123,8 @@ 5942 (bfd *, asymbol *, bfd_boolean, char **, bfd_vma *); 5943 static bfd_boolean mips_elf64_object_p 5944 (bfd *); 5945+static bfd_boolean mips_elf64_is_local_label_name 5946+ (bfd *, const char *); 5947 static irix_compat_t elf64_mips_irix_compat 5948 (bfd *); 5949 static bfd_boolean elf64_mips_grok_prstatus 5950@@ -3917,7 +3919,18 @@ 5951 bfd_default_set_arch_mach (abfd, bfd_arch_mips, mach); 5952 return TRUE; 5953 } 5954+ 5955+/* MIPS ELF local labels start with "$L". */ 5956+static bfd_boolean 5957+mips_elf64_is_local_label_name (bfd *abfd, const char *name) 5958+{ 5959+ if (name[0] == '$' && name[1] == 'L') 5960+ return TRUE; 5961 5962+ /* We accept the generic ELF local label syntax as well. */ 5963+ return _bfd_elf_is_local_label_name (abfd, name); 5964+} 5965+ 5966 /* Depending on the target vector we generate some version of Irix 5967 executables or "normal" MIPS ELF ABI executables. */ 5968 static irix_compat_t 5969@@ -4141,9 +4154,8 @@ 5970 5971 #define elf_backend_write_section _bfd_mips_elf_write_section 5972 5973-/* We don't set bfd_elf64_bfd_is_local_label_name because the 32-bit 5974- MIPS-specific function only applies to IRIX5, which had no 64-bit 5975- ABI. */ 5976+#define bfd_elf64_bfd_is_local_label_name \ 5977+ mips_elf64_is_local_label_name 5978 #define bfd_elf64_bfd_is_target_special_symbol \ 5979 _bfd_mips_elf_is_target_special_symbol 5980 #define bfd_elf64_find_nearest_line _bfd_mips_elf_find_nearest_line 5981diff -rNU3 dist.orig/bfd/elf64-ppc.c dist/bfd/elf64-ppc.c 5982--- dist.orig/bfd/elf64-ppc.c 2013-03-25 09:06:20.000000000 +0100 5983+++ dist/bfd/elf64-ppc.c 2015-10-18 13:11:13.000000000 +0200 5984@@ -3618,9 +3618,6 @@ 5985 struct ppc_link_hash_entry *h; 5986 struct plt_entry *plt_ent; 5987 5988- /* And the reloc addend that this was derived from. */ 5989- bfd_vma addend; 5990- 5991 /* Where this stub is being called from, or, in the case of combined 5992 stub sections, the first input section in the group. */ 5993 asection *id_sec; 5994@@ -9112,6 +9109,10 @@ 5995 { 5996 struct bfd_link_info *info = inf; 5997 5998+ if (info->warn_shared_textrel) 5999+ (*_bfd_error_handler) 6000+ (_("warning: dynamic relocation in readonly section `%s'"), 6001+ h->root.root.string); 6002 info->flags |= DF_TEXTREL; 6003 6004 /* Not an error, just cut short the traversal. */ 6005@@ -9192,7 +9193,13 @@ 6006 srel = htab->reliplt; 6007 srel->size += p->count * sizeof (Elf64_External_Rela); 6008 if ((p->sec->output_section->flags & SEC_READONLY) != 0) 6009- info->flags |= DF_TEXTREL; 6010+ { 6011+ if (info->warn_shared_textrel) 6012+ (*_bfd_error_handler) 6013+ (_("warning: dynamic relocation in readonly section `%s'"), 6014+ p->sec->output_section->name); 6015+ info->flags |= DF_TEXTREL; 6016+ } 6017 } 6018 } 6019 } 6020@@ -11659,7 +11666,6 @@ 6021 } 6022 stub_entry->h = hash; 6023 stub_entry->plt_ent = plt_ent; 6024- stub_entry->addend = irela->r_addend; 6025 6026 if (stub_entry->h != NULL) 6027 htab->stub_globals += 1; 6028@@ -12900,60 +12906,96 @@ 6029 { 6030 bfd_boolean can_plt_call = FALSE; 6031 6032+ /* All of these stubs will modify r2, so there must be a 6033+ branch and link followed by a nop. The nop is 6034+ replaced by an insn to restore r2. */ 6035 if (rel->r_offset + 8 <= input_section->size) 6036 { 6037- unsigned long nop; 6038- nop = bfd_get_32 (input_bfd, contents + rel->r_offset + 4); 6039- if (nop == NOP 6040- || nop == CROR_151515 || nop == CROR_313131) 6041- { 6042- if (h != NULL 6043- && (h == htab->tls_get_addr_fd 6044- || h == htab->tls_get_addr) 6045- && !htab->no_tls_get_addr_opt) 6046+ unsigned long br; 6047+ 6048+ br = bfd_get_32 (input_bfd, 6049+ contents + rel->r_offset); 6050+ if ((br & 1) != 0) 6051+ { 6052+ unsigned long nop; 6053+ 6054+ nop = bfd_get_32 (input_bfd, 6055+ contents + rel->r_offset + 4); 6056+ if (nop == NOP 6057+ || nop == CROR_151515 || nop == CROR_313131) 6058 { 6059- /* Special stub used, leave nop alone. */ 6060+ if (h != NULL 6061+ && (h == htab->tls_get_addr_fd 6062+ || h == htab->tls_get_addr) 6063+ && !htab->no_tls_get_addr_opt) 6064+ { 6065+ /* Special stub used, leave nop alone. */ 6066+ } 6067+ else 6068+ bfd_put_32 (input_bfd, LD_R2_40R1, 6069+ contents + rel->r_offset + 4); 6070+ can_plt_call = TRUE; 6071 } 6072- else 6073- bfd_put_32 (input_bfd, LD_R2_40R1, 6074- contents + rel->r_offset + 4); 6075- can_plt_call = TRUE; 6076 } 6077 } 6078 6079- if (!can_plt_call) 6080+ if (!can_plt_call && h != NULL) 6081 { 6082- if (stub_entry->stub_type == ppc_stub_plt_call 6083- || stub_entry->stub_type == ppc_stub_plt_call_r2save) 6084- { 6085- /* If this is a plain branch rather than a branch 6086- and link, don't require a nop. However, don't 6087- allow tail calls in a shared library as they 6088- will result in r2 being corrupted. */ 6089- unsigned long br; 6090- br = bfd_get_32 (input_bfd, contents + rel->r_offset); 6091- if (info->executable && (br & 1) == 0) 6092- can_plt_call = TRUE; 6093- else 6094- stub_entry = NULL; 6095- } 6096- else if (h != NULL 6097- && strcmp (h->elf.root.root.string, 6098- ".__libc_start_main") == 0) 6099+ const char *name = h->elf.root.root.string; 6100+ 6101+ if (*name == '.') 6102+ ++name; 6103+ 6104+ if (strncmp (name, "__libc_start_main", 17) == 0 6105+ && (name[17] == 0 || name[17] == '@')) 6106 { 6107- /* Allow crt1 branch to go via a toc adjusting stub. */ 6108+ /* Allow crt1 branch to go via a toc adjusting 6109+ stub. Other calls that never return could do 6110+ the same, if we could detect such. */ 6111 can_plt_call = TRUE; 6112 } 6113- else 6114+ } 6115+ 6116+ if (!can_plt_call) 6117+ { 6118+ /* g++ as of 20130507 emits self-calls without a 6119+ following nop. This is arguably wrong since we 6120+ have conflicting information. On the one hand a 6121+ global symbol and on the other a local call 6122+ sequence, but don't error for this special case. 6123+ It isn't possible to cheaply verify we have 6124+ exactly such a call. Allow all calls to the same 6125+ section. */ 6126+ asection *code_sec = sec; 6127+ 6128+ if (get_opd_info (sec) != NULL) 6129 { 6130- info->callbacks->einfo 6131- (_("%P: %H: call to `%T' lacks nop, can't restore toc; " 6132- "recompile with -fPIC"), 6133- input_bfd, input_section, rel->r_offset, sym_name); 6134+ bfd_vma off = (relocation + addend 6135+ - sec->output_section->vma 6136+ - sec->output_offset); 6137 6138- bfd_set_error (bfd_error_bad_value); 6139- ret = FALSE; 6140+ opd_entry_value (sec, off, &code_sec, NULL, FALSE); 6141 } 6142+ if (code_sec == input_section) 6143+ can_plt_call = TRUE; 6144+ } 6145+ 6146+ if (!can_plt_call) 6147+ { 6148+ 6149+ if (stub_entry->stub_type == ppc_stub_plt_call 6150+ || stub_entry->stub_type == ppc_stub_plt_call_r2save) 6151+ info->callbacks->einfo 6152+ (_("%P: %H: call to `%T' lacks nop, can't restore toc; " 6153+ "recompile with -fPIC"), 6154+ input_bfd, input_section, rel->r_offset, sym_name); 6155+ else 6156+ info->callbacks->einfo 6157+ (_("%P: %H: call to `%T' lacks nop, can't restore toc; " 6158+ "(-mcmodel=small toc adjust stub)"), 6159+ input_bfd, input_section, rel->r_offset, sym_name); 6160+ bfd_set_error (bfd_error_bad_value); 6161+ ret = FALSE; 6162 } 6163 6164 if (can_plt_call 6165diff -rNU3 dist.orig/bfd/elf64-x86-64.c dist/bfd/elf64-x86-64.c 6166--- dist.orig/bfd/elf64-x86-64.c 2013-03-25 09:06:20.000000000 +0100 6167+++ dist/bfd/elf64-x86-64.c 2015-10-18 13:11:13.000000000 +0200 6168@@ -2589,6 +2589,10 @@ 6169 { 6170 struct bfd_link_info *info = (struct bfd_link_info *) inf; 6171 6172+ if (info->warn_shared_textrel) 6173+ (*_bfd_error_handler) 6174+ (_("warning: dynamic relocation in readonly section `%s'"), 6175+ h->root.root.string); 6176 info->flags |= DF_TEXTREL; 6177 6178 if (info->warn_shared_textrel && info->shared) 6179diff -rNU3 dist.orig/bfd/elflink.c dist/bfd/elflink.c 6180--- dist.orig/bfd/elflink.c 2013-03-25 09:06:20.000000000 +0100 6181+++ dist/bfd/elflink.c 2015-10-18 13:11:13.000000000 +0200 6182@@ -1442,7 +1442,10 @@ 6183 if (!(oldbfd != NULL 6184 && (oldbfd->flags & BFD_PLUGIN) != 0 6185 && (abfd->flags & BFD_PLUGIN) == 0)) 6186- *skip = TRUE; 6187+ { 6188+ newdef = FALSE; 6189+ *skip = TRUE; 6190+ } 6191 6192 /* Merge st_other. If the symbol already has a dynamic index, 6193 but visibility says it should not be visible, turn it into a 6194@@ -10183,7 +10186,14 @@ 6195 if (bed->s->arch_size == 32) 6196 irel[0].r_info = ELF32_R_INFO (indx, howto->type); 6197 else 6198- irel[0].r_info = ELF64_R_INFO (indx, howto->type); 6199+#ifdef BFD64 6200+ { 6201+ bfd_uint64_t indx64 = indx; 6202+ irel[0].r_info = ELF64_R_INFO (indx64, howto->type); 6203+ } 6204+#else 6205+ BFD_FAIL(); 6206+#endif 6207 6208 rel_hdr = reldata->hdr; 6209 erel = rel_hdr->contents; 6210diff -rNU3 dist.orig/bfd/elfn32-mips.c dist/bfd/elfn32-mips.c 6211--- dist.orig/bfd/elfn32-mips.c 2012-09-04 16:13:08.000000000 +0200 6212+++ dist/bfd/elfn32-mips.c 2015-10-18 13:11:13.000000000 +0200 6213@@ -81,6 +81,8 @@ 6214 (bfd *, Elf_Internal_Note *); 6215 static bfd_boolean elf32_mips_grok_psinfo 6216 (bfd *, Elf_Internal_Note *); 6217+static bfd_boolean mips_elf_n32_is_local_label_name 6218+ (bfd *, const char *); 6219 static irix_compat_t elf_n32_mips_irix_compat 6220 (bfd *); 6221 6222@@ -3241,6 +3243,17 @@ 6223 return TRUE; 6224 } 6225 6226+/* MIPS ELF local labels start with "$L". */ 6227+static bfd_boolean 6228+mips_elf_n32_is_local_label_name (bfd *abfd, const char *name) 6229+{ 6230+ if (name[0] == '$' && name[1] == 'L') 6231+ return TRUE; 6232+ 6233+ /* We accept the generic ELF local label syntax as well. */ 6234+ return _bfd_elf_is_local_label_name (abfd, name); 6235+} 6236+ 6237 /* Depending on the target vector we generate some version of Irix 6238 executables or "normal" MIPS ELF ABI executables. */ 6239 static irix_compat_t 6240@@ -3364,6 +3377,9 @@ 6241 #define elf_backend_write_section _bfd_mips_elf_write_section 6242 #define elf_backend_mips_irix_compat elf_n32_mips_irix_compat 6243 #define elf_backend_mips_rtype_to_howto mips_elf_n32_rtype_to_howto 6244+ 6245+#define bfd_elf32_bfd_is_local_label_name \ 6246+ mips_elf_n32_is_local_label_name 6247 #define bfd_elf32_bfd_is_target_special_symbol \ 6248 _bfd_mips_elf_is_target_special_symbol 6249 #define bfd_elf32_find_nearest_line _bfd_mips_elf_find_nearest_line 6250diff -rNU3 dist.orig/bfd/elfnn-riscv.c dist/bfd/elfnn-riscv.c 6251--- dist.orig/bfd/elfnn-riscv.c 1970-01-01 01:00:00.000000000 +0100 6252+++ dist/bfd/elfnn-riscv.c 2015-10-18 13:11:13.000000000 +0200 6253@@ -0,0 +1,2957 @@ 6254+/* RISC-V-specific support for NN-bit ELF. 6255+ Copyright 2011-2014 Free Software Foundation, Inc. 6256+ 6257+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 6258+ Based on TILE-Gx and MIPS targets. 6259+ 6260+ This file is part of BFD, the Binary File Descriptor library. 6261+ 6262+ This program is free software; you can redistribute it and/or modify 6263+ it under the terms of the GNU General Public License as published by 6264+ the Free Software Foundation; either version 3 of the License, or 6265+ (at your option) any later version. 6266+ 6267+ This program is distributed in the hope that it will be useful, 6268+ but WITHOUT ANY WARRANTY; without even the implied warranty of 6269+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 6270+ GNU General Public License for more details. 6271+ 6272+ You should have received a copy of the GNU General Public License 6273+ along with this program; if not, write to the Free Software 6274+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 6275+ MA 02110-1301, USA. */ 6276+ 6277+ 6278+/* This file handles RISC-V ELF targets. */ 6279+ 6280+#include "sysdep.h" 6281+#include "bfd.h" 6282+#include "libbfd.h" 6283+#include "bfdlink.h" 6284+#include "genlink.h" 6285+#include "elf-bfd.h" 6286+#include "elfxx-riscv.h" 6287+#include "elf/riscv.h" 6288+#include "opcode/riscv.h" 6289+ 6290+#define ARCH_SIZE NN 6291+ 6292+#define MINUS_ONE ((bfd_vma)0 - 1) 6293+ 6294+#define RISCV_ELF_LOG_WORD_BYTES (ARCH_SIZE == 32 ? 2 : 3) 6295+ 6296+#define RISCV_ELF_WORD_BYTES (1 << RISCV_ELF_LOG_WORD_BYTES) 6297+ 6298+/* The name of the dynamic interpreter. This is put in the .interp 6299+ section. */ 6300+ 6301+#define ELF64_DYNAMIC_INTERPRETER "/lib/ld.so.1" 6302+#define ELF32_DYNAMIC_INTERPRETER "/lib32/ld.so.1" 6303+ 6304+/* The RISC-V linker needs to keep track of the number of relocs that it 6305+ decides to copy as dynamic relocs in check_relocs for each symbol. 6306+ This is so that it can later discard them if they are found to be 6307+ unnecessary. We store the information in a field extending the 6308+ regular ELF linker hash table. */ 6309+ 6310+struct riscv_elf_dyn_relocs 6311+{ 6312+ struct riscv_elf_dyn_relocs *next; 6313+ 6314+ /* The input section of the reloc. */ 6315+ asection *sec; 6316+ 6317+ /* Total number of relocs copied for the input section. */ 6318+ bfd_size_type count; 6319+ 6320+ /* Number of pc-relative relocs copied for the input section. */ 6321+ bfd_size_type pc_count; 6322+}; 6323+ 6324+/* RISC-V ELF linker hash entry. */ 6325+ 6326+struct riscv_elf_link_hash_entry 6327+{ 6328+ struct elf_link_hash_entry elf; 6329+ 6330+ /* Track dynamic relocs copied for this symbol. */ 6331+ struct riscv_elf_dyn_relocs *dyn_relocs; 6332+ 6333+#define GOT_UNKNOWN 0 6334+#define GOT_NORMAL 1 6335+#define GOT_TLS_GD 2 6336+#define GOT_TLS_IE 4 6337+#define GOT_TLS_LE 8 6338+ char tls_type; 6339+}; 6340+ 6341+#define riscv_elf_hash_entry(ent) \ 6342+ ((struct riscv_elf_link_hash_entry *)(ent)) 6343+ 6344+struct _bfd_riscv_elf_obj_tdata 6345+{ 6346+ struct elf_obj_tdata root; 6347+ 6348+ /* tls_type for each local got entry. */ 6349+ char *local_got_tls_type; 6350+}; 6351+ 6352+#define _bfd_riscv_elf_tdata(abfd) \ 6353+ ((struct _bfd_riscv_elf_obj_tdata *) (abfd)->tdata.any) 6354+ 6355+#define _bfd_riscv_elf_local_got_tls_type(abfd) \ 6356+ (_bfd_riscv_elf_tdata (abfd)->local_got_tls_type) 6357+ 6358+#define _bfd_riscv_elf_tls_type(abfd, h, symndx) \ 6359+ (*((h) != NULL ? &riscv_elf_hash_entry(h)->tls_type \ 6360+ : &_bfd_riscv_elf_local_got_tls_type (abfd) [symndx])) 6361+ 6362+#define is_riscv_elf(bfd) \ 6363+ (bfd_get_flavour (bfd) == bfd_target_elf_flavour \ 6364+ && elf_tdata (bfd) != NULL \ 6365+ && elf_object_id (bfd) == RISCV_ELF_DATA) 6366+ 6367+#include "elf/common.h" 6368+#include "elf/internal.h" 6369+ 6370+struct riscv_elf_link_hash_table 6371+{ 6372+ struct elf_link_hash_table elf; 6373+ 6374+ /* Short-cuts to get to dynamic linker sections. */ 6375+ asection *sdynbss; 6376+ asection *srelbss; 6377+ asection *sdyntdata; 6378+ 6379+ /* Small local sym to section mapping cache. */ 6380+ struct sym_cache sym_cache; 6381+}; 6382+ 6383+ 6384+/* Get the RISC-V ELF linker hash table from a link_info structure. */ 6385+#define riscv_elf_hash_table(p) \ 6386+ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \ 6387+ == RISCV_ELF_DATA ? ((struct riscv_elf_link_hash_table *) ((p)->hash)) : NULL) 6388+ 6389+static void 6390+riscv_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED, 6391+ arelent *cache_ptr, 6392+ Elf_Internal_Rela *dst) 6393+{ 6394+ cache_ptr->howto = riscv_elf_rtype_to_howto (ELFNN_R_TYPE (dst->r_info)); 6395+} 6396+ 6397+static void 6398+riscv_elf_append_rela (bfd *abfd, asection *s, Elf_Internal_Rela *rel) 6399+{ 6400+ const struct elf_backend_data *bed; 6401+ bfd_byte *loc; 6402+ 6403+ bed = get_elf_backend_data (abfd); 6404+ loc = s->contents + (s->reloc_count++ * bed->s->sizeof_rela); 6405+ bed->s->swap_reloca_out (abfd, rel, loc); 6406+} 6407+ 6408+/* PLT/GOT stuff */ 6409+ 6410+#define PLT_HEADER_INSNS 8 6411+#define PLT_ENTRY_INSNS 4 6412+#define PLT_HEADER_SIZE (PLT_HEADER_INSNS * 4) 6413+#define PLT_ENTRY_SIZE (PLT_ENTRY_INSNS * 4) 6414+ 6415+#define GOT_ENTRY_SIZE RISCV_ELF_WORD_BYTES 6416+ 6417+#define GOTPLT_HEADER_SIZE (2 * GOT_ENTRY_SIZE) 6418+ 6419+#define sec_addr(sec) ((sec)->output_section->vma + (sec)->output_offset) 6420+ 6421+static bfd_vma 6422+riscv_elf_got_plt_val (bfd_vma plt_index, struct bfd_link_info *info) 6423+{ 6424+ return sec_addr (riscv_elf_hash_table (info)->elf.sgotplt) 6425+ + GOTPLT_HEADER_SIZE + (plt_index * GOT_ENTRY_SIZE); 6426+} 6427+ 6428+#if ARCH_SIZE == 32 6429+# define MATCH_LREG MATCH_LW 6430+#else 6431+# define MATCH_LREG MATCH_LD 6432+#endif 6433+ 6434+/* The format of the first PLT entry. */ 6435+ 6436+static void 6437+riscv_make_plt0_entry(bfd_vma gotplt_addr, bfd_vma addr, uint32_t *entry) 6438+{ 6439+ /* auipc t2, %hi(.got.plt) 6440+ sub t1, t1, t0 # shifted .got.plt offset + hdr size + 12 6441+ l[w|d] t3, %lo(.got.plt)(t2) # _dl_runtime_resolve 6442+ addi t1, t1, -(hdr size + 12) # shifted .got.plt offset 6443+ addi t0, t2, %lo(.got.plt) # &.got.plt 6444+ srli t1, t1, log2(16/PTRSIZE) # .got.plt offset 6445+ l[w|d] t0, PTRSIZE(t0) # link map 6446+ jr t3 */ 6447+ 6448+ entry[0] = RISCV_UTYPE (AUIPC, X_T2, RISCV_PCREL_HIGH_PART (gotplt_addr, addr)); 6449+ entry[1] = RISCV_RTYPE (SUB, X_T1, X_T1, X_T0); 6450+ entry[2] = RISCV_ITYPE (LREG, X_T3, X_T2, RISCV_PCREL_LOW_PART (gotplt_addr, addr)); 6451+ entry[3] = RISCV_ITYPE (ADDI, X_T1, X_T1, -(PLT_HEADER_SIZE + 12)); 6452+ entry[4] = RISCV_ITYPE (ADDI, X_T0, X_T2, RISCV_PCREL_LOW_PART (gotplt_addr, addr)); 6453+ entry[5] = RISCV_ITYPE (SRLI, X_T1, X_T1, 4 - RISCV_ELF_LOG_WORD_BYTES); 6454+ entry[6] = RISCV_ITYPE (LREG, X_T0, X_T0, RISCV_ELF_WORD_BYTES); 6455+ entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0); 6456+} 6457+ 6458+/* The format of subsequent PLT entries. */ 6459+ 6460+static void 6461+riscv_make_plt_entry(bfd_vma got_address, bfd_vma addr, uint32_t *entry) 6462+{ 6463+ /* auipc t1, %hi(.got.plt entry) 6464+ l[w|d] t0, %lo(.got.plt entry)(t1) 6465+ jalr t1, t0 6466+ nop */ 6467+ 6468+ entry[0] = RISCV_UTYPE (AUIPC, X_T1, RISCV_PCREL_HIGH_PART (got_address, addr)); 6469+ entry[1] = RISCV_ITYPE (LREG, X_T0, X_T1, RISCV_PCREL_LOW_PART(got_address, addr)); 6470+ entry[2] = RISCV_ITYPE (JALR, X_T1, X_T0, 0); 6471+ entry[3] = RISCV_NOP; 6472+} 6473+ 6474+/* Create an entry in an RISC-V ELF linker hash table. */ 6475+ 6476+static struct bfd_hash_entry * 6477+link_hash_newfunc (struct bfd_hash_entry *entry, 6478+ struct bfd_hash_table *table, const char *string) 6479+{ 6480+ /* Allocate the structure if it has not already been allocated by a 6481+ subclass. */ 6482+ if (entry == NULL) 6483+ { 6484+ entry = 6485+ bfd_hash_allocate (table, 6486+ sizeof (struct riscv_elf_link_hash_entry)); 6487+ if (entry == NULL) 6488+ return entry; 6489+ } 6490+ 6491+ /* Call the allocation method of the superclass. */ 6492+ entry = _bfd_elf_link_hash_newfunc (entry, table, string); 6493+ if (entry != NULL) 6494+ { 6495+ struct riscv_elf_link_hash_entry *eh; 6496+ 6497+ eh = (struct riscv_elf_link_hash_entry *) entry; 6498+ eh->dyn_relocs = NULL; 6499+ eh->tls_type = GOT_UNKNOWN; 6500+ } 6501+ 6502+ return entry; 6503+} 6504+ 6505+/* Create a RISC-V ELF linker hash table. */ 6506+ 6507+static struct bfd_link_hash_table * 6508+riscv_elf_link_hash_table_create (bfd *abfd) 6509+{ 6510+ struct riscv_elf_link_hash_table *ret; 6511+ bfd_size_type amt = sizeof (struct riscv_elf_link_hash_table); 6512+ 6513+ ret = (struct riscv_elf_link_hash_table *) bfd_zmalloc (amt); 6514+ if (ret == NULL) 6515+ return NULL; 6516+ 6517+ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, 6518+ sizeof (struct riscv_elf_link_hash_entry), 6519+ RISCV_ELF_DATA)) 6520+ { 6521+ free (ret); 6522+ return NULL; 6523+ } 6524+ 6525+ return &ret->elf.root; 6526+} 6527+ 6528+/* Create the .got section. */ 6529+ 6530+static bfd_boolean 6531+riscv_elf_create_got_section (bfd *abfd, struct bfd_link_info *info) 6532+{ 6533+ flagword flags; 6534+ asection *s, *s_got; 6535+ struct elf_link_hash_entry *h; 6536+ const struct elf_backend_data *bed = get_elf_backend_data (abfd); 6537+ struct elf_link_hash_table *htab = elf_hash_table (info); 6538+ 6539+ /* This function may be called more than once. */ 6540+ s = bfd_get_linker_section (abfd, ".got"); 6541+ if (s != NULL) 6542+ return TRUE; 6543+ 6544+ flags = bed->dynamic_sec_flags; 6545+ 6546+ s = bfd_make_section_anyway_with_flags (abfd, 6547+ (bed->rela_plts_and_copies_p 6548+ ? ".rela.got" : ".rel.got"), 6549+ (bed->dynamic_sec_flags 6550+ | SEC_READONLY)); 6551+ if (s == NULL 6552+ || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) 6553+ return FALSE; 6554+ htab->srelgot = s; 6555+ 6556+ s = s_got = bfd_make_section_anyway_with_flags (abfd, ".got", flags); 6557+ if (s == NULL 6558+ || !bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) 6559+ return FALSE; 6560+ htab->sgot = s; 6561+ 6562+ /* The first bit of the global offset table is the header. */ 6563+ s->size += bed->got_header_size; 6564+ 6565+ if (bed->want_got_plt) 6566+ { 6567+ s = bfd_make_section_anyway_with_flags (abfd, ".got.plt", flags); 6568+ if (s == NULL 6569+ || !bfd_set_section_alignment (abfd, s, 6570+ bed->s->log_file_align)) 6571+ return FALSE; 6572+ htab->sgotplt = s; 6573+ 6574+ /* Reserve room for the header. */ 6575+ s->size += GOTPLT_HEADER_SIZE; 6576+ } 6577+ 6578+ if (bed->want_got_sym) 6579+ { 6580+ /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the .got 6581+ section. We don't do this in the linker script because we don't want 6582+ to define the symbol if we are not creating a global offset 6583+ table. */ 6584+ h = _bfd_elf_define_linkage_sym (abfd, info, s_got, 6585+ "_GLOBAL_OFFSET_TABLE_"); 6586+ elf_hash_table (info)->hgot = h; 6587+ if (h == NULL) 6588+ return FALSE; 6589+ } 6590+ 6591+ return TRUE; 6592+} 6593+ 6594+/* Create .plt, .rela.plt, .got, .got.plt, .rela.got, .dynbss, and 6595+ .rela.bss sections in DYNOBJ, and set up shortcuts to them in our 6596+ hash table. */ 6597+ 6598+static bfd_boolean 6599+riscv_elf_create_dynamic_sections (bfd *dynobj, 6600+ struct bfd_link_info *info) 6601+{ 6602+ struct riscv_elf_link_hash_table *htab; 6603+ 6604+ htab = riscv_elf_hash_table (info); 6605+ BFD_ASSERT (htab != NULL); 6606+ 6607+ if (!riscv_elf_create_got_section (dynobj, info)) 6608+ return FALSE; 6609+ 6610+ if (!_bfd_elf_create_dynamic_sections (dynobj, info)) 6611+ return FALSE; 6612+ 6613+ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss"); 6614+ if (!info->shared) 6615+ { 6616+ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss"); 6617+ htab->sdyntdata = 6618+ bfd_make_section_anyway_with_flags (dynobj, ".tdata.dyn", 6619+ SEC_ALLOC | SEC_THREAD_LOCAL); 6620+ } 6621+ 6622+ if (!htab->elf.splt || !htab->elf.srelplt || !htab->sdynbss 6623+ || (!info->shared && (!htab->srelbss || !htab->sdyntdata))) 6624+ abort (); 6625+ 6626+ return TRUE; 6627+} 6628+ 6629+/* Copy the extra info we tack onto an elf_link_hash_entry. */ 6630+ 6631+static void 6632+riscv_elf_copy_indirect_symbol (struct bfd_link_info *info, 6633+ struct elf_link_hash_entry *dir, 6634+ struct elf_link_hash_entry *ind) 6635+{ 6636+ struct riscv_elf_link_hash_entry *edir, *eind; 6637+ 6638+ edir = (struct riscv_elf_link_hash_entry *) dir; 6639+ eind = (struct riscv_elf_link_hash_entry *) ind; 6640+ 6641+ if (eind->dyn_relocs != NULL) 6642+ { 6643+ if (edir->dyn_relocs != NULL) 6644+ { 6645+ struct riscv_elf_dyn_relocs **pp; 6646+ struct riscv_elf_dyn_relocs *p; 6647+ 6648+ /* Add reloc counts against the indirect sym to the direct sym 6649+ list. Merge any entries against the same section. */ 6650+ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) 6651+ { 6652+ struct riscv_elf_dyn_relocs *q; 6653+ 6654+ for (q = edir->dyn_relocs; q != NULL; q = q->next) 6655+ if (q->sec == p->sec) 6656+ { 6657+ q->pc_count += p->pc_count; 6658+ q->count += p->count; 6659+ *pp = p->next; 6660+ break; 6661+ } 6662+ if (q == NULL) 6663+ pp = &p->next; 6664+ } 6665+ *pp = edir->dyn_relocs; 6666+ } 6667+ 6668+ edir->dyn_relocs = eind->dyn_relocs; 6669+ eind->dyn_relocs = NULL; 6670+ } 6671+ 6672+ if (ind->root.type == bfd_link_hash_indirect 6673+ && dir->got.refcount <= 0) 6674+ { 6675+ edir->tls_type = eind->tls_type; 6676+ eind->tls_type = GOT_UNKNOWN; 6677+ } 6678+ _bfd_elf_link_hash_copy_indirect (info, dir, ind); 6679+} 6680+ 6681+static bfd_boolean 6682+riscv_elf_record_tls_type (bfd *abfd, struct elf_link_hash_entry *h, 6683+ unsigned long symndx, char tls_type) 6684+{ 6685+ char *new_tls_type = &_bfd_riscv_elf_tls_type (abfd, h, symndx); 6686+ *new_tls_type |= tls_type; 6687+ if ((*new_tls_type & GOT_NORMAL) && (*new_tls_type & ~GOT_NORMAL)) 6688+ { 6689+ (*_bfd_error_handler) 6690+ (_("%B: `%s' accessed both as normal and thread local symbol"), 6691+ abfd, h ? h->root.root.string : "<local>"); 6692+ return FALSE; 6693+ } 6694+ return TRUE; 6695+} 6696+ 6697+static bfd_boolean 6698+riscv_elf_record_got_reference (bfd *abfd, struct bfd_link_info *info, 6699+ struct elf_link_hash_entry *h, long symndx) 6700+{ 6701+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); 6702+ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 6703+ 6704+ if (htab->elf.sgot == NULL) 6705+ { 6706+ if (!riscv_elf_create_got_section (htab->elf.dynobj, info)) 6707+ return FALSE; 6708+ } 6709+ 6710+ if (h != NULL) 6711+ { 6712+ h->got.refcount += 1; 6713+ return TRUE; 6714+ } 6715+ 6716+ /* This is a global offset table entry for a local symbol. */ 6717+ if (elf_local_got_refcounts (abfd) == NULL) 6718+ { 6719+ bfd_size_type size = symtab_hdr->sh_info * (sizeof (bfd_vma) + 1); 6720+ if (!(elf_local_got_refcounts (abfd) = bfd_zalloc (abfd, size))) 6721+ return FALSE; 6722+ _bfd_riscv_elf_local_got_tls_type (abfd) 6723+ = (char *) (elf_local_got_refcounts (abfd) + symtab_hdr->sh_info); 6724+ } 6725+ elf_local_got_refcounts (abfd) [symndx] += 1; 6726+ 6727+ return TRUE; 6728+} 6729+ 6730+static bfd_boolean 6731+bad_static_reloc (bfd *abfd, unsigned r_type, struct elf_link_hash_entry *h) 6732+{ 6733+ (*_bfd_error_handler) 6734+ (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"), 6735+ abfd, riscv_elf_rtype_to_howto (r_type)->name, 6736+ h != NULL ? h->root.root.string : "a local symbol"); 6737+ bfd_set_error (bfd_error_bad_value); 6738+ return FALSE; 6739+} 6740+/* Look through the relocs for a section during the first phase, and 6741+ allocate space in the global offset table or procedure linkage 6742+ table. */ 6743+ 6744+static bfd_boolean 6745+riscv_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, 6746+ asection *sec, const Elf_Internal_Rela *relocs) 6747+{ 6748+ struct riscv_elf_link_hash_table *htab; 6749+ Elf_Internal_Shdr *symtab_hdr; 6750+ struct elf_link_hash_entry **sym_hashes; 6751+ const Elf_Internal_Rela *rel; 6752+ asection *sreloc = NULL; 6753+ 6754+ if (info->relocatable) 6755+ return TRUE; 6756+ 6757+ htab = riscv_elf_hash_table (info); 6758+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 6759+ sym_hashes = elf_sym_hashes (abfd); 6760+ 6761+ if (htab->elf.dynobj == NULL) 6762+ htab->elf.dynobj = abfd; 6763+ 6764+ for (rel = relocs; rel < relocs + sec->reloc_count; rel++) 6765+ { 6766+ unsigned int r_type; 6767+ unsigned long r_symndx; 6768+ struct elf_link_hash_entry *h; 6769+ 6770+ r_symndx = ELFNN_R_SYM (rel->r_info); 6771+ r_type = ELFNN_R_TYPE (rel->r_info); 6772+ 6773+ if (r_symndx >= NUM_SHDR_ENTRIES (symtab_hdr)) 6774+ { 6775+ (*_bfd_error_handler) (_("%B: bad symbol index: %d"), 6776+ abfd, r_symndx); 6777+ return FALSE; 6778+ } 6779+ 6780+ if (r_symndx < symtab_hdr->sh_info) 6781+ h = NULL; 6782+ else 6783+ { 6784+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; 6785+ while (h->root.type == bfd_link_hash_indirect 6786+ || h->root.type == bfd_link_hash_warning) 6787+ h = (struct elf_link_hash_entry *) h->root.u.i.link; 6788+ 6789+ /* PR15323, ref flags aren't set for references in the same 6790+ object. */ 6791+ h->root.non_ir_ref = 1; 6792+ } 6793+ 6794+ switch (r_type) 6795+ { 6796+ case R_RISCV_TLS_GD_HI20: 6797+ if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx) 6798+ || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_GD)) 6799+ return FALSE; 6800+ break; 6801+ 6802+ case R_RISCV_TLS_GOT_HI20: 6803+ if (info->shared) 6804+ info->flags |= DF_STATIC_TLS; 6805+ if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx) 6806+ || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_IE)) 6807+ return FALSE; 6808+ break; 6809+ 6810+ case R_RISCV_GOT_HI20: 6811+ if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx) 6812+ || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_NORMAL)) 6813+ return FALSE; 6814+ break; 6815+ 6816+ case R_RISCV_CALL_PLT: 6817+ /* This symbol requires a procedure linkage table entry. We 6818+ actually build the entry in adjust_dynamic_symbol, 6819+ because this might be a case of linking PIC code without 6820+ linking in any dynamic objects, in which case we don't 6821+ need to generate a procedure linkage table after all. */ 6822+ 6823+ if (h != NULL) 6824+ { 6825+ h->needs_plt = 1; 6826+ h->plt.refcount += 1; 6827+ } 6828+ break; 6829+ 6830+ case R_RISCV_CALL: 6831+ case R_RISCV_JAL: 6832+ case R_RISCV_BRANCH: 6833+ case R_RISCV_PCREL_HI20: 6834+ /* In shared libs, these relocs are known to bind locally. */ 6835+ if (info->shared) 6836+ break; 6837+ goto static_reloc; 6838+ 6839+ case R_RISCV_TPREL_HI20: 6840+ if (!info->executable) 6841+ return bad_static_reloc (abfd, r_type, h); 6842+ if (h != NULL) 6843+ riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_LE); 6844+ goto static_reloc; 6845+ 6846+ case R_RISCV_HI20: 6847+ if (info->shared) 6848+ return bad_static_reloc (abfd, r_type, h); 6849+ /* Fall through. */ 6850+ 6851+ case R_RISCV_COPY: 6852+ case R_RISCV_JUMP_SLOT: 6853+ case R_RISCV_RELATIVE: 6854+ case R_RISCV_64: 6855+ case R_RISCV_32: 6856+ /* Fall through. */ 6857+ 6858+ static_reloc: 6859+ if (h != NULL) 6860+ h->non_got_ref = 1; 6861+ 6862+ if (h != NULL && !info->shared) 6863+ { 6864+ /* We may need a .plt entry if the function this reloc 6865+ refers to is in a shared lib. */ 6866+ h->plt.refcount += 1; 6867+ } 6868+ 6869+ /* If we are creating a shared library, and this is a reloc 6870+ against a global symbol, or a non PC relative reloc 6871+ against a local symbol, then we need to copy the reloc 6872+ into the shared library. However, if we are linking with 6873+ -Bsymbolic, we do not need to copy a reloc against a 6874+ global symbol which is defined in an object we are 6875+ including in the link (i.e., DEF_REGULAR is set). At 6876+ this point we have not seen all the input files, so it is 6877+ possible that DEF_REGULAR is not set now but will be set 6878+ later (it is never cleared). In case of a weak definition, 6879+ DEF_REGULAR may be cleared later by a strong definition in 6880+ a shared library. We account for that possibility below by 6881+ storing information in the relocs_copied field of the hash 6882+ table entry. A similar situation occurs when creating 6883+ shared libraries and symbol visibility changes render the 6884+ symbol local. 6885+ 6886+ If on the other hand, we are creating an executable, we 6887+ may need to keep relocations for symbols satisfied by a 6888+ dynamic library if we manage to avoid copy relocs for the 6889+ symbol. */ 6890+ if ((info->shared 6891+ && (sec->flags & SEC_ALLOC) != 0 6892+ && (! riscv_elf_rtype_to_howto (r_type)->pc_relative 6893+ || (h != NULL 6894+ && (! info->symbolic 6895+ || h->root.type == bfd_link_hash_defweak 6896+ || !h->def_regular)))) 6897+ || (!info->shared 6898+ && (sec->flags & SEC_ALLOC) != 0 6899+ && h != NULL 6900+ && (h->root.type == bfd_link_hash_defweak 6901+ || !h->def_regular))) 6902+ { 6903+ struct riscv_elf_dyn_relocs *p; 6904+ struct riscv_elf_dyn_relocs **head; 6905+ 6906+ /* When creating a shared object, we must copy these 6907+ relocs into the output file. We create a reloc 6908+ section in dynobj and make room for the reloc. */ 6909+ if (sreloc == NULL) 6910+ { 6911+ sreloc = _bfd_elf_make_dynamic_reloc_section 6912+ (sec, htab->elf.dynobj, RISCV_ELF_LOG_WORD_BYTES, 6913+ abfd, /*rela?*/ TRUE); 6914+ 6915+ if (sreloc == NULL) 6916+ return FALSE; 6917+ } 6918+ 6919+ /* If this is a global symbol, we count the number of 6920+ relocations we need for this symbol. */ 6921+ if (h != NULL) 6922+ head = &((struct riscv_elf_link_hash_entry *) h)->dyn_relocs; 6923+ else 6924+ { 6925+ /* Track dynamic relocs needed for local syms too. 6926+ We really need local syms available to do this 6927+ easily. Oh well. */ 6928+ 6929+ asection *s; 6930+ void *vpp; 6931+ Elf_Internal_Sym *isym; 6932+ 6933+ isym = bfd_sym_from_r_symndx (&htab->sym_cache, 6934+ abfd, r_symndx); 6935+ if (isym == NULL) 6936+ return FALSE; 6937+ 6938+ s = bfd_section_from_elf_index (abfd, isym->st_shndx); 6939+ if (s == NULL) 6940+ s = sec; 6941+ 6942+ vpp = &elf_section_data (s)->local_dynrel; 6943+ head = (struct riscv_elf_dyn_relocs **) vpp; 6944+ } 6945+ 6946+ p = *head; 6947+ if (p == NULL || p->sec != sec) 6948+ { 6949+ bfd_size_type amt = sizeof *p; 6950+ p = ((struct riscv_elf_dyn_relocs *) 6951+ bfd_alloc (htab->elf.dynobj, amt)); 6952+ if (p == NULL) 6953+ return FALSE; 6954+ p->next = *head; 6955+ *head = p; 6956+ p->sec = sec; 6957+ p->count = 0; 6958+ p->pc_count = 0; 6959+ } 6960+ 6961+ p->count += 1; 6962+ p->pc_count += riscv_elf_rtype_to_howto (r_type)->pc_relative; 6963+ } 6964+ 6965+ break; 6966+ 6967+ case R_RISCV_GNU_VTINHERIT: 6968+ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) 6969+ return FALSE; 6970+ break; 6971+ 6972+ case R_RISCV_GNU_VTENTRY: 6973+ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) 6974+ return FALSE; 6975+ break; 6976+ 6977+ default: 6978+ break; 6979+ } 6980+ } 6981+ 6982+ return TRUE; 6983+} 6984+ 6985+static asection * 6986+riscv_elf_gc_mark_hook (asection *sec, 6987+ struct bfd_link_info *info, 6988+ Elf_Internal_Rela *rel, 6989+ struct elf_link_hash_entry *h, 6990+ Elf_Internal_Sym *sym) 6991+{ 6992+ if (h != NULL) 6993+ switch (ELFNN_R_TYPE (rel->r_info)) 6994+ { 6995+ case R_RISCV_GNU_VTINHERIT: 6996+ case R_RISCV_GNU_VTENTRY: 6997+ return NULL; 6998+ } 6999+ 7000+ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); 7001+} 7002+ 7003+/* Update the got entry reference counts for the section being removed. */ 7004+static bfd_boolean 7005+riscv_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info, 7006+ asection *sec, const Elf_Internal_Rela *relocs) 7007+{ 7008+ const Elf_Internal_Rela *rel, *relend; 7009+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); 7010+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd); 7011+ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd); 7012+ 7013+ if (info->relocatable) 7014+ return TRUE; 7015+ 7016+ elf_section_data (sec)->local_dynrel = NULL; 7017+ 7018+ for (rel = relocs, relend = relocs + sec->reloc_count; rel < relend; rel++) 7019+ { 7020+ unsigned long r_symndx; 7021+ struct elf_link_hash_entry *h = NULL; 7022+ 7023+ r_symndx = ELFNN_R_SYM (rel->r_info); 7024+ if (r_symndx >= symtab_hdr->sh_info) 7025+ { 7026+ struct riscv_elf_link_hash_entry *eh; 7027+ struct riscv_elf_dyn_relocs **pp; 7028+ struct riscv_elf_dyn_relocs *p; 7029+ 7030+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; 7031+ while (h->root.type == bfd_link_hash_indirect 7032+ || h->root.type == bfd_link_hash_warning) 7033+ h = (struct elf_link_hash_entry *) h->root.u.i.link; 7034+ eh = (struct riscv_elf_link_hash_entry *) h; 7035+ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next) 7036+ if (p->sec == sec) 7037+ { 7038+ /* Everything must go for SEC. */ 7039+ *pp = p->next; 7040+ break; 7041+ } 7042+ } 7043+ 7044+ switch (ELFNN_R_TYPE (rel->r_info)) 7045+ { 7046+ case R_RISCV_GOT_HI20: 7047+ case R_RISCV_TLS_GOT_HI20: 7048+ case R_RISCV_TLS_GD_HI20: 7049+ if (h != NULL) 7050+ { 7051+ if (h->got.refcount > 0) 7052+ h->got.refcount--; 7053+ } 7054+ else 7055+ { 7056+ if (local_got_refcounts && 7057+ local_got_refcounts[r_symndx] > 0) 7058+ local_got_refcounts[r_symndx]--; 7059+ } 7060+ break; 7061+ 7062+ case R_RISCV_HI20: 7063+ case R_RISCV_PCREL_HI20: 7064+ case R_RISCV_COPY: 7065+ case R_RISCV_JUMP_SLOT: 7066+ case R_RISCV_RELATIVE: 7067+ case R_RISCV_64: 7068+ case R_RISCV_32: 7069+ case R_RISCV_BRANCH: 7070+ case R_RISCV_CALL: 7071+ case R_RISCV_JAL: 7072+ if (info->shared) 7073+ break; 7074+ /* Fall through. */ 7075+ 7076+ case R_RISCV_CALL_PLT: 7077+ if (h != NULL) 7078+ { 7079+ if (h->plt.refcount > 0) 7080+ h->plt.refcount--; 7081+ } 7082+ break; 7083+ 7084+ default: 7085+ break; 7086+ } 7087+ } 7088+ 7089+ return TRUE; 7090+} 7091+ 7092+/* Adjust a symbol defined by a dynamic object and referenced by a 7093+ regular object. The current definition is in some section of the 7094+ dynamic object, but we're not including those sections. We have to 7095+ change the definition to something the rest of the link can 7096+ understand. */ 7097+ 7098+static bfd_boolean 7099+riscv_elf_adjust_dynamic_symbol (struct bfd_link_info *info, 7100+ struct elf_link_hash_entry *h) 7101+{ 7102+ struct riscv_elf_link_hash_table *htab; 7103+ struct riscv_elf_link_hash_entry * eh; 7104+ struct riscv_elf_dyn_relocs *p; 7105+ bfd *dynobj; 7106+ asection *s; 7107+ 7108+ htab = riscv_elf_hash_table (info); 7109+ BFD_ASSERT (htab != NULL); 7110+ 7111+ dynobj = htab->elf.dynobj; 7112+ 7113+ /* Make sure we know what is going on here. */ 7114+ BFD_ASSERT (dynobj != NULL 7115+ && (h->needs_plt 7116+ || h->type == STT_GNU_IFUNC 7117+ || h->u.weakdef != NULL 7118+ || (h->def_dynamic 7119+ && h->ref_regular 7120+ && !h->def_regular))); 7121+ 7122+ /* If this is a function, put it in the procedure linkage table. We 7123+ will fill in the contents of the procedure linkage table later 7124+ (although we could actually do it here). */ 7125+ if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt) 7126+ { 7127+ if (h->plt.refcount <= 0 7128+ || SYMBOL_CALLS_LOCAL (info, h) 7129+ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT 7130+ && h->root.type == bfd_link_hash_undefweak)) 7131+ { 7132+ /* This case can occur if we saw a R_RISCV_CALL_PLT reloc in an 7133+ input file, but the symbol was never referred to by a dynamic 7134+ object, or if all references were garbage collected. In such 7135+ a case, we don't actually need to build a PLT entry. */ 7136+ h->plt.offset = (bfd_vma) -1; 7137+ h->needs_plt = 0; 7138+ } 7139+ 7140+ return TRUE; 7141+ } 7142+ else 7143+ h->plt.offset = (bfd_vma) -1; 7144+ 7145+ /* If this is a weak symbol, and there is a real definition, the 7146+ processor independent code will have arranged for us to see the 7147+ real definition first, and we can just use the same value. */ 7148+ if (h->u.weakdef != NULL) 7149+ { 7150+ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined 7151+ || h->u.weakdef->root.type == bfd_link_hash_defweak); 7152+ h->root.u.def.section = h->u.weakdef->root.u.def.section; 7153+ h->root.u.def.value = h->u.weakdef->root.u.def.value; 7154+ return TRUE; 7155+ } 7156+ 7157+ /* This is a reference to a symbol defined by a dynamic object which 7158+ is not a function. */ 7159+ 7160+ /* If we are creating a shared library, we must presume that the 7161+ only references to the symbol are via the global offset table. 7162+ For such cases we need not do anything here; the relocations will 7163+ be handled correctly by relocate_section. */ 7164+ if (info->shared) 7165+ return TRUE; 7166+ 7167+ /* If there are no references to this symbol that do not use the 7168+ GOT, we don't need to generate a copy reloc. */ 7169+ if (!h->non_got_ref) 7170+ return TRUE; 7171+ 7172+ /* If -z nocopyreloc was given, we won't generate them either. */ 7173+ if (info->nocopyreloc) 7174+ { 7175+ h->non_got_ref = 0; 7176+ return TRUE; 7177+ } 7178+ 7179+ eh = (struct riscv_elf_link_hash_entry *) h; 7180+ for (p = eh->dyn_relocs; p != NULL; p = p->next) 7181+ { 7182+ s = p->sec->output_section; 7183+ if (s != NULL && (s->flags & SEC_READONLY) != 0) 7184+ break; 7185+ } 7186+ 7187+ /* If we didn't find any dynamic relocs in read-only sections, then 7188+ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ 7189+ if (p == NULL) 7190+ { 7191+ h->non_got_ref = 0; 7192+ return TRUE; 7193+ } 7194+ 7195+ /* We must allocate the symbol in our .dynbss section, which will 7196+ become part of the .bss section of the executable. There will be 7197+ an entry for this symbol in the .dynsym section. The dynamic 7198+ object will contain position independent code, so all references 7199+ from the dynamic object to this symbol will go through the global 7200+ offset table. The dynamic linker will use the .dynsym entry to 7201+ determine the address it must put in the global offset table, so 7202+ both the dynamic object and the regular object will refer to the 7203+ same memory location for the variable. */ 7204+ 7205+ /* We must generate a R_RISCV_COPY reloc to tell the dynamic linker 7206+ to copy the initial value out of the dynamic object and into the 7207+ runtime process image. We need to remember the offset into the 7208+ .rel.bss section we are going to use. */ 7209+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0) 7210+ { 7211+ htab->srelbss->size += sizeof (ElfNN_External_Rela); 7212+ h->needs_copy = 1; 7213+ } 7214+ 7215+ if (eh->tls_type & ~GOT_NORMAL) 7216+ return _bfd_elf_adjust_dynamic_copy (h, htab->sdyntdata); 7217+ 7218+ return _bfd_elf_adjust_dynamic_copy (h, htab->sdynbss); 7219+} 7220+ 7221+/* Allocate space in .plt, .got and associated reloc sections for 7222+ dynamic relocs. */ 7223+ 7224+static bfd_boolean 7225+allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) 7226+{ 7227+ struct bfd_link_info *info; 7228+ struct riscv_elf_link_hash_table *htab; 7229+ struct riscv_elf_link_hash_entry *eh; 7230+ struct riscv_elf_dyn_relocs *p; 7231+ 7232+ if (h->root.type == bfd_link_hash_indirect) 7233+ return TRUE; 7234+ 7235+ info = (struct bfd_link_info *) inf; 7236+ htab = riscv_elf_hash_table (info); 7237+ BFD_ASSERT (htab != NULL); 7238+ 7239+ if (htab->elf.dynamic_sections_created 7240+ && h->plt.refcount > 0) 7241+ { 7242+ /* Make sure this symbol is output as a dynamic symbol. 7243+ Undefined weak syms won't yet be marked as dynamic. */ 7244+ if (h->dynindx == -1 7245+ && !h->forced_local) 7246+ { 7247+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 7248+ return FALSE; 7249+ } 7250+ 7251+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info->shared, h)) 7252+ { 7253+ asection *s = htab->elf.splt; 7254+ 7255+ if (s->size == 0) 7256+ s->size = PLT_HEADER_SIZE; 7257+ 7258+ h->plt.offset = s->size; 7259+ 7260+ /* Make room for this entry. */ 7261+ s->size += PLT_ENTRY_SIZE; 7262+ 7263+ /* We also need to make an entry in the .got.plt section. */ 7264+ htab->elf.sgotplt->size += GOT_ENTRY_SIZE; 7265+ 7266+ /* We also need to make an entry in the .rela.plt section. */ 7267+ htab->elf.srelplt->size += sizeof (ElfNN_External_Rela); 7268+ 7269+ /* If this symbol is not defined in a regular file, and we are 7270+ not generating a shared library, then set the symbol to this 7271+ location in the .plt. This is required to make function 7272+ pointers compare as equal between the normal executable and 7273+ the shared library. */ 7274+ if (! info->shared 7275+ && !h->def_regular) 7276+ { 7277+ h->root.u.def.section = s; 7278+ h->root.u.def.value = h->plt.offset; 7279+ } 7280+ } 7281+ else 7282+ { 7283+ h->plt.offset = (bfd_vma) -1; 7284+ h->needs_plt = 0; 7285+ } 7286+ } 7287+ else 7288+ { 7289+ h->plt.offset = (bfd_vma) -1; 7290+ h->needs_plt = 0; 7291+ } 7292+ 7293+ if (h->got.refcount > 0) 7294+ { 7295+ asection *s; 7296+ bfd_boolean dyn; 7297+ int tls_type = riscv_elf_hash_entry(h)->tls_type; 7298+ 7299+ /* Make sure this symbol is output as a dynamic symbol. 7300+ Undefined weak syms won't yet be marked as dynamic. */ 7301+ if (h->dynindx == -1 7302+ && !h->forced_local) 7303+ { 7304+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 7305+ return FALSE; 7306+ } 7307+ 7308+ s = htab->elf.sgot; 7309+ h->got.offset = s->size; 7310+ dyn = htab->elf.dynamic_sections_created; 7311+ if (tls_type & (GOT_TLS_GD | GOT_TLS_IE)) 7312+ { 7313+ /* TLS_GD needs two dynamic relocs and two GOT slots. */ 7314+ if (tls_type & GOT_TLS_GD) 7315+ { 7316+ s->size += 2 * RISCV_ELF_WORD_BYTES; 7317+ htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); 7318+ } 7319+ 7320+ /* TLS_IE needs one dynamic reloc and one GOT slot. */ 7321+ if (tls_type & GOT_TLS_IE) 7322+ { 7323+ s->size += RISCV_ELF_WORD_BYTES; 7324+ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); 7325+ } 7326+ } 7327+ else 7328+ { 7329+ s->size += RISCV_ELF_WORD_BYTES; 7330+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)) 7331+ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); 7332+ } 7333+ } 7334+ else 7335+ h->got.offset = (bfd_vma) -1; 7336+ 7337+ eh = (struct riscv_elf_link_hash_entry *) h; 7338+ if (eh->dyn_relocs == NULL) 7339+ return TRUE; 7340+ 7341+ /* In the shared -Bsymbolic case, discard space allocated for 7342+ dynamic pc-relative relocs against symbols which turn out to be 7343+ defined in regular objects. For the normal shared case, discard 7344+ space for pc-relative relocs that have become local due to symbol 7345+ visibility changes. */ 7346+ 7347+ if (info->shared) 7348+ { 7349+ if (SYMBOL_CALLS_LOCAL (info, h)) 7350+ { 7351+ struct riscv_elf_dyn_relocs **pp; 7352+ 7353+ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) 7354+ { 7355+ p->count -= p->pc_count; 7356+ p->pc_count = 0; 7357+ if (p->count == 0) 7358+ *pp = p->next; 7359+ else 7360+ pp = &p->next; 7361+ } 7362+ } 7363+ 7364+ /* Also discard relocs on undefined weak syms with non-default 7365+ visibility. */ 7366+ if (eh->dyn_relocs != NULL 7367+ && h->root.type == bfd_link_hash_undefweak) 7368+ { 7369+ if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT) 7370+ eh->dyn_relocs = NULL; 7371+ 7372+ /* Make sure undefined weak symbols are output as a dynamic 7373+ symbol in PIEs. */ 7374+ else if (h->dynindx == -1 7375+ && !h->forced_local) 7376+ { 7377+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 7378+ return FALSE; 7379+ } 7380+ } 7381+ } 7382+ else 7383+ { 7384+ /* For the non-shared case, discard space for relocs against 7385+ symbols which turn out to need copy relocs or are not 7386+ dynamic. */ 7387+ 7388+ if (!h->non_got_ref 7389+ && ((h->def_dynamic 7390+ && !h->def_regular) 7391+ || (htab->elf.dynamic_sections_created 7392+ && (h->root.type == bfd_link_hash_undefweak 7393+ || h->root.type == bfd_link_hash_undefined)))) 7394+ { 7395+ /* Make sure this symbol is output as a dynamic symbol. 7396+ Undefined weak syms won't yet be marked as dynamic. */ 7397+ if (h->dynindx == -1 7398+ && !h->forced_local) 7399+ { 7400+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) 7401+ return FALSE; 7402+ } 7403+ 7404+ /* If that succeeded, we know we'll be keeping all the 7405+ relocs. */ 7406+ if (h->dynindx != -1) 7407+ goto keep; 7408+ } 7409+ 7410+ eh->dyn_relocs = NULL; 7411+ 7412+ keep: ; 7413+ } 7414+ 7415+ /* Finally, allocate space. */ 7416+ for (p = eh->dyn_relocs; p != NULL; p = p->next) 7417+ { 7418+ asection *sreloc = elf_section_data (p->sec)->sreloc; 7419+ sreloc->size += p->count * sizeof (ElfNN_External_Rela); 7420+ } 7421+ 7422+ return TRUE; 7423+} 7424+ 7425+/* Find any dynamic relocs that apply to read-only sections. */ 7426+ 7427+static bfd_boolean 7428+readonly_dynrelocs (struct elf_link_hash_entry *h, void *inf) 7429+{ 7430+ struct riscv_elf_link_hash_entry *eh; 7431+ struct riscv_elf_dyn_relocs *p; 7432+ 7433+ eh = (struct riscv_elf_link_hash_entry *) h; 7434+ for (p = eh->dyn_relocs; p != NULL; p = p->next) 7435+ { 7436+ asection *s = p->sec->output_section; 7437+ 7438+ if (s != NULL && (s->flags & SEC_READONLY) != 0) 7439+ { 7440+ ((struct bfd_link_info *) inf)->flags |= DF_TEXTREL; 7441+ 7442+ /* Short-circuit the traversal. */ 7443+ return FALSE; 7444+ } 7445+ } 7446+ return TRUE; 7447+} 7448+ 7449+static bfd_boolean 7450+riscv_elf_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) 7451+{ 7452+ struct riscv_elf_link_hash_table *htab; 7453+ bfd *dynobj; 7454+ asection *s; 7455+ bfd *ibfd; 7456+ 7457+ htab = riscv_elf_hash_table (info); 7458+ BFD_ASSERT (htab != NULL); 7459+ dynobj = htab->elf.dynobj; 7460+ BFD_ASSERT (dynobj != NULL); 7461+ 7462+ if (elf_hash_table (info)->dynamic_sections_created) 7463+ { 7464+ /* Set the contents of the .interp section to the interpreter. */ 7465+ if (info->executable) 7466+ { 7467+ s = bfd_get_linker_section (dynobj, ".interp"); 7468+ BFD_ASSERT (s != NULL); 7469+ s->size = strlen (ELFNN_DYNAMIC_INTERPRETER) + 1; 7470+ s->contents = (unsigned char *) ELFNN_DYNAMIC_INTERPRETER; 7471+ } 7472+ } 7473+ 7474+ /* Set up .got offsets for local syms, and space for local dynamic 7475+ relocs. */ 7476+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next) 7477+ { 7478+ bfd_signed_vma *local_got; 7479+ bfd_signed_vma *end_local_got; 7480+ char *local_tls_type; 7481+ bfd_size_type locsymcount; 7482+ Elf_Internal_Shdr *symtab_hdr; 7483+ asection *srel; 7484+ 7485+ if (! is_riscv_elf (ibfd)) 7486+ continue; 7487+ 7488+ for (s = ibfd->sections; s != NULL; s = s->next) 7489+ { 7490+ struct riscv_elf_dyn_relocs *p; 7491+ 7492+ for (p = elf_section_data (s)->local_dynrel; p != NULL; p = p->next) 7493+ { 7494+ if (!bfd_is_abs_section (p->sec) 7495+ && bfd_is_abs_section (p->sec->output_section)) 7496+ { 7497+ /* Input section has been discarded, either because 7498+ it is a copy of a linkonce section or due to 7499+ linker script /DISCARD/, so we'll be discarding 7500+ the relocs too. */ 7501+ } 7502+ else if (p->count != 0) 7503+ { 7504+ srel = elf_section_data (p->sec)->sreloc; 7505+ srel->size += p->count * sizeof (ElfNN_External_Rela); 7506+ if ((p->sec->output_section->flags & SEC_READONLY) != 0) 7507+ info->flags |= DF_TEXTREL; 7508+ } 7509+ } 7510+ } 7511+ 7512+ local_got = elf_local_got_refcounts (ibfd); 7513+ if (!local_got) 7514+ continue; 7515+ 7516+ symtab_hdr = &elf_symtab_hdr (ibfd); 7517+ locsymcount = symtab_hdr->sh_info; 7518+ end_local_got = local_got + locsymcount; 7519+ local_tls_type = _bfd_riscv_elf_local_got_tls_type (ibfd); 7520+ s = htab->elf.sgot; 7521+ srel = htab->elf.srelgot; 7522+ for (; local_got < end_local_got; ++local_got, ++local_tls_type) 7523+ { 7524+ if (*local_got > 0) 7525+ { 7526+ *local_got = s->size; 7527+ s->size += RISCV_ELF_WORD_BYTES; 7528+ if (*local_tls_type & GOT_TLS_GD) 7529+ s->size += RISCV_ELF_WORD_BYTES; 7530+ if (info->shared 7531+ || (*local_tls_type & (GOT_TLS_GD | GOT_TLS_IE))) 7532+ srel->size += sizeof (ElfNN_External_Rela); 7533+ } 7534+ else 7535+ *local_got = (bfd_vma) -1; 7536+ } 7537+ } 7538+ 7539+ /* Allocate global sym .plt and .got entries, and space for global 7540+ sym dynamic relocs. */ 7541+ elf_link_hash_traverse (&htab->elf, allocate_dynrelocs, info); 7542+ 7543+ if (htab->elf.sgotplt) 7544+ { 7545+ struct elf_link_hash_entry *got; 7546+ got = elf_link_hash_lookup (elf_hash_table (info), 7547+ "_GLOBAL_OFFSET_TABLE_", 7548+ FALSE, FALSE, FALSE); 7549+ 7550+ /* Don't allocate .got.plt section if there are no GOT nor PLT 7551+ entries and there is no refeence to _GLOBAL_OFFSET_TABLE_. */ 7552+ if ((got == NULL 7553+ || !got->ref_regular_nonweak) 7554+ && (htab->elf.sgotplt->size == GOTPLT_HEADER_SIZE) 7555+ && (htab->elf.splt == NULL 7556+ || htab->elf.splt->size == 0) 7557+ && (htab->elf.sgot == NULL 7558+ || (htab->elf.sgot->size 7559+ == get_elf_backend_data (output_bfd)->got_header_size))) 7560+ htab->elf.sgotplt->size = 0; 7561+ } 7562+ 7563+ /* The check_relocs and adjust_dynamic_symbol entry points have 7564+ determined the sizes of the various dynamic sections. Allocate 7565+ memory for them. */ 7566+ for (s = dynobj->sections; s != NULL; s = s->next) 7567+ { 7568+ if ((s->flags & SEC_LINKER_CREATED) == 0) 7569+ continue; 7570+ 7571+ if (s == htab->elf.splt 7572+ || s == htab->elf.sgot 7573+ || s == htab->elf.sgotplt 7574+ || s == htab->sdynbss) 7575+ { 7576+ /* Strip this section if we don't need it; see the 7577+ comment below. */ 7578+ } 7579+ else if (strncmp (s->name, ".rela", 5) == 0) 7580+ { 7581+ if (s->size != 0) 7582+ { 7583+ /* We use the reloc_count field as a counter if we need 7584+ to copy relocs into the output file. */ 7585+ s->reloc_count = 0; 7586+ } 7587+ } 7588+ else 7589+ { 7590+ /* It's not one of our sections. */ 7591+ continue; 7592+ } 7593+ 7594+ if (s->size == 0) 7595+ { 7596+ /* If we don't need this section, strip it from the 7597+ output file. This is mostly to handle .rela.bss and 7598+ .rela.plt. We must create both sections in 7599+ create_dynamic_sections, because they must be created 7600+ before the linker maps input sections to output 7601+ sections. The linker does that before 7602+ adjust_dynamic_symbol is called, and it is that 7603+ function which decides whether anything needs to go 7604+ into these sections. */ 7605+ s->flags |= SEC_EXCLUDE; 7606+ continue; 7607+ } 7608+ 7609+ if ((s->flags & SEC_HAS_CONTENTS) == 0) 7610+ continue; 7611+ 7612+ /* Allocate memory for the section contents. Zero the memory 7613+ for the benefit of .rela.plt, which has 4 unused entries 7614+ at the beginning, and we don't want garbage. */ 7615+ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); 7616+ if (s->contents == NULL) 7617+ return FALSE; 7618+ } 7619+ 7620+ if (elf_hash_table (info)->dynamic_sections_created) 7621+ { 7622+ /* Add some entries to the .dynamic section. We fill in the 7623+ values later, in riscv_elf_finish_dynamic_sections, but we 7624+ must add the entries now so that we get the correct size for 7625+ the .dynamic section. The DT_DEBUG entry is filled in by the 7626+ dynamic linker and used by the debugger. */ 7627+#define add_dynamic_entry(TAG, VAL) \ 7628+ _bfd_elf_add_dynamic_entry (info, TAG, VAL) 7629+ 7630+ if (info->executable) 7631+ { 7632+ if (!add_dynamic_entry (DT_DEBUG, 0)) 7633+ return FALSE; 7634+ } 7635+ 7636+ if (htab->elf.srelplt->size != 0) 7637+ { 7638+ if (!add_dynamic_entry (DT_PLTGOT, 0) 7639+ || !add_dynamic_entry (DT_PLTRELSZ, 0) 7640+ || !add_dynamic_entry (DT_PLTREL, DT_RELA) 7641+ || !add_dynamic_entry (DT_JMPREL, 0)) 7642+ return FALSE; 7643+ } 7644+ 7645+ if (!add_dynamic_entry (DT_RELA, 0) 7646+ || !add_dynamic_entry (DT_RELASZ, 0) 7647+ || !add_dynamic_entry (DT_RELAENT, sizeof (ElfNN_External_Rela))) 7648+ return FALSE; 7649+ 7650+ /* If any dynamic relocs apply to a read-only section, 7651+ then we need a DT_TEXTREL entry. */ 7652+ if ((info->flags & DF_TEXTREL) == 0) 7653+ elf_link_hash_traverse (&htab->elf, readonly_dynrelocs, info); 7654+ 7655+ if (info->flags & DF_TEXTREL) 7656+ { 7657+ if (!add_dynamic_entry (DT_TEXTREL, 0)) 7658+ return FALSE; 7659+ } 7660+ } 7661+#undef add_dynamic_entry 7662+ 7663+ return TRUE; 7664+} 7665+ 7666+#define TP_OFFSET 0 7667+#define DTP_OFFSET 0x800 7668+ 7669+/* Return the relocation value for a TLS dtp-relative reloc. */ 7670+ 7671+static bfd_vma 7672+dtpoff (struct bfd_link_info *info, bfd_vma address) 7673+{ 7674+ /* If tls_sec is NULL, we should have signalled an error already. */ 7675+ if (elf_hash_table (info)->tls_sec == NULL) 7676+ return 0; 7677+ return address - elf_hash_table (info)->tls_sec->vma - DTP_OFFSET; 7678+} 7679+ 7680+/* Return the relocation value for a static TLS tp-relative relocation. */ 7681+ 7682+static bfd_vma 7683+tpoff (struct bfd_link_info *info, bfd_vma address) 7684+{ 7685+ /* If tls_sec is NULL, we should have signalled an error already. */ 7686+ if (elf_hash_table (info)->tls_sec == NULL) 7687+ return 0; 7688+ return address - elf_hash_table (info)->tls_sec->vma - TP_OFFSET; 7689+} 7690+ 7691+/* Return the global pointer's value, or 0 if it is not in use. */ 7692+ 7693+static bfd_vma 7694+riscv_global_pointer_value (struct bfd_link_info *info) 7695+{ 7696+ struct bfd_link_hash_entry *h; 7697+ 7698+ h = bfd_link_hash_lookup (info->hash, "_gp", FALSE, FALSE, TRUE); 7699+ if (h == NULL || h->type != bfd_link_hash_defined) 7700+ return 0; 7701+ 7702+ return h->u.def.value + sec_addr (h->u.def.section); 7703+} 7704+ 7705+/* Emplace a static relocation. */ 7706+ 7707+static bfd_reloc_status_type 7708+perform_relocation (const reloc_howto_type *howto, 7709+ const Elf_Internal_Rela *rel, 7710+ bfd_vma value, 7711+ asection *input_section, 7712+ bfd *input_bfd, 7713+ bfd_byte *contents) 7714+{ 7715+ if (howto->pc_relative) 7716+ value -= sec_addr (input_section) + rel->r_offset; 7717+ value += rel->r_addend; 7718+ 7719+ switch (ELFNN_R_TYPE (rel->r_info)) 7720+ { 7721+ case R_RISCV_HI20: 7722+ case R_RISCV_TPREL_HI20: 7723+ case R_RISCV_PCREL_HI20: 7724+ case R_RISCV_GOT_HI20: 7725+ case R_RISCV_TLS_GOT_HI20: 7726+ case R_RISCV_TLS_GD_HI20: 7727+ value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); 7728+ break; 7729+ 7730+ case R_RISCV_LO12_I: 7731+ case R_RISCV_TPREL_LO12_I: 7732+ case R_RISCV_PCREL_LO12_I: 7733+ value = ENCODE_ITYPE_IMM (value); 7734+ break; 7735+ 7736+ case R_RISCV_LO12_S: 7737+ case R_RISCV_TPREL_LO12_S: 7738+ case R_RISCV_PCREL_LO12_S: 7739+ value = ENCODE_STYPE_IMM (value); 7740+ break; 7741+ 7742+ case R_RISCV_CALL: 7743+ case R_RISCV_CALL_PLT: 7744+ if (!VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))) 7745+ return bfd_reloc_overflow; 7746+ value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)) 7747+ | (ENCODE_ITYPE_IMM (value) << 32); 7748+ break; 7749+ 7750+ case R_RISCV_JAL: 7751+ if (!VALID_UJTYPE_IMM (value)) 7752+ return bfd_reloc_overflow; 7753+ value = ENCODE_UJTYPE_IMM (value); 7754+ break; 7755+ 7756+ case R_RISCV_BRANCH: 7757+ if (!VALID_SBTYPE_IMM (value)) 7758+ return bfd_reloc_overflow; 7759+ value = ENCODE_SBTYPE_IMM (value); 7760+ break; 7761+ 7762+ case R_RISCV_32: 7763+ case R_RISCV_64: 7764+ case R_RISCV_ADD8: 7765+ case R_RISCV_ADD16: 7766+ case R_RISCV_ADD32: 7767+ case R_RISCV_ADD64: 7768+ case R_RISCV_SUB8: 7769+ case R_RISCV_SUB16: 7770+ case R_RISCV_SUB32: 7771+ case R_RISCV_SUB64: 7772+ case R_RISCV_TLS_DTPREL32: 7773+ case R_RISCV_TLS_DTPREL64: 7774+ break; 7775+ 7776+ default: 7777+ return bfd_reloc_notsupported; 7778+ } 7779+ 7780+ bfd_vma word = bfd_get (howto->bitsize, input_bfd, contents + rel->r_offset); 7781+ word = (word & ~howto->dst_mask) | (value & howto->dst_mask); 7782+ bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset); 7783+ 7784+ return bfd_reloc_ok; 7785+} 7786+ 7787+/* Remember all PC-relative high-part relocs we've encountered to help us 7788+ later resolve the corresponding low-part relocs. */ 7789+ 7790+typedef struct { 7791+ bfd_vma address; 7792+ bfd_vma value; 7793+} riscv_pcrel_hi_reloc; 7794+ 7795+typedef struct riscv_pcrel_lo_reloc { 7796+ asection *input_section; 7797+ struct bfd_link_info *info; 7798+ reloc_howto_type *howto; 7799+ const Elf_Internal_Rela *reloc; 7800+ bfd_vma addr; 7801+ const char *name; 7802+ bfd_byte *contents; 7803+ struct riscv_pcrel_lo_reloc *next; 7804+} riscv_pcrel_lo_reloc; 7805+ 7806+typedef struct { 7807+ htab_t hi_relocs; 7808+ riscv_pcrel_lo_reloc *lo_relocs; 7809+} riscv_pcrel_relocs; 7810+ 7811+static hashval_t 7812+riscv_pcrel_reloc_hash (const void *entry) 7813+{ 7814+ const riscv_pcrel_hi_reloc *e = entry; 7815+ return (hashval_t)(e->address >> 2); 7816+} 7817+ 7818+static bfd_boolean 7819+riscv_pcrel_reloc_eq (const void *entry1, const void *entry2) 7820+{ 7821+ const riscv_pcrel_hi_reloc *e1 = entry1, *e2 = entry2; 7822+ return e1->address == e2->address; 7823+} 7824+ 7825+static bfd_boolean 7826+riscv_init_pcrel_relocs (riscv_pcrel_relocs *p) 7827+{ 7828+ 7829+ p->lo_relocs = NULL; 7830+ p->hi_relocs = htab_create (1024, riscv_pcrel_reloc_hash, 7831+ riscv_pcrel_reloc_eq, free); 7832+ return p->hi_relocs != NULL; 7833+} 7834+ 7835+static void 7836+riscv_free_pcrel_relocs (riscv_pcrel_relocs *p) 7837+{ 7838+ riscv_pcrel_lo_reloc *cur = p->lo_relocs; 7839+ while (cur != NULL) 7840+ { 7841+ riscv_pcrel_lo_reloc *next = cur->next; 7842+ free (cur); 7843+ cur = next; 7844+ } 7845+ 7846+ htab_delete (p->hi_relocs); 7847+} 7848+ 7849+static bfd_boolean 7850+riscv_record_pcrel_hi_reloc (riscv_pcrel_relocs *p, bfd_vma addr, bfd_vma value) 7851+{ 7852+ riscv_pcrel_hi_reloc entry = {addr, value - addr}; 7853+ riscv_pcrel_hi_reloc **slot = 7854+ (riscv_pcrel_hi_reloc **) htab_find_slot (p->hi_relocs, &entry, INSERT); 7855+ BFD_ASSERT (*slot == NULL); 7856+ *slot = (riscv_pcrel_hi_reloc *) bfd_malloc (sizeof (riscv_pcrel_hi_reloc)); 7857+ if (*slot == NULL) 7858+ return FALSE; 7859+ **slot = entry; 7860+ return TRUE; 7861+} 7862+ 7863+static bfd_boolean 7864+riscv_record_pcrel_lo_reloc (riscv_pcrel_relocs *p, 7865+ asection *input_section, 7866+ struct bfd_link_info *info, 7867+ reloc_howto_type *howto, 7868+ const Elf_Internal_Rela *reloc, 7869+ bfd_vma addr, 7870+ const char *name, 7871+ bfd_byte *contents) 7872+{ 7873+ riscv_pcrel_lo_reloc *entry; 7874+ entry = (riscv_pcrel_lo_reloc *) bfd_malloc (sizeof (riscv_pcrel_lo_reloc)); 7875+ if (entry == NULL) 7876+ return FALSE; 7877+ *entry = (riscv_pcrel_lo_reloc) {input_section, info, howto, reloc, addr, 7878+ name, contents, p->lo_relocs}; 7879+ p->lo_relocs = entry; 7880+ return TRUE; 7881+} 7882+ 7883+static bfd_boolean 7884+riscv_resolve_pcrel_lo_relocs (riscv_pcrel_relocs *p) 7885+{ 7886+ riscv_pcrel_lo_reloc *r; 7887+ for (r = p->lo_relocs; r != NULL; r = r->next) 7888+ { 7889+ bfd *input_bfd = r->input_section->owner; 7890+ riscv_pcrel_hi_reloc search = {r->addr, 0}; 7891+ riscv_pcrel_hi_reloc *entry = htab_find (p->hi_relocs, &search); 7892+ if (entry == NULL) 7893+ return ((*r->info->callbacks->reloc_overflow) 7894+ (r->info, NULL, r->name, r->howto->name, (bfd_vma) 0, 7895+ input_bfd, r->input_section, r->reloc->r_offset)); 7896+ 7897+ perform_relocation (r->howto, r->reloc, entry->value, r->input_section, 7898+ input_bfd, r->contents); 7899+ } 7900+ 7901+ return TRUE; 7902+} 7903+ 7904+/* Relocate a RISC-V ELF section. 7905+ 7906+ The RELOCATE_SECTION function is called by the new ELF backend linker 7907+ to handle the relocations for a section. 7908+ 7909+ The relocs are always passed as Rela structures. 7910+ 7911+ This function is responsible for adjusting the section contents as 7912+ necessary, and (if generating a relocatable output file) adjusting 7913+ the reloc addend as necessary. 7914+ 7915+ This function does not have to worry about setting the reloc 7916+ address or the reloc symbol index. 7917+ 7918+ LOCAL_SYMS is a pointer to the swapped in local symbols. 7919+ 7920+ LOCAL_SECTIONS is an array giving the section in the input file 7921+ corresponding to the st_shndx field of each local symbol. 7922+ 7923+ The global hash table entry for the global symbols can be found 7924+ via elf_sym_hashes (input_bfd). 7925+ 7926+ When generating relocatable output, this function must handle 7927+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is 7928+ going to be the section symbol corresponding to the output 7929+ section, which means that the addend must be adjusted 7930+ accordingly. */ 7931+ 7932+static bfd_boolean 7933+riscv_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, 7934+ bfd *input_bfd, asection *input_section, 7935+ bfd_byte *contents, Elf_Internal_Rela *relocs, 7936+ Elf_Internal_Sym *local_syms, 7937+ asection **local_sections) 7938+{ 7939+ Elf_Internal_Rela *rel; 7940+ Elf_Internal_Rela *relend; 7941+ riscv_pcrel_relocs pcrel_relocs; 7942+ bfd_boolean ret = FALSE; 7943+ asection *sreloc = elf_section_data (input_section)->sreloc; 7944+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); 7945+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (input_bfd); 7946+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); 7947+ bfd_vma *local_got_offsets = elf_local_got_offsets (input_bfd); 7948+ 7949+ if (!riscv_init_pcrel_relocs (&pcrel_relocs)) 7950+ return FALSE; 7951+ 7952+ relend = relocs + input_section->reloc_count; 7953+ for (rel = relocs; rel < relend; rel++) 7954+ { 7955+ unsigned long r_symndx; 7956+ struct elf_link_hash_entry *h; 7957+ Elf_Internal_Sym *sym; 7958+ asection *sec; 7959+ bfd_vma relocation; 7960+ bfd_reloc_status_type r = bfd_reloc_ok; 7961+ const char *name; 7962+ bfd_vma off, ie_off; 7963+ bfd_boolean unresolved_reloc, is_ie = FALSE; 7964+ bfd_vma pc = sec_addr (input_section) + rel->r_offset; 7965+ int r_type = ELFNN_R_TYPE (rel->r_info), tls_type; 7966+ reloc_howto_type *howto = riscv_elf_rtype_to_howto (r_type); 7967+ const char *msg = NULL; 7968+ 7969+ if (r_type == R_RISCV_GNU_VTINHERIT || r_type == R_RISCV_GNU_VTENTRY) 7970+ continue; 7971+ 7972+ /* This is a final link. */ 7973+ r_symndx = ELFNN_R_SYM (rel->r_info); 7974+ h = NULL; 7975+ sym = NULL; 7976+ sec = NULL; 7977+ unresolved_reloc = FALSE; 7978+ if (r_symndx < symtab_hdr->sh_info) 7979+ { 7980+ sym = local_syms + r_symndx; 7981+ sec = local_sections[r_symndx]; 7982+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); 7983+ } 7984+ else 7985+ { 7986+ bfd_boolean warned; 7987+ /* bfd_boolean ignored; */ 7988+ 7989+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, 7990+ r_symndx, symtab_hdr, sym_hashes, 7991+ h, sec, relocation, 7992+ unresolved_reloc, warned /*, ignored */); 7993+ if (warned) 7994+ { 7995+ /* To avoid generating warning messages about truncated 7996+ relocations, set the relocation's address to be the same as 7997+ the start of this section. */ 7998+ if (input_section->output_section != NULL) 7999+ relocation = input_section->output_section->vma; 8000+ else 8001+ relocation = 0; 8002+ } 8003+ } 8004+ 8005+ if (sec != NULL && discarded_section (sec)) 8006+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, 8007+ rel, 1, relend, howto, 0, contents); 8008+ 8009+ if (info->relocatable) 8010+ continue; 8011+ 8012+ if (h != NULL) 8013+ name = h->root.root.string; 8014+ else 8015+ { 8016+ name = (bfd_elf_string_from_elf_section 8017+ (input_bfd, symtab_hdr->sh_link, sym->st_name)); 8018+ if (name == NULL || *name == '\0') 8019+ name = bfd_section_name (input_bfd, sec); 8020+ } 8021+ 8022+ switch (r_type) 8023+ { 8024+ case R_RISCV_NONE: 8025+ case R_RISCV_TPREL_ADD: 8026+ case R_RISCV_COPY: 8027+ case R_RISCV_JUMP_SLOT: 8028+ case R_RISCV_RELATIVE: 8029+ /* These require nothing of us at all. */ 8030+ continue; 8031+ 8032+ case R_RISCV_BRANCH: 8033+ case R_RISCV_HI20: 8034+ /* These require no special handling beyond perform_relocation. */ 8035+ break; 8036+ 8037+ case R_RISCV_GOT_HI20: 8038+ if (h != NULL) 8039+ { 8040+ bfd_boolean dyn; 8041+ 8042+ off = h->got.offset; 8043+ BFD_ASSERT (off != (bfd_vma) -1); 8044+ dyn = elf_hash_table (info)->dynamic_sections_created; 8045+ 8046+ if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h) 8047+ || (info->shared 8048+ && SYMBOL_REFERENCES_LOCAL (info, h))) 8049+ { 8050+ /* This is actually a static link, or it is a 8051+ -Bsymbolic link and the symbol is defined 8052+ locally, or the symbol was forced to be local 8053+ because of a version file. We must initialize 8054+ this entry in the global offset table. Since the 8055+ offset must always be a multiple of the word size, 8056+ we use the least significant bit to record whether 8057+ we have initialized it already. 8058+ 8059+ When doing a dynamic link, we create a .rela.got 8060+ relocation entry to initialize the value. This 8061+ is done in the finish_dynamic_symbol routine. */ 8062+ if ((off & 1) != 0) 8063+ off &= ~1; 8064+ else 8065+ { 8066+ bfd_put_NN (output_bfd, relocation, 8067+ htab->elf.sgot->contents + off); 8068+ h->got.offset |= 1; 8069+ } 8070+ } 8071+ else 8072+ unresolved_reloc = FALSE; 8073+ } 8074+ else 8075+ { 8076+ BFD_ASSERT (local_got_offsets != NULL 8077+ && local_got_offsets[r_symndx] != (bfd_vma) -1); 8078+ 8079+ off = local_got_offsets[r_symndx]; 8080+ 8081+ /* The offset must always be a multiple of 8 on 64-bit. 8082+ We use the least significant bit to record 8083+ whether we have already processed this entry. */ 8084+ if ((off & 1) != 0) 8085+ off &= ~1; 8086+ else 8087+ { 8088+ if (info->shared) 8089+ { 8090+ asection *s; 8091+ Elf_Internal_Rela outrel; 8092+ 8093+ /* We need to generate a R_RISCV_RELATIVE reloc 8094+ for the dynamic linker. */ 8095+ s = htab->elf.srelgot; 8096+ BFD_ASSERT (s != NULL); 8097+ 8098+ outrel.r_offset = sec_addr (htab->elf.sgot) + off; 8099+ outrel.r_info = 8100+ ELFNN_R_INFO (0, R_RISCV_RELATIVE); 8101+ outrel.r_addend = relocation; 8102+ relocation = 0; 8103+ riscv_elf_append_rela (output_bfd, s, &outrel); 8104+ } 8105+ 8106+ bfd_put_NN (output_bfd, relocation, 8107+ htab->elf.sgot->contents + off); 8108+ local_got_offsets[r_symndx] |= 1; 8109+ } 8110+ } 8111+ relocation = sec_addr (htab->elf.sgot) + off; 8112+ if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, relocation)) 8113+ r = bfd_reloc_overflow; 8114+ break; 8115+ 8116+ case R_RISCV_ADD8: 8117+ case R_RISCV_ADD16: 8118+ case R_RISCV_ADD32: 8119+ case R_RISCV_ADD64: 8120+ { 8121+ bfd_vma old_value = bfd_get (howto->bitsize, input_bfd, 8122+ contents + rel->r_offset); 8123+ relocation = old_value + relocation; 8124+ } 8125+ break; 8126+ 8127+ case R_RISCV_SUB8: 8128+ case R_RISCV_SUB16: 8129+ case R_RISCV_SUB32: 8130+ case R_RISCV_SUB64: 8131+ { 8132+ bfd_vma old_value = bfd_get (howto->bitsize, input_bfd, 8133+ contents + rel->r_offset); 8134+ relocation = old_value - relocation; 8135+ } 8136+ break; 8137+ 8138+ case R_RISCV_CALL_PLT: 8139+ case R_RISCV_CALL: 8140+ case R_RISCV_JAL: 8141+ if (info->shared && h != NULL && h->plt.offset != MINUS_ONE) 8142+ { 8143+ /* Refer to the PLT entry. */ 8144+ relocation = sec_addr (htab->elf.splt) + h->plt.offset; 8145+ unresolved_reloc = FALSE; 8146+ } 8147+ break; 8148+ 8149+ case R_RISCV_TPREL_HI20: 8150+ relocation = tpoff (info, relocation); 8151+ break; 8152+ 8153+ case R_RISCV_TPREL_LO12_I: 8154+ case R_RISCV_TPREL_LO12_S: 8155+ relocation = tpoff (info, relocation); 8156+ if (VALID_ITYPE_IMM (relocation + rel->r_addend)) 8157+ { 8158+ /* We can use tp as the base register. */ 8159+ bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset); 8160+ insn &= ~(OP_MASK_RS1 << OP_SH_RS1); 8161+ insn |= X_TP << OP_SH_RS1; 8162+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset); 8163+ } 8164+ break; 8165+ 8166+ case R_RISCV_LO12_I: 8167+ case R_RISCV_LO12_S: 8168+ { 8169+ bfd_vma gp = riscv_global_pointer_value (info); 8170+ bfd_boolean x0_base = VALID_ITYPE_IMM (relocation + rel->r_addend); 8171+ if (x0_base || VALID_ITYPE_IMM (relocation + rel->r_addend - gp)) 8172+ { 8173+ /* We can use x0 or gp as the base register. */ 8174+ bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset); 8175+ insn &= ~(OP_MASK_RS1 << OP_SH_RS1); 8176+ if (!x0_base) 8177+ { 8178+ rel->r_addend -= gp; 8179+ insn |= X_GP << OP_SH_RS1; 8180+ } 8181+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset); 8182+ } 8183+ break; 8184+ } 8185+ 8186+ case R_RISCV_PCREL_HI20: 8187+ if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, 8188+ relocation + rel->r_addend)) 8189+ r = bfd_reloc_overflow; 8190+ break; 8191+ 8192+ case R_RISCV_PCREL_LO12_I: 8193+ case R_RISCV_PCREL_LO12_S: 8194+ if (riscv_record_pcrel_lo_reloc (&pcrel_relocs, input_section, info, 8195+ howto, rel, relocation, name, 8196+ contents)) 8197+ continue; 8198+ r = bfd_reloc_overflow; 8199+ break; 8200+ 8201+ case R_RISCV_TLS_DTPREL32: 8202+ case R_RISCV_TLS_DTPREL64: 8203+ relocation = dtpoff (info, relocation); 8204+ break; 8205+ 8206+ case R_RISCV_32: 8207+ case R_RISCV_64: 8208+ if ((input_section->flags & SEC_ALLOC) == 0) 8209+ break; 8210+ 8211+ if ((info->shared 8212+ && (h == NULL 8213+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 8214+ || h->root.type != bfd_link_hash_undefweak) 8215+ && (! howto->pc_relative 8216+ || !SYMBOL_CALLS_LOCAL (info, h))) 8217+ || (!info->shared 8218+ && h != NULL 8219+ && h->dynindx != -1 8220+ && !h->non_got_ref 8221+ && ((h->def_dynamic 8222+ && !h->def_regular) 8223+ || h->root.type == bfd_link_hash_undefweak 8224+ || h->root.type == bfd_link_hash_undefined))) 8225+ { 8226+ Elf_Internal_Rela outrel; 8227+ bfd_boolean skip_static_relocation, skip_dynamic_relocation; 8228+ 8229+ /* When generating a shared object, these relocations 8230+ are copied into the output file to be resolved at run 8231+ time. */ 8232+ 8233+ outrel.r_offset = 8234+ _bfd_elf_section_offset (output_bfd, info, input_section, 8235+ rel->r_offset); 8236+ skip_static_relocation = outrel.r_offset != (bfd_vma) -2; 8237+ skip_dynamic_relocation = outrel.r_offset >= (bfd_vma) -2; 8238+ outrel.r_offset += sec_addr (input_section); 8239+ 8240+ if (skip_dynamic_relocation) 8241+ memset (&outrel, 0, sizeof outrel); 8242+ else if (h != NULL && h->dynindx != -1 8243+ && !(info->shared 8244+ && SYMBOLIC_BIND (info, h) 8245+ && h->def_regular)) 8246+ { 8247+ outrel.r_info = ELFNN_R_INFO (h->dynindx, r_type); 8248+ outrel.r_addend = rel->r_addend; 8249+ } 8250+ else 8251+ { 8252+ outrel.r_info = ELFNN_R_INFO (0, R_RISCV_RELATIVE); 8253+ outrel.r_addend = relocation + rel->r_addend; 8254+ } 8255+ 8256+ riscv_elf_append_rela (output_bfd, sreloc, &outrel); 8257+ if (skip_static_relocation) 8258+ continue; 8259+ } 8260+ break; 8261+ 8262+ case R_RISCV_TLS_GOT_HI20: 8263+ is_ie = TRUE; 8264+ /* Fall through. */ 8265+ 8266+ case R_RISCV_TLS_GD_HI20: 8267+ if (h != NULL) 8268+ { 8269+ off = h->got.offset; 8270+ h->got.offset |= 1; 8271+ } 8272+ else 8273+ { 8274+ off = local_got_offsets[r_symndx]; 8275+ local_got_offsets[r_symndx] |= 1; 8276+ } 8277+ 8278+ tls_type = _bfd_riscv_elf_tls_type (input_bfd, h, r_symndx); 8279+ BFD_ASSERT (tls_type & (GOT_TLS_IE | GOT_TLS_GD)); 8280+ /* If this symbol is referenced by both GD and IE TLS, the IE 8281+ reference's GOT slot follows the GD reference's slots. */ 8282+ ie_off = 0; 8283+ if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_IE)) 8284+ ie_off = 2 * GOT_ENTRY_SIZE; 8285+ 8286+ if ((off & 1) != 0) 8287+ off &= ~1; 8288+ else 8289+ { 8290+ Elf_Internal_Rela outrel; 8291+ int indx = 0; 8292+ bfd_boolean need_relocs = FALSE; 8293+ 8294+ if (htab->elf.srelgot == NULL) 8295+ abort (); 8296+ 8297+ if (h != NULL) 8298+ { 8299+ bfd_boolean dyn; 8300+ dyn = htab->elf.dynamic_sections_created; 8301+ 8302+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h) 8303+ && (!info->shared 8304+ || !SYMBOL_REFERENCES_LOCAL (info, h))) 8305+ { 8306+ indx = h->dynindx; 8307+ } 8308+ } 8309+ 8310+ /* The GOT entries have not been initialized yet. Do it 8311+ now, and emit any relocations. */ 8312+ if ((info->shared || indx != 0) 8313+ && (h == NULL 8314+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 8315+ || h->root.type != bfd_link_hash_undefweak)) 8316+ need_relocs = TRUE; 8317+ 8318+ if (tls_type & GOT_TLS_GD) 8319+ { 8320+ if (need_relocs) 8321+ { 8322+ outrel.r_offset = sec_addr (htab->elf.sgot) + off; 8323+ outrel.r_addend = 0; 8324+ outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPMODNN); 8325+ bfd_put_NN (output_bfd, 0, 8326+ htab->elf.sgot->contents + off); 8327+ riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel); 8328+ if (indx == 0) 8329+ { 8330+ BFD_ASSERT (! unresolved_reloc); 8331+ bfd_put_NN (output_bfd, 8332+ dtpoff (info, relocation), 8333+ (htab->elf.sgot->contents + off + 8334+ RISCV_ELF_WORD_BYTES)); 8335+ } 8336+ else 8337+ { 8338+ bfd_put_NN (output_bfd, 0, 8339+ (htab->elf.sgot->contents + off + 8340+ RISCV_ELF_WORD_BYTES)); 8341+ outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPRELNN); 8342+ outrel.r_offset += RISCV_ELF_WORD_BYTES; 8343+ riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel); 8344+ } 8345+ } 8346+ else 8347+ { 8348+ /* If we are not emitting relocations for a 8349+ general dynamic reference, then we must be in a 8350+ static link or an executable link with the 8351+ symbol binding locally. Mark it as belonging 8352+ to module 1, the executable. */ 8353+ bfd_put_NN (output_bfd, 1, 8354+ htab->elf.sgot->contents + off); 8355+ bfd_put_NN (output_bfd, 8356+ dtpoff (info, relocation), 8357+ (htab->elf.sgot->contents + off + 8358+ RISCV_ELF_WORD_BYTES)); 8359+ } 8360+ } 8361+ 8362+ if (tls_type & GOT_TLS_IE) 8363+ { 8364+ if (need_relocs) 8365+ { 8366+ bfd_put_NN (output_bfd, 0, 8367+ htab->elf.sgot->contents + off + ie_off); 8368+ outrel.r_offset = sec_addr (htab->elf.sgot) 8369+ + off + ie_off; 8370+ outrel.r_addend = 0; 8371+ if (indx == 0) 8372+ outrel.r_addend = tpoff (info, relocation); 8373+ outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_TPRELNN); 8374+ riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel); 8375+ } 8376+ else 8377+ { 8378+ bfd_put_NN (output_bfd, tpoff (info, relocation), 8379+ htab->elf.sgot->contents + off + ie_off); 8380+ } 8381+ } 8382+ } 8383+ 8384+ BFD_ASSERT (off < (bfd_vma) -2); 8385+ relocation = sec_addr (htab->elf.sgot) + off + (is_ie ? ie_off : 0); 8386+ if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, relocation)) 8387+ r = bfd_reloc_overflow; 8388+ unresolved_reloc = FALSE; 8389+ break; 8390+ 8391+ default: 8392+ r = bfd_reloc_notsupported; 8393+ } 8394+ 8395+ /* Dynamic relocs are not propagated for SEC_DEBUGGING sections 8396+ because such sections are not SEC_ALLOC and thus ld.so will 8397+ not process them. */ 8398+ if (unresolved_reloc 8399+ && !((input_section->flags & SEC_DEBUGGING) != 0 8400+ && h->def_dynamic) 8401+ && _bfd_elf_section_offset (output_bfd, info, input_section, 8402+ rel->r_offset) != (bfd_vma) -1) 8403+ { 8404+ (*_bfd_error_handler) 8405+ (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"), 8406+ input_bfd, 8407+ input_section, 8408+ (long) rel->r_offset, 8409+ howto->name, 8410+ h->root.root.string); 8411+ continue; 8412+ } 8413+ 8414+ if (r == bfd_reloc_ok) 8415+ r = perform_relocation (howto, rel, relocation, input_section, 8416+ input_bfd, contents); 8417+ 8418+ switch (r) 8419+ { 8420+ case bfd_reloc_ok: 8421+ continue; 8422+ 8423+ case bfd_reloc_overflow: 8424+ r = info->callbacks->reloc_overflow 8425+ (info, (h ? &h->root : NULL), name, howto->name, 8426+ (bfd_vma) 0, input_bfd, input_section, rel->r_offset); 8427+ break; 8428+ 8429+ case bfd_reloc_undefined: 8430+ r = info->callbacks->undefined_symbol 8431+ (info, name, input_bfd, input_section, rel->r_offset, 8432+ TRUE); 8433+ break; 8434+ 8435+ case bfd_reloc_outofrange: 8436+ msg = _("internal error: out of range error"); 8437+ break; 8438+ 8439+ case bfd_reloc_notsupported: 8440+ msg = _("internal error: unsupported relocation error"); 8441+ break; 8442+ 8443+ case bfd_reloc_dangerous: 8444+ msg = _("internal error: dangerous relocation"); 8445+ break; 8446+ 8447+ default: 8448+ msg = _("internal error: unknown error"); 8449+ break; 8450+ } 8451+ 8452+ if (msg) 8453+ r = info->callbacks->warning 8454+ (info, msg, name, input_bfd, input_section, rel->r_offset); 8455+ goto out; 8456+ } 8457+ 8458+ ret = riscv_resolve_pcrel_lo_relocs (&pcrel_relocs); 8459+out: 8460+ riscv_free_pcrel_relocs (&pcrel_relocs); 8461+ return ret; 8462+} 8463+ 8464+/* Finish up dynamic symbol handling. We set the contents of various 8465+ dynamic sections here. */ 8466+ 8467+static bfd_boolean 8468+riscv_elf_finish_dynamic_symbol (bfd *output_bfd, 8469+ struct bfd_link_info *info, 8470+ struct elf_link_hash_entry *h, 8471+ Elf_Internal_Sym *sym) 8472+{ 8473+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); 8474+ const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); 8475+ 8476+ if (h->plt.offset != (bfd_vma) -1) 8477+ { 8478+ /* We've decided to create a PLT entry for this symbol. */ 8479+ bfd_byte *loc; 8480+ bfd_vma i, header_address, plt_idx, got_address; 8481+ uint32_t plt_entry[PLT_ENTRY_INSNS]; 8482+ Elf_Internal_Rela rela; 8483+ 8484+ BFD_ASSERT (h->dynindx != -1); 8485+ 8486+ /* Calculate the address of the PLT header. */ 8487+ header_address = sec_addr (htab->elf.splt); 8488+ 8489+ /* Calculate the index of the entry. */ 8490+ plt_idx = (h->plt.offset - PLT_HEADER_SIZE) / PLT_ENTRY_SIZE; 8491+ 8492+ /* Calculate the address of the .got.plt entry. */ 8493+ got_address = riscv_elf_got_plt_val (plt_idx, info); 8494+ 8495+ /* Find out where the .plt entry should go. */ 8496+ loc = htab->elf.splt->contents + h->plt.offset; 8497+ 8498+ /* Fill in the PLT entry itself. */ 8499+ riscv_make_plt_entry (got_address, header_address + h->plt.offset, 8500+ plt_entry); 8501+ for (i = 0; i < PLT_ENTRY_INSNS; i++) 8502+ bfd_put_32 (output_bfd, plt_entry[i], loc + 4*i); 8503+ 8504+ /* Fill in the initial value of the .got.plt entry. */ 8505+ loc = htab->elf.sgotplt->contents 8506+ + (got_address - sec_addr (htab->elf.sgotplt)); 8507+ bfd_put_NN (output_bfd, sec_addr (htab->elf.splt), loc); 8508+ 8509+ /* Fill in the entry in the .rela.plt section. */ 8510+ rela.r_offset = got_address; 8511+ rela.r_addend = 0; 8512+ rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_JUMP_SLOT); 8513+ 8514+ loc = htab->elf.srelplt->contents + plt_idx * sizeof (ElfNN_External_Rela); 8515+ bed->s->swap_reloca_out (output_bfd, &rela, loc); 8516+ 8517+ if (!h->def_regular) 8518+ { 8519+ /* Mark the symbol as undefined, rather than as defined in 8520+ the .plt section. Leave the value alone. */ 8521+ sym->st_shndx = SHN_UNDEF; 8522+ /* If the symbol is weak, we do need to clear the value. 8523+ Otherwise, the PLT entry would provide a definition for 8524+ the symbol even if the symbol wasn't defined anywhere, 8525+ and so the symbol would never be NULL. */ 8526+ if (!h->ref_regular_nonweak) 8527+ sym->st_value = 0; 8528+ } 8529+ } 8530+ 8531+ if (h->got.offset != (bfd_vma) -1 8532+ && !(riscv_elf_hash_entry(h)->tls_type & (GOT_TLS_GD | GOT_TLS_IE))) 8533+ { 8534+ asection *sgot; 8535+ asection *srela; 8536+ Elf_Internal_Rela rela; 8537+ 8538+ /* This symbol has an entry in the GOT. Set it up. */ 8539+ 8540+ sgot = htab->elf.sgot; 8541+ srela = htab->elf.srelgot; 8542+ BFD_ASSERT (sgot != NULL && srela != NULL); 8543+ 8544+ rela.r_offset = sec_addr (sgot) + (h->got.offset &~ (bfd_vma) 1); 8545+ 8546+ /* If this is a -Bsymbolic link, and the symbol is defined 8547+ locally, we just want to emit a RELATIVE reloc. Likewise if 8548+ the symbol was forced to be local because of a version file. 8549+ The entry in the global offset table will already have been 8550+ initialized in the relocate_section function. */ 8551+ if (info->shared 8552+ && (info->symbolic || h->dynindx == -1) 8553+ && h->def_regular) 8554+ { 8555+ asection *sec = h->root.u.def.section; 8556+ rela.r_info = ELFNN_R_INFO (0, R_RISCV_RELATIVE); 8557+ rela.r_addend = (h->root.u.def.value 8558+ + sec->output_section->vma 8559+ + sec->output_offset); 8560+ } 8561+ else 8562+ { 8563+ BFD_ASSERT (h->dynindx != -1); 8564+ rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_NN); 8565+ rela.r_addend = 0; 8566+ } 8567+ 8568+ bfd_put_NN (output_bfd, 0, 8569+ sgot->contents + (h->got.offset & ~(bfd_vma) 1)); 8570+ riscv_elf_append_rela (output_bfd, srela, &rela); 8571+ } 8572+ 8573+ if (h->needs_copy) 8574+ { 8575+ Elf_Internal_Rela rela; 8576+ 8577+ /* This symbols needs a copy reloc. Set it up. */ 8578+ BFD_ASSERT (h->dynindx != -1); 8579+ 8580+ rela.r_offset = sec_addr (h->root.u.def.section) + h->root.u.def.value; 8581+ rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_COPY); 8582+ rela.r_addend = 0; 8583+ riscv_elf_append_rela (output_bfd, htab->srelbss, &rela); 8584+ } 8585+ 8586+ /* Mark some specially defined symbols as absolute. */ 8587+ if (/*h == htab->elf.hdynamic*/ 8588+ strcmp (h->root.root.string, "_DYNAMIC") == 0 8589+ || (h == htab->elf.hgot || h == htab->elf.hplt)) 8590+ sym->st_shndx = SHN_ABS; 8591+ 8592+ return TRUE; 8593+} 8594+ 8595+/* Finish up the dynamic sections. */ 8596+ 8597+static bfd_boolean 8598+riscv_finish_dyn (bfd *output_bfd, struct bfd_link_info *info, 8599+ bfd *dynobj, asection *sdyn) 8600+{ 8601+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); 8602+ const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); 8603+ size_t dynsize = bed->s->sizeof_dyn; 8604+ bfd_byte *dyncon, *dynconend; 8605+ 8606+ dynconend = sdyn->contents + sdyn->size; 8607+ for (dyncon = sdyn->contents; dyncon < dynconend; dyncon += dynsize) 8608+ { 8609+ Elf_Internal_Dyn dyn; 8610+ asection *s; 8611+ 8612+ bed->s->swap_dyn_in (dynobj, dyncon, &dyn); 8613+ 8614+ switch (dyn.d_tag) 8615+ { 8616+ case DT_PLTGOT: 8617+ s = htab->elf.sgotplt; 8618+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; 8619+ break; 8620+ case DT_JMPREL: 8621+ s = htab->elf.srelplt; 8622+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; 8623+ break; 8624+ case DT_PLTRELSZ: 8625+ s = htab->elf.srelplt; 8626+ dyn.d_un.d_val = s->size; 8627+ break; 8628+ default: 8629+ continue; 8630+ } 8631+ 8632+ bed->s->swap_dyn_out (output_bfd, &dyn, dyncon); 8633+ } 8634+ return TRUE; 8635+} 8636+ 8637+static bfd_boolean 8638+riscv_elf_finish_dynamic_sections (bfd *output_bfd, 8639+ struct bfd_link_info *info) 8640+{ 8641+ bfd *dynobj; 8642+ asection *sdyn; 8643+ struct riscv_elf_link_hash_table *htab; 8644+ 8645+ htab = riscv_elf_hash_table (info); 8646+ BFD_ASSERT (htab != NULL); 8647+ dynobj = htab->elf.dynobj; 8648+ 8649+ sdyn = bfd_get_linker_section (dynobj, ".dynamic"); 8650+ 8651+ if (elf_hash_table (info)->dynamic_sections_created) 8652+ { 8653+ asection *splt; 8654+ bfd_boolean ret; 8655+ 8656+ splt = htab->elf.splt; 8657+ BFD_ASSERT (splt != NULL && sdyn != NULL); 8658+ 8659+ ret = riscv_finish_dyn (output_bfd, info, dynobj, sdyn); 8660+ 8661+ if (ret != TRUE) 8662+ return ret; 8663+ 8664+ /* Fill in the head and tail entries in the procedure linkage table. */ 8665+ if (splt->size > 0) 8666+ { 8667+ int i; 8668+ uint32_t plt_header[PLT_HEADER_INSNS]; 8669+ riscv_make_plt0_entry (sec_addr (htab->elf.sgotplt), 8670+ sec_addr (splt), plt_header); 8671+ 8672+ for (i = 0; i < PLT_HEADER_INSNS; i++) 8673+ bfd_put_32 (output_bfd, plt_header[i], splt->contents + 4*i); 8674+ } 8675+ 8676+ elf_section_data (splt->output_section)->this_hdr.sh_entsize 8677+ = PLT_ENTRY_SIZE; 8678+ } 8679+ 8680+ if (htab->elf.sgotplt) 8681+ { 8682+ if (bfd_is_abs_section (htab->elf.sgotplt->output_section)) 8683+ { 8684+ (*_bfd_error_handler) 8685+ (_("discarded output section: `%A'"), htab->elf.sgotplt); 8686+ return FALSE; 8687+ } 8688+ 8689+ if (htab->elf.sgotplt->size > 0) 8690+ { 8691+ /* Write the first two entries in .got.plt, needed for the dynamic 8692+ linker. */ 8693+ bfd_put_NN (output_bfd, (bfd_vma) -1, htab->elf.sgotplt->contents); 8694+ bfd_put_NN (output_bfd, (bfd_vma) 0, 8695+ htab->elf.sgotplt->contents + GOT_ENTRY_SIZE); 8696+ } 8697+ 8698+ elf_section_data (htab->elf.sgotplt->output_section)->this_hdr.sh_entsize = 8699+ GOT_ENTRY_SIZE; 8700+ } 8701+ 8702+ if (htab->elf.sgot) 8703+ { 8704+ if (htab->elf.sgot->size > 0) 8705+ { 8706+ /* Set the first entry in the global offset table to the address of 8707+ the dynamic section. */ 8708+ bfd_vma val = sdyn ? sec_addr (sdyn) : 0; 8709+ bfd_put_NN (output_bfd, val, htab->elf.sgot->contents); 8710+ } 8711+ 8712+ elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize = 8713+ GOT_ENTRY_SIZE; 8714+ } 8715+ 8716+ return TRUE; 8717+} 8718+ 8719+/* Return address for Ith PLT stub in section PLT, for relocation REL 8720+ or (bfd_vma) -1 if it should not be included. */ 8721+ 8722+static bfd_vma 8723+riscv_elf_plt_sym_val (bfd_vma i, const asection *plt, 8724+ const arelent *rel ATTRIBUTE_UNUSED) 8725+{ 8726+ return plt->vma + PLT_HEADER_SIZE + i * PLT_ENTRY_SIZE; 8727+} 8728+ 8729+static enum elf_reloc_type_class 8730+riscv_reloc_type_class (/*const struct bfd_link_info *info ATTRIBUTE_UNUSED, 8731+ const asection *rel_sec ATTRIBUTE_UNUSED,*/ 8732+ const Elf_Internal_Rela *rela) 8733+{ 8734+ switch (ELFNN_R_TYPE (rela->r_info)) 8735+ { 8736+ case R_RISCV_RELATIVE: 8737+ return reloc_class_relative; 8738+ case R_RISCV_JUMP_SLOT: 8739+ return reloc_class_plt; 8740+ case R_RISCV_COPY: 8741+ return reloc_class_copy; 8742+ default: 8743+ return reloc_class_normal; 8744+ } 8745+} 8746+ 8747+/* Return true if bfd machine EXTENSION is an extension of machine BASE. */ 8748+ 8749+static bfd_boolean 8750+riscv_mach_extends_p (unsigned long base, unsigned long extension) 8751+{ 8752+ return extension == base; 8753+} 8754+ 8755+/* Merge backend specific data from an object file to the output 8756+ object file when linking. */ 8757+ 8758+static bfd_boolean 8759+_bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) 8760+{ 8761+ flagword old_flags; 8762+ flagword new_flags; 8763+ 8764+ if (!is_riscv_elf (ibfd) || !is_riscv_elf (obfd)) 8765+ return TRUE; 8766+ 8767+ if (strcmp (bfd_get_target (ibfd), bfd_get_target (obfd)) != 0) 8768+ { 8769+ (*_bfd_error_handler) 8770+ (_("%B: ABI is incompatible with that of the selected emulation"), 8771+ ibfd); 8772+ return FALSE; 8773+ } 8774+ 8775+ if (!_bfd_elf_merge_object_attributes (ibfd, obfd)) 8776+ return FALSE; 8777+ 8778+ new_flags = elf_elfheader (ibfd)->e_flags; 8779+ old_flags = elf_elfheader (obfd)->e_flags; 8780+ 8781+ if (! elf_flags_init (obfd)) 8782+ { 8783+ elf_flags_init (obfd) = TRUE; 8784+ elf_elfheader (obfd)->e_flags = new_flags; 8785+ elf_elfheader (obfd)->e_ident[EI_CLASS] 8786+ = elf_elfheader (ibfd)->e_ident[EI_CLASS]; 8787+ 8788+ if (bfd_get_arch (obfd) == bfd_get_arch (ibfd) 8789+ && (bfd_get_arch_info (obfd)->the_default 8790+ || riscv_mach_extends_p (bfd_get_mach (obfd), 8791+ bfd_get_mach (ibfd)))) 8792+ { 8793+ if (! bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), 8794+ bfd_get_mach (ibfd))) 8795+ return FALSE; 8796+ } 8797+ 8798+ return TRUE; 8799+ } 8800+ 8801+ /* Check flag compatibility. */ 8802+ 8803+ if (new_flags == old_flags) 8804+ return TRUE; 8805+ 8806+ /* Don't link RV32 and RV64. */ 8807+ if (elf_elfheader (ibfd)->e_ident[EI_CLASS] 8808+ != elf_elfheader (obfd)->e_ident[EI_CLASS]) 8809+ { 8810+ (*_bfd_error_handler) 8811+ (_("%B: ELF class mismatch: can't link 32- and 64-bit modules"), ibfd); 8812+ goto fail; 8813+ } 8814+ 8815+ /* Warn about any other mismatches. */ 8816+ if (new_flags != old_flags) 8817+ { 8818+ if (!EF_IS_RISCV_EXT_Xcustom (new_flags) && 8819+ !EF_IS_RISCV_EXT_Xcustom (old_flags)) 8820+ { 8821+ (*_bfd_error_handler) 8822+ (_("%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"), 8823+ ibfd, (unsigned long) new_flags, 8824+ (unsigned long) old_flags); 8825+ goto fail; 8826+ } 8827+ else if (EF_IS_RISCV_EXT_Xcustom(new_flags)) 8828+ EF_SET_RISCV_EXT (elf_elfheader (obfd)->e_flags, 8829+ EF_GET_RISCV_EXT (old_flags)); 8830+ } 8831+ 8832+ return TRUE; 8833+ 8834+fail: 8835+ bfd_set_error (bfd_error_bad_value); 8836+ return FALSE; 8837+} 8838+ 8839+/* Delete some bytes from a section while relaxing. */ 8840+ 8841+static bfd_boolean 8842+riscv_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, size_t count) 8843+{ 8844+ unsigned int i, symcount; 8845+ bfd_vma toaddr = sec->size; 8846+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd); 8847+ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 8848+ unsigned int sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); 8849+ struct bfd_elf_section_data *data = elf_section_data (sec); 8850+ bfd_byte *contents = data->this_hdr.contents; 8851+ 8852+ /* Actually delete the bytes. */ 8853+ sec->size -= count; 8854+ memmove (contents + addr, contents + addr + count, toaddr - addr - count); 8855+ 8856+ /* Adjust the location of all of the relocs. Note that we need not 8857+ adjust the addends, since all PC-relative references must be against 8858+ symbols, which we will adjust below. */ 8859+ for (i = 0; i < sec->reloc_count; i++) 8860+ if (data->relocs[i].r_offset > addr && data->relocs[i].r_offset < toaddr) 8861+ data->relocs[i].r_offset -= count; 8862+ 8863+ /* Adjust the local symbols defined in this section. */ 8864+ for (i = 0; i < symtab_hdr->sh_info; i++) 8865+ { 8866+ Elf_Internal_Sym *sym = (Elf_Internal_Sym *) symtab_hdr->contents + i; 8867+ if (sym->st_shndx == sec_shndx) 8868+ { 8869+ /* If the symbol is in the range of memory we just moved, we 8870+ have to adjust its value. */ 8871+ if (sym->st_value > addr && sym->st_value <= toaddr) 8872+ sym->st_value -= count; 8873+ 8874+ /* If the symbol *spans* the bytes we just deleted (i.e. its 8875+ *end* is in the moved bytes but its *start* isn't), then we 8876+ must adjust its size. */ 8877+ if (sym->st_value <= addr 8878+ && sym->st_value + sym->st_size > addr 8879+ && sym->st_value + sym->st_size <= toaddr) 8880+ sym->st_size -= count; 8881+ } 8882+ } 8883+ 8884+ /* Now adjust the global symbols defined in this section. */ 8885+ symcount = ((symtab_hdr->sh_size / sizeof(ElfNN_External_Sym)) 8886+ - symtab_hdr->sh_info); 8887+ 8888+ for (i = 0; i < symcount; i++) 8889+ { 8890+ struct elf_link_hash_entry *sym_hash = sym_hashes[i]; 8891+ 8892+ if ((sym_hash->root.type == bfd_link_hash_defined 8893+ || sym_hash->root.type == bfd_link_hash_defweak) 8894+ && sym_hash->root.u.def.section == sec) 8895+ { 8896+ /* As above, adjust the value if needed. */ 8897+ if (sym_hash->root.u.def.value > addr 8898+ && sym_hash->root.u.def.value <= toaddr) 8899+ sym_hash->root.u.def.value -= count; 8900+ 8901+ /* As above, adjust the size if needed. */ 8902+ if (sym_hash->root.u.def.value <= addr 8903+ && sym_hash->root.u.def.value + sym_hash->size > addr 8904+ && sym_hash->root.u.def.value + sym_hash->size <= toaddr) 8905+ sym_hash->size -= count; 8906+ } 8907+ } 8908+ 8909+ return TRUE; 8910+} 8911+ 8912+/* Relax AUIPC + JALR into JAL. */ 8913+ 8914+static bfd_boolean 8915+_bfd_riscv_relax_call (bfd *abfd, asection *sec, 8916+ struct bfd_link_info *link_info, 8917+ Elf_Internal_Rela *rel, 8918+ bfd_vma symval, 8919+ bfd_boolean *again) 8920+{ 8921+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; 8922+ bfd_signed_vma foff = symval - (sec_addr (sec) + rel->r_offset); 8923+ bfd_boolean near_zero = (symval + RISCV_IMM_REACH/2) < RISCV_IMM_REACH; 8924+ bfd_vma auipc, jalr; 8925+ int r_type; 8926+ 8927+ /* See if this function call can be shortened. */ 8928+ if (!VALID_UJTYPE_IMM (foff) && !(!link_info->shared && near_zero)) 8929+ return TRUE; 8930+ 8931+ /* Shorten the function call. */ 8932+ BFD_ASSERT (rel->r_offset + 8 <= sec->size); 8933+ 8934+ auipc = bfd_get_32 (abfd, contents + rel->r_offset); 8935+ jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4); 8936+ 8937+ if (VALID_UJTYPE_IMM (foff)) 8938+ { 8939+ /* Relax to JAL rd, addr. */ 8940+ r_type = R_RISCV_JAL; 8941+ auipc = (jalr & (OP_MASK_RD << OP_SH_RD)) | MATCH_JAL; 8942+ } 8943+ else /* near_zero */ 8944+ { 8945+ /* Relax to JALR rd, x0, addr. */ 8946+ r_type = R_RISCV_LO12_I; 8947+ auipc = (jalr & (OP_MASK_RD << OP_SH_RD)) | MATCH_JALR; 8948+ } 8949+ 8950+ /* Replace the R_RISCV_CALL reloc. */ 8951+ rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), r_type); 8952+ /* Replace the AUIPC. */ 8953+ bfd_put_32 (abfd, auipc, contents + rel->r_offset); 8954+ 8955+ /* Delete unnecessary JALR. */ 8956+ *again = TRUE; 8957+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 4, 4); 8958+} 8959+ 8960+/* Relax non-PIC global variable references. */ 8961+ 8962+static bfd_boolean 8963+_bfd_riscv_relax_lui (bfd *abfd, asection *sec, 8964+ struct bfd_link_info *link_info, 8965+ Elf_Internal_Rela *rel, 8966+ bfd_vma symval, 8967+ bfd_boolean *again) 8968+{ 8969+ bfd_vma gp = riscv_global_pointer_value (link_info); 8970+ 8971+ /* Bail out if this symbol isn't in range of either gp or x0. */ 8972+ if (!VALID_ITYPE_IMM (symval - gp) && !(symval < RISCV_IMM_REACH/2)) 8973+ return TRUE; 8974+ 8975+ /* We can delete the unnecessary AUIPC. The corresponding LO12 reloc 8976+ will be converted to GPREL during relocation. */ 8977+ BFD_ASSERT (rel->r_offset + 4 <= sec->size); 8978+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE); 8979+ 8980+ *again = TRUE; 8981+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4); 8982+} 8983+ 8984+/* Relax non-PIC TLS references. */ 8985+ 8986+static bfd_boolean 8987+_bfd_riscv_relax_tls_le (bfd *abfd, asection *sec, 8988+ struct bfd_link_info *link_info, 8989+ Elf_Internal_Rela *rel, 8990+ bfd_vma symval, 8991+ bfd_boolean *again) 8992+{ 8993+ /* See if this symbol is in range of tp. */ 8994+ if (RISCV_CONST_HIGH_PART (tpoff (link_info, symval)) != 0) 8995+ return TRUE; 8996+ 8997+ /* We can delete the unnecessary LUI and tp add. The LO12 reloc will be 8998+ made directly tp-relative. */ 8999+ BFD_ASSERT (rel->r_offset + 4 <= sec->size); 9000+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE); 9001+ 9002+ *again = TRUE; 9003+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4); 9004+} 9005+ 9006+/* Implement R_RISCV_ALIGN by deleting excess alignment NOPs. */ 9007+ 9008+static bfd_boolean 9009+_bfd_riscv_relax_align (bfd *abfd, asection *sec, 9010+ struct bfd_link_info *link_info ATTRIBUTE_UNUSED, 9011+ Elf_Internal_Rela *rel, 9012+ bfd_vma symval, 9013+ bfd_boolean *again ATTRIBUTE_UNUSED) 9014+{ 9015+ bfd_vma alignment = 1; 9016+ while (alignment <= rel->r_addend) 9017+ alignment *= 2; 9018+ 9019+ symval -= rel->r_addend; 9020+ bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment; 9021+ bfd_vma nop_bytes_needed = aligned_addr - symval; 9022+ 9023+ /* Make sure there are enough NOPs to actually achieve the alignment. */ 9024+ if (rel->r_addend < nop_bytes_needed) 9025+ return FALSE; 9026+ 9027+ /* Delete the reloc. */ 9028+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE); 9029+ 9030+ /* If the number of NOPs is already correct, there's nothing to do. */ 9031+ if (nop_bytes_needed == rel->r_addend) 9032+ return TRUE; 9033+ 9034+ /* Delete the excess NOPs. */ 9035+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 9036+ rel->r_addend - nop_bytes_needed); 9037+} 9038+ 9039+/* Relax a section. Pass 0 shortens code sequences unless disabled. 9040+ Pass 1, which cannot be disabled, handles code alignment directives. */ 9041+ 9042+static bfd_boolean 9043+_bfd_riscv_relax_section (bfd *abfd, asection *sec, 9044+ struct bfd_link_info *info, bfd_boolean *again) 9045+{ 9046+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); 9047+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); 9048+ struct bfd_elf_section_data *data = elf_section_data (sec); 9049+ Elf_Internal_Rela *relocs; 9050+ bfd_boolean ret = FALSE; 9051+ unsigned int i; 9052+ 9053+ *again = FALSE; 9054+ 9055+ if (info->relocatable 9056+ || (sec->flags & SEC_RELOC) == 0 9057+ || sec->reloc_count == 0 9058+ || (/*info->disable_target_specific_optimizations*/ 0 9059+ && info->relax_pass == 0)) 9060+ return TRUE; 9061+ 9062+ /* Read this BFD's relocs if we haven't done so already. */ 9063+ if (data->relocs) 9064+ relocs = data->relocs; 9065+ else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, 9066+ info->keep_memory))) 9067+ goto fail; 9068+ 9069+ /* Examine and consider relaxing each reloc. */ 9070+ for (i = 0; i < sec->reloc_count; i++) 9071+ { 9072+ Elf_Internal_Rela *rel = data->relocs + i; 9073+ typeof(&_bfd_riscv_relax_call) relax_func = NULL; 9074+ int type = ELFNN_R_TYPE (rel->r_info); 9075+ bfd_vma symval; 9076+ 9077+ if (info->relax_pass == 0) 9078+ { 9079+ if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT) 9080+ relax_func = _bfd_riscv_relax_call; 9081+ else if (type == R_RISCV_HI20) 9082+ relax_func = _bfd_riscv_relax_lui; 9083+ else if (type == R_RISCV_TPREL_HI20 || type == R_RISCV_TPREL_ADD) 9084+ relax_func = _bfd_riscv_relax_tls_le; 9085+ } 9086+ else if (type == R_RISCV_ALIGN) 9087+ relax_func = _bfd_riscv_relax_align; 9088+ 9089+ if (!relax_func) 9090+ continue; 9091+ 9092+ data->relocs = relocs; 9093+ 9094+ /* Read this BFD's contents if we haven't done so already. */ 9095+ if (!data->this_hdr.contents 9096+ && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents)) 9097+ goto fail; 9098+ 9099+ /* Read this BFD's symbols if we haven't done so already. */ 9100+ if (symtab_hdr->sh_info != 0 9101+ && !symtab_hdr->contents 9102+ && !(symtab_hdr->contents = 9103+ (unsigned char *) bfd_elf_get_elf_syms (abfd, symtab_hdr, 9104+ symtab_hdr->sh_info, 9105+ 0, NULL, NULL, NULL))) 9106+ goto fail; 9107+ 9108+ /* Get the value of the symbol referred to by the reloc. */ 9109+ if (ELFNN_R_SYM (rel->r_info) < symtab_hdr->sh_info) 9110+ { 9111+ /* A local symbol. */ 9112+ Elf_Internal_Sym *isym = ((Elf_Internal_Sym *) symtab_hdr->contents 9113+ + ELFNN_R_SYM (rel->r_info)); 9114+ 9115+ if (isym->st_shndx == SHN_UNDEF) 9116+ symval = sec_addr (sec) + rel->r_offset; 9117+ else 9118+ { 9119+ asection *isec; 9120+ BFD_ASSERT (isym->st_shndx < elf_numsections (abfd)); 9121+ isec = elf_elfsections (abfd)[isym->st_shndx]->bfd_section; 9122+ if (sec_addr (isec) == 0) 9123+ continue; 9124+ symval = sec_addr (isec) + isym->st_value; 9125+ } 9126+ } 9127+ else 9128+ { 9129+ unsigned long indx; 9130+ struct elf_link_hash_entry *h; 9131+ 9132+ indx = ELFNN_R_SYM (rel->r_info) - symtab_hdr->sh_info; 9133+ h = elf_sym_hashes (abfd)[indx]; 9134+ 9135+ while (h->root.type == bfd_link_hash_indirect 9136+ || h->root.type == bfd_link_hash_warning) 9137+ h = (struct elf_link_hash_entry *) h->root.u.i.link; 9138+ 9139+ if (h->plt.offset != MINUS_ONE) 9140+ symval = sec_addr (htab->elf.splt) + h->plt.offset; 9141+ else if (h->root.type == bfd_link_hash_undefweak) 9142+ symval = 0; 9143+ else if (h->root.u.def.section->output_section == NULL 9144+ || (h->root.type != bfd_link_hash_defined 9145+ && h->root.type != bfd_link_hash_defweak)) 9146+ continue; 9147+ else 9148+ symval = sec_addr (h->root.u.def.section) + h->root.u.def.value; 9149+ } 9150+ 9151+ symval += rel->r_addend; 9152+ 9153+ if (!relax_func (abfd, sec, info, rel, symval, again)) 9154+ goto fail; 9155+ } 9156+ 9157+ ret = TRUE; 9158+ 9159+fail: 9160+ if (relocs != data->relocs) 9161+ free (relocs); 9162+ 9163+ return ret; 9164+} 9165+ 9166+#define ELF_ARCH bfd_arch_riscv 9167+#define ELF_TARGET_ID RISCV_ELF_DATA 9168+#define ELF_MACHINE_CODE EM_RISCV 9169+#define ELF_MAXPAGESIZE 0x2000 9170+#define ELF_COMMONPAGESIZE 0x2000 9171+ 9172+#define TARGET_LITTLE_SYM bfd_elfNN_riscv_vec 9173+#define TARGET_LITTLE_NAME "elfNN-littleriscv" 9174+ 9175+#define elf_backend_reloc_type_class riscv_reloc_type_class 9176+ 9177+#define bfd_elfNN_bfd_reloc_name_lookup riscv_reloc_name_lookup 9178+#define bfd_elfNN_bfd_link_hash_table_create riscv_elf_link_hash_table_create 9179+#define bfd_elfNN_bfd_reloc_type_lookup riscv_reloc_type_lookup 9180+#define bfd_elfNN_bfd_merge_private_bfd_data \ 9181+ _bfd_riscv_elf_merge_private_bfd_data 9182+ 9183+#define elf_backend_copy_indirect_symbol riscv_elf_copy_indirect_symbol 9184+#define elf_backend_create_dynamic_sections riscv_elf_create_dynamic_sections 9185+#define elf_backend_check_relocs riscv_elf_check_relocs 9186+#define elf_backend_adjust_dynamic_symbol riscv_elf_adjust_dynamic_symbol 9187+#define elf_backend_size_dynamic_sections riscv_elf_size_dynamic_sections 9188+#define elf_backend_relocate_section riscv_elf_relocate_section 9189+#define elf_backend_finish_dynamic_symbol riscv_elf_finish_dynamic_symbol 9190+#define elf_backend_finish_dynamic_sections riscv_elf_finish_dynamic_sections 9191+#define elf_backend_gc_mark_hook riscv_elf_gc_mark_hook 9192+#define elf_backend_gc_sweep_hook riscv_elf_gc_sweep_hook 9193+#define elf_backend_plt_sym_val riscv_elf_plt_sym_val 9194+#define elf_info_to_howto_rel NULL 9195+#define elf_info_to_howto riscv_info_to_howto_rela 9196+#define bfd_elfNN_bfd_relax_section _bfd_riscv_relax_section 9197+ 9198+#define elf_backend_init_index_section _bfd_elf_init_1_index_section 9199+ 9200+#define elf_backend_can_gc_sections 1 9201+#define elf_backend_can_refcount 1 9202+#define elf_backend_want_got_plt 1 9203+#define elf_backend_plt_readonly 1 9204+#define elf_backend_plt_alignment 4 9205+#define elf_backend_want_plt_sym 1 9206+#define elf_backend_got_header_size (ARCH_SIZE / 8) 9207+#define elf_backend_rela_normal 1 9208+#define elf_backend_default_execstack 0 9209+ 9210+#include "elfNN-target.h" 9211diff -rNU3 dist.orig/bfd/elfxx-mips.c dist/bfd/elfxx-mips.c 9212--- dist.orig/bfd/elfxx-mips.c 2013-03-25 09:06:20.000000000 +0100 9213+++ dist/bfd/elfxx-mips.c 2015-10-18 13:11:13.000000000 +0200 9214@@ -8191,10 +8191,24 @@ 9215 reloc types into the output file as R_MIPS_REL32 9216 relocs. Make room for this reloc in .rel(a).dyn. */ 9217 mips_elf_allocate_dynamic_relocations (dynobj, info, 1); 9218- if (MIPS_ELF_READONLY_SECTION (sec)) 9219- /* We tell the dynamic linker that there are 9220- relocations against the text segment. */ 9221- info->flags |= DF_TEXTREL; 9222+ /* In the N32 and 64-bit ABIs there may be multiple 9223+ consecutive relocations for the same offset. If we have 9224+ a R_MIPS_GPREL32 followed by a R_MIPS_64 then that 9225+ relocation is complete and needs no futher adjustment. */ 9226+ if ((rel == relocs 9227+ || rel[-1].r_offset != rel->r_offset 9228+ || r_type != R_MIPS_64 9229+ || ELF_R_TYPE(abfd, rel[-1].r_info) != R_MIPS_GPREL32) 9230+ && MIPS_ELF_READONLY_SECTION (sec)) 9231+ { 9232+ /* We tell the dynamic linker that there are 9233+ relocations against the text segment. */ 9234+ info->flags |= DF_TEXTREL; 9235+ info->callbacks->warning 9236+ (info, 9237+ _("relocation emitted against readonly section"), 9238+ NULL, abfd, sec, rel->r_offset); 9239+ } 9240 } 9241 else 9242 { 9243@@ -8612,6 +8626,7 @@ 9244 /* Make sure we know what is going on here. */ 9245 BFD_ASSERT (dynobj != NULL 9246 && (h->needs_plt 9247+ || h->type == STT_GNU_IFUNC 9248 || h->u.weakdef != NULL 9249 || (h->def_dynamic 9250 && h->ref_regular 9251diff -rNU3 dist.orig/bfd/elfxx-riscv.c dist/bfd/elfxx-riscv.c 9252--- dist.orig/bfd/elfxx-riscv.c 1970-01-01 01:00:00.000000000 +0100 9253+++ dist/bfd/elfxx-riscv.c 2015-10-18 13:11:13.000000000 +0200 9254@@ -0,0 +1,730 @@ 9255+/* RISC-V-specific support for ELF. 9256+ Copyright 2011-2014 Free Software Foundation, Inc. 9257+ 9258+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 9259+ Based on TILE-Gx and MIPS targets. 9260+ 9261+ This file is part of BFD, the Binary File Descriptor library. 9262+ 9263+ This program is free software; you can redistribute it and/or modify 9264+ it under the terms of the GNU General Public License as published by 9265+ the Free Software Foundation; either version 3 of the License, or 9266+ (at your option) any later version. 9267+ 9268+ This program is distributed in the hope that it will be useful, 9269+ but WITHOUT ANY WARRANTY; without even the implied warranty of 9270+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9271+ GNU General Public License for more details. 9272+ 9273+ You should have received a copy of the GNU General Public License 9274+ along with this program; if not, write to the Free Software 9275+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 9276+ MA 02110-1301, USA. */ 9277+ 9278+#include "sysdep.h" 9279+#include "bfd.h" 9280+#include "libbfd.h" 9281+#include "elf-bfd.h" 9282+#include "elf/riscv.h" 9283+#include "opcode/riscv.h" 9284+#include "libiberty.h" 9285+#include "elfxx-riscv.h" 9286+#include <stdint.h> 9287+ 9288+#define MINUS_ONE ((bfd_vma)0 - 1) 9289+ 9290+/* The relocation table used for SHT_RELA sections. */ 9291+ 9292+static reloc_howto_type howto_table[] = 9293+{ 9294+ /* No relocation. */ 9295+ HOWTO (R_RISCV_NONE, /* type */ 9296+ 0, /* rightshift */ 9297+ 0, /* size (0 = byte, 1 = short, 2 = long) */ 9298+ 0, /* bitsize */ 9299+ FALSE, /* pc_relative */ 9300+ 0, /* bitpos */ 9301+ complain_overflow_dont, /* complain_on_overflow */ 9302+ bfd_elf_generic_reloc, /* special_function */ 9303+ "R_RISCV_NONE", /* name */ 9304+ FALSE, /* partial_inplace */ 9305+ 0, /* src_mask */ 9306+ 0, /* dst_mask */ 9307+ FALSE), /* pcrel_offset */ 9308+ 9309+ /* 32 bit relocation. */ 9310+ HOWTO (R_RISCV_32, /* type */ 9311+ 0, /* rightshift */ 9312+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9313+ 32, /* bitsize */ 9314+ FALSE, /* pc_relative */ 9315+ 0, /* bitpos */ 9316+ complain_overflow_dont, /* complain_on_overflow */ 9317+ bfd_elf_generic_reloc, /* special_function */ 9318+ "R_RISCV_32", /* name */ 9319+ FALSE, /* partial_inplace */ 9320+ 0, /* src_mask */ 9321+ 0xffffffff, /* dst_mask */ 9322+ FALSE), /* pcrel_offset */ 9323+ 9324+ /* 64 bit relocation. */ 9325+ HOWTO (R_RISCV_64, /* type */ 9326+ 0, /* rightshift */ 9327+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9328+ 64, /* bitsize */ 9329+ FALSE, /* pc_relative */ 9330+ 0, /* bitpos */ 9331+ complain_overflow_dont, /* complain_on_overflow */ 9332+ bfd_elf_generic_reloc, /* special_function */ 9333+ "R_RISCV_64", /* name */ 9334+ FALSE, /* partial_inplace */ 9335+ 0, /* src_mask */ 9336+ MINUS_ONE, /* dst_mask */ 9337+ FALSE), /* pcrel_offset */ 9338+ 9339+ /* Relocation against a local symbol in a shared object. */ 9340+ HOWTO (R_RISCV_RELATIVE, /* type */ 9341+ 0, /* rightshift */ 9342+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9343+ 32, /* bitsize */ 9344+ FALSE, /* pc_relative */ 9345+ 0, /* bitpos */ 9346+ complain_overflow_dont, /* complain_on_overflow */ 9347+ bfd_elf_generic_reloc, /* special_function */ 9348+ "R_RISCV_RELATIVE", /* name */ 9349+ FALSE, /* partial_inplace */ 9350+ 0, /* src_mask */ 9351+ 0xffffffff, /* dst_mask */ 9352+ FALSE), /* pcrel_offset */ 9353+ 9354+ HOWTO (R_RISCV_COPY, /* type */ 9355+ 0, /* rightshift */ 9356+ 0, /* this one is variable size */ 9357+ 0, /* bitsize */ 9358+ FALSE, /* pc_relative */ 9359+ 0, /* bitpos */ 9360+ complain_overflow_bitfield, /* complain_on_overflow */ 9361+ bfd_elf_generic_reloc, /* special_function */ 9362+ "R_RISCV_COPY", /* name */ 9363+ FALSE, /* partial_inplace */ 9364+ 0x0, /* src_mask */ 9365+ 0x0, /* dst_mask */ 9366+ FALSE), /* pcrel_offset */ 9367+ 9368+ HOWTO (R_RISCV_JUMP_SLOT, /* type */ 9369+ 0, /* rightshift */ 9370+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9371+ 64, /* bitsize */ 9372+ FALSE, /* pc_relative */ 9373+ 0, /* bitpos */ 9374+ complain_overflow_bitfield, /* complain_on_overflow */ 9375+ bfd_elf_generic_reloc, /* special_function */ 9376+ "R_RISCV_JUMP_SLOT", /* name */ 9377+ FALSE, /* partial_inplace */ 9378+ 0x0, /* src_mask */ 9379+ 0x0, /* dst_mask */ 9380+ FALSE), /* pcrel_offset */ 9381+ 9382+ /* Dynamic TLS relocations. */ 9383+ HOWTO (R_RISCV_TLS_DTPMOD32, /* type */ 9384+ 0, /* rightshift */ 9385+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9386+ 32, /* bitsize */ 9387+ FALSE, /* pc_relative */ 9388+ 0, /* bitpos */ 9389+ complain_overflow_dont, /* complain_on_overflow */ 9390+ bfd_elf_generic_reloc, /* special_function */ 9391+ "R_RISCV_TLS_DTPMOD32", /* name */ 9392+ FALSE, /* partial_inplace */ 9393+ MINUS_ONE, /* src_mask */ 9394+ MINUS_ONE, /* dst_mask */ 9395+ FALSE), /* pcrel_offset */ 9396+ 9397+ HOWTO (R_RISCV_TLS_DTPMOD64, /* type */ 9398+ 0, /* rightshift */ 9399+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9400+ 64, /* bitsize */ 9401+ FALSE, /* pc_relative */ 9402+ 0, /* bitpos */ 9403+ complain_overflow_dont, /* complain_on_overflow */ 9404+ bfd_elf_generic_reloc, /* special_function */ 9405+ "R_RISCV_TLS_DTPMOD64", /* name */ 9406+ FALSE, /* partial_inplace */ 9407+ MINUS_ONE, /* src_mask */ 9408+ MINUS_ONE, /* dst_mask */ 9409+ FALSE), /* pcrel_offset */ 9410+ 9411+ HOWTO (R_RISCV_TLS_DTPREL32, /* type */ 9412+ 0, /* rightshift */ 9413+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9414+ 32, /* bitsize */ 9415+ FALSE, /* pc_relative */ 9416+ 0, /* bitpos */ 9417+ complain_overflow_dont, /* complain_on_overflow */ 9418+ bfd_elf_generic_reloc, /* special_function */ 9419+ "R_RISCV_TLS_DTPREL32", /* name */ 9420+ TRUE, /* partial_inplace */ 9421+ MINUS_ONE, /* src_mask */ 9422+ MINUS_ONE, /* dst_mask */ 9423+ FALSE), /* pcrel_offset */ 9424+ 9425+ HOWTO (R_RISCV_TLS_DTPREL64, /* type */ 9426+ 0, /* rightshift */ 9427+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9428+ 64, /* bitsize */ 9429+ FALSE, /* pc_relative */ 9430+ 0, /* bitpos */ 9431+ complain_overflow_dont, /* complain_on_overflow */ 9432+ bfd_elf_generic_reloc, /* special_function */ 9433+ "R_RISCV_TLS_DTPREL64", /* name */ 9434+ TRUE, /* partial_inplace */ 9435+ MINUS_ONE, /* src_mask */ 9436+ MINUS_ONE, /* dst_mask */ 9437+ FALSE), /* pcrel_offset */ 9438+ 9439+ HOWTO (R_RISCV_TLS_TPREL32, /* type */ 9440+ 0, /* rightshift */ 9441+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9442+ 32, /* bitsize */ 9443+ FALSE, /* pc_relative */ 9444+ 0, /* bitpos */ 9445+ complain_overflow_dont, /* complain_on_overflow */ 9446+ bfd_elf_generic_reloc, /* special_function */ 9447+ "R_RISCV_TLS_TPREL32", /* name */ 9448+ FALSE, /* partial_inplace */ 9449+ MINUS_ONE, /* src_mask */ 9450+ MINUS_ONE, /* dst_mask */ 9451+ FALSE), /* pcrel_offset */ 9452+ 9453+ HOWTO (R_RISCV_TLS_TPREL64, /* type */ 9454+ 0, /* rightshift */ 9455+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9456+ 64, /* bitsize */ 9457+ FALSE, /* pc_relative */ 9458+ 0, /* bitpos */ 9459+ complain_overflow_dont, /* complain_on_overflow */ 9460+ bfd_elf_generic_reloc, /* special_function */ 9461+ "R_RISCV_TLS_TPREL64", /* name */ 9462+ FALSE, /* partial_inplace */ 9463+ MINUS_ONE, /* src_mask */ 9464+ MINUS_ONE, /* dst_mask */ 9465+ FALSE), /* pcrel_offset */ 9466+ 9467+ EMPTY_HOWTO (12), 9468+ EMPTY_HOWTO (13), 9469+ EMPTY_HOWTO (14), 9470+ EMPTY_HOWTO (15), 9471+ 9472+ /* 12-bit PC-relative branch offset. */ 9473+ HOWTO (R_RISCV_BRANCH, /* type */ 9474+ 0, /* rightshift */ 9475+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9476+ 32, /* bitsize */ 9477+ TRUE, /* pc_relative */ 9478+ 0, /* bitpos */ 9479+ complain_overflow_signed, /* complain_on_overflow */ 9480+ bfd_elf_generic_reloc, /* special_function */ 9481+ "R_RISCV_BRANCH", /* name */ 9482+ FALSE, /* partial_inplace */ 9483+ 0, /* src_mask */ 9484+ ENCODE_SBTYPE_IMM(-1U),/* dst_mask */ 9485+ TRUE), /* pcrel_offset */ 9486+ 9487+ /* 20-bit PC-relative jump offset. */ 9488+ HOWTO (R_RISCV_JAL, /* type */ 9489+ 0, /* rightshift */ 9490+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9491+ 32, /* bitsize */ 9492+ TRUE, /* pc_relative */ 9493+ 0, /* bitpos */ 9494+ complain_overflow_dont, /* complain_on_overflow */ 9495+ /* This needs complex overflow 9496+ detection, because the upper 36 9497+ bits must match the PC + 4. */ 9498+ bfd_elf_generic_reloc, /* special_function */ 9499+ "R_RISCV_JAL", /* name */ 9500+ FALSE, /* partial_inplace */ 9501+ 0, /* src_mask */ 9502+ ENCODE_UJTYPE_IMM(-1U), /* dst_mask */ 9503+ TRUE), /* pcrel_offset */ 9504+ 9505+ /* 32-bit PC-relative function call (AUIPC/JALR). */ 9506+ HOWTO (R_RISCV_CALL, /* type */ 9507+ 0, /* rightshift */ 9508+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9509+ 64, /* bitsize */ 9510+ TRUE, /* pc_relative */ 9511+ 0, /* bitpos */ 9512+ complain_overflow_dont, /* complain_on_overflow */ 9513+ bfd_elf_generic_reloc, /* special_function */ 9514+ "R_RISCV_CALL", /* name */ 9515+ FALSE, /* partial_inplace */ 9516+ 0, /* src_mask */ 9517+ ENCODE_UTYPE_IMM(-1U) | ((bfd_vma) ENCODE_ITYPE_IMM(-1U) << 32), /* dst_mask */ 9518+ TRUE), /* pcrel_offset */ 9519+ 9520+ /* 32-bit PC-relative function call (AUIPC/JALR). */ 9521+ HOWTO (R_RISCV_CALL_PLT, /* type */ 9522+ 0, /* rightshift */ 9523+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9524+ 64, /* bitsize */ 9525+ TRUE, /* pc_relative */ 9526+ 0, /* bitpos */ 9527+ complain_overflow_dont, /* complain_on_overflow */ 9528+ bfd_elf_generic_reloc, /* special_function */ 9529+ "R_RISCV_CALL_PLT", /* name */ 9530+ FALSE, /* partial_inplace */ 9531+ 0, /* src_mask */ 9532+ ENCODE_UTYPE_IMM(-1U) | ((bfd_vma) ENCODE_ITYPE_IMM(-1U) << 32), /* dst_mask */ 9533+ TRUE), /* pcrel_offset */ 9534+ 9535+ /* High 20 bits of 32-bit PC-relative GOT access. */ 9536+ HOWTO (R_RISCV_GOT_HI20, /* type */ 9537+ 0, /* rightshift */ 9538+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9539+ 32, /* bitsize */ 9540+ TRUE, /* pc_relative */ 9541+ 0, /* bitpos */ 9542+ complain_overflow_dont, /* complain_on_overflow */ 9543+ bfd_elf_generic_reloc, /* special_function */ 9544+ "R_RISCV_GOT_HI20", /* name */ 9545+ FALSE, /* partial_inplace */ 9546+ 0, /* src_mask */ 9547+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ 9548+ FALSE), /* pcrel_offset */ 9549+ 9550+ /* High 20 bits of 32-bit PC-relative TLS IE GOT access. */ 9551+ HOWTO (R_RISCV_TLS_GOT_HI20, /* type */ 9552+ 0, /* rightshift */ 9553+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9554+ 32, /* bitsize */ 9555+ TRUE, /* pc_relative */ 9556+ 0, /* bitpos */ 9557+ complain_overflow_dont, /* complain_on_overflow */ 9558+ bfd_elf_generic_reloc, /* special_function */ 9559+ "R_RISCV_TLS_GOT_HI20", /* name */ 9560+ FALSE, /* partial_inplace */ 9561+ 0, /* src_mask */ 9562+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ 9563+ FALSE), /* pcrel_offset */ 9564+ 9565+ /* High 20 bits of 32-bit PC-relative TLS GD GOT reference. */ 9566+ HOWTO (R_RISCV_TLS_GD_HI20, /* type */ 9567+ 0, /* rightshift */ 9568+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9569+ 32, /* bitsize */ 9570+ TRUE, /* pc_relative */ 9571+ 0, /* bitpos */ 9572+ complain_overflow_dont, /* complain_on_overflow */ 9573+ bfd_elf_generic_reloc, /* special_function */ 9574+ "R_RISCV_TLS_GD_HI20", /* name */ 9575+ FALSE, /* partial_inplace */ 9576+ 0, /* src_mask */ 9577+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ 9578+ FALSE), /* pcrel_offset */ 9579+ 9580+ /* High 20 bits of 32-bit PC-relative reference. */ 9581+ HOWTO (R_RISCV_PCREL_HI20, /* type */ 9582+ 0, /* rightshift */ 9583+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9584+ 32, /* bitsize */ 9585+ TRUE, /* pc_relative */ 9586+ 0, /* bitpos */ 9587+ complain_overflow_dont, /* complain_on_overflow */ 9588+ bfd_elf_generic_reloc, /* special_function */ 9589+ "R_RISCV_PCREL_HI20", /* name */ 9590+ FALSE, /* partial_inplace */ 9591+ 0, /* src_mask */ 9592+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ 9593+ TRUE), /* pcrel_offset */ 9594+ 9595+ /* Low 12 bits of a 32-bit PC-relative load or add. */ 9596+ HOWTO (R_RISCV_PCREL_LO12_I, /* type */ 9597+ 0, /* rightshift */ 9598+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9599+ 32, /* bitsize */ 9600+ FALSE, /* pc_relative */ 9601+ 0, /* bitpos */ 9602+ complain_overflow_dont, /* complain_on_overflow */ 9603+ bfd_elf_generic_reloc, /* special_function */ 9604+ "R_RISCV_PCREL_LO12_I",/* name */ 9605+ FALSE, /* partial_inplace */ 9606+ 0, /* src_mask */ 9607+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ 9608+ FALSE), /* pcrel_offset */ 9609+ 9610+ /* Low 12 bits of a 32-bit PC-relative store. */ 9611+ HOWTO (R_RISCV_PCREL_LO12_S, /* type */ 9612+ 0, /* rightshift */ 9613+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9614+ 32, /* bitsize */ 9615+ FALSE, /* pc_relative */ 9616+ 0, /* bitpos */ 9617+ complain_overflow_dont, /* complain_on_overflow */ 9618+ bfd_elf_generic_reloc, /* special_function */ 9619+ "R_RISCV_PCREL_LO12_S",/* name */ 9620+ FALSE, /* partial_inplace */ 9621+ 0, /* src_mask */ 9622+ ENCODE_STYPE_IMM(-1U), /* dst_mask */ 9623+ FALSE), /* pcrel_offset */ 9624+ 9625+ /* High 20 bits of 32-bit absolute address. */ 9626+ HOWTO (R_RISCV_HI20, /* type */ 9627+ 0, /* rightshift */ 9628+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9629+ 32, /* bitsize */ 9630+ FALSE, /* pc_relative */ 9631+ 0, /* bitpos */ 9632+ complain_overflow_dont, /* complain_on_overflow */ 9633+ bfd_elf_generic_reloc, /* special_function */ 9634+ "R_RISCV_HI20", /* name */ 9635+ FALSE, /* partial_inplace */ 9636+ 0, /* src_mask */ 9637+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ 9638+ FALSE), /* pcrel_offset */ 9639+ 9640+ /* High 12 bits of 32-bit load or add. */ 9641+ HOWTO (R_RISCV_LO12_I, /* type */ 9642+ 0, /* rightshift */ 9643+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9644+ 32, /* bitsize */ 9645+ FALSE, /* pc_relative */ 9646+ 0, /* bitpos */ 9647+ complain_overflow_dont, /* complain_on_overflow */ 9648+ bfd_elf_generic_reloc, /* special_function */ 9649+ "R_RISCV_LO12_I", /* name */ 9650+ FALSE, /* partial_inplace */ 9651+ 0, /* src_mask */ 9652+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ 9653+ FALSE), /* pcrel_offset */ 9654+ 9655+ /* High 12 bits of 32-bit store. */ 9656+ HOWTO (R_RISCV_LO12_S, /* type */ 9657+ 0, /* rightshift */ 9658+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9659+ 32, /* bitsize */ 9660+ FALSE, /* pc_relative */ 9661+ 0, /* bitpos */ 9662+ complain_overflow_dont, /* complain_on_overflow */ 9663+ bfd_elf_generic_reloc, /* special_function */ 9664+ "R_RISCV_LO12_S", /* name */ 9665+ FALSE, /* partial_inplace */ 9666+ 0, /* src_mask */ 9667+ ENCODE_STYPE_IMM(-1U), /* dst_mask */ 9668+ FALSE), /* pcrel_offset */ 9669+ 9670+ /* High 20 bits of TLS LE thread pointer offset. */ 9671+ HOWTO (R_RISCV_TPREL_HI20, /* type */ 9672+ 0, /* rightshift */ 9673+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9674+ 32, /* bitsize */ 9675+ FALSE, /* pc_relative */ 9676+ 0, /* bitpos */ 9677+ complain_overflow_signed, /* complain_on_overflow */ 9678+ bfd_elf_generic_reloc, /* special_function */ 9679+ "R_RISCV_TPREL_HI20", /* name */ 9680+ TRUE, /* partial_inplace */ 9681+ 0, /* src_mask */ 9682+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ 9683+ FALSE), /* pcrel_offset */ 9684+ 9685+ /* Low 12 bits of TLS LE thread pointer offset for loads and adds. */ 9686+ HOWTO (R_RISCV_TPREL_LO12_I, /* type */ 9687+ 0, /* rightshift */ 9688+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9689+ 32, /* bitsize */ 9690+ FALSE, /* pc_relative */ 9691+ 0, /* bitpos */ 9692+ complain_overflow_signed, /* complain_on_overflow */ 9693+ bfd_elf_generic_reloc, /* special_function */ 9694+ "R_RISCV_TPREL_LO12_I",/* name */ 9695+ FALSE, /* partial_inplace */ 9696+ 0, /* src_mask */ 9697+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ 9698+ FALSE), /* pcrel_offset */ 9699+ 9700+ /* Low 12 bits of TLS LE thread pointer offset for stores. */ 9701+ HOWTO (R_RISCV_TPREL_LO12_S, /* type */ 9702+ 0, /* rightshift */ 9703+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9704+ 32, /* bitsize */ 9705+ FALSE, /* pc_relative */ 9706+ 0, /* bitpos */ 9707+ complain_overflow_signed, /* complain_on_overflow */ 9708+ bfd_elf_generic_reloc, /* special_function */ 9709+ "R_RISCV_TPREL_LO12_S",/* name */ 9710+ FALSE, /* partial_inplace */ 9711+ 0, /* src_mask */ 9712+ ENCODE_STYPE_IMM(-1U), /* dst_mask */ 9713+ FALSE), /* pcrel_offset */ 9714+ 9715+ /* TLS LE thread pointer usage. */ 9716+ HOWTO (R_RISCV_TPREL_ADD, /* type */ 9717+ 0, /* rightshift */ 9718+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9719+ 32, /* bitsize */ 9720+ FALSE, /* pc_relative */ 9721+ 0, /* bitpos */ 9722+ complain_overflow_dont,/* complain_on_overflow */ 9723+ bfd_elf_generic_reloc, /* special_function */ 9724+ "R_RISCV_TPREL_ADD", /* name */ 9725+ TRUE, /* partial_inplace */ 9726+ 0, /* src_mask */ 9727+ 0, /* dst_mask */ 9728+ FALSE), /* pcrel_offset */ 9729+ 9730+ /* 8-bit in-place addition, for local label subtraction. */ 9731+ HOWTO (R_RISCV_ADD8, /* type */ 9732+ 0, /* rightshift */ 9733+ 0, /* size (0 = byte, 1 = short, 2 = long) */ 9734+ 32, /* bitsize */ 9735+ FALSE, /* pc_relative */ 9736+ 0, /* bitpos */ 9737+ complain_overflow_dont, /* complain_on_overflow */ 9738+ bfd_elf_generic_reloc, /* special_function */ 9739+ "R_RISCV_ADD8", /* name */ 9740+ FALSE, /* partial_inplace */ 9741+ 0, /* src_mask */ 9742+ MINUS_ONE, /* dst_mask */ 9743+ FALSE), /* pcrel_offset */ 9744+ 9745+ /* 16-bit in-place addition, for local label subtraction. */ 9746+ HOWTO (R_RISCV_ADD16, /* type */ 9747+ 0, /* rightshift */ 9748+ 1, /* size (0 = byte, 1 = short, 2 = long) */ 9749+ 16, /* bitsize */ 9750+ FALSE, /* pc_relative */ 9751+ 0, /* bitpos */ 9752+ complain_overflow_dont, /* complain_on_overflow */ 9753+ bfd_elf_generic_reloc, /* special_function */ 9754+ "R_RISCV_ADD16", /* name */ 9755+ FALSE, /* partial_inplace */ 9756+ 0, /* src_mask */ 9757+ MINUS_ONE, /* dst_mask */ 9758+ FALSE), /* pcrel_offset */ 9759+ 9760+ /* 32-bit in-place addition, for local label subtraction. */ 9761+ HOWTO (R_RISCV_ADD32, /* type */ 9762+ 0, /* rightshift */ 9763+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9764+ 32, /* bitsize */ 9765+ FALSE, /* pc_relative */ 9766+ 0, /* bitpos */ 9767+ complain_overflow_dont, /* complain_on_overflow */ 9768+ bfd_elf_generic_reloc, /* special_function */ 9769+ "R_RISCV_ADD32", /* name */ 9770+ FALSE, /* partial_inplace */ 9771+ 0, /* src_mask */ 9772+ MINUS_ONE, /* dst_mask */ 9773+ FALSE), /* pcrel_offset */ 9774+ 9775+ /* 64-bit in-place addition, for local label subtraction. */ 9776+ HOWTO (R_RISCV_ADD64, /* type */ 9777+ 0, /* rightshift */ 9778+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9779+ 64, /* bitsize */ 9780+ FALSE, /* pc_relative */ 9781+ 0, /* bitpos */ 9782+ complain_overflow_dont, /* complain_on_overflow */ 9783+ bfd_elf_generic_reloc, /* special_function */ 9784+ "R_RISCV_ADD64", /* name */ 9785+ FALSE, /* partial_inplace */ 9786+ 0, /* src_mask */ 9787+ MINUS_ONE, /* dst_mask */ 9788+ FALSE), /* pcrel_offset */ 9789+ 9790+ /* 8-bit in-place addition, for local label subtraction. */ 9791+ HOWTO (R_RISCV_SUB8, /* type */ 9792+ 0, /* rightshift */ 9793+ 0, /* size (0 = byte, 1 = short, 2 = long) */ 9794+ 8, /* bitsize */ 9795+ FALSE, /* pc_relative */ 9796+ 0, /* bitpos */ 9797+ complain_overflow_dont, /* complain_on_overflow */ 9798+ bfd_elf_generic_reloc, /* special_function */ 9799+ "R_RISCV_SUB8", /* name */ 9800+ FALSE, /* partial_inplace */ 9801+ 0, /* src_mask */ 9802+ MINUS_ONE, /* dst_mask */ 9803+ FALSE), /* pcrel_offset */ 9804+ 9805+ /* 16-bit in-place addition, for local label subtraction. */ 9806+ HOWTO (R_RISCV_SUB16, /* type */ 9807+ 0, /* rightshift */ 9808+ 1, /* size (0 = byte, 1 = short, 2 = long) */ 9809+ 16, /* bitsize */ 9810+ FALSE, /* pc_relative */ 9811+ 0, /* bitpos */ 9812+ complain_overflow_dont, /* complain_on_overflow */ 9813+ bfd_elf_generic_reloc, /* special_function */ 9814+ "R_RISCV_SUB16", /* name */ 9815+ FALSE, /* partial_inplace */ 9816+ 0, /* src_mask */ 9817+ MINUS_ONE, /* dst_mask */ 9818+ FALSE), /* pcrel_offset */ 9819+ 9820+ /* 32-bit in-place addition, for local label subtraction. */ 9821+ HOWTO (R_RISCV_SUB32, /* type */ 9822+ 0, /* rightshift */ 9823+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9824+ 32, /* bitsize */ 9825+ FALSE, /* pc_relative */ 9826+ 0, /* bitpos */ 9827+ complain_overflow_dont, /* complain_on_overflow */ 9828+ bfd_elf_generic_reloc, /* special_function */ 9829+ "R_RISCV_SUB32", /* name */ 9830+ FALSE, /* partial_inplace */ 9831+ 0, /* src_mask */ 9832+ MINUS_ONE, /* dst_mask */ 9833+ FALSE), /* pcrel_offset */ 9834+ 9835+ /* 64-bit in-place addition, for local label subtraction. */ 9836+ HOWTO (R_RISCV_SUB64, /* type */ 9837+ 0, /* rightshift */ 9838+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9839+ 64, /* bitsize */ 9840+ FALSE, /* pc_relative */ 9841+ 0, /* bitpos */ 9842+ complain_overflow_dont, /* complain_on_overflow */ 9843+ bfd_elf_generic_reloc, /* special_function */ 9844+ "R_RISCV_SUB64", /* name */ 9845+ FALSE, /* partial_inplace */ 9846+ 0, /* src_mask */ 9847+ MINUS_ONE, /* dst_mask */ 9848+ FALSE), /* pcrel_offset */ 9849+ 9850+ /* GNU extension to record C++ vtable hierarchy */ 9851+ HOWTO (R_RISCV_GNU_VTINHERIT, /* type */ 9852+ 0, /* rightshift */ 9853+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9854+ 0, /* bitsize */ 9855+ FALSE, /* pc_relative */ 9856+ 0, /* bitpos */ 9857+ complain_overflow_dont,/* complain_on_overflow */ 9858+ NULL, /* special_function */ 9859+ "R_RISCV_GNU_VTINHERIT", /* name */ 9860+ FALSE, /* partial_inplace */ 9861+ 0, /* src_mask */ 9862+ 0, /* dst_mask */ 9863+ FALSE), /* pcrel_offset */ 9864+ 9865+ /* GNU extension to record C++ vtable member usage */ 9866+ HOWTO (R_RISCV_GNU_VTENTRY, /* type */ 9867+ 0, /* rightshift */ 9868+ 4, /* size (0 = byte, 1 = short, 2 = long) */ 9869+ 0, /* bitsize */ 9870+ FALSE, /* pc_relative */ 9871+ 0, /* bitpos */ 9872+ complain_overflow_dont,/* complain_on_overflow */ 9873+ _bfd_elf_rel_vtable_reloc_fn, /* special_function */ 9874+ "R_RISCV_GNU_VTENTRY", /* name */ 9875+ FALSE, /* partial_inplace */ 9876+ 0, /* src_mask */ 9877+ 0, /* dst_mask */ 9878+ FALSE), /* pcrel_offset */ 9879+ 9880+ /* Indicates an alignment statement. The addend field encodes how many 9881+ bytes of NOPs follow the statement. The desired alignment is the 9882+ addend rounded up to the next power of two. */ 9883+ HOWTO (R_RISCV_ALIGN, /* type */ 9884+ 0, /* rightshift */ 9885+ 2, /* size (0 = byte, 1 = short, 2 = long) */ 9886+ 0, /* bitsize */ 9887+ FALSE, /* pc_relative */ 9888+ 0, /* bitpos */ 9889+ complain_overflow_dont, /* complain_on_overflow */ 9890+ bfd_elf_generic_reloc, /* special_function */ 9891+ "R_RISCV_ALIGN", /* name */ 9892+ FALSE, /* partial_inplace */ 9893+ 0, /* src_mask */ 9894+ 0, /* dst_mask */ 9895+ TRUE), /* pcrel_offset */ 9896+}; 9897+ 9898+/* A mapping from BFD reloc types to RISC-V ELF reloc types. */ 9899+ 9900+struct elf_reloc_map { 9901+ bfd_reloc_code_real_type bfd_val; 9902+ enum elf_riscv_reloc_type elf_val; 9903+}; 9904+ 9905+static const struct elf_reloc_map riscv_reloc_map[] = 9906+{ 9907+ { BFD_RELOC_NONE, R_RISCV_NONE }, 9908+ { BFD_RELOC_32, R_RISCV_32 }, 9909+ { BFD_RELOC_64, R_RISCV_64 }, 9910+ { BFD_RELOC_RISCV_ADD8, R_RISCV_ADD8 }, 9911+ { BFD_RELOC_RISCV_ADD16, R_RISCV_ADD16 }, 9912+ { BFD_RELOC_RISCV_ADD32, R_RISCV_ADD32 }, 9913+ { BFD_RELOC_RISCV_ADD64, R_RISCV_ADD64 }, 9914+ { BFD_RELOC_RISCV_SUB8, R_RISCV_SUB8 }, 9915+ { BFD_RELOC_RISCV_SUB16, R_RISCV_SUB16 }, 9916+ { BFD_RELOC_RISCV_SUB32, R_RISCV_SUB32 }, 9917+ { BFD_RELOC_RISCV_SUB64, R_RISCV_SUB64 }, 9918+ { BFD_RELOC_CTOR, R_RISCV_64 }, 9919+ { BFD_RELOC_12_PCREL, R_RISCV_BRANCH }, 9920+ { BFD_RELOC_RISCV_HI20, R_RISCV_HI20 }, 9921+ { BFD_RELOC_RISCV_LO12_I, R_RISCV_LO12_I }, 9922+ { BFD_RELOC_RISCV_LO12_S, R_RISCV_LO12_S }, 9923+ { BFD_RELOC_RISCV_PCREL_LO12_I, R_RISCV_PCREL_LO12_I }, 9924+ { BFD_RELOC_RISCV_PCREL_LO12_S, R_RISCV_PCREL_LO12_S }, 9925+ { BFD_RELOC_RISCV_CALL, R_RISCV_CALL }, 9926+ { BFD_RELOC_RISCV_CALL_PLT, R_RISCV_CALL_PLT }, 9927+ { BFD_RELOC_RISCV_PCREL_HI20, R_RISCV_PCREL_HI20 }, 9928+ { BFD_RELOC_RISCV_JMP, R_RISCV_JAL }, 9929+ { BFD_RELOC_RISCV_GOT_HI20, R_RISCV_GOT_HI20 }, 9930+ { BFD_RELOC_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD32 }, 9931+ { BFD_RELOC_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL32 }, 9932+ { BFD_RELOC_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPMOD64 }, 9933+ { BFD_RELOC_RISCV_TLS_DTPREL64, R_RISCV_TLS_DTPREL64 }, 9934+ { BFD_RELOC_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL32 }, 9935+ { BFD_RELOC_RISCV_TLS_TPREL64, R_RISCV_TLS_TPREL64 }, 9936+ { BFD_RELOC_RISCV_TPREL_HI20, R_RISCV_TPREL_HI20 }, 9937+ { BFD_RELOC_RISCV_TPREL_ADD, R_RISCV_TPREL_ADD }, 9938+ { BFD_RELOC_RISCV_TPREL_LO12_S, R_RISCV_TPREL_LO12_S }, 9939+ { BFD_RELOC_RISCV_TPREL_LO12_I, R_RISCV_TPREL_LO12_I }, 9940+ { BFD_RELOC_RISCV_TLS_GOT_HI20, R_RISCV_TLS_GOT_HI20 }, 9941+ { BFD_RELOC_RISCV_TLS_GD_HI20, R_RISCV_TLS_GD_HI20 }, 9942+ { BFD_RELOC_RISCV_ALIGN, R_RISCV_ALIGN }, 9943+}; 9944+ 9945+/* Given a BFD reloc type, return a howto structure. */ 9946+ 9947+reloc_howto_type * 9948+riscv_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, 9949+ bfd_reloc_code_real_type code) 9950+{ 9951+ unsigned int i; 9952+ 9953+ for (i = 0; i < ARRAY_SIZE (riscv_reloc_map); i++) 9954+ if (riscv_reloc_map[i].bfd_val == code) 9955+ return &howto_table[(int) riscv_reloc_map[i].elf_val]; 9956+ 9957+ bfd_set_error (bfd_error_bad_value); 9958+ return NULL; 9959+} 9960+ 9961+reloc_howto_type * 9962+riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 9963+ const char *r_name) 9964+{ 9965+ unsigned int i; 9966+ 9967+ for (i = 0; i < ARRAY_SIZE (howto_table); i++) 9968+ if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0) 9969+ return &howto_table[i]; 9970+ 9971+ return NULL; 9972+} 9973+ 9974+reloc_howto_type * 9975+riscv_elf_rtype_to_howto (unsigned int r_type) 9976+{ 9977+ if ((unsigned int)r_type >= ARRAY_SIZE (howto_table)) 9978+ { 9979+ (*_bfd_error_handler)(_("unrecognized relocation (0x%x)"), r_type); 9980+ bfd_set_error (bfd_error_bad_value); 9981+ return NULL; 9982+ } 9983+ return &howto_table[r_type]; 9984+} 9985diff -rNU3 dist.orig/bfd/elfxx-riscv.h dist/bfd/elfxx-riscv.h 9986--- dist.orig/bfd/elfxx-riscv.h 1970-01-01 01:00:00.000000000 +0100 9987+++ dist/bfd/elfxx-riscv.h 2015-10-18 13:11:13.000000000 +0200 9988@@ -0,0 +1,34 @@ 9989+/* RISC-V ELF specific backend routines. 9990+ Copyright 2011-2014 Free Software Foundation, Inc. 9991+ 9992+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 9993+ Based on MIPS target. 9994+ 9995+ This file is part of BFD, the Binary File Descriptor library. 9996+ 9997+ This program is free software; you can redistribute it and/or modify 9998+ it under the terms of the GNU General Public License as published by 9999+ the Free Software Foundation; either version 3 of the License, or 10000+ (at your option) any later version. 10001+ 10002+ This program is distributed in the hope that it will be useful, 10003+ but WITHOUT ANY WARRANTY; without even the implied warranty of 10004+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10005+ GNU General Public License for more details. 10006+ 10007+ You should have received a copy of the GNU General Public License 10008+ along with this program; if not, write to the Free Software 10009+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 10010+ MA 02110-1301, USA. */ 10011+ 10012+#include "elf/common.h" 10013+#include "elf/internal.h" 10014+ 10015+extern reloc_howto_type * 10016+riscv_reloc_name_lookup (bfd *, const char *); 10017+ 10018+extern reloc_howto_type * 10019+riscv_reloc_type_lookup (bfd *, bfd_reloc_code_real_type); 10020+ 10021+extern reloc_howto_type * 10022+riscv_elf_rtype_to_howto (unsigned int r_type); 10023diff -rNU3 dist.orig/bfd/elfxx-sparc.c dist/bfd/elfxx-sparc.c 10024--- dist.orig/bfd/elfxx-sparc.c 2013-03-25 09:06:20.000000000 +0100 10025+++ dist/bfd/elfxx-sparc.c 2015-10-18 13:11:13.000000000 +0200 10026@@ -2508,6 +2508,10 @@ 10027 { 10028 struct bfd_link_info *info = (struct bfd_link_info *) inf; 10029 10030+ if (info->warn_shared_textrel) 10031+ (*_bfd_error_handler) 10032+ (_("warning: dynamic relocation in readonly section `%s'"), 10033+ h->root.root.string); 10034 info->flags |= DF_TEXTREL; 10035 10036 /* Not an error, just cut short the traversal. */ 10037@@ -3460,10 +3464,8 @@ 10038 memset (&outrel, 0, sizeof outrel); 10039 /* h->dynindx may be -1 if the symbol was marked to 10040 become local. */ 10041- else if (h != NULL && 10042- h->dynindx != -1 10043- && (! is_plt 10044- || !info->shared 10045+ else if (h != NULL && h->dynindx != -1 && ! is_plt 10046+ && (!info->shared 10047 || !SYMBOLIC_BIND (info, h) 10048 || !h->def_regular)) 10049 { 10050diff -rNU3 dist.orig/bfd/libbfd.h dist/bfd/libbfd.h 10051--- dist.orig/bfd/libbfd.h 2012-09-04 14:53:42.000000000 +0200 10052+++ dist/bfd/libbfd.h 2015-10-18 13:11:13.000000000 +0200 10053@@ -2295,8 +2295,65 @@ 10054 "BFD_RELOC_860_HIGH", 10055 "BFD_RELOC_860_HIGOT", 10056 "BFD_RELOC_860_HIGOTOFF", 10057- "BFD_RELOC_OPENRISC_ABS_26", 10058- "BFD_RELOC_OPENRISC_REL_26", 10059+ "BFD_RELOC_OR1K_REL_26", 10060+ "BFD_RELOC_OR1K_GOTPC_HI16", 10061+ "BFD_RELOC_OR1K_GOTPC_LO16", 10062+ "BFD_RELOC_OR1K_GOT16", 10063+ "BFD_RELOC_OR1K_PLT26", 10064+ "BFD_RELOC_OR1K_GOTOFF_HI16", 10065+ "BFD_RELOC_OR1K_GOTOFF_LO16", 10066+ "BFD_RELOC_OR1K_COPY", 10067+ "BFD_RELOC_OR1K_GLOB_DAT", 10068+ "BFD_RELOC_OR1K_JMP_SLOT", 10069+ "BFD_RELOC_OR1K_RELATIVE", 10070+ "BFD_RELOC_OR1K_TLS_GD_HI16", 10071+ "BFD_RELOC_OR1K_TLS_GD_LO16", 10072+ "BFD_RELOC_OR1K_TLS_LDM_HI16", 10073+ "BFD_RELOC_OR1K_TLS_LDM_LO16", 10074+ "BFD_RELOC_OR1K_TLS_LDO_HI16", 10075+ "BFD_RELOC_OR1K_TLS_LDO_LO16", 10076+ "BFD_RELOC_OR1K_TLS_IE_HI16", 10077+ "BFD_RELOC_OR1K_TLS_IE_LO16", 10078+ "BFD_RELOC_OR1K_TLS_LE_HI16", 10079+ "BFD_RELOC_OR1K_TLS_LE_LO16", 10080+ "BFD_RELOC_OR1K_TLS_TPOFF", 10081+ "BFD_RELOC_OR1K_TLS_DTPOFF", 10082+ "BFD_RELOC_OR1K_TLS_DTPMOD", 10083+ "BFD_RELOC_RISCV_ADD32", 10084+ "BFD_RELOC_RISCV_ADD64", 10085+ "BFD_RELOC_RISCV_SUB32", 10086+ "BFD_RELOC_RISCV_SUB64", 10087+ "BFD_RELOC_RISCV_HI20", 10088+ "BFD_RELOC_RISCV_LO12_I", 10089+ "BFD_RELOC_RISCV_LO12_S", 10090+ "BFD_RELOC_RISCV_PCREL_LO12_I", 10091+ "BFD_RELOC_RISCV_PCREL_LO12_S", 10092+ "BFD_RELOC_RISCV_CALL", 10093+ "BFD_RELOC_RISCV_CALL_PLT", 10094+ "BFD_RELOC_RISCV_PCREL_HI20", 10095+ "BFD_RELOC_RISCV_JMP", 10096+ "BFD_RELOC_RISCV_GOT_HI20", 10097+ "BFD_RELOC_RISCV_GOT_LO12", 10098+ "BFD_RELOC_RISCV_TLS_DTPMOD32", 10099+ "BFD_RELOC_RISCV_TLS_DTPREL32", 10100+ "BFD_RELOC_RISCV_TLS_DTPMOD64", 10101+ "BFD_RELOC_RISCV_TLS_DTPREL64", 10102+ "BFD_RELOC_RISCV_TLS_TPREL32", 10103+ "BFD_RELOC_RISCV_TLS_TPREL64", 10104+ "BFD_RELOC_RISCV_TPREL_HI20", 10105+ "BFD_RELOC_RISCV_TPREL_ADD", 10106+ "BFD_RELOC_RISCV_TPREL_LO12_S", 10107+ "BFD_RELOC_RISCV_TPREL_LO12_I", 10108+ "BFD_RELOC_RISCV_TLS_IE_HI20", 10109+ "BFD_RELOC_RISCV_TLS_IE_LO12", 10110+ "BFD_RELOC_RISCV_TLS_IE_ADD", 10111+ "BFD_RELOC_RISCV_TLS_IE_LO12_S", 10112+ "BFD_RELOC_RISCV_TLS_IE_LO12_I", 10113+ "BFD_RELOC_RISCV_TLS_GOT_HI20", 10114+ "BFD_RELOC_RISCV_TLS_GOT_LO12", 10115+ "BFD_RELOC_RISCV_TLS_GD_HI20", 10116+ "BFD_RELOC_RISCV_TLS_GD_LO12", 10117+ "BFD_RELOC_RISCV_TLS_PCREL_LO12", 10118 "BFD_RELOC_H8_DIR16A8", 10119 "BFD_RELOC_H8_DIR16R8", 10120 "BFD_RELOC_H8_DIR24A8", 10121@@ -2313,6 +2370,7 @@ 10122 "BFD_RELOC_XC16X_SEG", 10123 "BFD_RELOC_XC16X_SOF", 10124 "BFD_RELOC_VAX_GLOB_DAT", 10125+ "BFD_RELOC_VAX_GLOB_REF", 10126 "BFD_RELOC_VAX_JMP_SLOT", 10127 "BFD_RELOC_VAX_RELATIVE", 10128 "BFD_RELOC_MT_PC16", 10129diff -rNU3 dist.orig/bfd/reloc.c dist/bfd/reloc.c 10130--- dist.orig/bfd/reloc.c 2012-09-04 14:53:42.000000000 +0200 10131+++ dist/bfd/reloc.c 2015-10-18 13:11:13.000000000 +0200 10132@@ -1776,6 +1776,17 @@ 10133 Relocations used by 68K ELF. 10134 10135 ENUM 10136+ BFD_RELOC_VAX_GLOB_DAT 10137+ENUMX 10138+ BFD_RELOC_VAX_GLOB_REF 10139+ENUMX 10140+ BFD_RELOC_VAX_JMP_SLOT 10141+ENUMX 10142+ BFD_RELOC_VAX_RELATIVE 10143+ENUMDOC 10144+ Relocations used by VAX ELF. 10145+ 10146+ENUM 10147 BFD_RELOC_32_BASEREL 10148 ENUMX 10149 BFD_RELOC_16_BASEREL 10150diff -rNU3 dist.orig/bfd/targets.c dist/bfd/targets.c 10151--- dist.orig/bfd/targets.c 2012-09-04 14:53:42.000000000 +0200 10152+++ dist/bfd/targets.c 2015-10-18 13:11:13.000000000 +0200 10153@@ -670,13 +670,14 @@ 10154 extern const bfd_target bfd_elf32_ntradbigmips_freebsd_vec; 10155 extern const bfd_target bfd_elf32_ntradlittlemips_freebsd_vec; 10156 extern const bfd_target bfd_elf32_openrisc_vec; 10157-extern const bfd_target bfd_elf32_or32_big_vec; 10158+extern const bfd_target bfd_elf32_or1k_big_vec; 10159 extern const bfd_target bfd_elf32_pj_vec; 10160 extern const bfd_target bfd_elf32_pjl_vec; 10161 extern const bfd_target bfd_elf32_powerpc_vec; 10162 extern const bfd_target bfd_elf32_powerpcle_vec; 10163 extern const bfd_target bfd_elf32_powerpc_freebsd_vec; 10164 extern const bfd_target bfd_elf32_powerpc_vxworks_vec; 10165+extern const bfd_target bfd_elf32_riscv_vec; 10166 extern const bfd_target bfd_elf32_rl78_vec; 10167 extern const bfd_target bfd_elf32_rx_le_vec; 10168 extern const bfd_target bfd_elf32_rx_be_vec; 10169@@ -729,8 +730,8 @@ 10170 extern const bfd_target bfd_elf64_alpha_freebsd_vec; 10171 extern const bfd_target bfd_elf64_alpha_vec; 10172 extern const bfd_target bfd_elf64_big_generic_vec; 10173-extern const bfd_target bfd_elf64_bigmips_vec; 10174 extern const bfd_target bfd_elf64_bigaarch64_vec; 10175+extern const bfd_target bfd_elf64_bigmips_vec; 10176 extern const bfd_target bfd_elf64_hppa_linux_vec; 10177 extern const bfd_target bfd_elf64_hppa_vec; 10178 extern const bfd_target bfd_elf64_ia64_big_vec; 10179@@ -738,12 +739,13 @@ 10180 extern const bfd_target bfd_elf64_ia64_little_vec; 10181 extern const bfd_target bfd_elf64_ia64_vms_vec; 10182 extern const bfd_target bfd_elf64_little_generic_vec; 10183-extern const bfd_target bfd_elf64_littlemips_vec; 10184 extern const bfd_target bfd_elf64_littleaarch64_vec; 10185+extern const bfd_target bfd_elf64_littlemips_vec; 10186 extern const bfd_target bfd_elf64_mmix_vec; 10187 extern const bfd_target bfd_elf64_powerpc_vec; 10188 extern const bfd_target bfd_elf64_powerpcle_vec; 10189 extern const bfd_target bfd_elf64_powerpc_freebsd_vec; 10190+extern const bfd_target bfd_elf64_riscv_vec; 10191 extern const bfd_target bfd_elf64_s390_vec; 10192 extern const bfd_target bfd_elf64_sh64_vec; 10193 extern const bfd_target bfd_elf64_sh64l_vec; 10194@@ -833,7 +835,7 @@ 10195 extern const bfd_target nlm32_powerpc_vec; 10196 extern const bfd_target nlm32_sparc_vec; 10197 extern const bfd_target oasys_vec; 10198-extern const bfd_target or32coff_big_vec; 10199+extern const bfd_target or1kcoff_big_vec; 10200 extern const bfd_target pc532machaout_vec; 10201 extern const bfd_target pc532netbsd_vec; 10202 extern const bfd_target pdp11_aout_vec; 10203@@ -1046,13 +1048,14 @@ 10204 &bfd_elf32_ntradlittlemips_freebsd_vec, 10205 #endif 10206 &bfd_elf32_openrisc_vec, 10207- &bfd_elf32_or32_big_vec, 10208+ &bfd_elf32_or1k_big_vec, 10209 &bfd_elf32_pj_vec, 10210 &bfd_elf32_pjl_vec, 10211 &bfd_elf32_powerpc_vec, 10212 &bfd_elf32_powerpc_vxworks_vec, 10213 &bfd_elf32_powerpcle_vec, 10214 &bfd_elf32_powerpc_freebsd_vec, 10215+ &bfd_elf32_riscv_vec, 10216 &bfd_elf32_rl78_vec, 10217 &bfd_elf32_rx_be_vec, 10218 &bfd_elf32_rx_be_ns_vec, 10219@@ -1106,8 +1109,8 @@ 10220 &bfd_elf64_alpha_freebsd_vec, 10221 &bfd_elf64_alpha_vec, 10222 &bfd_elf64_big_generic_vec, 10223- &bfd_elf64_bigmips_vec, 10224 &bfd_elf64_bigaarch64_vec, 10225+ &bfd_elf64_bigmips_vec, 10226 &bfd_elf64_hppa_linux_vec, 10227 &bfd_elf64_hppa_vec, 10228 &bfd_elf64_ia64_big_vec, 10229@@ -1115,12 +1118,13 @@ 10230 &bfd_elf64_ia64_little_vec, 10231 &bfd_elf64_ia64_vms_vec, 10232 &bfd_elf64_little_generic_vec, 10233- &bfd_elf64_littlemips_vec, 10234 &bfd_elf64_littleaarch64_vec, 10235+ &bfd_elf64_littlemips_vec, 10236 &bfd_elf64_mmix_vec, 10237 &bfd_elf64_powerpc_vec, 10238 &bfd_elf64_powerpcle_vec, 10239 &bfd_elf64_powerpc_freebsd_vec, 10240+ &bfd_elf64_riscv_vec, 10241 &bfd_elf64_s390_vec, 10242 &bfd_elf64_sh64_vec, 10243 &bfd_elf64_sh64l_vec, 10244@@ -1252,7 +1256,7 @@ 10245 &oasys_vec, 10246 #endif 10247 /* Entry for the OpenRISC family. */ 10248- &or32coff_big_vec, 10249+ &or1kcoff_big_vec, 10250 10251 &pc532machaout_vec, 10252 &pc532netbsd_vec, 10253diff -rNU3 dist.orig/binutils/Makefile.in dist/binutils/Makefile.in 10254--- dist.orig/binutils/Makefile.in 2012-05-18 00:23:39.000000000 +0200 10255+++ dist/binutils/Makefile.in 2015-10-18 13:11:13.000000000 +0200 10256@@ -1,4 +1,4 @@ 10257-# Makefile.in generated by automake 1.11.1 from Makefile.am. 10258+# Makefile.in generated by automake 1.11 from Makefile.am. 10259 # @configure_input@ 10260 10261 # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 10262@@ -49,10 +49,12 @@ 10263 DIST_COMMON = NEWS README ChangeLog $(srcdir)/Makefile.in \ 10264 $(srcdir)/Makefile.am $(top_srcdir)/configure \ 10265 $(am__configure_deps) $(srcdir)/config.in \ 10266- $(srcdir)/../mkinstalldirs $(top_srcdir)/po/Make-in arparse.h \ 10267- arparse.c arlex.c defparse.h defparse.c deflex.c nlmheader.h \ 10268- nlmheader.c arparse.h arparse.c arlex.c mcparse.h mcparse.c \ 10269- rcparse.h rcparse.c $(srcdir)/../depcomp $(srcdir)/../ylwrap 10270+ $(srcdir)/../mkinstalldirs $(srcdir)/../mkinstalldirs \ 10271+ $(top_srcdir)/po/Make-in arparse.h arparse.c arlex.c \ 10272+ defparse.h defparse.c deflex.c nlmheader.h nlmheader.c \ 10273+ arparse.h arparse.c arlex.c mcparse.h mcparse.c rcparse.h \ 10274+ rcparse.c $(srcdir)/../depcomp $(srcdir)/../depcomp \ 10275+ $(srcdir)/../ylwrap $(srcdir)/../ylwrap 10276 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 10277 am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \ 10278 $(top_srcdir)/../config/zlib.m4 \ 10279@@ -385,6 +387,7 @@ 10280 libexecdir = @libexecdir@ 10281 localedir = @localedir@ 10282 localstatedir = @localstatedir@ 10283+lt_ECHO = @lt_ECHO@ 10284 mandir = @mandir@ 10285 mkdir_p = @mkdir_p@ 10286 oldincludedir = @oldincludedir@ 10287@@ -931,7 +934,7 @@ 10288 # (which will cause the Makefiles to be regenerated when you run `make'); 10289 # (2) otherwise, pass the desired values on the `make' command line. 10290 $(RECURSIVE_TARGETS): 10291- @fail= failcom='exit 1'; \ 10292+ @failcom='exit 1'; \ 10293 for f in x $$MAKEFLAGS; do \ 10294 case $$f in \ 10295 *=* | --[!k]*);; \ 10296@@ -956,7 +959,7 @@ 10297 fi; test -z "$$fail" 10298 10299 $(RECURSIVE_CLEAN_TARGETS): 10300- @fail= failcom='exit 1'; \ 10301+ @failcom='exit 1'; \ 10302 for f in x $$MAKEFLAGS; do \ 10303 case $$f in \ 10304 *=* | --[!k]*);; \ 10305diff -rNU3 dist.orig/binutils/aclocal.m4 dist/binutils/aclocal.m4 10306--- dist.orig/binutils/aclocal.m4 2012-05-18 00:23:39.000000000 +0200 10307+++ dist/binutils/aclocal.m4 2015-10-18 13:11:13.000000000 +0200 10308@@ -1,4 +1,4 @@ 10309-# generated automatically by aclocal 1.11.1 -*- Autoconf -*- 10310+# generated automatically by aclocal 1.11 -*- Autoconf -*- 10311 10312 # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 10313 # 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. 10314@@ -19,6 +19,31 @@ 10315 If you have problems, you may need to regenerate the build system entirely. 10316 To do so, use the procedure documented by the package, typically `autoreconf'.])]) 10317 10318+# isc-posix.m4 serial 2 (gettext-0.11.2) 10319+dnl Copyright (C) 1995-2002 Free Software Foundation, Inc. 10320+dnl This file is free software; the Free Software Foundation 10321+dnl gives unlimited permission to copy and/or distribute it, 10322+dnl with or without modifications, as long as this notice is preserved. 10323+ 10324+# This file is not needed with autoconf-2.53 and newer. Remove it in 2005. 10325+ 10326+# This test replaces the one in autoconf. 10327+# Currently this macro should have the same name as the autoconf macro 10328+# because gettext's gettext.m4 (distributed in the automake package) 10329+# still uses it. Otherwise, the use in gettext.m4 makes autoheader 10330+# give these diagnostics: 10331+# configure.in:556: AC_TRY_COMPILE was called before AC_ISC_POSIX 10332+# configure.in:556: AC_TRY_RUN was called before AC_ISC_POSIX 10333+ 10334+undefine([AC_ISC_POSIX]) 10335+ 10336+AC_DEFUN([AC_ISC_POSIX], 10337+ [ 10338+ dnl This test replaces the obsolescent AC_ISC_POSIX kludge. 10339+ AC_CHECK_LIB(cposix, strerror, [LIBS="$LIBS -lcposix"]) 10340+ ] 10341+) 10342+ 10343 # Copyright (C) 2002, 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. 10344 # 10345 # This file is free software; the Free Software Foundation 10346@@ -34,7 +59,7 @@ 10347 [am__api_version='1.11' 10348 dnl Some users find AM_AUTOMAKE_VERSION and mistake it for a way to 10349 dnl require some minimum version. Point them to the right macro. 10350-m4_if([$1], [1.11.1], [], 10351+m4_if([$1], [1.11], [], 10352 [AC_FATAL([Do not call $0, use AM_INIT_AUTOMAKE([$1]).])])dnl 10353 ]) 10354 10355@@ -50,7 +75,7 @@ 10356 # Call AM_AUTOMAKE_VERSION and AM_AUTOMAKE_VERSION so they can be traced. 10357 # This function is AC_REQUIREd by AM_INIT_AUTOMAKE. 10358 AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION], 10359-[AM_AUTOMAKE_VERSION([1.11.1])dnl 10360+[AM_AUTOMAKE_VERSION([1.11])dnl 10361 m4_ifndef([AC_AUTOCONF_VERSION], 10362 [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl 10363 _AM_AUTOCONF_VERSION(m4_defn([AC_AUTOCONF_VERSION]))]) 10364diff -rNU3 dist.orig/binutils/bucomm.c dist/binutils/bucomm.c 10365--- dist.orig/binutils/bucomm.c 2012-06-29 14:59:49.000000000 +0200 10366+++ dist/binutils/bucomm.c 2015-10-18 13:11:13.000000000 +0200 10367@@ -580,7 +580,14 @@ 10368 file_name, strerror (errno)); 10369 } 10370 else if (! S_ISREG (statbuf.st_mode)) 10371- non_fatal (_("Warning: '%s' is not an ordinary file"), file_name); 10372+ { 10373+ if (!S_ISCHR(statbuf.st_mode)) 10374+ { 10375+ non_fatal (_("Warning: '%s' is not an ordinary file"), file_name); 10376+ return 0; 10377+ } 10378+ return statbuf.st_size ? statbuf.st_size : 1; 10379+ } 10380 else if (statbuf.st_size < 0) 10381 non_fatal (_("Warning: '%s' has negative size, probably it is too large"), 10382 file_name); 10383diff -rNU3 dist.orig/binutils/doc/Makefile.am dist/binutils/doc/Makefile.am 10384--- dist.orig/binutils/doc/Makefile.am 2010-01-06 17:52:14.000000000 +0100 10385+++ dist/binutils/doc/Makefile.am 2015-10-18 13:11:13.000000000 +0200 10386@@ -42,6 +42,8 @@ 10387 10388 # Man page generation from texinfo 10389 addr2line.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10390+ @echo "NOT REBUILDING $@" 10391+NetBSD_DISABLED_addr2line.1: 10392 touch $@ 10393 -$(TEXI2POD) $(MANCONF) -Daddr2line < $(binutils_TEXI) > addr2line.pod 10394 -($(POD2MAN) addr2line.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10395@@ -49,6 +51,8 @@ 10396 rm -f addr2line.pod 10397 10398 ar.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10399+ @echo "NOT REBUILDING $@" 10400+NetBSD_DISABLED_ar.1: 10401 touch $@ 10402 -$(TEXI2POD) $(MANCONF) -Dar < $(binutils_TEXI) > ar.pod 10403 -($(POD2MAN) ar.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10404@@ -56,6 +60,8 @@ 10405 rm -f ar.pod 10406 10407 dlltool.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10408+ @echo "NOT REBUILDING $@" 10409+NetBSD_DISABLED_dlltool.1: 10410 touch $@ 10411 -$(TEXI2POD) $(MANCONF) -Ddlltool < $(binutils_TEXI) > dlltool.pod 10412 -($(POD2MAN) dlltool.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10413@@ -63,6 +69,8 @@ 10414 rm -f dlltool.pod 10415 10416 nlmconv.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10417+ @echo "NOT REBUILDING $@" 10418+NetBSD_DISABLED_nlmconv.1: 10419 touch $@ 10420 -$(TEXI2POD) $(MANCONF) -Dnlmconv < $(binutils_TEXI) > nlmconv.pod 10421 -($(POD2MAN) nlmconv.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10422@@ -70,6 +78,8 @@ 10423 rm -f nlmconv.pod 10424 10425 nm.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10426+ @echo "NOT REBUILDING $@" 10427+NetBSD_DISABLED_nm.1: 10428 touch $@ 10429 -$(TEXI2POD) $(MANCONF) -Dnm < $(binutils_TEXI) > nm.pod 10430 -($(POD2MAN) nm.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10431@@ -77,6 +87,8 @@ 10432 rm -f nm.pod 10433 10434 objcopy.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10435+ @echo "NOT REBUILDING $@" 10436+NetBSD_DISABLED_objcopy.1: 10437 touch $@ 10438 -$(TEXI2POD) $(MANCONF) -Dobjcopy < $(binutils_TEXI) > objcopy.pod 10439 -($(POD2MAN) objcopy.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10440@@ -84,6 +96,8 @@ 10441 rm -f objcopy.pod 10442 10443 objdump.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10444+ @echo "NOT REBUILDING $@" 10445+NetBSD_DISABLED_objdump.1: 10446 touch $@ 10447 -$(TEXI2POD) $(MANCONF) -Dobjdump < $(binutils_TEXI) > objdump.pod 10448 -($(POD2MAN) objdump.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10449@@ -91,6 +105,8 @@ 10450 rm -f objdump.pod 10451 10452 ranlib.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10453+ @echo "NOT REBUILDING $@" 10454+NetBSD_DISABLED_ranlib.1: 10455 touch $@ 10456 -$(TEXI2POD) $(MANCONF) -Dranlib < $(binutils_TEXI) > ranlib.pod 10457 -($(POD2MAN) ranlib.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10458@@ -98,6 +114,8 @@ 10459 rm -f ranlib.pod 10460 10461 readelf.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10462+ @echo "NOT REBUILDING $@" 10463+NetBSD_DISABLED_readelf.1: 10464 touch $@ 10465 -$(TEXI2POD) $(MANCONF) -Dreadelf < $(binutils_TEXI) > readelf.pod 10466 -($(POD2MAN) readelf.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10467@@ -105,6 +123,8 @@ 10468 rm -f readelf.pod 10469 10470 size.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10471+ @echo "NOT REBUILDING $@" 10472+NetBSD_DISABLED_size.1: 10473 touch $@ 10474 -$(TEXI2POD) $(MANCONF) -Dsize < $(binutils_TEXI) > size.pod 10475 -($(POD2MAN) size.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10476@@ -112,6 +132,8 @@ 10477 rm -f size.pod 10478 10479 strings.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10480+ @echo "NOT REBUILDING $@" 10481+NetBSD_DISABLED_strings.1: 10482 touch $@ 10483 -$(TEXI2POD) $(MANCONF) -Dstrings < $(binutils_TEXI) > strings.pod 10484 -($(POD2MAN) strings.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10485@@ -119,6 +141,8 @@ 10486 rm -f strings.pod 10487 10488 strip.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10489+ @echo "NOT REBUILDING $@" 10490+NetBSD_DISABLED_strip.1: 10491 touch $@ 10492 -$(TEXI2POD) $(MANCONF) -Dstrip < $(binutils_TEXI) > strip.pod 10493 -($(POD2MAN) strip.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10494@@ -133,6 +157,8 @@ 10495 rm -f elfedit.pod 10496 10497 windres.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10498+ @echo "NOT REBUILDING $@" 10499+NetBSD_DISABLED_windres.1: 10500 touch $@ 10501 -$(TEXI2POD) $(MANCONF) -Dwindres < $(binutils_TEXI) > windres.pod 10502 -($(POD2MAN) windres.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10503@@ -140,6 +166,8 @@ 10504 rm -f windres.pod 10505 10506 windmc.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10507+ @echo "NOT REBUILDING $@" 10508+NetBSD_DISABLED_windmc.1: 10509 touch $@ 10510 -$(TEXI2POD) $(MANCONF) -Dwindmc < $(binutils_TEXI) > windmc.pod 10511 -($(POD2MAN) windmc.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10512@@ -147,6 +175,8 @@ 10513 rm -f windmc.pod 10514 10515 cxxfilt.man: $(binutils_TEXI) $(binutils_TEXINFOS) 10516+ @echo "NOT REBUILDING $@" 10517+NetBSD_DISABLED_cxxfilt.man: 10518 touch $@ 10519 -$(TEXI2POD) $(MANCONF) -Dcxxfilt < $(binutils_TEXI) > $(DEMANGLER_NAME).pod 10520 -($(POD2MAN) $(DEMANGLER_NAME).pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10521diff -rNU3 dist.orig/binutils/doc/Makefile.in dist/binutils/doc/Makefile.in 10522--- dist.orig/binutils/doc/Makefile.in 2012-09-04 14:53:44.000000000 +0200 10523+++ dist/binutils/doc/Makefile.in 2015-10-18 13:11:13.000000000 +0200 10524@@ -1,4 +1,4 @@ 10525-# Makefile.in generated by automake 1.11.1 from Makefile.am. 10526+# Makefile.in generated by automake 1.11 from Makefile.am. 10527 # @configure_input@ 10528 10529 # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 10530@@ -242,6 +242,7 @@ 10531 libexecdir = @libexecdir@ 10532 localedir = @localedir@ 10533 localstatedir = @localstatedir@ 10534+lt_ECHO = @lt_ECHO@ 10535 mandir = @mandir@ 10536 mkdir_p = @mkdir_p@ 10537 oldincludedir = @oldincludedir@ 10538@@ -349,6 +350,8 @@ 10539 -rm -rf .libs _libs 10540 10541 binutils.info: binutils.texi 10542+ @echo "NOT REBUILDING $@" 10543+NetBSD_DISABLED_binutils.info: binutils.texi 10544 restore=: && backupdir="$(am__leading_dot)am$$$$" && \ 10545 rm -rf $$backupdir && mkdir $$backupdir && \ 10546 if ($(MAKEINFO) --version) >/dev/null 2>&1; then \ 10547@@ -735,6 +738,8 @@ 10548 10549 # Man page generation from texinfo 10550 addr2line.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10551+ @echo "NOT REBUILDING $@" 10552+NetBSD_DISABLED_addr2line.1: 10553 touch $@ 10554 -$(TEXI2POD) $(MANCONF) -Daddr2line < $(binutils_TEXI) > addr2line.pod 10555 -($(POD2MAN) addr2line.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10556@@ -742,6 +747,8 @@ 10557 rm -f addr2line.pod 10558 10559 ar.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10560+ @echo "NOT REBUILDING $@" 10561+NetBSD_DISABLED_ar.1: 10562 touch $@ 10563 -$(TEXI2POD) $(MANCONF) -Dar < $(binutils_TEXI) > ar.pod 10564 -($(POD2MAN) ar.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10565@@ -749,6 +756,8 @@ 10566 rm -f ar.pod 10567 10568 dlltool.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10569+ @echo "NOT REBUILDING $@" 10570+NetBSD_DISABLED_dlltool.1: 10571 touch $@ 10572 -$(TEXI2POD) $(MANCONF) -Ddlltool < $(binutils_TEXI) > dlltool.pod 10573 -($(POD2MAN) dlltool.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10574@@ -756,6 +765,8 @@ 10575 rm -f dlltool.pod 10576 10577 nlmconv.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10578+ @echo "NOT REBUILDING $@" 10579+NetBSD_DISABLED_nlmconv.1: 10580 touch $@ 10581 -$(TEXI2POD) $(MANCONF) -Dnlmconv < $(binutils_TEXI) > nlmconv.pod 10582 -($(POD2MAN) nlmconv.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10583@@ -763,6 +774,8 @@ 10584 rm -f nlmconv.pod 10585 10586 nm.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10587+ @echo "NOT REBUILDING $@" 10588+NetBSD_DISABLED_nm.1: 10589 touch $@ 10590 -$(TEXI2POD) $(MANCONF) -Dnm < $(binutils_TEXI) > nm.pod 10591 -($(POD2MAN) nm.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10592@@ -770,6 +783,8 @@ 10593 rm -f nm.pod 10594 10595 objcopy.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10596+ @echo "NOT REBUILDING $@" 10597+NetBSD_DISABLED_objcopy.1: 10598 touch $@ 10599 -$(TEXI2POD) $(MANCONF) -Dobjcopy < $(binutils_TEXI) > objcopy.pod 10600 -($(POD2MAN) objcopy.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10601@@ -777,6 +792,8 @@ 10602 rm -f objcopy.pod 10603 10604 objdump.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10605+ @echo "NOT REBUILDING $@" 10606+NetBSD_DISABLED_objdump.1: 10607 touch $@ 10608 -$(TEXI2POD) $(MANCONF) -Dobjdump < $(binutils_TEXI) > objdump.pod 10609 -($(POD2MAN) objdump.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10610@@ -784,6 +801,8 @@ 10611 rm -f objdump.pod 10612 10613 ranlib.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10614+ @echo "NOT REBUILDING $@" 10615+NetBSD_DISABLED_ranlib.1: 10616 touch $@ 10617 -$(TEXI2POD) $(MANCONF) -Dranlib < $(binutils_TEXI) > ranlib.pod 10618 -($(POD2MAN) ranlib.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10619@@ -791,6 +810,8 @@ 10620 rm -f ranlib.pod 10621 10622 readelf.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10623+ @echo "NOT REBUILDING $@" 10624+NetBSD_DISABLED_readelf.1: 10625 touch $@ 10626 -$(TEXI2POD) $(MANCONF) -Dreadelf < $(binutils_TEXI) > readelf.pod 10627 -($(POD2MAN) readelf.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10628@@ -798,6 +819,8 @@ 10629 rm -f readelf.pod 10630 10631 size.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10632+ @echo "NOT REBUILDING $@" 10633+NetBSD_DISABLED_size.1: 10634 touch $@ 10635 -$(TEXI2POD) $(MANCONF) -Dsize < $(binutils_TEXI) > size.pod 10636 -($(POD2MAN) size.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10637@@ -805,6 +828,8 @@ 10638 rm -f size.pod 10639 10640 strings.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10641+ @echo "NOT REBUILDING $@" 10642+NetBSD_DISABLED_strings.1: 10643 touch $@ 10644 -$(TEXI2POD) $(MANCONF) -Dstrings < $(binutils_TEXI) > strings.pod 10645 -($(POD2MAN) strings.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10646@@ -812,6 +837,8 @@ 10647 rm -f strings.pod 10648 10649 strip.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10650+ @echo "NOT REBUILDING $@" 10651+NetBSD_DISABLED_strip.1: 10652 touch $@ 10653 -$(TEXI2POD) $(MANCONF) -Dstrip < $(binutils_TEXI) > strip.pod 10654 -($(POD2MAN) strip.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10655@@ -819,6 +846,8 @@ 10656 rm -f strip.pod 10657 10658 elfedit.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10659+ @echo "NOT REBUILDING $@" 10660+NetBSD_DISABLED_elfedit.1: 10661 touch $@ 10662 -$(TEXI2POD) $(MANCONF) -Delfedit < $(binutils_TEXI) > elfedit.pod 10663 -($(POD2MAN) elfedit.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10664@@ -826,6 +855,8 @@ 10665 rm -f elfedit.pod 10666 10667 windres.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10668+ @echo "NOT REBUILDING $@" 10669+NetBSD_DISABLED_windres.1: 10670 touch $@ 10671 -$(TEXI2POD) $(MANCONF) -Dwindres < $(binutils_TEXI) > windres.pod 10672 -($(POD2MAN) windres.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10673@@ -833,6 +864,8 @@ 10674 rm -f windres.pod 10675 10676 windmc.1: $(binutils_TEXI) $(binutils_TEXINFOS) 10677+ @echo "NOT REBUILDING $@" 10678+NetBSD_DISABLED_windmc.1: 10679 touch $@ 10680 -$(TEXI2POD) $(MANCONF) -Dwindmc < $(binutils_TEXI) > windmc.pod 10681 -($(POD2MAN) windmc.pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10682@@ -840,6 +873,8 @@ 10683 rm -f windmc.pod 10684 10685 cxxfilt.man: $(binutils_TEXI) $(binutils_TEXINFOS) 10686+ @echo "NOT REBUILDING $@" 10687+NetBSD_DISABLED_cxxfilt.man: 10688 touch $@ 10689 -$(TEXI2POD) $(MANCONF) -Dcxxfilt < $(binutils_TEXI) > $(DEMANGLER_NAME).pod 10690 -($(POD2MAN) $(DEMANGLER_NAME).pod | sed -e '/^.if n .na/d' > $@.T$$$$ && \ 10691diff -rNU3 dist.orig/binutils/doc/readelf.1 dist/binutils/doc/readelf.1 10692--- dist.orig/binutils/doc/readelf.1 2013-03-25 10:10:25.000000000 +0100 10693+++ dist/binutils/doc/readelf.1 2015-10-18 13:11:13.000000000 +0200 10694@@ -146,6 +146,7 @@ 10695 [\fB\-r\fR|\fB\-\-relocs\fR] 10696 [\fB\-u\fR|\fB\-\-unwind\fR] 10697 [\fB\-d\fR|\fB\-\-dynamic\fR] 10698+ [\fB\-f\fR|\fB\-\-special-files\fR] 10699 [\fB\-V\fR|\fB\-\-version\-info\fR] 10700 [\fB\-A\fR|\fB\-\-arch\-specific\fR] 10701 [\fB\-D\fR|\fB\-\-use\-dynamic\fR] 10702@@ -282,6 +283,13 @@ 10703 .IX Item "--dynamic" 10704 .PD 10705 Displays the contents of the file's dynamic section, if it has one. 10706+.IP "\fB\-f\fR" 4 10707+.IX Item "-f" 10708+.PD 0 10709+.IP "\fB\-\-special-files\fR" 4 10710+.IX Item "--special-files" 10711+.PD 10712+Allows processing of non-plain files. 10713 .IP "\fB\-V\fR" 4 10714 .IX Item "-V" 10715 .PD 0 10716diff -rNU3 dist.orig/binutils/doc/strings.1 dist/binutils/doc/strings.1 10717--- dist.orig/binutils/doc/strings.1 2013-03-25 10:10:26.000000000 +0100 10718+++ dist/binutils/doc/strings.1 2015-10-18 13:11:13.000000000 +0200 10719@@ -208,7 +208,7 @@ 10720 characters (\s-1ASCII\s0, \s-1ISO\s0 8859, etc., default), \fBS\fR = 10721 single\-8\-bit\-byte characters, \fBb\fR = 16\-bit bigendian, \fBl\fR = 10722 16\-bit littleendian, \fBB\fR = 32\-bit bigendian, \fBL\fR = 32\-bit 10723-littleendian. Useful for finding wide character strings. (\fBl\fR 10724+littleendian. Useful for finding wide-character strings. (\fBl\fR 10725 and \fBb\fR apply to, for example, Unicode \s-1UTF\-16/UCS\-2\s0 encodings). 10726 .IP "\fB\-T\fR \fIbfdname\fR" 4 10727 .IX Item "-T bfdname" 10728diff -rNU3 dist.orig/binutils/objcopy.c dist/binutils/objcopy.c 10729--- dist.orig/binutils/objcopy.c 2013-03-25 09:06:21.000000000 +0100 10730+++ dist/binutils/objcopy.c 2015-10-18 13:11:13.000000000 +0200 10731@@ -30,6 +30,8 @@ 10732 #include "filenames.h" 10733 #include "fnmatch.h" 10734 #include "elf-bfd.h" 10735+#include <sys/stat.h> 10736+#include <ctype.h> 10737 #include "libbfd.h" 10738 #include "coff/internal.h" 10739 #include "libcoff.h" 10740diff -rNU3 dist.orig/binutils/readelf.c dist/binutils/readelf.c 10741--- dist.orig/binutils/readelf.c 2013-03-25 09:06:21.000000000 +0100 10742+++ dist/binutils/readelf.c 2015-10-18 13:11:13.000000000 +0200 10743@@ -126,13 +126,14 @@ 10744 #include "elf/mep.h" 10745 #include "elf/microblaze.h" 10746 #include "elf/mips.h" 10747+#include "elf/riscv.h" 10748 #include "elf/mmix.h" 10749 #include "elf/mn10200.h" 10750 #include "elf/mn10300.h" 10751 #include "elf/moxie.h" 10752 #include "elf/mt.h" 10753 #include "elf/msp430.h" 10754-#include "elf/or32.h" 10755+#include "elf/or1k.h" 10756 #include "elf/pj.h" 10757 #include "elf/ppc.h" 10758 #include "elf/ppc64.h" 10759@@ -184,6 +185,7 @@ 10760 static Elf_Internal_Dyn * dynamic_section; 10761 static Elf_Internal_Shdr * symtab_shndx_hdr; 10762 static int show_name; 10763+static int do_special_files; 10764 static int do_dynamic; 10765 static int do_syms; 10766 static int do_dyn_syms; 10767@@ -555,8 +557,7 @@ 10768 case EM_MIPS: 10769 case EM_MIPS_RS3_LE: 10770 case EM_CYGNUS_M32R: 10771- case EM_OPENRISC: 10772- case EM_OR32: 10773+ case EM_OR1K: 10774 case EM_SCORE: 10775 case EM_XGATE: 10776 return FALSE; 10777@@ -604,6 +605,7 @@ 10778 case EM_NIOS32: 10779 case EM_PPC64: 10780 case EM_PPC: 10781+ case EM_RISCV: 10782 case EM_RL78: 10783 case EM_RX: 10784 case EM_S390: 10785@@ -1134,9 +1136,8 @@ 10786 rtype = elf_h8_reloc_type (type); 10787 break; 10788 10789- case EM_OPENRISC: 10790- case EM_OR32: 10791- rtype = elf_or32_reloc_type (type); 10792+ case EM_OR1K: 10793+ rtype = elf_or1k_reloc_type (type); 10794 break; 10795 10796 case EM_PJ: 10797@@ -1234,6 +1235,10 @@ 10798 rtype = elf_microblaze_reloc_type (type); 10799 break; 10800 10801+ case EM_RISCV: 10802+ rtype = elf_riscv_reloc_type (type); 10803+ break; 10804+ 10805 case EM_RL78: 10806 rtype = elf_rl78_reloc_type (type); 10807 break; 10808@@ -1941,8 +1946,7 @@ 10809 case EM_S390: return "IBM S/390"; 10810 case EM_SCORE: return "SUNPLUS S+Core"; 10811 case EM_XSTORMY16: return "Sanyo XStormy16 CPU core"; 10812- case EM_OPENRISC: 10813- case EM_OR32: return "OpenRISC"; 10814+ case EM_OR1K: return "OpenRISC"; 10815 case EM_ARC_A5: return "ARC International ARCompact processor"; 10816 case EM_CRX: return "National Semiconductor CRX microprocessor"; 10817 case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY"; 10818@@ -2005,6 +2009,7 @@ 10819 case EM_CR16: 10820 case EM_MICROBLAZE: 10821 case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze"; 10822+ case EM_RISCV: return "RISC-V"; 10823 case EM_RL78: return "Renesas RL78"; 10824 case EM_RX: return "Renesas RX"; 10825 case EM_METAG: return "Imagination Technologies META processor architecture"; 10826@@ -2488,6 +2493,14 @@ 10827 strcat (buf, ", fdpic"); 10828 break; 10829 10830+ case EM_RISCV: 10831+ { 10832+ unsigned int riscv_extension = EF_GET_RISCV_EXT(e_flags); 10833+ strcat (buf, ", "); 10834+ strcat (buf, riscv_elf_flag_to_name (riscv_extension)); 10835+ } 10836+ break; 10837+ 10838 case EM_SH: 10839 switch ((e_flags & EF_SH_MACH_MASK)) 10840 { 10841@@ -3198,6 +3211,7 @@ 10842 {"relocs", no_argument, 0, 'r'}, 10843 {"notes", no_argument, 0, 'n'}, 10844 {"dynamic", no_argument, 0, 'd'}, 10845+ {"special-files", no_argument, 0, 'f'}, 10846 {"arch-specific", no_argument, 0, 'A'}, 10847 {"version-info", no_argument, 0, 'V'}, 10848 {"use-dynamic", no_argument, 0, 'D'}, 10849@@ -3243,6 +3257,7 @@ 10850 -r --relocs Display the relocations (if present)\n\ 10851 -u --unwind Display the unwind info (if present)\n\ 10852 -d --dynamic Display the dynamic section (if present)\n\ 10853+ -f --special-files Process non-plain files too\n\ 10854 -V --version-info Display the version sections (if present)\n\ 10855 -A --arch-specific Display architecture specific information (if any)\n\ 10856 -c --archive-index Display the symbol/file index in an archive\n\ 10857@@ -3362,7 +3377,7 @@ 10858 usage (stderr); 10859 10860 while ((c = getopt_long 10861- (argc, argv, "ADHINR:SVWacdeghi:lnp:rstuvw::x:", options, NULL)) != EOF) 10862+ (argc, argv, "ADHINR:SVWacdefghi:lnp:rstuvw::x:", options, NULL)) != EOF) 10863 { 10864 switch (c) 10865 { 10866@@ -3412,6 +3427,9 @@ 10867 case 'u': 10868 do_unwind++; 10869 break; 10870+ case 'f': 10871+ do_special_files++; 10872+ break; 10873 case 'h': 10874 do_header++; 10875 break; 10876@@ -3801,7 +3819,7 @@ 10877 if (elf_header.e_phnum > 1) 10878 printf (_("\nProgram Headers:\n")); 10879 else 10880- printf (_("\nProgram Headers:\n")); 10881+ printf (_("\nProgram Header:\n")); 10882 10883 if (is_32bit_elf) 10884 printf 10885@@ -6974,6 +6992,11 @@ 10886 10887 remaining = 4; 10888 } 10889+ else 10890+ { 10891+ addr.section = SHN_UNDEF; 10892+ addr.offset = 0; 10893+ } 10894 10895 if ((word & 0x80000000) == 0) 10896 { 10897@@ -8842,6 +8865,20 @@ 10898 } 10899 10900 static const char * 10901+get_alpha_symbol_other (unsigned int other) 10902+{ 10903+ switch (other) 10904+ { 10905+ case STO_ALPHA_NOPV: 10906+ return "NOPV"; 10907+ case STO_ALPHA_STD_GPLOAD: 10908+ return "STD GPLOAD"; 10909+ default: 10910+ return NULL; 10911+ } 10912+} 10913+ 10914+static const char * 10915 get_mips_symbol_other (unsigned int other) 10916 { 10917 switch (other) 10918@@ -8935,6 +8972,9 @@ 10919 10920 switch (elf_header.e_machine) 10921 { 10922+ case EM_ALPHA: 10923+ result = get_alpha_symbol_other (other); 10924+ break; 10925 case EM_MIPS: 10926 result = get_mips_symbol_other (other); 10927 break; 10928@@ -9902,9 +9942,8 @@ 10929 case EM_ALTERA_NIOS2: 10930 case EM_NIOS32: 10931 return reloc_type == 1; /* R_NIOS_32. */ 10932- case EM_OPENRISC: 10933- case EM_OR32: 10934- return reloc_type == 1; /* R_OR32_32. */ 10935+ case EM_OR1K: 10936+ return reloc_type == 1; /* R_OR1K_32. */ 10937 case EM_PARISC: 10938 return (reloc_type == 1 /* R_PARISC_DIR32. */ 10939 || reloc_type == 41); /* R_PARISC_SECREL32. */ 10940@@ -9915,6 +9954,8 @@ 10941 return reloc_type == 1; /* R_PPC64_ADDR32. */ 10942 case EM_PPC: 10943 return reloc_type == 1; /* R_PPC_ADDR32. */ 10944+ case EM_RISCV: 10945+ return reloc_type == 1; /* R_RISCV_32. */ 10946 case EM_RL78: 10947 return reloc_type == 1; /* R_RL78_DIR32. */ 10948 case EM_RX: 10949@@ -10015,6 +10056,8 @@ 10950 case EM_L1OM: 10951 case EM_K1OM: 10952 return reloc_type == 2; /* R_X86_64_PC32. */ 10953+ case EM_VAX: 10954+ return reloc_type == 4; /* R_VAX_PCREL32. */ 10955 case EM_XTENSA_OLD: 10956 case EM_XTENSA: 10957 return reloc_type == 14; /* R_XTENSA_32_PCREL. */ 10958@@ -10046,6 +10089,8 @@ 10959 return reloc_type == 80; /* R_PARISC_DIR64. */ 10960 case EM_PPC64: 10961 return reloc_type == 38; /* R_PPC64_ADDR64. */ 10962+ case EM_RISCV: 10963+ return reloc_type == 2; /* R_RISCV_64. */ 10964 case EM_SPARC32PLUS: 10965 case EM_SPARCV9: 10966 case EM_SPARC: 10967@@ -10187,6 +10232,7 @@ 10968 case EM_ADAPTEVA_EPIPHANY: 10969 case EM_PPC: /* R_PPC_NONE. */ 10970 case EM_PPC64: /* R_PPC64_NONE. */ 10971+ case EM_RISCV: /* R_RISCV_NONE. */ 10972 case EM_ARM: /* R_ARM_NONE. */ 10973 case EM_IA_64: /* R_IA64_NONE. */ 10974 case EM_SH: /* R_SH_NONE. */ 10975@@ -12665,6 +12711,48 @@ 10976 return buff; 10977 } 10978 10979+static int 10980+process_netbsd_elf_note (Elf_Internal_Note * pnote) 10981+{ 10982+ unsigned int version; 10983+ 10984+ switch (pnote->type) 10985+ { 10986+ case NT_NETBSD_IDENT: 10987+ version = byte_get((unsigned char *)pnote->descdata, sizeof(version)); 10988+ if ((version / 10000) % 100) 10989+ printf (" NetBSD\t0x%08lx\tIDENT %u (%u.%u%s%c)\n", pnote->descsz, 10990+ version, version / 100000000, (version / 1000000) % 100, 10991+ (version / 10000) % 100 > 26 ? "Z" : "", 10992+ 'A' + (version / 10000) % 26); 10993+ else 10994+ printf (" NetBSD\t\t0x%08lx\tIDENT %u (%u.%u.%u)\n", pnote->descsz, 10995+ version, version / 100000000, (version / 1000000) % 100, 10996+ (version / 100) % 100); 10997+ return 1; 10998+ case NT_NETBSD_MARCH: 10999+ printf (" NetBSD\t\t0x%08lx\tMARCH <%s>\n", pnote->descsz, 11000+ pnote->descdata); 11001+ return 1; 11002+ case NT_NETBSD_PAX: 11003+ version = byte_get((unsigned char *)pnote->descdata, sizeof(version)); 11004+ printf (" NetBSD\t\t0x%08lx\tPaX <%s%s%s%s%s%s>\n", pnote->descsz, 11005+ ((version & NT_NETBSD_PAX_MPROTECT) ? "+mprotect" : ""), 11006+ ((version & NT_NETBSD_PAX_NOMPROTECT) ? "-mprotect" : ""), 11007+ ((version & NT_NETBSD_PAX_GUARD) ? "+guard" : ""), 11008+ ((version & NT_NETBSD_PAX_NOGUARD) ? "-guard" : ""), 11009+ ((version & NT_NETBSD_PAX_ASLR) ? "+ASLR" : ""), 11010+ ((version & NT_NETBSD_PAX_NOASLR) ? "-ASLR" : "")); 11011+ return 1; 11012+ default: 11013+ break; 11014+ } 11015+ 11016+ printf (" NetBSD\t0x%08lx\tUnknown note type: (0x%08lx)\n", pnote->descsz, 11017+ pnote->type); 11018+ return 1; 11019+} 11020+ 11021 static int 11022 print_gnu_note (Elf_Internal_Note *pnote) 11023 { 11024@@ -12765,6 +12853,23 @@ 11025 } 11026 break; 11027 11028+ /* On SuperH, PT_GETREGS == mach+3 and PT_GETFPREGS == mach+5. 11029+ There's also old PT___GETREGS40 == mach + 1 for old reg 11030+ structure which lacks GBR. */ 11031+ case EM_SH: 11032+ switch (e_type) 11033+ { 11034+ case NT_NETBSDCORE_FIRSTMACH + 1: 11035+ return _("PT___GETREGS40 (old reg structure)"); 11036+ case NT_NETBSDCORE_FIRSTMACH + 3: 11037+ return _("PT_GETREGS (reg structure)"); 11038+ case NT_NETBSDCORE_FIRSTMACH + 5: 11039+ return _("PT_GETFPREGS (fpreg structure)"); 11040+ default: 11041+ break; 11042+ } 11043+ break; 11044+ 11045 /* On all other arch's, PT_GETREGS == mach+1 and 11046 PT_GETFPREGS == mach+3. */ 11047 default: 11048@@ -12971,6 +13076,14 @@ 11049 /* GNU-specific object file notes. */ 11050 nt = get_gnu_elf_note_type (pnote->type); 11051 11052+ else if (const_strneq (pnote->namedata, "NetBSD")) 11053+ /* NetBSD-specific core file notes. */ 11054+ return process_netbsd_elf_note (pnote); 11055+ 11056+ else if (const_strneq (pnote->namedata, "PaX")) 11057+ /* NetBSD-specific core file notes. */ 11058+ return process_netbsd_elf_note (pnote); 11059+ 11060 else if (const_strneq (pnote->namedata, "NetBSD-CORE")) 11061 /* NetBSD-specific core file notes. */ 11062 nt = get_netbsd_elfcore_note_type (pnote->type); 11063@@ -13710,7 +13823,7 @@ 11064 return 1; 11065 } 11066 11067- if (! S_ISREG (statbuf.st_mode)) 11068+ if (!do_special_files && ! S_ISREG (statbuf.st_mode)) 11069 { 11070 error (_("'%s' is not an ordinary file\n"), file_name); 11071 return 1; 11072diff -rNU3 dist.orig/binutils/strings.c dist/binutils/strings.c 11073--- dist.orig/binutils/strings.c 2012-02-09 05:51:44.000000000 +0100 11074+++ dist/binutils/strings.c 2015-10-18 13:11:13.000000000 +0200 11075@@ -598,7 +598,7 @@ 11076 else 11077 #elif !BFD_HOST_64BIT_LONG 11078 if (start != (unsigned long) start) 11079- printf ("++%7ld ", (unsigned long) start); 11080+ printf ("++%7llu ", (unsigned long) start); 11081 else 11082 #endif 11083 printf ("%7ld ", (long) start); 11084diff -rNU3 dist.orig/config.guess dist/config.guess 11085--- dist.orig/config.guess 2011-06-06 12:36:06.000000000 +0200 11086+++ dist/config.guess 2015-10-18 13:11:13.000000000 +0200 11087@@ -160,14 +160,28 @@ 11088 case "${UNAME_MACHINE_ARCH}" in 11089 armeb) machine=armeb-unknown ;; 11090 arm*) machine=arm-unknown ;; 11091+ coldfire) machine=m5407-unknown ;; 11092+ earm*eb*) machine=armeb-unknown ;; 11093+ earm*) machine=arm-unknown ;; 11094 sh3el) machine=shl-unknown ;; 11095 sh3eb) machine=sh-unknown ;; 11096 sh5el) machine=sh5le-unknown ;; 11097 *) machine=${UNAME_MACHINE_ARCH}-unknown ;; 11098 esac 11099 # The Operating System including object format, if it has switched 11100- # to ELF recently, or will in the future. 11101+ # to ELF recently, or will in the future and ABI. 11102 case "${UNAME_MACHINE_ARCH}" in 11103+ coldfire) os=netbsdelf ;; 11104+ earm*) 11105+ eval $set_cc_for_build 11106+ if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ 11107+ | grep -q __ARM_PCS_VFP 11108+ then 11109+ os=netbsdelf-eabi 11110+ else 11111+ os=netbsdelf-eabihf 11112+ fi 11113+ ;; 11114 arm*|i386|m68k|ns32k|sh3*|sparc|vax) 11115 eval $set_cc_for_build 11116 if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ 11117diff -rNU3 dist.orig/config.sub dist/config.sub 11118--- dist.orig/config.sub 2012-04-25 17:53:25.000000000 +0200 11119+++ dist/config.sub 2015-10-18 13:11:13.000000000 +0200 11120@@ -122,9 +122,9 @@ 11121 # Here we must recognize all the valid KERNEL-OS combinations. 11122 maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` 11123 case $maybe_os in 11124- nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ 11125- linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ 11126- knetbsd*-gnu* | netbsd*-gnu* | \ 11127+ nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ 11128+ uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | \ 11129+ netbsd*-gnu* | netbsd*-eabi* | \ 11130 kopensolaris*-gnu* | \ 11131 storm-chaos* | os2-emx* | rtmk-nova*) 11132 os=-$maybe_os 11133@@ -300,7 +300,7 @@ 11134 | nios | nios2 \ 11135 | ns16k | ns32k \ 11136 | open8 \ 11137- | or32 \ 11138+ | or1k | or1knd \ 11139 | pdp10 | pdp11 | pj | pjl \ 11140 | powerpc | powerpc64 | powerpc64le | powerpcle \ 11141 | pyramid \ 11142@@ -332,12 +332,21 @@ 11143 basic_machine=$basic_machine-unknown 11144 os=-none 11145 ;; 11146- m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) 11147+ m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | m5407 \ 11148+ | v70 | w65 | z8k) 11149 ;; 11150 ms1) 11151 basic_machine=mt-unknown 11152 ;; 11153 11154+ riscv32-*) 11155+ basic_machine=riscv32-ucb 11156+ ;; 11157+ 11158+ riscv*-*) 11159+ basic_machine=riscv-ucb 11160+ ;; 11161+ 11162 strongarm | thumb | xscale) 11163 basic_machine=arm-unknown 11164 ;; 11165@@ -375,7 +384,7 @@ 11166 | avr-* | avr32-* \ 11167 | be32-* | be64-* \ 11168 | bfin-* | bs2000-* \ 11169- | c[123]* | c30-* | [cjt]90-* | c4x-* \ 11170+ | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ 11171 | clipper-* | craynv-* | cydra-* \ 11172 | d10v-* | d30v-* | dlx-* \ 11173 | elxsi-* \ 11174@@ -388,6 +397,7 @@ 11175 | le32-* | le64-* \ 11176 | lm32-* \ 11177 | m32c-* | m32r-* | m32rle-* \ 11178+ | m5200-* | m5407-* \ 11179 | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ 11180 | m88110-* | m88k-* | maxq-* | mcore-* | metag-* | microblaze-* \ 11181 | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ 11182@@ -528,15 +538,6 @@ 11183 basic_machine=powerpc-ibm 11184 os=-cnk 11185 ;; 11186- c54x-*) 11187- basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'` 11188- ;; 11189- c55x-*) 11190- basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'` 11191- ;; 11192- c6x-*) 11193- basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'` 11194- ;; 11195 c90) 11196 basic_machine=c90-cray 11197 os=-unicos 11198@@ -916,8 +917,11 @@ 11199 basic_machine=hppa1.1-oki 11200 os=-proelf 11201 ;; 11202- openrisc | openrisc-*) 11203- basic_machine=or32-unknown 11204+ or1k | or1k-*) 11205+ basic_machine=or1k-unknown 11206+ ;; 11207+ or1knd | or1knd-*) 11208+ basic_machine=or1knd-unknown 11209 ;; 11210 os400) 11211 basic_machine=powerpc-ibm 11212@@ -1543,15 +1547,6 @@ 11213 c4x-* | tic4x-*) 11214 os=-coff 11215 ;; 11216- tic54x-*) 11217- os=-coff 11218- ;; 11219- tic55x-*) 11220- os=-coff 11221- ;; 11222- tic6x-*) 11223- os=-coff 11224- ;; 11225 # This must come before the *-dec entry. 11226 pdp10-*) 11227 os=-tops20 11228@@ -1583,8 +1578,11 @@ 11229 mips*-*) 11230 os=-elf 11231 ;; 11232- or32-*) 11233- os=-coff 11234+ or1k-*) 11235+ os=-elf 11236+ ;; 11237+ or1knd-*) 11238+ os=-elf 11239 ;; 11240 *-tti) # must be before sparc entry or we get the wrong os. 11241 os=-sysv3 11242diff -rNU3 dist.orig/cpu/openrisc.cpu dist/cpu/openrisc.cpu 11243--- dist.orig/cpu/openrisc.cpu 2011-08-22 17:25:07.000000000 +0200 11244+++ dist/cpu/openrisc.cpu 1970-01-01 01:00:00.000000000 +0100 11245@@ -1,774 +0,0 @@ 11246-; OpenRISC family. -*- Scheme -*- 11247-; Copyright 2000, 2001, 2011 Free Software Foundation, Inc. 11248-; Contributed by Johan Rydberg, jrydberg@opencores.org 11249-; 11250-; This program is free software; you can redistribute it and/or modify 11251-; it under the terms of the GNU General Public License as published by 11252-; the Free Software Foundation; either version 2 of the License, or 11253-; (at your option) any later version. 11254-; 11255-; This program is distributed in the hope that it will be useful, 11256-; but WITHOUT ANY WARRANTY; without even the implied warranty of 11257-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11258-; GNU General Public License for more details. 11259-; 11260-; You should have received a copy of the GNU General Public License 11261-; along with this program; if not, write to the Free Software 11262-; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 11263- 11264-(include "simplify.inc") 11265- 11266-; OpenRISC 1000 is an architecture of a family of open source, 11267-; synthesizeable RISC microprocessor cores. It is a 32-bit load 11268-; and store RISC architecture designed with emphasis on speed, 11269-; compact instruction set and scalability. OpenRISC 1000 targets 11270-; wide range of embedded environments. 11271- 11272-(define-arch 11273- (name openrisc) 11274- (comment "OpenRISC 1000") 11275- (insn-lsb0? #t) 11276- (machs openrisc or1300) 11277- (isas or32) 11278-) 11279- 11280- 11281-; Attributes 11282- 11283-; An attribute to describe if a model has insn and/or data caches. 11284-(define-attr 11285- (for model) 11286- (type enum) 11287- (name HAS-CACHE) 11288- (comment "if this model has caches") 11289- (values DATA-CACHE INSN-CACHE) 11290-) 11291- 11292-; An attribute to describe if an insn can be in the delay slot or not. 11293-(define-attr 11294- (for insn) 11295- (type boolean) 11296- (name NOT-IN-DELAY-SLOT) 11297- (comment "insn can't go in delay slot") 11298-) 11299- 11300-; IDOC attribute for instruction documentation. 11301- 11302-(define-attr 11303- (for insn) 11304- (type enum) 11305- (name IDOC) 11306- (comment "insn kind for documentation") 11307- (attrs META) 11308- (values 11309- (MEM - () "Memory") 11310- (ALU - () "ALU") 11311- (FPU - () "FPU") 11312- (BR - () "Branch") 11313- (PRIV - () "Priviledged") 11314- (MISC - () "Miscellaneous") 11315- ) 11316-) 11317- 11318-; Enum for exception vectors. 11319-(define-enum 11320- (name e-exception) 11321- (comment "exception vectors") 11322- (attrs) 11323- (prefix E_) 11324- (values (("RESET") ("BUSERR" -) ("DPF" -) ("IPF" -) ("EXTINT" -) ("ALIGN" -) 11325- ("ILLEGAL" -) ("PEINT" -) ("DTLBMISS" -) ("ITLBMISS" -) ("RRANGE" -) 11326- ("SYSCALL" -) ("BREAK" -) ("RESERVED" -))) 11327-) 11328- 11329- 11330-; Instruction set parameters. 11331- 11332-(define-isa 11333- ; Name of the ISA. 11334- (name or32) 11335- 11336- ; Base insturction length. The insns is always 32 bits wide. 11337- (base-insn-bitsize 32) 11338- 11339- ; Address of insn in delay slot 11340- (setup-semantics (set-quiet (reg h-delay-insn) (add pc 4))) 11341-) 11342- 11343- 11344-; CPU family definitions. 11345- 11346-(define-cpu 11347- ; CPU names must be distinct from the architecture name and machine names. 11348- ; The "b" suffix stands for "base" and is the convention. 11349- ; The "f" suffix stands for "family" and is the convention. 11350- (name openriscbf) 11351- (comment "OpenRISC base family") 11352- (endian big) 11353- (word-bitsize 32) 11354-) 11355- 11356-; Generic machine 11357-(define-mach 11358- (name openrisc) 11359- (comment "Generic OpenRISC cpu") 11360- (cpu openriscbf) 11361- (bfd-name "openrisc") 11362-) 11363- 11364-; OpenRISC 1300 machine 11365-(define-mach 11366- (name or1300) 11367- (comment "OpenRISC 1300") 11368- (cpu openriscbf) 11369- (bfd-name "openrisc:1300") 11370-) 11371- 11372- 11373-; Model descriptions 11374- 11375-; Generic OpenRISC model 11376-(define-model 11377- (name openrisc-1) (comment "OpenRISC generic model") (attrs) 11378- (mach openrisc) 11379- 11380- ; Nothing special about this. 11381- (unit u-exec "Execution Unit" () 1 1 () () () ()) 11382-) 11383- 11384-; OpenRISC 1320 11385-(define-model 11386- (name or1320-1) (comment "OpenRISC 1320 model") 11387- 11388- ; This model has both instruction and data cache 11389- (attrs (HAS-CACHE INSN-CACHE,DATA-CACHE)) 11390- (mach or1300) 11391- 11392- ; Nothing special about this. 11393- (unit u-exec "Execution Unit" () 1 1 () () () ()) 11394-) 11395- 11396- 11397-; Instruction fields. 11398- 11399-; Attributes: 11400-; . PCREL-ADDR pc relative value (for reloc and disassembly purposes) 11401-; . ABS-ADDR absolute address (for reloc and disassembly purposes?) 11402-; . RESERVED bits are not used to decode insn, must be all 0 11403- 11404-; Instruction classes. 11405-(dnf f-class "insn class" () 31 2) 11406-(dnf f-sub "sub class" () 29 4) 11407- 11408-; Register fields. 11409-(dnf f-r1 "r1" () 25 5) 11410-(dnf f-r2 "r2" () 20 5) 11411-(dnf f-r3 "r3" () 15 5) 11412- 11413-; Immediates. 11414-(df f-simm16 "signed imm (16)" () 15 16 INT #f #f) 11415-(dnf f-uimm16 "unsigned imm (16)" () 15 16) 11416-(dnf f-uimm5 "unsigned imm (5)" () 4 5) 11417-(df f-hi16 "high 16" () 15 16 INT #f #f) 11418-(df f-lo16 "low 16" () 15 16 INT #f #f) 11419- 11420-; Sub fields 11421-(dnf f-op1 "op1" () 31 2) 11422-(dnf f-op2 "op2" () 29 4) 11423-(dnf f-op3 "op3" () 25 2) 11424-(dnf f-op4 "op4" () 23 3) 11425-(dnf f-op5 "op3" () 25 5) 11426-(dnf f-op6 "op4" () 7 3) 11427-(dnf f-op7 "op5" () 3 4) 11428- 11429-(dnf f-i16-1 "uimm16-1" () 10 11) 11430-(dnf f-i16-2 "uimm16-2" () 25 5) 11431- 11432-; PC relative, 26-bit (2 shifted to right) 11433-(df f-disp26 "disp26" (PCREL-ADDR) 25 26 INT 11434- ((value pc) (sra WI (sub WI value pc) (const 2))) 11435- ((value pc) (add WI (sll WI value (const 2)) pc))) 11436- 11437-; absolute, 26-bit (2 shifted to right) 11438-(df f-abs26 "abs26" (ABS-ADDR) 25 26 INT 11439- ((value pc) (sra WI pc (const 2))) 11440- ((value pc) (sll WI value (const 2)))) 11441- 11442-(define-multi-ifield 11443- (name f-i16nc) 11444- (comment "16 bit signed") 11445- (attrs SIGN-OPT) 11446- (mode HI) 11447- (subfields f-i16-1 f-i16-2) 11448- (insert (sequence () 11449- (set (ifield f-i16-2) (and (sra (ifield f-i16nc) 11450- (const 11)) 11451- (const #x1f))) 11452- (set (ifield f-i16-1) (and (ifield f-i16nc) 11453- (const #x7ff))))) 11454- (extract (sequence () 11455- (set (ifield f-i16nc) (c-raw-call SI "@arch@_sign_extend_16bit" 11456- (or (sll (ifield f-i16-2) 11457- (const 11)) 11458- (ifield f-i16-1)))))) 11459-) 11460- 11461- 11462-; Enums. 11463- 11464-; insn-class: bits 31-30 11465-(define-normal-insn-enum insn-class "FIXME" () OP1_ f-class 11466- (.map .str (.iota 4)) 11467-) 11468- 11469-(define-normal-insn-enum insn-sub "FIXME" () OP2_ f-sub 11470- (.map .str (.iota 16)) 11471-) 11472- 11473-(define-normal-insn-enum insn-op3 "FIXME" () OP3_ f-op3 11474- (.map .str (.iota 4)) 11475-) 11476- 11477-(define-normal-insn-enum insn-op4 "FIXME" () OP4_ f-op4 11478- (.map .str (.iota 8)) 11479-) 11480- 11481-(define-normal-insn-enum insn-op5 "FIXME" () OP5_ f-op5 11482- (.map .str (.iota 32)) 11483-) 11484- 11485-(define-normal-insn-enum insn-op6 "FIXME" () OP6_ f-op6 11486- (.map .str (.iota 8)) 11487-) 11488- 11489-(define-normal-insn-enum insn-op7 "FIXME" () OP7_ f-op7 11490- (.map .str (.iota 16)) 11491-) 11492- 11493- 11494- 11495-; Hardware pieces. 11496-; These entries list the elements of the raw hardware. 11497-; They're also used to provide tables and other elements of the assembly 11498-; language. 11499- 11500-(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) 11501- 11502-(define-hardware 11503- (name h-gr) (comment "general registers") (attrs PROFILE) 11504- (type register WI (32)) 11505- (indices keyword "" 11506- ((r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) 11507- (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) 11508- (r15 15) (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) 11509- (r21 21) (r22 22) (r23 23) (r24 24) (r25 25) (r26 26) 11510- (r27 27) (r28 28) (r29 29) (r30 30) (r31 31) (lr 11) 11511- (sp 1) (fp 2))) 11512-) 11513- 11514-(define-hardware 11515- (name h-sr) (comment "special registers") 11516- (type register WI (#x20000)) 11517- (get (index) (c-call SI "@arch@_h_sr_get_handler" index)) 11518- (set (index newval) (c-call VOID "@arch@_h_sr_set_handler" index newval)) 11519-) 11520- 11521-(dnh h-hi16 "high 16 bits" () (immediate (INT 16)) () () ()) 11522-(dnh h-lo16 "low 16 bits" () (immediate (INT 16)) () () ()) 11523- 11524-(dsh h-cbit "condition bit" () (register BI)) 11525-(dsh h-delay-insn "delay insn addr" () (register SI)) 11526- 11527- 11528-; Instruction operands. 11529- 11530-(dnop sr "special register" (SEM-ONLY) h-sr f-nil) 11531-(dnop cbit "condition bit" (SEM-ONLY) h-cbit f-nil) 11532-(dnop simm-16 "16 bit signed immediate" () h-sint f-simm16) 11533-(dnop uimm-16 "16 bit unsigned immediate" () h-uint f-uimm16) 11534-(dnop disp-26 "pc-rel 26 bit" () h-iaddr f-disp26) 11535-(dnop abs-26 "abs 26 bit" () h-iaddr f-abs26) 11536-(dnop uimm-5 "imm5" () h-uint f-uimm5) 11537- 11538-(dnop rD "destination register" () h-gr f-r1) 11539-(dnop rA "source register A" () h-gr f-r2) 11540-(dnop rB "source register B" () h-gr f-r3) 11541- 11542-(dnop op-f-23 "f-op23" () h-uint f-op4) 11543-(dnop op-f-3 "f-op3" () h-uint f-op5) 11544- 11545-; For hi(foo). 11546-(define-operand 11547- (name hi16) (comment "high 16 bit immediate, sign optional") 11548- (attrs SIGN-OPT) 11549- (type h-hi16) 11550- (index f-simm16) 11551- (handlers (parse "hi16")) 11552-) 11553- 11554-; For lo(foo) 11555-(define-operand 11556- (name lo16) (comment "low 16 bit immediate, sign optional") 11557- (attrs SIGN-OPT) 11558- (type h-lo16) 11559- (index f-lo16) 11560- (handlers (parse "lo16")) 11561-) 11562- 11563-(define-operand 11564- (name ui16nc) 11565- (comment "16 bit immediate, sign optional") 11566- (attrs) 11567- (type h-lo16) 11568- (index f-i16nc) 11569- (handlers (parse "lo16")) 11570-) 11571- 11572- 11573-; Instructions. 11574- 11575-; Branch releated instructions 11576- 11577-(dni l-j "jump (absolute iaddr)" 11578- ; This function may not be in delay slot 11579- (NOT-IN-DELAY-SLOT) 11580- 11581- "l.j ${abs-26}" 11582- (+ OP1_0 OP2_0 abs-26) 11583- 11584- ; We execute the delay slot before doin' the real branch 11585- (delay 1 (set pc abs-26)) 11586- () 11587-) 11588- 11589-(dni l-jal "jump and link (absolute iaddr)" 11590- ; This function may not be in delay slot 11591- (NOT-IN-DELAY-SLOT) 11592- 11593- "l.jal ${abs-26}" 11594- (+ OP1_0 OP2_1 abs-26) 11595- 11596- ; We execute the delay slot before doin' the real branch 11597- ; Set LR to (delay insn addr + 4) 11598- (sequence () 11599- (set (reg h-gr 11) (add (reg h-delay-insn) 4)) 11600- (delay 1 (set pc abs-26))) 11601- () 11602-) 11603- 11604-(dni l-jr "jump register (absolute iaddr)" 11605- ; This function may not be in delay slot 11606- (NOT-IN-DELAY-SLOT) 11607- 11608- "l.jr $rA" 11609- (+ OP1_0 OP2_5 OP3_0 OP4_0 rA uimm-16) 11610- 11611- ; We execute the delay slot before doin' the real branch 11612- (delay 1 (set pc rA)) 11613- () 11614-) 11615- 11616-(dni l-jalr "jump register and link (absolute iaddr)" 11617- ; This function may not be in delay slot 11618- (NOT-IN-DELAY-SLOT) 11619- 11620- "l.jalr $rA" 11621- (+ OP1_0 OP2_5 OP3_0 OP4_1 rA uimm-16) 11622- 11623- ; We save the value of rA in a temporary slot before setting 11624- ; the link register. This because "l.jalr r11" would cause 11625- ; a forever-and-ever loop otherwise. 11626- ; 11627- ; We execute the delay slot before doin' the real branch 11628- (sequence ((WI tmp-slot)) 11629- (set tmp-slot rA) 11630- (set (reg h-gr 11) (add (reg h-delay-insn) 4)) 11631- (delay 1 (set pc tmp-slot))) 11632- () 11633-) 11634- 11635-(dni l-bal "branch and link (pc relative iaddr)" 11636- ; This function may not be in delay slot 11637- (NOT-IN-DELAY-SLOT) 11638- 11639- "l.bal ${disp-26}" 11640- (+ OP1_0 OP2_2 disp-26) 11641- 11642- ; We execute the delay slot before doin' the real branch 11643- ; Set LR to (delay insn addr + 4) 11644- (sequence () 11645- (set (reg h-gr 11) (add (reg h-delay-insn) 4)) 11646- (delay 1 (set pc disp-26))) 11647- () 11648-) 11649- 11650-(dni l-bnf "branch if condition bit not set (pc relative iaddr)" 11651- ; This function may not be in delay slot 11652- (NOT-IN-DELAY-SLOT) 11653- 11654- "l.bnf ${disp-26}" 11655- (+ OP1_0 OP2_3 disp-26) 11656- 11657- ; We execute the delay slot before doin' the real branch 11658- (if (eq cbit 0) 11659- (sequence () 11660- (delay 1 (set pc disp-26)))) 11661- () 11662-) 11663- 11664-(dni l-bf "branch if condition bit is set (pc relative iaddr)" 11665- ; This function may not be in delay slot 11666- (NOT-IN-DELAY-SLOT) 11667- 11668- "l.bf ${disp-26}" 11669- (+ OP1_0 OP2_4 disp-26) 11670- 11671- ; We execute the delay slot before doin' the real branch 11672- (if (eq cbit 1) 11673- (sequence () 11674- (delay 1 (set pc disp-26)))) 11675- () 11676-) 11677- 11678-(dni l-brk "break (exception)" 11679- ; This function may not be in delay slot 11680- (NOT-IN-DELAY-SLOT) 11681- 11682- "l.brk ${uimm-16}" 11683- (+ OP1_0 OP2_5 OP3_3 OP4_0 rA uimm-16) 11684- 11685- ; FIXME should we do it like this ?? 11686- (c-call VOID "@cpu@_cpu_brk" uimm-16) 11687- () 11688-) 11689- 11690-(dni l-rfe "return from exception" 11691- ; This function may not be in delay slot 11692- (NOT-IN-DELAY-SLOT) 11693- 11694- "l.rfe $rA" 11695- (+ OP1_0 OP2_5 OP3_0 OP4_2 rA uimm-16) 11696- (sequence () 11697- (delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA)))) 11698- () 11699-) 11700- 11701-(dni l-sys "syscall (exception)" 11702- ; This function may not be in delay slot 11703- (NOT-IN-DELAY-SLOT) 11704- 11705- "l.sys ${uimm-16}" 11706- (+ OP1_0 OP2_5 OP3_2 OP4_0 rA uimm-16) 11707- (sequence() 11708- (delay 1 (set pc (c-call SI "@cpu@_except" pc 11709- #xc00 uimm-16)))) 11710- () 11711-) 11712- 11713- 11714-; Misc instructions 11715- 11716-(dni l-nop "nop" 11717- () 11718- "l.nop" 11719- (+ OP1_0 OP2_5 OP3_1 OP4_0 rA uimm-16) 11720- (nop) 11721- () 11722-) 11723- 11724-(dnmi l-ret "ret" () 11725- "l.ret" 11726- (emit l-jr (rA 11) (uimm-16 0)) 11727-) 11728- 11729-(dni l-movhi "movhi" 11730- (DELAY-SLOT) 11731- "l.movhi $rD,$hi16" 11732- (+ OP1_0 OP2_6 hi16 rD rA) 11733- (set rD (sll WI hi16 (const 16))) 11734- () 11735-) 11736- 11737- 11738-; System releated instructions 11739- 11740-(dni l-mfsr "mfsr" 11741- (DELAY-SLOT) 11742- "l.mfsr $rD,$rA" 11743- (+ OP1_0 OP2_7 rD rA uimm-16) 11744- (set rD (c-call SI "@cpu@_cpu_mfsr" rA)) 11745- () 11746-) 11747- 11748-(dni l-mtsr "mtsr" 11749- (DELAY-SLOT) 11750- "l.mtsr $rA,$rB" 11751- (+ OP1_1 OP2_0 rA rB rD (f-i16-1 0)) 11752- (c-call VOID "@cpu@_cpu_mtsr" rA rB) 11753- () 11754-) 11755- 11756- 11757- 11758-; Load instructions 11759- 11760-(dni l-lw "load word" 11761- (DELAY-SLOT) 11762- "l.lw $rD,${simm-16}($rA)" 11763- (+ OP1_2 OP2_0 rD rA simm-16) 11764- (set rD (mem SI (add rA simm-16))) 11765- () 11766-) 11767- 11768-(dni l-lbz "load byte (zero extend)" 11769- (DELAY-SLOT) 11770- "l.lbz $rD,${simm-16}($rA)" 11771- (+ OP1_2 OP2_1 rD rA simm-16) 11772- (set rD (zext SI (mem QI (add rA simm-16)))) 11773- () 11774-) 11775- 11776-(dni l-lbs "load byte (sign extend)" 11777- (DELAY-SLOT) 11778- "l.lbs $rD,${simm-16}($rA)" 11779- (+ OP1_2 OP2_2 rD rA simm-16) 11780- (set rD (ext SI (mem QI (add rA simm-16)))) 11781- () 11782-) 11783- 11784-(dni l-lhz "load halfword (zero extend)" 11785- (DELAY-SLOT) 11786- "l.lhz $rD,${simm-16}($rA)" 11787- (+ OP1_2 OP2_3 rD simm-16 rA) 11788- (set rD (zext SI (mem HI (add rA simm-16)))) 11789- () 11790-) 11791- 11792-(dni l-lhs "load halfword (sign extend)" 11793- (DELAY-SLOT) 11794- "l.lhs $rD,${simm-16}($rA)" 11795- (+ OP1_2 OP2_4 rD rA simm-16) 11796- (set rD (ext SI (mem HI (add rA simm-16)))) 11797- () 11798-) 11799- 11800- 11801-; Store instructions 11802-; 11803-; We have to use a multi field since the integer is splited over 2 fields 11804- 11805-(define-pmacro (store-insn mnemonic op2-op mode-op) 11806- (begin 11807- (dni (.sym l- mnemonic) 11808- (.str "l." mnemonic " imm(reg)/reg") 11809- (DELAY-SLOT) 11810- (.str "l." mnemonic " ${ui16nc}($rA),$rB") 11811- (+ OP1_3 op2-op rB rD ui16nc) 11812- (set (mem mode-op (add rA ui16nc)) rB) 11813- () 11814- ) 11815- ) 11816-) 11817- 11818-(store-insn sw OP2_5 SI) 11819-(store-insn sb OP2_6 QI) 11820-(store-insn sh OP2_7 HI) 11821- 11822- 11823- 11824-; Shift and rotate instructions 11825- 11826-; Reserved fields. 11827-(dnf f-f-15-8 "nop" (RESERVED) 15 8) 11828-(dnf f-f-10-3 "nop" (RESERVED) 10 3) 11829-(dnf f-f-4-1 "nop" (RESERVED) 4 1) 11830-(dnf f-f-7-3 "nop" (RESERVED) 7 3) 11831- 11832-(define-pmacro (shift-insn mnemonic op4-op) 11833- (begin 11834- (dni (.sym l- mnemonic) 11835- (.str "l." mnemonic " reg/reg/reg") 11836- () 11837- (.str "l." mnemonic " $rD,$rA,$rB") 11838- (+ OP1_3 OP2_8 rD rA rB (f-f-10-3 0) op4-op (f-f-4-1 0) OP7_8) 11839- (set rD (mnemonic rA rB)) 11840- () 11841- ) 11842- (dni (.sym l- mnemonic "i") 11843- (.str "l." mnemonic " reg/reg/imm") 11844- () 11845- (.str "l." mnemonic "i $rD,$rA,${uimm-5}") 11846- (+ OP1_2 OP2_13 rD rA (f-f-15-8 0) op4-op uimm-5) 11847- (set rD (mnemonic rA uimm-5)) 11848- () 11849- ) 11850- ) 11851-) 11852- 11853-(shift-insn sll OP6_0) 11854-(shift-insn srl OP6_1) 11855-(shift-insn sra OP6_2) 11856-(shift-insn ror OP6_4) 11857- 11858- 11859-; Arethmetic insns 11860- 11861-; Reserved fields. 11862-(dnf f-f-10-7 "nop" (RESERVED) 10 7) 11863- 11864-(define-pmacro (ar-insn-u mnemonic op2-op op5-op) 11865- (begin 11866- (dni (.sym l- mnemonic) 11867- (.str "l." mnemonic " reg/reg/reg") 11868- () 11869- (.str "l." mnemonic " $rD,$rA,$rB") 11870- (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) 11871- (set rD (mnemonic rA rB)) 11872- () 11873- ) 11874- (dni (.sym l- mnemonic "i") 11875- (.str "l." mnemonic " reg/reg/lo16") 11876- () 11877- (.str "l." mnemonic "i $rD,$rA,$lo16") 11878- (+ OP1_2 op2-op rD rA lo16) 11879- (set rD (mnemonic rA (and lo16 #xffff))) 11880- () 11881- ) 11882- ) 11883-) 11884- 11885-(define-pmacro (ar-insn-s mnemonic op2-op op5-op) 11886- (begin 11887- (dni (.sym l- mnemonic) 11888- (.str "l." mnemonic " reg/reg/reg") 11889- () 11890- (.str "l." mnemonic " $rD,$rA,$rB") 11891- (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) 11892- (set rD (mnemonic rA rB)) 11893- () 11894- ) 11895- (dni (.sym l- mnemonic "i") 11896- (.str "l." mnemonic " reg/reg/lo16") 11897- () 11898- (.str "l." mnemonic "i $rD,$rA,$lo16") 11899- (+ OP1_2 op2-op rD rA lo16) 11900- (set rD (mnemonic rA lo16)) 11901- () 11902- ) 11903- ) 11904-) 11905- 11906-(ar-insn-s add OP2_5 OP7_0) 11907-;;(ar-op-s addc OP2_5 OP7_0) 11908-(ar-insn-s sub OP2_7 OP7_2) 11909-(ar-insn-u and OP2_8 OP7_3) 11910-(ar-insn-u or OP2_9 OP7_4) 11911-(ar-insn-u xor OP2_10 OP7_5) 11912-(ar-insn-u mul OP2_11 OP7_6) 11913-;;(ar-op-u mac OP2_12 OP7_7) 11914- 11915- 11916-(dni l-div "divide (signed)" 11917- (DELAY-SLOT) 11918- "l.div $rD,$rA,$rB" 11919- (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_9) 11920- (if VOID (eq rB (const 0)) 11921- (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) 11922- (set rD (div rA rB))) 11923- () 11924-) 11925- 11926-(dni l-divu "divide (unsigned)" 11927- (DELAY-SLOT) 11928- "l.divu $rD,$rA,$rB" 11929- (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_10) 11930- (if VOID (eq rB (const 0)) 11931- (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) 11932- (set rD (udiv rA rB))) 11933- () 11934-) 11935- 11936- 11937-; Compare instructions 11938- 11939-; Reserved fields. 11940-(dnf f-f-10-11 "nop" (RESERVED) 10 11) 11941- 11942-; Register compare (both signed and unsigned) 11943-(define-pmacro (sf-insn-r op1-op op2-op op3-op op3-op-2 sem-op) 11944- (begin 11945- (dni (.sym l- "sf" (.sym sem-op "s")) 11946- (.str "l." mnemonic " reg/reg") 11947- (DELAY-SLOT) 11948- (.str "l.sf" (.str sem-op) "s $rA,$rB") 11949- (+ op1-op op2-op op3-op-2 rA rB (f-f-10-11 0)) 11950- (set cbit (sem-op rA rB)) 11951- () 11952- ) 11953- (dni (.sym l- "sf" (.sym sem-op "u")) 11954- (.str "l." mnemonic " reg/reg") 11955- (DELAY-SLOT) 11956- (.str "l.sf" (.str sem-op) "u $rA,$rB") 11957- (+ op1-op op2-op op3-op rA rB (f-f-10-11 0)) 11958- (set cbit (sem-op rA rB)) 11959- () 11960- ) 11961- ) 11962-) 11963- 11964-; Immediate compare (both signed and unsigned) 11965-(define-pmacro (sf-insn-i op1-op op2-op op3-op op3-op-2 sem-op) 11966- (begin 11967- (dni (.sym l- "sf" (.sym sem-op "si")) 11968- (.str "l." mnemonic "si reg/imm") 11969- (DELAY-SLOT) 11970- (.str "l.sf" (.str sem-op) "si $rA,${simm-16}") 11971- (+ op1-op op2-op op3-op-2 rA simm-16) 11972- (set cbit (sem-op rA simm-16)) 11973- () 11974- ) 11975- (dni (.sym l- "sf" (.sym sem-op "ui")) 11976- (.str "l." mnemonic "ui reg/imm") 11977- (DELAY-SLOT) 11978- (.str "l.sf" (.str sem-op) "ui $rA,${uimm-16}") 11979- (+ op1-op op2-op op3-op rA uimm-16) 11980- (set cbit (sem-op rA uimm-16)) 11981- () 11982- ) 11983- ) 11984-) 11985- 11986-(define-pmacro (sf-insn op5-op sem-op) 11987- (begin 11988- (dni (.sym l- "sf" sem-op) 11989- (.str "l." mnemonic " reg/reg") 11990- (DELAY-SLOT) 11991- (.str "l.sf" (.str sem-op) " $rA,$rB") 11992- (+ OP1_3 OP2_9 op5-op rA rB (f-f-10-11 0)) 11993- (set cbit (sem-op rA rB)) 11994- () 11995- ) 11996- (dni (.sym l- "sf" (.sym sem-op "i")) 11997- (.str "l." mnemonic "i reg/imm") 11998- (DELAY-SLOT) 11999- (.str "l.sf" (.str sem-op) "i $rA,${simm-16}") 12000- (+ OP1_2 OP2_14 op5-op rA simm-16) 12001- (set cbit (sem-op rA simm-16)) 12002- () 12003- ) 12004- ) 12005-) 12006- 12007- 12008-(sf-insn-r OP1_3 OP2_9 OP5_2 OP5_6 gt) 12009-(sf-insn-r OP1_3 OP2_9 OP5_3 OP5_7 ge) 12010-(sf-insn-r OP1_3 OP2_9 OP5_4 OP5_8 lt) 12011-(sf-insn-r OP1_3 OP2_9 OP5_5 OP5_9 le) 12012- 12013-(sf-insn-i OP1_2 OP2_14 OP5_2 OP5_6 gt) 12014-(sf-insn-i OP1_2 OP2_14 OP5_3 OP5_7 ge) 12015-(sf-insn-i OP1_2 OP2_14 OP5_4 OP5_8 lt) 12016-(sf-insn-i OP1_2 OP2_14 OP5_5 OP5_9 le) 12017- 12018-(sf-insn OP5_0 eq) 12019-(sf-insn OP5_1 ne) 12020diff -rNU3 dist.orig/cpu/openrisc.opc dist/cpu/openrisc.opc 12021--- dist.orig/cpu/openrisc.opc 2011-08-22 17:25:07.000000000 +0200 12022+++ dist/cpu/openrisc.opc 1970-01-01 01:00:00.000000000 +0100 12023@@ -1,164 +0,0 @@ 12024-/* OpenRISC opcode support. -*- C -*- 12025- Copyright 2000, 2001, 2003, 2005, 2011 Free Software Foundation, Inc. 12026- 12027- Contributed by Red Hat Inc; 12028- 12029- This file is part of the GNU Binutils. 12030- 12031- This program is free software; you can redistribute it and/or modify 12032- it under the terms of the GNU General Public License as published by 12033- the Free Software Foundation; either version 3 of the License, or 12034- (at your option) any later version. 12035- 12036- This program is distributed in the hope that it will be useful, 12037- but WITHOUT ANY WARRANTY; without even the implied warranty of 12038- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12039- GNU General Public License for more details. 12040- 12041- You should have received a copy of the GNU General Public License 12042- along with this program; if not, write to the Free Software 12043- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 12044- MA 02110-1301, USA. */ 12045- 12046-/* This file is an addendum to or32.cpu. Heavy use of C code isn't 12047- appropriate in .cpu files, so it resides here. This especially applies 12048- to assembly/disassembly where parsing/printing can be quite involved. 12049- Such things aren't really part of the specification of the cpu, per se, 12050- so .cpu files provide the general framework and .opc files handle the 12051- nitty-gritty details as necessary. 12052- 12053- Each section is delimited with start and end markers. 12054- 12055- <arch>-opc.h additions use: "-- opc.h" 12056- <arch>-opc.c additions use: "-- opc.c" 12057- <arch>-asm.c additions use: "-- asm.c" 12058- <arch>-dis.c additions use: "-- dis.c" 12059- <arch>-ibd.h additions use: "-- ibd.h" */ 12060- 12061-/* -- opc.h */ 12062-#undef CGEN_DIS_HASH_SIZE 12063-#define CGEN_DIS_HASH_SIZE 64 12064-#undef CGEN_DIS_HASH 12065-#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) 12066- 12067-extern long openrisc_sign_extend_16bit (long); 12068-/* -- */ 12069- 12070-/* -- opc.c */ 12071-/* -- */ 12072- 12073-/* -- asm.c */ 12074- 12075-static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); 12076- 12077-#define CGEN_VERBOSE_ASSEMBLER_ERRORS 12078- 12079-long 12080-openrisc_sign_extend_16bit (long value) 12081-{ 12082- return ((value & 0xffff) ^ 0x8000) - 0x8000; 12083-} 12084- 12085-/* Handle hi(). */ 12086- 12087-static const char * 12088-parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) 12089-{ 12090- const char *errmsg; 12091- enum cgen_parse_operand_result result_type; 12092- unsigned long ret; 12093- 12094- if (**strp == '#') 12095- ++*strp; 12096- 12097- if (strncasecmp (*strp, "hi(", 3) == 0) 12098- { 12099- bfd_vma value; 12100- 12101- *strp += 3; 12102- errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, 12103- & result_type, & value); 12104- if (**strp != ')') 12105- return MISSING_CLOSING_PARENTHESIS; 12106- 12107- ++*strp; 12108- if (errmsg == NULL 12109- && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12110- value >>= 16; 12111- ret = value; 12112- } 12113- else 12114- { 12115- if (**strp == '-') 12116- { 12117- long value; 12118- 12119- errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); 12120- ret = value; 12121- } 12122- else 12123- { 12124- unsigned long value; 12125- 12126- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); 12127- ret = value; 12128- } 12129- } 12130- 12131- *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; 12132- return errmsg; 12133-} 12134- 12135-/* Handle lo(). */ 12136- 12137-static const char * 12138-parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) 12139-{ 12140- const char *errmsg; 12141- enum cgen_parse_operand_result result_type; 12142- unsigned long ret; 12143- 12144- if (**strp == '#') 12145- ++*strp; 12146- 12147- if (strncasecmp (*strp, "lo(", 3) == 0) 12148- { 12149- bfd_vma value; 12150- 12151- *strp += 3; 12152- errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, 12153- & result_type, & value); 12154- if (**strp != ')') 12155- return MISSING_CLOSING_PARENTHESIS; 12156- 12157- ++*strp; 12158- ret = value; 12159- } 12160- else 12161- { 12162- if (**strp == '-') 12163- { 12164- long value; 12165- 12166- errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); 12167- ret = value; 12168- } 12169- else 12170- { 12171- unsigned long value; 12172- 12173- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); 12174- ret = value; 12175- } 12176- } 12177- 12178- *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; 12179- return errmsg; 12180-} 12181- 12182-/* -- */ 12183- 12184-/* -- ibd.h */ 12185-extern long openrisc_sign_extend_16bit (long); 12186- 12187-/* -- */ 12188diff -rNU3 dist.orig/cpu/or1k.cpu dist/cpu/or1k.cpu 12189--- dist.orig/cpu/or1k.cpu 1970-01-01 01:00:00.000000000 +0100 12190+++ dist/cpu/or1k.cpu 2015-10-18 13:11:13.000000000 +0200 12191@@ -0,0 +1,131 @@ 12192+; OpenRISC 1000 architecture. -*- Scheme -*- 12193+; Copyright 2000-2014 Free Software Foundation, Inc. 12194+; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 12195+; Modified by Julius Baxter, juliusbaxter@gmail.com 12196+; Modified by Peter Gavin, pgavin@gmail.com 12197+; 12198+; This program is free software; you can redistribute it and/or modify 12199+; it under the terms of the GNU General Public License as published by 12200+; the Free Software Foundation; either version 3 of the License, or 12201+; (at your option) any later version. 12202+; 12203+; This program is distributed in the hope that it will be useful, 12204+; but WITHOUT ANY WARRANTY; without even the implied warranty of 12205+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12206+; GNU General Public License for more details. 12207+; 12208+; You should have received a copy of the GNU General Public License 12209+; along with this program; if not, see <http://www.gnu.org/licenses/> 12210+ 12211+(include "simplify.inc") 12212+ 12213+; The OpenRISC family is a set of RISC microprocessor architectures with an 12214+; emphasis on scalability and is targetted at embedded use. 12215+; The CPU RTL development is a collaborative open source effort. 12216+; http://opencores.org/or1k 12217+; http://openrisc.net 12218+ 12219+(define-arch 12220+ (name or1k) 12221+ (comment "OpenRISC 1000") 12222+ (default-alignment aligned) 12223+ (insn-lsb0? #t) 12224+ (machs or32 or32nd or64 or64nd) 12225+ (isas openrisc) 12226+) 12227+ 12228+; Instruction set parameters. 12229+(define-isa 12230+ ; Name of the ISA. 12231+ (name openrisc) 12232+ ; Base insturction length. The insns are always 32 bits wide. 12233+ (base-insn-bitsize 32) 12234+ ) 12235+ 12236+(define-pmacro OR32-MACHS or32,or32nd) 12237+(define-pmacro OR64-MACHS or64,or64nd) 12238+(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd) 12239+(define-pmacro ORFPX-MACHS or32,or32nd,or64,or64nd) 12240+(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd) 12241+(define-pmacro ORFPX64-MACHS or64,or64nd) 12242+ 12243+(define-attr 12244+ (for model) 12245+ (type boolean) 12246+ (name NO-DELAY-SLOT) 12247+ (comment "does not have delay slots") 12248+ ) 12249+ 12250+(if (keep-mach? (or32 or32nd)) 12251+ (begin 12252+ (define-cpu 12253+ (name or1k32bf) 12254+ (comment "OpenRISC 1000 32-bit CPU family") 12255+ (insn-endian big) 12256+ (data-endian big) 12257+ (word-bitsize 32) 12258+ (file-transform "") 12259+ ) 12260+ 12261+ (define-mach 12262+ (name or32) 12263+ (comment "Generic OpenRISC 1000 32-bit CPU") 12264+ (cpu or1k32bf) 12265+ (bfd-name "or1k") 12266+ ) 12267+ 12268+ (define-mach 12269+ (name or32nd) 12270+ (comment "Generic OpenRISC 1000 32-bit CPU") 12271+ (cpu or1k32bf) 12272+ (bfd-name "or1knd") 12273+ ) 12274+ 12275+ ; OpenRISC 1200 - 32-bit or1k CPU implementation 12276+ (define-model 12277+ (name or1200) (comment "OpenRISC 1200 model") 12278+ (attrs) 12279+ (mach or32) 12280+ (unit u-exec "Execution Unit" () 1 1 () () () ()) 12281+ ) 12282+ 12283+ ; OpenRISC 1200 - 32-bit or1k CPU implementation 12284+ (define-model 12285+ (name or1200nd) (comment "OpenRISC 1200 model") 12286+ (attrs NO-DELAY-SLOT) 12287+ (mach or32nd) 12288+ (unit u-exec "Execution Unit" () 1 1 () () () ()) 12289+ ) 12290+ ) 12291+ ) 12292+ 12293+(if (keep-mach? (or64 or64nd)) 12294+ (begin 12295+ (define-cpu 12296+ (name or1k64bf) 12297+ (comment "OpenRISC 1000 64-bit CPU family") 12298+ (insn-endian big) 12299+ (data-endian big) 12300+ (word-bitsize 64) 12301+ (file-transform "64") 12302+ ) 12303+ 12304+ (define-mach 12305+ (name or64) 12306+ (comment "Generic OpenRISC 1000 64-bit CPU") 12307+ (cpu or1k64bf) 12308+ (bfd-name "or1k64") 12309+ ) 12310+ 12311+ (define-mach 12312+ (name or64nd) 12313+ (comment "Generic OpenRISC 1000 ND 64-bit CPU") 12314+ (cpu or1k64bf) 12315+ (bfd-name "or1k64nd") 12316+ ) 12317+ ) 12318+ ) 12319+ 12320+(include "or1kcommon.cpu") 12321+(include "or1korbis.cpu") 12322+(include "or1korfpx.cpu") 12323diff -rNU3 dist.orig/cpu/or1k.opc dist/cpu/or1k.opc 12324--- dist.orig/cpu/or1k.opc 1970-01-01 01:00:00.000000000 +0100 12325+++ dist/cpu/or1k.opc 2015-10-18 13:11:13.000000000 +0200 12326@@ -0,0 +1,421 @@ 12327+/* OpenRISC 1000 opcode support. -*- C -*- 12328+ Copyright 2000-2014 Free Software Foundation, Inc. 12329+ 12330+ Originally ontributed for OR32 by Red Hat Inc; 12331+ 12332+ This file is part of the GNU Binutils. 12333+ 12334+ This program is free software; you can redistribute it and/or modify 12335+ it under the terms of the GNU General Public License as published by 12336+ the Free Software Foundation; either version 3 of the License, or 12337+ (at your option) any later version. 12338+ 12339+ This program is distributed in the hope that it will be useful, 12340+ but WITHOUT ANY WARRANTY; without even the implied warranty of 12341+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12342+ GNU General Public License for more details. 12343+ 12344+ You should have received a copy of the GNU General Public License 12345+ along with this program; if not, see <http://www.gnu.org/licenses/>. */ 12346+ 12347+/* This file is an addendum to or1k.cpu. Heavy use of C code isn't 12348+ appropriate in .cpu files, so it resides here. This especially applies 12349+ to assembly/disassembly where parsing/printing can be quite involved. 12350+ Such things aren't really part of the specification of the cpu, per se, 12351+ so .cpu files provide the general framework and .opc files handle the 12352+ nitty-gritty details as necessary. 12353+ 12354+ Each section is delimited with start and end markers. 12355+ 12356+ <arch>-opc.h additions use: "-- opc.h" 12357+ <arch>-opc.c additions use: "-- opc.c" 12358+ <arch>-asm.c additions use: "-- asm.c" 12359+ <arch>-dis.c additions use: "-- dis.c" 12360+ <arch>-ibd.h additions use: "-- ibd.h" */ 12361+ 12362+/* -- opc.h */ 12363+ 12364+#undef CGEN_DIS_HASH_SIZE 12365+#define CGEN_DIS_HASH_SIZE 256 12366+#undef CGEN_DIS_HASH 12367+#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) 12368+ 12369+/* -- */ 12370+ 12371+/* -- opc.c */ 12372+/* -- */ 12373+ 12374+/* -- asm.c */ 12375+ 12376+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); 12377+ 12378+#define CGEN_VERBOSE_ASSEMBLER_ERRORS 12379+ 12380+static const char * 12381+parse_disp26 (CGEN_CPU_DESC cd, 12382+ const char ** strp, 12383+ int opindex, 12384+ int opinfo, 12385+ enum cgen_parse_operand_result * resultp, 12386+ bfd_vma * valuep) 12387+{ 12388+ const char *errmsg = NULL; 12389+ enum cgen_parse_operand_result result_type; 12390+ 12391+ if (strncasecmp (*strp, "plt(", 4) == 0) 12392+ { 12393+ bfd_vma value; 12394+ 12395+ *strp += 4; 12396+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_PLT26, 12397+ & result_type, & value); 12398+ if (**strp != ')') 12399+ return MISSING_CLOSING_PARENTHESIS; 12400+ ++*strp; 12401+ if (errmsg == NULL 12402+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12403+ value = (value >> 2) & 0xffff; 12404+ *valuep = value; 12405+ return errmsg; 12406+ } 12407+ return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep); 12408+} 12409+ 12410+static const char * 12411+parse_simm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) 12412+{ 12413+ const char *errmsg; 12414+ enum cgen_parse_operand_result result_type; 12415+ long ret; 12416+ 12417+ if (**strp == '#') 12418+ ++*strp; 12419+ 12420+ if (strncasecmp (*strp, "hi(", 3) == 0) 12421+ { 12422+ bfd_vma value; 12423+ 12424+ *strp += 3; 12425+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, 12426+ & result_type, & value); 12427+ if (**strp != ')') 12428+ errmsg = MISSING_CLOSING_PARENTHESIS; 12429+ ++*strp; 12430+ 12431+ ret = value; 12432+ 12433+ if (errmsg == NULL 12434+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12435+ { 12436+ ret >>= 16; 12437+ ret &= 0xffff; 12438+ ret = (ret ^ 0x8000) - 0x8000; 12439+ } 12440+ } 12441+ else if (strncasecmp (*strp, "lo(", 3) == 0) 12442+ { 12443+ bfd_vma value; 12444+ 12445+ *strp += 3; 12446+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, 12447+ & result_type, & value); 12448+ if (**strp != ')') 12449+ return MISSING_CLOSING_PARENTHESIS; 12450+ ++*strp; 12451+ 12452+ ret = value; 12453+ 12454+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12455+ { 12456+ ret &= 0xffff; 12457+ ret = (ret ^ 0x8000) - 0x8000; 12458+ } 12459+ } 12460+ else if (strncasecmp (*strp, "got(", 4) == 0) 12461+ { 12462+ bfd_vma value; 12463+ 12464+ *strp += 4; 12465+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_GOT16, 12466+ & result_type, & value); 12467+ if (**strp != ')') 12468+ return MISSING_CLOSING_PARENTHESIS; 12469+ ++*strp; 12470+ if (errmsg == NULL 12471+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12472+ value &= 0xffff; 12473+ *valuep = value; 12474+ return errmsg; 12475+ } 12476+ else if (strncasecmp (*strp, "gotpchi(", 8) == 0) 12477+ { 12478+ bfd_vma value; 12479+ 12480+ *strp += 8; 12481+ errmsg = cgen_parse_address (cd, strp, opindex, 12482+ BFD_RELOC_OR1K_GOTPC_HI16, 12483+ & result_type, & value); 12484+ if (**strp != ')') 12485+ return MISSING_CLOSING_PARENTHESIS; 12486+ ++*strp; 12487+ if (errmsg == NULL 12488+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12489+ value = (value >> 16) & 0xffff; 12490+ *valuep = value; 12491+ return errmsg; 12492+ } 12493+ else if (strncasecmp (*strp, "gotpclo(", 8) == 0) 12494+ { 12495+ bfd_vma value; 12496+ 12497+ *strp += 8; 12498+ errmsg = cgen_parse_address (cd, strp, opindex, 12499+ BFD_RELOC_OR1K_GOTPC_LO16, 12500+ &result_type, &value); 12501+ if (**strp != ')') 12502+ return MISSING_CLOSING_PARENTHESIS; 12503+ ++*strp; 12504+ if (errmsg == NULL 12505+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12506+ value &= 0xffff; 12507+ *valuep = value; 12508+ return errmsg; 12509+ } 12510+ else if (strncasecmp (*strp, "gotoffhi(", 9) == 0) 12511+ { 12512+ bfd_vma value; 12513+ 12514+ *strp += 9; 12515+ errmsg = cgen_parse_address (cd, strp, opindex, 12516+ BFD_RELOC_OR1K_GOTOFF_HI16, 12517+ & result_type, & value); 12518+ 12519+ if (**strp != ')') 12520+ return MISSING_CLOSING_PARENTHESIS; 12521+ ++*strp; 12522+ if (errmsg == NULL 12523+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12524+ value = (value >> 16) & 0xffff; 12525+ *valuep = value; 12526+ return errmsg; 12527+ } 12528+ else if (strncasecmp (*strp, "gotofflo(", 9) == 0) 12529+ { 12530+ bfd_vma value; 12531+ 12532+ *strp += 9; 12533+ errmsg = cgen_parse_address (cd, strp, opindex, 12534+ BFD_RELOC_OR1K_GOTOFF_LO16, 12535+ &result_type, &value); 12536+ if (**strp != ')') 12537+ return MISSING_CLOSING_PARENTHESIS; 12538+ ++*strp; 12539+ if (errmsg == NULL 12540+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12541+ value &= 0xffff; 12542+ *valuep = value; 12543+ return errmsg; 12544+ } 12545+ else if (strncasecmp (*strp, "tlsgdhi(", 8) == 0) 12546+ { 12547+ bfd_vma value; 12548+ 12549+ *strp += 8; 12550+ errmsg = cgen_parse_address (cd, strp, opindex, 12551+ BFD_RELOC_OR1K_TLS_GD_HI16, 12552+ & result_type, & value); 12553+ 12554+ if (**strp != ')') 12555+ return MISSING_CLOSING_PARENTHESIS; 12556+ ++*strp; 12557+ if (errmsg == NULL 12558+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12559+ value = (value >> 16) & 0xffff; 12560+ *valuep = value; 12561+ return errmsg; 12562+ } 12563+ else if (strncasecmp (*strp, "tlsgdlo(", 8) == 0) 12564+ { 12565+ bfd_vma value; 12566+ 12567+ *strp += 8; 12568+ errmsg = cgen_parse_address (cd, strp, opindex, 12569+ BFD_RELOC_OR1K_TLS_GD_LO16, 12570+ &result_type, &value); 12571+ if (**strp != ')') 12572+ return MISSING_CLOSING_PARENTHESIS; 12573+ ++*strp; 12574+ if (errmsg == NULL 12575+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12576+ value &= 0xffff; 12577+ *valuep = value; 12578+ return errmsg; 12579+ } 12580+ else if (strncasecmp (*strp, "tlsldmhi(", 9) == 0) 12581+ { 12582+ bfd_vma value; 12583+ 12584+ *strp += 9; 12585+ errmsg = cgen_parse_address (cd, strp, opindex, 12586+ BFD_RELOC_OR1K_TLS_LDM_HI16, 12587+ & result_type, & value); 12588+ 12589+ if (**strp != ')') 12590+ return MISSING_CLOSING_PARENTHESIS; 12591+ ++*strp; 12592+ if (errmsg == NULL 12593+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12594+ value = (value >> 16) & 0xffff; 12595+ *valuep = value; 12596+ return errmsg; 12597+ } 12598+ else if (strncasecmp (*strp, "tlsldmlo(", 9) == 0) 12599+ { 12600+ bfd_vma value; 12601+ 12602+ *strp += 9; 12603+ errmsg = cgen_parse_address (cd, strp, opindex, 12604+ BFD_RELOC_OR1K_TLS_LDM_LO16, 12605+ &result_type, &value); 12606+ if (**strp != ')') 12607+ return MISSING_CLOSING_PARENTHESIS; 12608+ ++*strp; 12609+ if (errmsg == NULL 12610+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12611+ value &= 0xffff; 12612+ *valuep = value; 12613+ return errmsg; 12614+ } 12615+ else if (strncasecmp (*strp, "dtpoffhi(", 9) == 0) 12616+ { 12617+ bfd_vma value; 12618+ 12619+ *strp += 9; 12620+ errmsg = cgen_parse_address (cd, strp, opindex, 12621+ BFD_RELOC_OR1K_TLS_LDO_HI16, 12622+ & result_type, & value); 12623+ 12624+ if (**strp != ')') 12625+ return MISSING_CLOSING_PARENTHESIS; 12626+ ++*strp; 12627+ if (errmsg == NULL 12628+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12629+ value = (value >> 16) & 0xffff; 12630+ *valuep = value; 12631+ return errmsg; 12632+ } 12633+ else if (strncasecmp (*strp, "dtpofflo(", 9) == 0) 12634+ { 12635+ bfd_vma value; 12636+ 12637+ *strp += 9; 12638+ errmsg = cgen_parse_address (cd, strp, opindex, 12639+ BFD_RELOC_OR1K_TLS_LDO_LO16, 12640+ &result_type, &value); 12641+ if (**strp != ')') 12642+ return MISSING_CLOSING_PARENTHESIS; 12643+ ++*strp; 12644+ if (errmsg == NULL 12645+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12646+ value &= 0xffff; 12647+ *valuep = value; 12648+ return errmsg; 12649+ } 12650+ else if (strncasecmp (*strp, "gottpoffhi(", 11) == 0) 12651+ { 12652+ bfd_vma value; 12653+ 12654+ *strp += 11; 12655+ errmsg = cgen_parse_address (cd, strp, opindex, 12656+ BFD_RELOC_OR1K_TLS_IE_HI16, 12657+ & result_type, & value); 12658+ 12659+ if (**strp != ')') 12660+ return MISSING_CLOSING_PARENTHESIS; 12661+ ++*strp; 12662+ if (errmsg == NULL 12663+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12664+ value = (value >> 16) & 0xffff; 12665+ *valuep = value; 12666+ return errmsg; 12667+ } 12668+ else if (strncasecmp (*strp, "gottpofflo(", 11) == 0) 12669+ { 12670+ bfd_vma value; 12671+ 12672+ *strp += 11; 12673+ errmsg = cgen_parse_address (cd, strp, opindex, 12674+ BFD_RELOC_OR1K_TLS_IE_LO16, 12675+ &result_type, &value); 12676+ if (**strp != ')') 12677+ return MISSING_CLOSING_PARENTHESIS; 12678+ ++*strp; 12679+ if (errmsg == NULL 12680+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12681+ value &= 0xffff; 12682+ *valuep = value; 12683+ return errmsg; 12684+ } 12685+ else if (strncasecmp (*strp, "tpoffhi(", 8) == 0) 12686+ { 12687+ bfd_vma value; 12688+ 12689+ *strp += 8; 12690+ errmsg = cgen_parse_address (cd, strp, opindex, 12691+ BFD_RELOC_OR1K_TLS_LE_HI16, 12692+ & result_type, & value); 12693+ 12694+ if (**strp != ')') 12695+ return MISSING_CLOSING_PARENTHESIS; 12696+ ++*strp; 12697+ if (errmsg == NULL 12698+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12699+ value = (value >> 16) & 0xffff; 12700+ *valuep = value; 12701+ return errmsg; 12702+ } 12703+ else if (strncasecmp (*strp, "tpofflo(", 8) == 0) 12704+ { 12705+ bfd_vma value; 12706+ 12707+ *strp += 8; 12708+ errmsg = cgen_parse_address (cd, strp, opindex, 12709+ BFD_RELOC_OR1K_TLS_LE_LO16, 12710+ &result_type, &value); 12711+ if (**strp != ')') 12712+ return MISSING_CLOSING_PARENTHESIS; 12713+ ++*strp; 12714+ if (errmsg == NULL 12715+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 12716+ value &= 0xffff; 12717+ *valuep = value; 12718+ return errmsg; 12719+ } 12720+ else 12721+ { 12722+ long value; 12723+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); 12724+ ret = value; 12725+ } 12726+ 12727+ if (errmsg == NULL) 12728+ *valuep = ret; 12729+ 12730+ return errmsg; 12731+} 12732+ 12733+static const char * 12734+parse_uimm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep) 12735+{ 12736+ const char *errmsg = parse_simm16(cd, strp, opindex, (long *) valuep); 12737+ 12738+ if (errmsg == NULL) 12739+ *valuep &= 0xffff; 12740+ return errmsg; 12741+} 12742+ 12743+/* -- */ 12744+ 12745+/* -- ibd.h */ 12746+ 12747+/* -- */ 12748diff -rNU3 dist.orig/cpu/or1kcommon.cpu dist/cpu/or1kcommon.cpu 12749--- dist.orig/cpu/or1kcommon.cpu 1970-01-01 01:00:00.000000000 +0100 12750+++ dist/cpu/or1kcommon.cpu 2015-10-18 13:11:13.000000000 +0200 12751@@ -0,0 +1,360 @@ 12752+; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*- 12753+; Copyright 2000-2014 Free Software Foundation, Inc. 12754+; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 12755+; Modified by Julius Baxter, juliusbaxter@gmail.com 12756+; 12757+; This program is free software; you can redistribute it and/or modify 12758+; it under the terms of the GNU General Public License as published by 12759+; the Free Software Foundation; either version 3 of the License, or 12760+; (at your option) any later version. 12761+; 12762+; This program is distributed in the hope that it will be useful, 12763+; but WITHOUT ANY WARRANTY; without even the implied warranty of 12764+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12765+; GNU General Public License for more details. 12766+; 12767+; You should have received a copy of the GNU General Public License 12768+; along with this program; if not, see <http://www.gnu.org/licenses/> 12769+ 12770+; Hardware pieces. 12771+; These entries list the elements of the raw hardware. 12772+; They're also used to provide tables and other elements of the assembly 12773+; language. 12774+ 12775+(define-hardware 12776+ (name h-pc) 12777+ (comment "program counter") 12778+ (attrs PC (MACH ORBIS-MACHS)) 12779+ (type pc UWI) 12780+ ) 12781+ 12782+(define-pmacro REG-INDICES 12783+ ((r0 0) 12784+ (r1 1) 12785+ (r2 2) 12786+ (r3 3) 12787+ (r4 4) 12788+ (r5 5) 12789+ (r6 6) 12790+ (r7 7) 12791+ (r8 8) 12792+ (r9 9) 12793+ (r10 10) 12794+ (r11 11) 12795+ (r12 12) 12796+ (r13 13) 12797+ (r14 14) 12798+ (r15 15) 12799+ (r16 16) 12800+ (r17 17) 12801+ (r18 18) 12802+ (r19 19) 12803+ (r20 20) 12804+ (r21 21) 12805+ (r22 22) 12806+ (r23 23) 12807+ (r24 24) 12808+ (r25 25) 12809+ (r26 26) 12810+ (r27 27) 12811+ (r28 28) 12812+ (r29 29) 12813+ (r30 30) 12814+ (r31 31) 12815+ (lr 9) 12816+ (sp 1) 12817+ (fp 2)) 12818+ ) 12819+ 12820+(define-hardware 12821+ (name h-fsr) 12822+ (comment "floating point registers (single, virtual)") 12823+ (attrs VIRTUAL (MACH ORFPX32-MACHS)) 12824+ (type register SF (32)) 12825+ (indices keyword "" REG-INDICES) 12826+ (get (index) (subword SF (trunc SI (reg h-gpr index)) 0)) 12827+ (set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0)))) 12828+ ) 12829+ 12830+(define-hardware 12831+ (name h-fdr) (comment "floating point registers (double, virtual)") 12832+ (attrs VIRTUAL (MACH ORFPX64-MACHS)) 12833+ (type register DF (32)) 12834+ (indices keyword "" REG-INDICES) 12835+ (get (index) (subword DF (trunc DI (reg h-gpr index)) 0)) 12836+ (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0)))) 12837+ ) 12838+ 12839+(define-hardware 12840+ (name h-spr) (comment "special purpose registers") 12841+ (attrs VIRTUAL (MACH ORBIS-MACHS)) 12842+ (type register UWI (#x20000)) 12843+ (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index)) 12844+ (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval)) 12845+) 12846+ 12847+(define-pmacro spr-shift 11) 12848+(define-pmacro (spr-address spr-group spr-index) 12849+ (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift) 12850+ (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index)))) 12851+ 12852+(define-hardware 12853+ (name h-gpr) (comment "general registers") 12854+ (attrs (MACH ORBIS-MACHS)) 12855+ (type register UWI (32)) 12856+ (indices keyword "" REG-INDICES) 12857+ (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0)))) 12858+ (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval)) 12859+ ) 12860+ 12861+(define-normal-enum 12862+ except-number 12863+ "Exception numbers" 12864+ () 12865+ EXCEPT- 12866+ (("NONE" #x00) 12867+ ("RESET" #x01) 12868+ ("BUSERR" #x02) 12869+ ("DPF" #x03) 12870+ ("IPF" #x04) 12871+ ("TICK" #x05) 12872+ ("ALIGN" #x06) 12873+ ("ILLEGAL" #x07) 12874+ ("INT" #x08) 12875+ ("DTLBMISS" #x09) 12876+ ("ITLBMISS" #x0a) 12877+ ("RANGE" #x0b) 12878+ ("SYSCALL" #x0c) 12879+ ("FPE" #x0d) 12880+ ("TRAP" #x0e) 12881+ ) 12882+ ) 12883+ 12884+(define-pmacro (raise-exception exnum) 12885+ (c-call VOID "@cpu@_exception" pc exnum)) 12886+ 12887+(define-normal-enum 12888+ spr-groups 12889+ "special purpose register groups" 12890+ () 12891+ SPR-GROUP- 12892+ (("SYS" #x0) 12893+ ("DMMU" #x1) 12894+ ("IMMU" #x2) 12895+ ("DCACHE" #x3) 12896+ ("ICACHE" #x4) 12897+ ("MAC" #x5) 12898+ ("DEBUG" #x6) 12899+ ("PERF" #x7) 12900+ ("POWER" #x8) 12901+ ("PIC" #x9) 12902+ ("TICK" #xa) 12903+ ("FPU" #xb) 12904+ ) 12905+ ) 12906+ 12907+(define-pmacro (spr-reg-info) 12908+ (.splice 12909+ (SYS VR #x000 "version register") 12910+ (SYS UPR #x001 "unit present register") 12911+ (SYS CPUCFGR #x002 "cpu configuration register") 12912+ (SYS DMMUCFGR #x003 "Data MMU configuration register") 12913+ (SYS IMMUCFGR #x004 "Insn MMU configuration register") 12914+ (SYS DCCFGR #x005 "Data cache configuration register") 12915+ (SYS ICCFGR #x006 "Insn cache configuration register") 12916+ (SYS DCFGR #x007 "Debug configuration register") 12917+ (SYS PCCFGR #x008 "Performance counters configuration register") 12918+ (SYS NPC #x010 "Next program counter") 12919+ (SYS SR #x011 "Supervision Regsiter") 12920+ (SYS PPC #x012 "Previous program counter") 12921+ (SYS FPCSR #x014 "Floating point control status register") 12922+ (.unsplice 12923+ (.map (.pmacro (n) (.splice SYS (.sym "EPCR" n) (.add n #x20) (.str "Exception PC register " n))) 12924+ (.iota #x10))) 12925+ (.unsplice 12926+ (.map (.pmacro (n) (.splice SYS (.sym "EEAR" n) (.add n #x30) (.str "Exception effective address register " n))) 12927+ (.iota #x10))) 12928+ (.unsplice 12929+ (.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n))) 12930+ (.iota #x10))) 12931+ (.unsplice 12932+ (.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n))) 12933+ (.iota #x200))) 12934+ 12935+ (MAC MACLO #x001 "Multiply and accumulate result (low)") 12936+ (MAC MACHI #x002 "Multiply and accumulate result (high)") 12937+ (TICK TTMR #x000 "Tick timer mode register") 12938+ ) 12939+ ) 12940+ 12941+(define-normal-enum 12942+ spr-reg-indices 12943+ "special purpose register indicies" 12944+ () 12945+ SPR-INDEX- 12946+ (.map (.pmacro (args) 12947+ (.apply (.pmacro (group index n comment) 12948+ ((.sym group "-" index) n)) 12949+ args) 12950+ ) 12951+ (spr-reg-info) 12952+ ) 12953+ ) 12954+ 12955+(define-pmacro (define-h-spr-reg spr-group spr-index n spr-comment) 12956+ (define-hardware 12957+ (name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index))) 12958+ (comment spr-comment) 12959+ (attrs VIRTUAL (MACH ORBIS-MACHS)) 12960+ (type register UWI) 12961+ (get () (reg UWI h-spr (spr-address spr-group spr-index))) 12962+ (set (newval) (set (reg UWI h-spr (spr-address spr-group spr-index)) newval)) 12963+ ) 12964+ ) 12965+(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-reg args)) (spr-reg-info)))) 12966+ 12967+(define-pmacro (spr-field-info) 12968+ ((SYS VR REV 5 0 "revision field") 12969+ (SYS VR CFG 23 16 "configuration template field") 12970+ (SYS VR VER 31 24 "version field") 12971+ (SYS UPR UP 0 0 "UPR present bit") 12972+ (SYS UPR DCP 1 1 "data cache present bit") 12973+ (SYS UPR ICP 2 2 "insn cache present bit") 12974+ (SYS UPR DMP 3 3 "data MMU present bit") 12975+ (SYS UPR MP 4 4 "MAC unit present bit") 12976+ (SYS UPR IMP 5 5 "insn MMU present bit") 12977+ (SYS UPR DUP 6 6 "debug unit present bit") 12978+ (SYS UPR PCUP 7 7 "performance counters unit present bit") 12979+ (SYS UPR PICP 8 8 "programmable interrupt controller present bit") 12980+ (SYS UPR PMP 9 9 "power management present bit") 12981+ (SYS UPR TTP 10 10 "tick timer present bit") 12982+ (SYS UPR CUP 31 24 "custom units present field") 12983+ (SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field") 12984+ (SYS CPUCFGR CGF 4 4 "custom GPR file bit") 12985+ (SYS CPUCFGR OB32S 5 5 "ORBIS32 supported bit") 12986+ (SYS CPUCFGR OB64S 6 6 "ORBIS64 supported bit") 12987+ (SYS CPUCFGR OF32S 7 7 "ORFPX32 supported bit") 12988+ (SYS CPUCFGR OF64S 8 8 "ORFPX64 supported bit") 12989+ (SYS CPUCFGR OV64S 9 9 "ORVDX64 supported bit") 12990+ (SYS CPUCFGR ND 10 10 "no transfer delay bit") 12991+ (SYS SR SM 0 0 "supervisor mode bit") 12992+ (SYS SR TEE 1 1 "tick timer exception enabled bit") 12993+ (SYS SR IEE 2 2 "interrupt exception enabled bit") 12994+ (SYS SR DCE 3 3 "data cache enabled bit") 12995+ (SYS SR ICE 4 4 "insn cache enabled bit") 12996+ (SYS SR DME 5 5 "data MMU enabled bit") 12997+ (SYS SR IME 6 6 "insn MMU enabled bit") 12998+ (SYS SR LEE 7 7 "little endian enabled bit") 12999+ (SYS SR CE 8 8 "CID enable bit") 13000+ (SYS SR F 9 9 "flag bit") 13001+ (SYS SR CY 10 10 "carry bit") 13002+ (SYS SR OV 11 11 "overflow bit") 13003+ (SYS SR OVE 12 12 "overflow exception enabled bit") 13004+ (SYS SR DSX 13 13 "delay slot exception bit") 13005+ (SYS SR EPH 14 14 "exception prefix high bit") 13006+ (SYS SR FO 15 15 "fixed one bit") 13007+ (SYS SR SUMRA 16 16 "SPRs user mode read access bit") 13008+ (SYS SR CID 31 28 "context ID field") 13009+ (SYS FPCSR FPEE 0 0 "floating point exceptions enabled bit") 13010+ (SYS FPCSR RM 2 1 "floating point rounding mode field") 13011+ (SYS FPCSR OVF 3 3 "floating point overflow flag bit") 13012+ (SYS FPCSR UNF 4 4 "floating point underflow bit") 13013+ (SYS FPCSR SNF 5 5 "floating point SNAN flag bit") 13014+ (SYS FPCSR QNF 6 6 "floating point QNAN flag bit") 13015+ (SYS FPCSR ZF 7 7 "floating point zero flag bit") 13016+ (SYS FPCSR IXF 8 8 "floating point inexact flag bit") 13017+ (SYS FPCSR IVF 9 9 "floating point invalid flag bit") 13018+ (SYS FPCSR INF 10 10 "floating point infinity flag bit") 13019+ (SYS FPCSR DZF 11 11 "floating point divide by zero flag bit") 13020+ ) 13021+ ) 13022+ 13023+(define-normal-enum 13024+ spr-field-msbs 13025+ "SPR field msb positions" 13026+ () 13027+ SPR-FIELD-MSB- 13028+ (.map (.pmacro (args) 13029+ (.apply (.pmacro (group index field msb lsb comment) 13030+ ((.sym group "-" index "-" field) msb) 13031+ ) 13032+ args 13033+ ) 13034+ ) 13035+ (spr-field-info) 13036+ ) 13037+ ) 13038+ 13039+(define-normal-enum 13040+ spr-field-lsbs 13041+ "SPR field lsb positions" 13042+ () 13043+ SPR-FIELD-SIZE- 13044+ (.map (.pmacro (args) 13045+ (.apply (.pmacro (group index field msb lsb comment) 13046+ ((.sym group "-" index "-" field) lsb) 13047+ ) 13048+ args 13049+ ) 13050+ ) 13051+ (spr-field-info) 13052+ ) 13053+ ) 13054+ 13055+(define-normal-enum 13056+ spr-field-masks 13057+ "SPR field masks" 13058+ () 13059+ SPR-FIELD-MASK- 13060+ (.map (.pmacro (args) 13061+ (.apply (.pmacro (group index field msb lsb comment) 13062+ (.splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb)) 13063+ ) 13064+ args 13065+ ) 13066+ ) 13067+ (spr-field-info) 13068+ ) 13069+ ) 13070+ 13071+(define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-field-comment) 13072+ (.let ((spr-field-name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index) "-" (.downcase spr-field))) 13073+ ) 13074+ (begin 13075+ (define-hardware 13076+ (name spr-field-name) 13077+ (comment spr-field-comment) 13078+ (attrs VIRTUAL (MACH ORBIS-MACHS)) 13079+ (type register UWI) 13080+ (get () (c-call UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb)) 13081+ (set (value) (c-call VOID "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value)) 13082+ ) 13083+ ) 13084+ ) 13085+ ) 13086+(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-field args)) (spr-field-info)))) 13087+ 13088+(define-attr 13089+ (type boolean) 13090+ (for insn) 13091+ (name DELAYED-CTI) 13092+ (comment "delayed control transfer instruction") 13093+ (values #f #t) 13094+ (default #f) 13095+ ) 13096+ 13097+(define-attr 13098+ (for insn) 13099+ (type boolean) 13100+ (name NOT-IN-DELAY-SLOT) 13101+ (comment "instruction cannot be in delay slot") 13102+ (values #f #t) 13103+ (default #f) 13104+ ) 13105+ 13106+(define-attr 13107+ (for insn) 13108+ (type boolean) 13109+ (name FORCED-CTI) 13110+ (comment "instruction may forcefully transfer control (e.g., rfe)") 13111+ ) 13112diff -rNU3 dist.orig/cpu/or1korbis.cpu dist/cpu/or1korbis.cpu 13113--- dist.orig/cpu/or1korbis.cpu 1970-01-01 01:00:00.000000000 +0100 13114+++ dist/cpu/or1korbis.cpu 2015-10-18 13:11:13.000000000 +0200 13115@@ -0,0 +1,1145 @@ 13116+; OpenRISC Basic Instruction Set 32-bit (ORBIS) -*- Scheme -*- 13117+; Copyright 2000-2014 Free Software Foundation, Inc. 13118+; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 13119+; Modified by Julius Baxter, juliusbaxter@gmail.com 13120+; Modified by Peter Gavin, pgavin@gmail.com 13121+; 13122+; This program is free software; you can redistribute it and/or modify 13123+; it under the terms of the GNU General Public License as published by 13124+; the Free Software Foundation; either version 3 of the License, or 13125+; (at your option) any later version. 13126+; 13127+; This program is distributed in the hope that it will be useful, 13128+; but WITHOUT ANY WARRANTY; without even the implied warranty of 13129+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13130+; GNU General Public License for more details. 13131+; 13132+; You should have received a copy of the GNU General Public License 13133+; along with this program; if not, see <http://www.gnu.org/licenses/> 13134+ 13135+; Instruction fields. 13136+ 13137+; Hardware for immediate operands 13138+(dnh h-simm16 "16-bit signed immediate" ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ()) 13139+(dnh h-uimm16 "16-bit unsigned immediate" () (immediate (UINT 16)) () () ()) 13140+(dnh h-uimm6 "6-bit unsigned immediate" () (immediate (UINT 6)) () () ()) 13141+ 13142+; Hardware for the (internal) atomic registers 13143+(dsh h-atomic-reserve "atomic reserve flag" () (register BI)) 13144+(dsh h-atomic-address "atomic reserve address" () (register SI)) 13145+ 13146+; Instruction classes. 13147+(dnf f-opcode "insn opcode" ((MACH ORBIS-MACHS)) 31 6) 13148+ 13149+; Register fields. 13150+(dnf f-r1 "r1" ((MACH ORBIS-MACHS)) 25 5) 13151+(dnf f-r2 "r2" ((MACH ORBIS-MACHS)) 20 5) 13152+(dnf f-r3 "r3" ((MACH ORBIS-MACHS)) 15 5) 13153+ 13154+; Sub fields 13155+(dnf f-op-25-2 "op-25-2" ((MACH ORBIS-MACHS)) 25 2) ;; nop 13156+(dnf f-op-25-5 "op-25-5" ((MACH ORBIS-MACHS)) 25 5) ;; sys, trap, *sync, sf* 13157+(dnf f-op-16-1 "op-16-1" ((MACH ORBIS-MACHS)) 16 1) ;; movhi,macrc 13158+(dnf f-op-7-4 "op-7-4" ((MACH ORBIS-MACHS)) 7 4) 13159+(dnf f-op-3-4 "op-3-4" ((MACH ORBIS-MACHS)) 3 4) 13160+(dnf f-op-9-2 "op-9-2" ((MACH ORBIS-MACHS)) 9 2) ;; alu ops upper opcode 13161+(dnf f-op-9-4 "op-9-4" ((MACH ORBIS-MACHS)) 9 4) ;; 13162+(dnf f-op-7-8 "op-7-8" ((MACH ORBIS-MACHS)) 7 8) 13163+(dnf f-op-7-2 "op-7-2" ((MACH ORBIS-MACHS)) 7 2) ;; alu lower upper opc,shroti 13164+ 13165+; Reserved fields 13166+(dnf f-resv-25-26 "resv-25-26" ((MACH ORBIS-MACHS) RESERVED) 25 26) 13167+(dnf f-resv-25-10 "resv-25-10" ((MACH ORBIS-MACHS) RESERVED) 25 10) 13168+(dnf f-resv-25-5 "resv-25-5" ((MACH ORBIS-MACHS) RESERVED) 25 5) 13169+(dnf f-resv-23-8 "resv-23-8" ((MACH ORBIS-MACHS) RESERVED) 23 8) 13170+(dnf f-resv-20-21 "resv-20-21" ((MACH ORBIS-MACHS) RESERVED) 20 21) 13171+(dnf f-resv-20-5 "resv-20-5" ((MACH ORBIS-MACHS) RESERVED) 20 5) 13172+(dnf f-resv-20-4 "resv-20-4" ((MACH ORBIS-MACHS) RESERVED) 20 4) 13173+(dnf f-resv-15-8 "resv-15-8" ((MACH ORBIS-MACHS) RESERVED) 15 8) 13174+(dnf f-resv-15-6 "resv-15-6" ((MACH ORBIS-MACHS) RESERVED) 15 6) 13175+(dnf f-resv-10-11 "resv-10-11" ((MACH ORBIS-MACHS) RESERVED) 10 11) 13176+(dnf f-resv-10-7 "resv-10-7" ((MACH ORBIS-MACHS) RESERVED) 10 7) 13177+(dnf f-resv-10-3 "resv-10-3" ((MACH ORBIS-MACHS) RESERVED) 10 3) 13178+(dnf f-resv-10-1 "resv-10-1" ((MACH ORBIS-MACHS) RESERVED) 10 1) 13179+(dnf f-resv-7-4 "resv-7-4" ((MACH ORBIS-MACHS) RESERVED) 7 4) 13180+(dnf f-resv-5-2 "resv-5-2" ((MACH ORBIS-MACHS) RESERVED) 5 2) 13181+ 13182+(dnf f-imm16-25-5 "imm16-25-5" ((MACH ORBIS-MACHS)) 25 5) 13183+(dnf f-imm16-10-11 "imm16-10-11" ((MACH ORBIS-MACHS)) 10 11) 13184+ 13185+; PC relative, 26-bit (2 shifted to right) 13186+(df f-disp26 13187+ "disp26" 13188+ ((MACH ORBIS-MACHS) PCREL-ADDR) 13189+ 25 13190+ 26 13191+ INT 13192+ ((value pc) (sra SI (sub IAI value pc) (const 2))) 13193+ ((value pc) (add IAI (sll IAI value (const 2)) pc)) 13194+ ) 13195+ 13196+; Immediates. 13197+(dnf f-uimm16 "uimm16" ((MACH ORBIS-MACHS)) 15 16) 13198+(df f-simm16 "simm16" ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f) 13199+(dnf f-uimm6 "uimm6" ((MACH ORBIS-MACHS)) 5 6) ;; shroti 13200+ 13201+(define-multi-ifield 13202+ (name f-uimm16-split) 13203+ (comment "16-bit split unsigned immediate") 13204+ (attrs (MACH ORBIS-MACHS)) 13205+ (mode UINT) 13206+ (subfields f-imm16-25-5 f-imm16-10-11) 13207+ (insert (sequence () 13208+ (set (ifield f-imm16-25-5) 13209+ (and (srl (ifield f-uimm16-split) 13210+ (const 11)) 13211+ (const #x1f))) 13212+ (set (ifield f-imm16-10-11) 13213+ (and (ifield f-uimm16-split) 13214+ (const #x7ff))))) 13215+ (extract 13216+ (set (ifield f-uimm16-split) 13217+ (trunc UHI 13218+ (or (sll (ifield f-imm16-25-5) 13219+ (const 11)) 13220+ (ifield f-imm16-10-11))))) 13221+ ) 13222+ 13223+(define-multi-ifield 13224+ (name f-simm16-split) 13225+ (comment "16-bit split signed immediate") 13226+ (attrs (MACH ORBIS-MACHS) SIGN-OPT) 13227+ (mode INT) 13228+ (subfields f-imm16-25-5 f-imm16-10-11) 13229+ (insert (sequence () 13230+ (set (ifield f-imm16-25-5) 13231+ (and (sra (ifield f-simm16-split) 13232+ (const 11)) 13233+ (const #x1f))) 13234+ (set (ifield f-imm16-10-11) 13235+ (and (ifield f-simm16-split) 13236+ (const #x7ff))))) 13237+ (extract 13238+ (set (ifield f-simm16-split) 13239+ (trunc HI 13240+ (or (sll (ifield f-imm16-25-5) 13241+ (const 11)) 13242+ (ifield f-imm16-10-11))))) 13243+ ) 13244+ 13245+; Enums. 13246+ 13247+; insn-opcode: bits 31-26 13248+(define-normal-insn-enum 13249+ insn-opcode "insn main opcode enums" ((MACH ORBIS-MACHS)) OPC_ f-opcode 13250+ (("J" #x00) 13251+ ("JAL" #x01) 13252+ ("BNF" #x03) 13253+ ("BF" #x04) 13254+ ("NOP" #x05) 13255+ ("MOVHIMACRC" #x06) 13256+ ("SYSTRAPSYNCS" #x08) 13257+ ("RFE" #x09) 13258+ ("VECTOR" #x0a) 13259+ ("JR" #x11) 13260+ ("JALR" #x12) 13261+ ("MACI" #x13) 13262+ ("LWA" #x1b) 13263+ ("CUST1" #x1c) 13264+ ("CUST2" #x1d) 13265+ ("CUST3" #x1e) 13266+ ("CUST4" #x1f) 13267+ ("LD" #x20) 13268+ ("LWZ" #x21) 13269+ ("LWS" #x22) 13270+ ("LBZ" #x23) 13271+ ("LBS" #x24) 13272+ ("LHZ" #x25) 13273+ ("LHS" #x26) 13274+ ("ADDI" #x27) 13275+ ("ADDIC" #x28) 13276+ ("ANDI" #x29) 13277+ ("ORI" #x2a) 13278+ ("XORI" #x2b) 13279+ ("MULI" #x2c) 13280+ ("MFSPR" #x2d) 13281+ ("SHROTI" #x2e) 13282+ ("SFI" #x2f) 13283+ ("MTSPR" #x30) 13284+ ("MAC" #x31) 13285+ ("FLOAT" #x32) 13286+ ("SWA" #x33) 13287+ ("SD" #x34) 13288+ ("SW" #x35) 13289+ ("SB" #x36) 13290+ ("SH" #x37) 13291+ ("ALU" #x38) 13292+ ("SF" #x39) 13293+ ("CUST5" #x3c) 13294+ ("CUST6" #x3d) 13295+ ("CUST7" #x3e) 13296+ ("CUST8" #x3f) 13297+ ) 13298+) 13299+ 13300+(define-normal-insn-enum insn-opcode-systrapsyncs 13301+ "systrapsync insn opcode enums" ((MACH ORBIS-MACHS)) 13302+ OPC_SYSTRAPSYNCS_ f-op-25-5 13303+ (("SYSCALL" #x00 ) 13304+ ("TRAP" #x08 ) 13305+ ("MSYNC" #x10 ) 13306+ ("PSYNC" #x14 ) 13307+ ("CSYNC" #x18 ) 13308+ ) 13309+) 13310+ 13311+(define-normal-insn-enum insn-opcode-movehimacrc 13312+ "movhi/macrc insn opcode enums" ((MACH ORBIS-MACHS)) 13313+ OPC_MOVHIMACRC_ f-op-16-1 13314+ (("MOVHI" #x0) 13315+ ("MACRC" #x1) 13316+ ) 13317+) 13318+ 13319+(define-normal-insn-enum insn-opcode-mac 13320+ "multiply/accumulate insn opcode enums" ((MACH ORBIS-MACHS)) 13321+ OPC_MAC_ f-op-3-4 13322+ (("MAC" #x1) 13323+ ("MSB" #x2) 13324+ ) 13325+ ) 13326+ 13327+(define-normal-insn-enum insn-opcode-shorts 13328+ "shift/rotate insn opcode enums" ((MACH ORBIS-MACHS)) 13329+ OPC_SHROTS_ f-op-7-2 13330+ (("SLL" #x0 ) 13331+ ("SRL" #x1 ) 13332+ ("SRA" #x2 ) 13333+ ("ROR" #x3 ) 13334+ ) 13335+) 13336+ 13337+(define-normal-insn-enum insn-opcode-extbhs 13338+ "extend byte/half opcode enums" ((MACH ORBIS-MACHS)) 13339+ OPC_EXTBHS_ f-op-9-4 13340+ (("EXTHS" #x0) 13341+ ("EXTBS" #x1) 13342+ ("EXTHZ" #x2) 13343+ ("EXTBZ" #x3) 13344+ ) 13345+) 13346+ 13347+(define-normal-insn-enum insn-opcode-extws 13348+ "extend word opcode enums" ((MACH ORBIS-MACHS)) 13349+ OPC_EXTWS_ f-op-9-4 13350+ (("EXTWS" #x0) 13351+ ("EXTWZ" #x1) 13352+ ) 13353+) 13354+ 13355+(define-normal-insn-enum insn-opcode-alu-regreg 13356+ "alu reg/reg insn opcode enums" ((MACH ORBIS-MACHS)) 13357+ OPC_ALU_REGREG_ f-op-3-4 13358+ (("ADD" #x0) 13359+ ("ADDC" #x1) 13360+ ("SUB" #x2) 13361+ ("AND" #x3) 13362+ ("OR" #x4) 13363+ ("XOR" #x5) 13364+ ("MUL" #x6) 13365+ ("SHROT" #x8) 13366+ ("DIV" #x9) 13367+ ("DIVU" #xA) 13368+ ("MULU" #xB) 13369+ ("EXTBH" #xC) 13370+ ("EXTW" #xD) 13371+ ("CMOV" #xE) 13372+ ("FFL1" #xF) 13373+ ) 13374+) 13375+ 13376+(define-normal-insn-enum insn-opcode-setflag 13377+ "setflag insn opcode enums" ((MACH ORBIS-MACHS)) 13378+ OPC_SF_ f-op-25-5 13379+ (("EQ" #x00) 13380+ ("NE" #x01) 13381+ ("GTU" #x02) 13382+ ("GEU" #x03) 13383+ ("LTU" #x04) 13384+ ("LEU" #x05) 13385+ ("GTS" #x0A) 13386+ ("GES" #x0B) 13387+ ("LTS" #x0C) 13388+ ("LES" #x0D) 13389+ ) 13390+) 13391+ 13392+ 13393+; Instruction operands. 13394+ 13395+(dnop sys-sr "supervision register" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr f-nil) 13396+(dnop sys-esr0 "exception supervision register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-esr0 f-nil) 13397+(dnop sys-epcr0 "exception PC register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-epcr0 f-nil) 13398+ 13399+(dnop sys-sr-lee "SR little endian enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-lee f-nil) 13400+(dnop sys-sr-f "SR flag bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-f f-nil) 13401+(dnop sys-sr-cy "SR carry bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-cy f-nil) 13402+(dnop sys-sr-ov "SR overflow bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ov f-nil) 13403+(dnop sys-sr-ove "SR overflow exception enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ove f-nil) 13404+(dnop sys-cpucfgr-ob64s "CPUCFGR ORBIS64 supported bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-ob64s f-nil) 13405+(dnop sys-cpucfgr-nd "CPUCFGR no delay bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-nd f-nil) 13406+(dnop sys-fpcsr-rm "floating point round mode" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-fpcsr-rm f-nil) 13407+ 13408+(dnop mac-machi "MAC HI result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi f-nil) 13409+(dnop mac-maclo "MAC LO result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo f-nil) 13410+ 13411+(dnop atomic-reserve "atomic reserve flag" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-reserve f-nil) 13412+(dnop atomic-address "atomic address" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-address f-nil) 13413+ 13414+(dnop uimm6 "uimm6" ((MACH ORBIS-MACHS)) h-uimm6 f-uimm6) 13415+ 13416+(dnop rD "destination register" ((MACH ORBIS-MACHS)) h-gpr f-r1) 13417+(dnop rA "source register A" ((MACH ORBIS-MACHS)) h-gpr f-r2) 13418+(dnop rB "source register B" ((MACH ORBIS-MACHS)) h-gpr f-r3) 13419+ 13420+(define-operand 13421+ (name disp26) 13422+ (comment "pc-rel 26 bit") 13423+ (attrs (MACH ORBIS-MACHS)) 13424+ (type h-iaddr) 13425+ (index f-disp26) 13426+ (handlers (parse "disp26")) 13427+ ) 13428+ 13429+(define-operand 13430+ (name simm16) 13431+ (comment "16-bit signed immediate") 13432+ (attrs (MACH ORBIS-MACHS) SIGN-OPT) 13433+ (type h-simm16) 13434+ (index f-simm16) 13435+ (handlers (parse "simm16")) 13436+ ) 13437+ 13438+(define-operand 13439+ (name uimm16) 13440+ (comment "16-bit unsigned immediate") 13441+ (attrs (MACH ORBIS-MACHS)) 13442+ (type h-uimm16) 13443+ (index f-uimm16) 13444+ (handlers (parse "uimm16")) 13445+ ) 13446+ 13447+(define-operand 13448+ (name simm16-split) 13449+ (comment "split 16-bit signed immediate") 13450+ (attrs (MACH ORBIS-MACHS) SIGN-OPT) 13451+ (type h-simm16) 13452+ (index f-simm16-split) 13453+ (handlers (parse "simm16")) 13454+) 13455+ 13456+(define-operand 13457+ (name uimm16-split) 13458+ (comment "split 16-bit unsigned immediate") 13459+ (attrs (MACH ORBIS-MACHS)) 13460+ (type h-uimm16) 13461+ (index f-uimm16-split) 13462+ (handlers (parse "uimm16")) 13463+) 13464+ 13465+; Instructions. 13466+ 13467+; Branch releated instructions 13468+ 13469+(define-pmacro (cti-link-return) 13470+ (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8))) 13471+ ) 13472+(define-pmacro (cti-transfer-control condition target) 13473+ ;; this mess is necessary because we're 13474+ ;; skipping the delay slot, but it's 13475+ ;; actually the start of the next basic 13476+ ;; block 13477+ (sequence () 13478+ (if condition 13479+ (delay 1 (set IAI pc target)) 13480+ (if sys-cpucfgr-nd 13481+ (delay 1 (set IAI pc (add pc 4)))) 13482+ ) 13483+ (if sys-cpucfgr-nd 13484+ (skip 1) 13485+ ) 13486+ ) 13487+ ) 13488+ 13489+(define-pmacro 13490+ (define-cti 13491+ cti-name 13492+ cti-comment 13493+ cti-attrs 13494+ cti-syntax 13495+ cti-format 13496+ cti-semantics) 13497+ (begin 13498+ (dni 13499+ cti-name 13500+ cti-comment 13501+ (.splice (MACH ORBIS-MACHS) DELAYED-CTI NOT-IN-DELAY-SLOT (.unsplice cti-attrs)) 13502+ cti-syntax 13503+ cti-format 13504+ (cti-semantics) 13505+ () 13506+ ) 13507+ ) 13508+ ) 13509+ 13510+(define-cti 13511+ l-j 13512+ "jump (pc-relative iaddr)" 13513+ (!COND-CTI UNCOND-CTI) 13514+ "l.j ${disp26}" 13515+ (+ OPC_J disp26) 13516+ (.pmacro () 13517+ (cti-transfer-control 1 disp26) 13518+ ) 13519+ ) 13520+ 13521+(define-cti 13522+ l-jal 13523+ "jump and link (pc-relative iaddr)" 13524+ (!COND-CTI UNCOND-CTI) 13525+ "l.jal ${disp26}" 13526+ (+ OPC_JAL disp26) 13527+ (.pmacro () 13528+ (sequence () 13529+ (cti-link-return) 13530+ (cti-transfer-control 1 disp26) 13531+ ) 13532+ ) 13533+ ) 13534+ 13535+(define-cti 13536+ l-jr 13537+ "jump register (absolute iaddr)" 13538+ (!COND-CTI UNCOND-CTI) 13539+ "l.jr $rB" 13540+ (+ OPC_JR (f-resv-25-10 0) rB (f-resv-10-11 0)) 13541+ (.pmacro () 13542+ (cti-transfer-control 1 rB) 13543+ ) 13544+ ) 13545+ 13546+(define-cti 13547+ l-jalr 13548+ "jump register and link (absolute iaddr)" 13549+ (!COND-CTI UNCOND-CTI) 13550+ "l.jalr $rB" 13551+ (+ OPC_JALR (f-resv-25-10 0) rB (f-resv-10-11 0) ) 13552+ (.pmacro () 13553+ (sequence () 13554+ (cti-link-return) 13555+ (cti-transfer-control 1 rB) 13556+ ) 13557+ ) 13558+ ) 13559+ 13560+(define-cti 13561+ l-bnf 13562+ "branch if condition bit not set (pc relative iaddr)" 13563+ (COND-CTI !UNCOND-CTI) 13564+ "l.bnf ${disp26}" 13565+ (+ OPC_BNF disp26) 13566+ (.pmacro () 13567+ (cti-transfer-control (not sys-sr-f) disp26) 13568+ ) 13569+ ) 13570+ 13571+(define-cti 13572+ l-bf 13573+ "branch if condition bit set (pc relative iaddr)" 13574+ (COND-CTI !UNCOND-CTI) 13575+ "l.bf ${disp26}" 13576+ (+ OPC_BF disp26) 13577+ (.pmacro () 13578+ (cti-transfer-control sys-sr-f disp26) 13579+ ) 13580+ ) 13581+ 13582+(dni l-trap "trap (exception)" 13583+ ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) 13584+ "l.trap ${uimm16}" 13585+ (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_TRAP (f-resv-20-5 0) uimm16) 13586+ ; Do exception entry handling in C function, PC set based on SR state 13587+ (raise-exception EXCEPT-TRAP) 13588+ () 13589+) 13590+ 13591+ 13592+(dni l-sys "syscall (exception)" 13593+ ; This function may not be in delay slot 13594+ ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) 13595+ 13596+ "l.sys ${uimm16}" 13597+ (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_SYSCALL (f-resv-20-5 0) uimm16) 13598+ ; Do exception entry handling in C function, PC set based on SR state 13599+ (raise-exception EXCEPT-SYSCALL) 13600+ () 13601+) 13602+ 13603+(dni l-msync "memory sync" 13604+ ((MACH ORBIS-MACHS)) 13605+ "l.msync" 13606+ (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_MSYNC (f-resv-20-21 0)) 13607+ (nop) 13608+ () 13609+) 13610+ 13611+(dni l-psync "pipeline sync" 13612+ ((MACH ORBIS-MACHS)) 13613+ "l.psync" 13614+ (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_PSYNC (f-resv-20-21 0)) 13615+ (nop) 13616+ () 13617+) 13618+ 13619+(dni l-csync "context sync" 13620+ ((MACH ORBIS-MACHS)) 13621+ "l.csync" 13622+ (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_CSYNC (f-resv-20-21 0)) 13623+ (nop) 13624+ () 13625+) 13626+ 13627+(dni l-rfe "return from exception" 13628+ ; This function may not be in delay slot 13629+ ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT FORCED-CTI) 13630+ 13631+ "l.rfe" 13632+ (+ OPC_RFE (f-resv-25-26 0)) 13633+ (c-call VOID "@cpu@_rfe") 13634+ () 13635+) 13636+ 13637+ 13638+; Misc instructions 13639+ 13640+; l.nop with immediate must be first so it handles all l.nops in sim 13641+(dni l-nop-imm "nop uimm16" 13642+ ((MACH ORBIS-MACHS)) 13643+ "l.nop ${uimm16}" 13644+ (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) 13645+ (c-call VOID "@cpu@_nop" (zext UWI uimm16)) 13646+ () 13647+ ) 13648+ 13649+(if (application-is? SIMULATOR) 13650+ (begin) 13651+ (begin 13652+ (dni l-nop "nop" 13653+ ((MACH ORBIS-MACHS)) 13654+ "l.nop" 13655+ (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) 13656+ (nop) 13657+ () 13658+ ) 13659+ ) 13660+) 13661+ 13662+(dni l-movhi "movhi reg/uimm16" 13663+ ((MACH ORBIS-MACHS)) 13664+ "l.movhi $rD,$uimm16" 13665+ (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MOVHI uimm16) 13666+ (set UWI rD (sll UWI (zext UWI uimm16) (const 16))) 13667+ () 13668+) 13669+ 13670+(dni l-macrc "macrc reg" 13671+ ((MACH ORBIS-MACHS)) 13672+ "l.macrc $rD" 13673+ (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MACRC (f-uimm16 0)) 13674+ (sequence () 13675+ (set UWI rD mac-maclo) 13676+ (set UWI mac-maclo 0) 13677+ (set UWI mac-machi 0) 13678+ ) 13679+ () 13680+ ) 13681+ 13682+ 13683+; System releated instructions 13684+ 13685+(dni l-mfspr "mfspr" 13686+ ((MACH ORBIS-MACHS)) 13687+ "l.mfspr $rD,$rA,${uimm16}" 13688+ (+ OPC_MFSPR rD rA uimm16) 13689+ (set UWI rD (c-call UWI "@cpu@_mfspr" (or rA (zext UWI uimm16)))) 13690+ () 13691+) 13692+ 13693+(dni l-mtspr "mtspr" 13694+ ((MACH ORBIS-MACHS)) 13695+ "l.mtspr $rA,$rB,${uimm16-split}" 13696+ (+ OPC_MTSPR rA rB uimm16-split ) 13697+ (c-call VOID "@cpu@_mtspr" (or rA (zext WI uimm16-split)) rB) 13698+ () 13699+) 13700+ 13701+ 13702+; Load instructions 13703+(define-pmacro (load-store-addr base offset size) 13704+ (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size)) 13705+ 13706+(dni l-lwz "l.lwz reg/simm16(reg)" 13707+ ((MACH ORBIS-MACHS)) 13708+ "l.lwz $rD,${simm16}($rA)" 13709+ (+ OPC_LWZ rD rA simm16) 13710+ (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) 13711+ () 13712+) 13713+ 13714+ 13715+(dni l-lws "l.lws reg/simm16(reg)" 13716+ ((MACH ORBIS-MACHS)) 13717+ "l.lws $rD,${simm16}($rA)" 13718+ (+ OPC_LWS rD rA simm16) 13719+ (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4)))) 13720+ () 13721+) 13722+ 13723+(dni l-lwa "l.lwa reg/simm16(reg)" 13724+ ((MACH ORBIS-MACHS)) 13725+ "l.lwa $rD,${simm16}($rA)" 13726+ (+ OPC_LWA rD rA simm16) 13727+ (sequence () 13728+ (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) 13729+ (set atomic-reserve (const 1)) 13730+ (set atomic-address (load-store-addr rA simm16 4)) 13731+ ) 13732+ () 13733+) 13734+ 13735+(dni l-lbz "l.lbz reg/simm16(reg)" 13736+ ((MACH ORBIS-MACHS)) 13737+ "l.lbz $rD,${simm16}($rA)" 13738+ (+ OPC_LBZ rD rA simm16) 13739+ (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1)))) 13740+ () 13741+) 13742+ 13743+(dni l-lbs "l.lbs reg/simm16(reg)" 13744+ ((MACH ORBIS-MACHS)) 13745+ "l.lbs $rD,${simm16}($rA)" 13746+ (+ OPC_LBS rD rA simm16) 13747+ (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1)))) 13748+ () 13749+) 13750+ 13751+(dni l-lhz "l.lhz reg/simm16(reg)" 13752+ ((MACH ORBIS-MACHS)) 13753+ "l.lhz $rD,${simm16}($rA)" 13754+ (+ OPC_LHZ rD simm16 rA) 13755+ (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2)))) 13756+ () 13757+) 13758+ 13759+(dni l-lhs "l.lhs reg/simm16(reg)" 13760+ ((MACH ORBIS-MACHS)) 13761+ "l.lhs $rD,${simm16}($rA)" 13762+ (+ OPC_LHS rD rA simm16) 13763+ (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2)))) 13764+ () 13765+) 13766+ 13767+ 13768+; Store instructions 13769+ 13770+(define-pmacro (store-insn mnemonic opc-op mode size) 13771+ (begin 13772+ (dni (.sym l- mnemonic) 13773+ (.str "l." mnemonic " simm16(reg)/reg") 13774+ ((MACH ORBIS-MACHS)) 13775+ (.str "l." mnemonic " ${simm16-split}($rA),$rB") 13776+ (+ opc-op rA rB simm16-split) 13777+ (sequence ((SI addr)) 13778+ (set addr (load-store-addr rA simm16-split size)) 13779+ (set mode (mem mode addr) (trunc mode rB)) 13780+ (if (eq (and addr #xffffffc) atomic-address) 13781+ (set atomic-reserve (const 0)) 13782+ ) 13783+ ) 13784+ () 13785+ ) 13786+ ) 13787+) 13788+ 13789+(store-insn sw OPC_SW USI 4) 13790+(store-insn sb OPC_SB UQI 1) 13791+(store-insn sh OPC_SH UHI 2) 13792+ 13793+(dni l-swa "l.swa simm16(reg)/reg" 13794+ ((MACH ORBIS-MACHS)) 13795+ "l.swa ${simm16-split}($rA),$rB" 13796+ (+ OPC_SWA rA rB simm16) 13797+ (sequence ((SI addr) (BI flag)) 13798+ (set addr (load-store-addr rA simm16-split 4)) 13799+ (set sys-sr-f (and atomic-reserve (eq addr atomic-address))) 13800+ (if sys-sr-f 13801+ (set USI (mem USI addr) (trunc USI rB)) 13802+ ) 13803+ (set atomic-reserve (const 0)) 13804+ ) 13805+ () 13806+) 13807+ 13808+ 13809+; Shift and rotate instructions 13810+ 13811+(define-pmacro (shift-insn mnemonic) 13812+ (begin 13813+ (dni (.sym l- mnemonic) 13814+ (.str "l." mnemonic " reg/reg/reg") 13815+ ((MACH ORBIS-MACHS)) 13816+ (.str "l." mnemonic " $rD,$rA,$rB") 13817+ (+ OPC_ALU rD rA rB (f-resv-10-3 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) (f-resv-5-2 0) 13818+ OPC_ALU_REGREG_SHROT ) 13819+ (set UWI rD (mnemonic rA rB)) 13820+ () 13821+ ) 13822+ (dni (.sym l- mnemonic "i") 13823+ (.str "l." mnemonic " reg/reg/uimm6") 13824+ ((MACH ORBIS-MACHS)) 13825+ (.str "l." mnemonic "i $rD,$rA,${uimm6}") 13826+ (+ OPC_SHROTI rD rA (f-resv-15-8 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) uimm6) 13827+ (set rD (mnemonic rA uimm6)) 13828+ () 13829+ ) 13830+ ) 13831+) 13832+ 13833+(shift-insn sll) 13834+(shift-insn srl) 13835+(shift-insn sra) 13836+(shift-insn ror) 13837+ 13838+ 13839+; Arithmetic insns 13840+ 13841+; ALU op macro 13842+(define-pmacro (alu-insn mnemonic) 13843+ (begin 13844+ (dni (.sym l- mnemonic) 13845+ (.str "l." mnemonic " reg/reg/reg") 13846+ ((MACH ORBIS-MACHS)) 13847+ (.str "l." mnemonic " $rD,$rA,$rB") 13848+ (+ OPC_ALU rD rA rB (f-resv-10-7 0) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) 13849+ (set rD (mnemonic rA rB)) 13850+ () 13851+ ) 13852+ ) 13853+) 13854+ 13855+(alu-insn and) 13856+(alu-insn or) 13857+(alu-insn xor) 13858+ 13859+(define-pmacro (alu-carry-insn mnemonic) 13860+ (begin 13861+ (dni (.sym l- mnemonic) 13862+ (.str "l." mnemonic " reg/reg/reg") 13863+ ((MACH ORBIS-MACHS)) 13864+ (.str "l." mnemonic " $rD,$rA,$rB") 13865+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) 13866+ (sequence () 13867+ (sequence () 13868+ (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA rB 0)) 13869+ (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA rB 0)) 13870+ (set rD (mnemonic WI rA rB)) 13871+ ) 13872+ (if (andif sys-sr-ov sys-sr-ove) 13873+ (raise-exception EXCEPT-RANGE)) 13874+ ) 13875+ () 13876+ ) 13877+ ) 13878+ ) 13879+ 13880+(alu-carry-insn add) 13881+(alu-carry-insn sub) 13882+ 13883+(dni (l-addc) "l.addc reg/reg/reg" 13884+ ((MACH ORBIS-MACHS)) 13885+ ("l.addc $rD,$rA,$rB") 13886+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_ADDC) 13887+ (sequence () 13888+ (sequence ((BI tmp-sys-sr-cy)) 13889+ (set BI tmp-sys-sr-cy sys-sr-cy) 13890+ (set BI sys-sr-cy (addc-cflag WI rA rB tmp-sys-sr-cy)) 13891+ (set BI sys-sr-ov (addc-oflag WI rA rB tmp-sys-sr-cy)) 13892+ (set rD (addc WI rA rB tmp-sys-sr-cy)) 13893+ ) 13894+ (if (andif sys-sr-ov sys-sr-ove) 13895+ (raise-exception EXCEPT-RANGE)) 13896+ ) 13897+ () 13898+) 13899+ 13900+(dni (l-mul) "l.mul reg/reg/reg" 13901+ ((MACH ORBIS-MACHS)) 13902+ ("l.mul $rD,$rA,$rB") 13903+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MUL) 13904+ (sequence () 13905+ (sequence () 13906+ ; 2's complement overflow 13907+ (set BI sys-sr-ov (mul-o2flag WI rA rB)) 13908+ ; 1's complement overflow 13909+ (set BI sys-sr-cy (mul-o1flag WI rA rB)) 13910+ (set rD (mul WI rA rB)) 13911+ ) 13912+ (if (andif sys-sr-ov sys-sr-ove) 13913+ (raise-exception EXCEPT-RANGE)) 13914+ ) 13915+ () 13916+) 13917+ 13918+(dni (l-mulu) "l.mulu reg/reg/reg" 13919+ ((MACH ORBIS-MACHS)) 13920+ ("l.mulu $rD,$rA,$rB") 13921+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULU) 13922+ (sequence () 13923+ (sequence () 13924+ ; 2's complement overflow 13925+ (set BI sys-sr-ov 0) 13926+ ; 1's complement overflow 13927+ (set BI sys-sr-cy (mul-o1flag UWI rA rB)) 13928+ (set rD (mul UWI rA rB)) 13929+ ) 13930+ (if (andif sys-sr-ov sys-sr-ove) 13931+ (raise-exception EXCEPT-RANGE)) 13932+ ) 13933+ () 13934+) 13935+ 13936+(dni l-div "divide (signed)" 13937+ ((MACH ORBIS-MACHS)) 13938+ "l.div $rD,$rA,$rB" 13939+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIV) 13940+ (sequence () 13941+ (if (ne rB 0) 13942+ (sequence () 13943+ (set BI sys-sr-cy 0) 13944+ (set WI rD (div WI rA rB)) 13945+ ) 13946+ (set BI sys-sr-cy 1) 13947+ ) 13948+ (set BI sys-sr-ov 0) 13949+ (if (andif sys-sr-cy sys-sr-ove) 13950+ (raise-exception EXCEPT-RANGE)) 13951+ ) 13952+ () 13953+) 13954+ 13955+(dni l-divu "divide (unsigned)" 13956+ ((MACH ORBIS-MACHS)) 13957+ "l.divu $rD,$rA,$rB" 13958+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIVU) 13959+ (sequence () 13960+ (if (ne rB 0) 13961+ (sequence () 13962+ (set BI sys-sr-cy 0) 13963+ (set rD (udiv UWI rA rB)) 13964+ ) 13965+ (set BI sys-sr-cy 1) 13966+ ) 13967+ (set BI sys-sr-ov 0) 13968+ (if (andif sys-sr-cy sys-sr-ove) 13969+ (raise-exception EXCEPT-RANGE)) 13970+ ) 13971+ () 13972+) 13973+ 13974+(dni l-ff1 "find first '1'" 13975+ ((MACH ORBIS-MACHS)) 13976+ "l.ff1 $rD,$rA" 13977+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_FFL1) 13978+ (set rD (c-call UWI "@cpu@_ff1" rA)) 13979+ () 13980+) 13981+ 13982+(dni l-fl1 "find last '1'" 13983+ ((MACH ORBIS-MACHS)) 13984+ "l.fl1 $rD,$rA" 13985+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x10) OPC_ALU_REGREG_FFL1) 13986+ (set rD (c-call UWI "@cpu@_fl1" rA)) 13987+ () 13988+) 13989+ 13990+ 13991+(define-pmacro (alu-insn-simm mnemonic) 13992+ (begin 13993+ (dni (.sym l- mnemonic "i") 13994+ (.str "l." mnemonic " reg/reg/simm16") 13995+ ((MACH ORBIS-MACHS)) 13996+ (.str "l." mnemonic "i $rD,$rA,$simm16") 13997+ (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) 13998+ (set rD (mnemonic rA (ext WI simm16))) 13999+ () 14000+ ) 14001+ ) 14002+) 14003+ 14004+(define-pmacro (alu-insn-uimm mnemonic) 14005+ (begin 14006+ (dni (.sym l- mnemonic "i") 14007+ (.str "l." mnemonic " reg/reg/uimm16") 14008+ ((MACH ORBIS-MACHS)) 14009+ (.str "l." mnemonic "i $rD,$rA,$uimm16") 14010+ (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA uimm16) 14011+ (set rD (mnemonic rA (zext UWI uimm16))) 14012+ () 14013+ ) 14014+ ) 14015+) 14016+ 14017+(alu-insn-uimm and) 14018+(alu-insn-uimm or) 14019+(alu-insn-simm xor) 14020+ 14021+(define-pmacro (alu-carry-insn-simm mnemonic) 14022+ (begin 14023+ (dni (.sym l- mnemonic "i") 14024+ (.str "l." mnemonic "i reg/reg/simm16") 14025+ ((MACH ORBIS-MACHS)) 14026+ (.str "l." mnemonic "i $rD,$rA,$simm16") 14027+ (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) 14028+ (sequence () 14029+ (sequence () 14030+ (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA (ext WI simm16) 0)) 14031+ (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA (ext WI simm16) 0)) 14032+ (set rD (mnemonic WI rA (ext WI simm16))) 14033+ ) 14034+ (if (andif sys-sr-ov sys-sr-ove) 14035+ (raise-exception EXCEPT-RANGE)) 14036+ ) 14037+ () 14038+ ) 14039+ ) 14040+ ) 14041+ 14042+(alu-carry-insn-simm add) 14043+ 14044+(dni (l-addic) 14045+ ("l.addic reg/reg/simm16") 14046+ ((MACH ORBIS-MACHS)) 14047+ ("l.addic $rD,$rA,$simm16") 14048+ (+ OPC_ADDIC rD rA simm16) 14049+ (sequence () 14050+ (sequence ((BI tmp-sys-sr-cy)) 14051+ (set BI tmp-sys-sr-cy sys-sr-cy) 14052+ (set BI sys-sr-cy (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy)) 14053+ (set BI sys-sr-ov (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy)) 14054+ (set WI rD (addc WI rA (ext WI simm16) tmp-sys-sr-cy)) 14055+ ) 14056+ (if (andif sys-sr-ov sys-sr-ove) 14057+ (raise-exception EXCEPT-RANGE)) 14058+ ) 14059+ () 14060+) 14061+ 14062+(dni (l-muli) 14063+ "l.muli reg/reg/simm16" 14064+ ((MACH ORBIS-MACHS)) 14065+ ("l.muli $rD,$rA,$simm16") 14066+ (+ OPC_MULI rD rA simm16) 14067+ (sequence () 14068+ (sequence () 14069+ ; 2's complement overflow 14070+ (set sys-sr-ov (mul-o2flag WI rA (ext WI simm16))) 14071+ ; 1's complement overflow 14072+ (set sys-sr-cy (mul-o1flag UWI rA (ext UWI simm16))) 14073+ (set rD (mul WI rA (ext WI simm16))) 14074+ ) 14075+ (if (andif sys-sr-ov sys-sr-ove) 14076+ (raise-exception EXCEPT-RANGE)) 14077+ ) 14078+ () 14079+ ) 14080+ 14081+(define-pmacro (extbh-insn mnemonic extop extmode truncmode) 14082+ (begin 14083+ (dni (.sym l- mnemonic) 14084+ (.str "l." mnemonic " reg/reg") 14085+ ((MACH ORBIS-MACHS)) 14086+ (.str "l." mnemonic " $rD,$rA") 14087+ (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTBHS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTBH) 14088+ (set rD (extop extmode (trunc truncmode rA))) 14089+ () 14090+ ) 14091+ ) 14092+ ) 14093+ 14094+(extbh-insn exths ext WI HI) 14095+(extbh-insn extbs ext WI QI) 14096+(extbh-insn exthz zext UWI UHI) 14097+(extbh-insn extbz zext UWI UQI) 14098+ 14099+(define-pmacro (extw-insn mnemonic extop extmode truncmode) 14100+ (begin 14101+ (dni (.sym l- mnemonic) 14102+ (.str "l." mnemonic " reg/reg") 14103+ ((MACH ORBIS-MACHS)) 14104+ (.str "l." mnemonic " $rD,$rA") 14105+ (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTWS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTW) 14106+ (set rD (extop extmode (trunc truncmode rA))) 14107+ () 14108+ ) 14109+ ) 14110+ ) 14111+ 14112+(extw-insn extws ext WI SI) 14113+(extw-insn extwz zext USI USI) 14114+ 14115+(dni l-cmov 14116+ "l.cmov reg/reg/reg" 14117+ ((MACH ORBIS-MACHS)) 14118+ "l.cmov $rD,$rA,$rB" 14119+ (+ OPC_ALU rD rA rB (f-resv-10-1 0) (f-op-9-2 0) (f-resv-7-4 0) OPC_ALU_REGREG_CMOV) 14120+ (if sys-sr-f 14121+ (set UWI rD rA) 14122+ (set UWI rD rB) 14123+ ) 14124+ () 14125+ ) 14126+ 14127+; Compare instructions 14128+ 14129+; Ordering compare 14130+(define-pmacro (sf-insn op) 14131+ (begin 14132+ (dni (.sym l- "sf" op "s") ; l-sfgts 14133+ (.str "l.sf" op "s reg/reg") ; "l.sfgts reg/reg" 14134+ ((MACH ORBIS-MACHS)) 14135+ (.str "l.sf" op "s $rA,$rB") ; "l.sfgts $rA,$rB" 14136+ (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "S") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTS rA rB (f-resv-10-11 0)) 14137+ (set sys-sr-f (op WI rA rB)) ; (set sys-sr-f (gt WI rA rB)) 14138+ () 14139+ ) 14140+ (dni (.sym l- "sf" op "si") ; l-sfgtsi 14141+ (.str "l.sf" op "si reg/simm16") ; "l.sfgtsi reg/simm16" 14142+ ((MACH ORBIS-MACHS)) 14143+ (.str "l.sf" op "si $rA,$simm16") ; "l.sfgtsi $rA,$simm16" 14144+ (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "S") rA simm16) ; (+ OPC_SFI OPC_SF_GTS rA simm16) 14145+ (set sys-sr-f (op WI rA (ext WI simm16))) ; (set sys-sr-f (gt WI rA (ext WI simm16))) 14146+ () 14147+ ) 14148+ (dni (.sym l- "sf" op "u") ; l-sfgtu 14149+ (.str "l.sf" op "u reg/reg") ; "l.sfgtu reg/reg" 14150+ ((MACH ORBIS-MACHS)) 14151+ (.str "l.sf" op "u $rA,$rB") ; "l.sfgtu $rA,$rB" 14152+ (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "U") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTU rA rB (f-resv-10-11 0)) 14153+ (set sys-sr-f ((.sym op "u") WI rA rB)) ; (set sys-sr-f (gtu WI rA rB)) 14154+ () 14155+ ) 14156+ ; immediate is sign extended even for unsigned compare 14157+ (dni (.sym l- "sf" op "ui") ; l-sfgtui 14158+ (.str "l.sf" op "ui reg/simm16") ; "l.sfgtui reg/uimm16" 14159+ ((MACH ORBIS-MACHS)) 14160+ (.str "l.sf" op "ui $rA,$simm16") ; "l.sfgtui $rA,$simm16" 14161+ (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "U") rA simm16) ; (+ OPC_SFI OPC_SF_GTU rA simm16) 14162+ (set sys-sr-f ((.sym op "u") WI rA (ext WI simm16))) ; (set sys-sr-f (gtu WI rA (ext WI simm16))) 14163+ () 14164+ ) 14165+ ) 14166+ ) 14167+ 14168+(sf-insn gt) 14169+(sf-insn ge) 14170+(sf-insn lt) 14171+(sf-insn le) 14172+ 14173+; Equality compare 14174+(define-pmacro (sf-insn-eq op) 14175+ (begin 14176+ (dni (.sym l- "sf" op) 14177+ (.str "l." op " reg/reg") 14178+ ((MACH ORBIS-MACHS)) 14179+ (.str "l.sf" op " $rA,$rB") 14180+ (+ OPC_SF (.sym "OPC_SF_" (.upcase op)) rA rB (f-resv-10-11 0)) 14181+ (set sys-sr-f (op WI rA rB)) 14182+ () 14183+ ) 14184+ (dni (.sym l- "sf" op "i") 14185+ (.str "l.sf" op "i reg/simm16") 14186+ ((MACH ORBIS-MACHS)) 14187+ (.str "l.sf" op "i $rA,$simm16") 14188+ (+ OPC_SFI (.sym "OPC_SF_" (.upcase op)) rA simm16) 14189+ (set sys-sr-f (op WI rA (ext WI simm16))) 14190+ () 14191+ ) 14192+ ) 14193+) 14194+ 14195+(sf-insn-eq eq) 14196+(sf-insn-eq ne) 14197+ 14198+(dni l-mac 14199+ "l.mac reg/reg" 14200+ ((MACH ORBIS-MACHS)) 14201+ "l.mac $rA,$rB" 14202+ (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MAC) 14203+ (sequence ((WI prod) (DI result)) 14204+ (set WI prod (mul WI rA rB)) 14205+ (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod))) 14206+ (set SI mac-machi (subword SI result 0)) 14207+ (set SI mac-maclo (subword SI result 1)) 14208+ ) 14209+ () 14210+ ) 14211+ 14212+(dni l-msb 14213+ "l.msb reg/reg" 14214+ ((MACH ORBIS-MACHS)) 14215+ "l.msb $rA,$rB" 14216+ (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSB) 14217+ (sequence ((WI prod) (DI result)) 14218+ (set WI prod (mul WI rA rB)) 14219+ (set DI result (sub (join DI SI mac-machi mac-maclo) (ext DI prod))) 14220+ (set SI mac-machi (subword SI result 0)) 14221+ (set SI mac-maclo (subword SI result 1)) 14222+ ) 14223+ () 14224+ ) 14225+ 14226+(dni l-maci 14227+ "l.maci reg/simm16" 14228+ ((MACH ORBIS-MACHS)) 14229+ "l.maci $rA,${simm16}" 14230+ (+ OPC_MACI (f-resv-25-5 0) rA simm16) 14231+ (sequence ((WI prod) (DI result)) 14232+ (set WI prod (mul WI (ext WI simm16) rA)) 14233+ (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod))) 14234+ (set SI mac-machi (subword SI result 0)) 14235+ (set SI mac-maclo (subword SI result 1)) 14236+ ) 14237+ () 14238+ ) 14239+ 14240+(define-pmacro (cust-insn cust-num) 14241+ (begin 14242+ (dni (.sym l- "cust" cust-num) 14243+ (.str "l.cust" cust-num) 14244+ ((MACH ORBIS-MACHS)) 14245+ (.str "l.cust" cust-num) 14246+ (+ (.sym OPC_CUST cust-num) (f-resv-25-26 0)) 14247+ (nop) 14248+ () 14249+ ) 14250+ ) 14251+ ) 14252+ 14253+(cust-insn "1") 14254+(cust-insn "2") 14255+(cust-insn "3") 14256+(cust-insn "4") 14257+(cust-insn "5") 14258+(cust-insn "6") 14259+(cust-insn "7") 14260+(cust-insn "8") 14261diff -rNU3 dist.orig/cpu/or1korfpx.cpu dist/cpu/or1korfpx.cpu 14262--- dist.orig/cpu/or1korfpx.cpu 1970-01-01 01:00:00.000000000 +0100 14263+++ dist/cpu/or1korfpx.cpu 2015-10-18 13:11:13.000000000 +0200 14264@@ -0,0 +1,222 @@ 14265+; OpenRISC 1000 architecture. -*- Scheme -*- 14266+; Copyright 2000-2014 Free Software Foundation, Inc. 14267+; Contributed by Peter Gavin, pgavin@gmail.com 14268+; 14269+; This program is free software; you can redistribute it and/or modify 14270+; it under the terms of the GNU General Public License as published by 14271+; the Free Software Foundation; either version 3 of the License, or 14272+; (at your option) any later version. 14273+; 14274+; This program is distributed in the hope that it will be useful, 14275+; but WITHOUT ANY WARRANTY; without even the implied warranty of 14276+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14277+; GNU General Public License for more details. 14278+; 14279+; You should have received a copy of the GNU General Public License 14280+; along with this program; if not, see <http://www.gnu.org/licenses/> 14281+ 14282+; Initial ORFPX32 instruction set 14283+ 14284+; I'm not sure how CGEN handles rounding in FP operations, except for 14285+; in conversions to/from integers. So lf.add, lf.sub, lf.mul, and 14286+; lf.div do not round according to the FPCSR RM field. 14287+; NaN, overflow, and underflow are not yet handled either. 14288+ 14289+(define-normal-insn-enum insn-opcode-float-regreg 14290+ "floating point reg/reg insn opcode enums" () 14291+ OPC_FLOAT_REGREG_ f-op-7-8 14292+ (("ADD_S" #x00) 14293+ ("SUB_S" #x01) 14294+ ("MUL_S" #x02) 14295+ ("DIV_S" #x03) 14296+ ("ITOF_S" #x04) 14297+ ("FTOI_S" #x05) 14298+ ("REM_S" #x06) 14299+ ("MADD_S" #x07) 14300+ ("SFEQ_S" #x08) 14301+ ("SFNE_S" #x09) 14302+ ("SFGT_S" #x0a) 14303+ ("SFGE_S" #x0b) 14304+ ("SFLT_S" #x0c) 14305+ ("SFLE_S" #x0d) 14306+ ("ADD_D" #x10) 14307+ ("SUB_D" #x11) 14308+ ("MUL_D" #x12) 14309+ ("DIV_D" #x13) 14310+ ("ITOF_D" #x14) 14311+ ("FTOI_D" #x15) 14312+ ("REM_D" #x16) 14313+ ("MADD_D" #x17) 14314+ ("SFEQ_D" #x18) 14315+ ("SFNE_D" #x19) 14316+ ("SFGT_D" #x1a) 14317+ ("SFGE_D" #x1b) 14318+ ("SFLT_D" #x1c) 14319+ ("SFLE_D" #x1d) 14320+ ("CUST1_S" #xd0) 14321+ ("CUST1_D" #xe0) 14322+ ) 14323+ ) 14324+ 14325+(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1) 14326+(dnop rASF "source register A (single floating point mode)" () h-fsr f-r2) 14327+(dnop rBSF "source register B (single floating point mode)" () h-fsr f-r3) 14328+ 14329+(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1) 14330+(dnop rADF "source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1) 14331+(dnop rBDF "source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1) 14332+ 14333+(define-pmacro (float-regreg-insn mnemonic) 14334+ (begin 14335+ (dni (.sym lf- mnemonic -s) 14336+ (.str "lf." mnemonic ".s reg/reg/reg") 14337+ ((MACH ORFPX-MACHS)) 14338+ (.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF") 14339+ (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S)) 14340+ (set SF rDSF (mnemonic SF rASF rBSF)) 14341+ () 14342+ ) 14343+ (dni (.sym lf- mnemonic -d) 14344+ (.str "lf." mnemonic ".d reg/reg/reg") 14345+ ((MACH ORFPX64-MACHS)) 14346+ (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF") 14347+ (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D)) 14348+ (set DF rDDF (mnemonic DF rADF rBDF)) 14349+ () 14350+ ) 14351+ ) 14352+ ) 14353+ 14354+(float-regreg-insn add) 14355+(float-regreg-insn sub) 14356+(float-regreg-insn mul) 14357+(float-regreg-insn div) 14358+ 14359+(dni lf-rem-s 14360+ "lf.rem.s reg/reg/reg" 14361+ ((MACH ORFPX-MACHS)) 14362+ "lf.rem.s $rDSF,$rASF,$rBSF" 14363+ (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S) 14364+ (set SF rDSF (rem SF rASF rBSF)) 14365+ () 14366+ ) 14367+(dni lf-rem-d 14368+ "lf.rem.d reg/reg/reg" 14369+ ((MACH ORFPX64-MACHS)) 14370+ "lf.rem.d $rDDF,$rADF,$rBDF" 14371+ (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D) 14372+ (set DF rDDF (mod DF rADF rBDF)) 14373+ () 14374+ ) 14375+ 14376+(define-pmacro (get-rounding-mode) 14377+ (case INT sys-fpcsr-rm 14378+ ((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest" 14379+ ((1) 3) ; TOWARD-ZERO 14380+ ((2) 4) ; TOWARD-POSITIVE 14381+ (else 5) ; TOWARD-NEGATIVE 14382+ ) 14383+ ) 14384+ 14385+(dni lf-itof-s 14386+ "lf.itof.s reg/reg" 14387+ ((MACH ORFPX-MACHS)) 14388+ "lf.itof.s $rDSF,$rA" 14389+ (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S) 14390+ (set SF rDSF (float SF (get-rounding-mode) (trunc SI rA))) 14391+ () 14392+ ) 14393+(dni lf-itof-d 14394+ "lf.itof.d reg/reg" 14395+ ((MACH ORFPX64-MACHS)) 14396+ "lf.itof.d $rDSF,$rA" 14397+ (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D) 14398+ (set DF rDDF (float DF (get-rounding-mode) rA)) 14399+ () 14400+ ) 14401+ 14402+(dni lf-ftoi-s 14403+ "lf.ftoi.s reg/reg" 14404+ ((MACH ORFPX-MACHS)) 14405+ "lf.ftoi.s $rD,$rASF" 14406+ (+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S) 14407+ (set WI rD (ext WI (fix SI (get-rounding-mode) rASF))) 14408+ () 14409+ ) 14410+ 14411+(dni lf-ftoi-d 14412+ "lf.ftoi.d reg/reg" 14413+ ((MACH ORFPX64-MACHS)) 14414+ "lf.ftoi.d $rD,$rADF" 14415+ (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D) 14416+ (set DI rD (fix DI (get-rounding-mode) rADF)) 14417+ () 14418+ ) 14419+ 14420+(define-pmacro (float-setflag-insn mnemonic) 14421+ (begin 14422+ (dni (.sym lf- mnemonic -s) 14423+ (.str "lf.sf" mnemonic ".s reg/reg") 14424+ ((MACH ORFPX-MACHS)) 14425+ (.str "lf.sf" mnemonic ".s $rASF,$rBSF") 14426+ (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S)) 14427+ (set BI sys-sr-f (mnemonic SF rASF rBSF)) 14428+ () 14429+ ) 14430+ (dni (.sym lf- mnemonic -d) 14431+ (.str "lf.sf" mnemonic ".d reg/reg") 14432+ ((MACH ORFPX64-MACHS)) 14433+ (.str "lf.sf" mnemonic ".d $rASF,$rBSF") 14434+ (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D)) 14435+ (set BI sys-sr-f (mnemonic DF rADF rBDF)) 14436+ () 14437+ ) 14438+ ) 14439+ ) 14440+ 14441+(float-setflag-insn eq) 14442+(float-setflag-insn ne) 14443+(float-setflag-insn ge) 14444+(float-setflag-insn gt) 14445+(float-setflag-insn lt) 14446+(float-setflag-insn le) 14447+ 14448+(dni lf-madd-s 14449+ "lf.madd.s reg/reg/reg" 14450+ ((MACH ORFPX-MACHS)) 14451+ "lf.madd.s $rDSF,$rASF,$rBSF" 14452+ (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S) 14453+ (set SF rDSF (add SF (mul SF rASF rBSF) rDSF)) 14454+ () 14455+ ) 14456+(dni lf-madd-d 14457+ "lf.madd.d reg/reg/reg" 14458+ ((MACH ORFPX64-MACHS)) 14459+ "lf.madd.d $rDDF,$rADF,$rBDF" 14460+ (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D) 14461+ (set DF rDDF (add DF (mul DF rADF rBDF) rDDF)) 14462+ () 14463+ ) 14464+ 14465+(define-pmacro (float-cust-insn cust-num) 14466+ (begin 14467+ (dni (.sym "lf-cust" cust-num "-s") 14468+ (.str "lf.cust" cust-num ".s") 14469+ ((MACH ORFPX-MACHS)) 14470+ (.str "lf.cust" cust-num ".s $rASF,$rBSF") 14471+ (+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S")) 14472+ (nop) 14473+ () 14474+ ) 14475+ (dni (.sym "lf-cust" cust-num "-d") 14476+ (.str "lf.cust" cust-num ".d") 14477+ ((MACH ORFPX64-MACHS)) 14478+ (.str "lf.cust" cust-num ".d") 14479+ (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D")) 14480+ (nop) 14481+ () 14482+ ) 14483+ ) 14484+ ) 14485+ 14486+(float-cust-insn "1") 14487diff -rNU3 dist.orig/gas/Makefile.am dist/gas/Makefile.am 14488--- dist.orig/gas/Makefile.am 2012-09-04 14:53:45.000000000 +0200 14489+++ dist/gas/Makefile.am 2015-10-18 13:11:13.000000000 +0200 14490@@ -147,11 +147,11 @@ 14491 config/tc-msp430.c \ 14492 config/tc-mt.c \ 14493 config/tc-ns32k.c \ 14494- config/tc-openrisc.c \ 14495- config/tc-or32.c \ 14496+ config/tc-or1k.c \ 14497 config/tc-pdp11.c \ 14498 config/tc-pj.c \ 14499 config/tc-ppc.c \ 14500+ config/tc-riscv.c \ 14501 config/tc-rl78.c \ 14502 config/tc-rx.c \ 14503 config/tc-s390.c \ 14504@@ -216,11 +216,11 @@ 14505 config/tc-msp430.h \ 14506 config/tc-mt.h \ 14507 config/tc-ns32k.h \ 14508- config/tc-openrisc.h \ 14509- config/tc-or32.h \ 14510+ config/tc-or1k.h \ 14511 config/tc-pdp11.h \ 14512 config/tc-pj.h \ 14513 config/tc-ppc.h \ 14514+ config/tc-riscv.h \ 14515 config/tc-rl78.h \ 14516 config/tc-rx.h \ 14517 config/tc-s390.h \ 14518diff -rNU3 dist.orig/gas/Makefile.in dist/gas/Makefile.in 14519--- dist.orig/gas/Makefile.in 2012-09-04 14:53:45.000000000 +0200 14520+++ dist/gas/Makefile.in 2015-10-18 13:11:13.000000000 +0200 14521@@ -415,11 +415,11 @@ 14522 config/tc-msp430.c \ 14523 config/tc-mt.c \ 14524 config/tc-ns32k.c \ 14525- config/tc-openrisc.c \ 14526- config/tc-or32.c \ 14527+ config/tc-or1k.c \ 14528 config/tc-pdp11.c \ 14529 config/tc-pj.c \ 14530 config/tc-ppc.c \ 14531+ config/tc-riscv.c \ 14532 config/tc-rl78.c \ 14533 config/tc-rx.c \ 14534 config/tc-s390.c \ 14535@@ -484,11 +484,11 @@ 14536 config/tc-msp430.h \ 14537 config/tc-mt.h \ 14538 config/tc-ns32k.h \ 14539- config/tc-openrisc.h \ 14540- config/tc-or32.h \ 14541+ config/tc-or1k.h \ 14542 config/tc-pdp11.h \ 14543 config/tc-pj.h \ 14544 config/tc-ppc.h \ 14545+ config/tc-riscv.h \ 14546 config/tc-rl78.h \ 14547 config/tc-rx.h \ 14548 config/tc-s390.h \ 14549@@ -835,11 +835,11 @@ 14550 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-msp430.Po@am__quote@ 14551 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mt.Po@am__quote@ 14552 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ns32k.Po@am__quote@ 14553-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-openrisc.Po@am__quote@ 14554-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-or32.Po@am__quote@ 14555+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-or1k.Po@am__quote@ 14556 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@ 14557 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@ 14558 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@ 14559+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-riscv.Po@am__quote@ 14560 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rl78.Po@am__quote@ 14561 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@ 14562 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@ 14563@@ -1447,33 +1447,19 @@ 14564 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14565 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ns32k.obj `if test -f 'config/tc-ns32k.c'; then $(CYGPATH_W) 'config/tc-ns32k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ns32k.c'; fi` 14566 14567-tc-openrisc.o: config/tc-openrisc.c 14568-@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-openrisc.o -MD -MP -MF $(DEPDIR)/tc-openrisc.Tpo -c -o tc-openrisc.o `test -f 'config/tc-openrisc.c' || echo '$(srcdir)/'`config/tc-openrisc.c 14569-@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-openrisc.Tpo $(DEPDIR)/tc-openrisc.Po 14570-@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-openrisc.c' object='tc-openrisc.o' libtool=no @AMDEPBACKSLASH@ 14571+tc-or1k.o: config/tc-or1k.c 14572+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or1k.o -MD -MP -MF $(DEPDIR)/tc-or1k.Tpo -c -o tc-or1k.o `test -f 'config/tc-or1k.c' || echo '$(srcdir)/'`config/tc-or1k.c 14573+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or1k.Tpo $(DEPDIR)/tc-or1k.Po 14574+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or1k.c' object='tc-or1k.o' libtool=no @AMDEPBACKSLASH@ 14575+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14576+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or1k.o `test -f 'config/tc-or1k.c' || echo '$(srcdir)/'`config/tc-or1k.c 14577+ 14578+tc-or1k.obj: config/tc-or1k.c 14579+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or1k.obj -MD -MP -MF $(DEPDIR)/tc-or1k.Tpo -c -o tc-or1k.obj `if test -f 'config/tc-or1k.c'; then $(CYGPATH_W) 'config/tc-or1k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or1k.c'; fi` 14580+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or1k.Tpo $(DEPDIR)/tc-or1k.Po 14581+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or1k.c' object='tc-or1k.obj' libtool=no @AMDEPBACKSLASH@ 14582 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14583-@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-openrisc.o `test -f 'config/tc-openrisc.c' || echo '$(srcdir)/'`config/tc-openrisc.c 14584- 14585-tc-openrisc.obj: config/tc-openrisc.c 14586-@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-openrisc.obj -MD -MP -MF $(DEPDIR)/tc-openrisc.Tpo -c -o tc-openrisc.obj `if test -f 'config/tc-openrisc.c'; then $(CYGPATH_W) 'config/tc-openrisc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-openrisc.c'; fi` 14587-@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-openrisc.Tpo $(DEPDIR)/tc-openrisc.Po 14588-@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-openrisc.c' object='tc-openrisc.obj' libtool=no @AMDEPBACKSLASH@ 14589-@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14590-@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-openrisc.obj `if test -f 'config/tc-openrisc.c'; then $(CYGPATH_W) 'config/tc-openrisc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-openrisc.c'; fi` 14591- 14592-tc-or32.o: config/tc-or32.c 14593-@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or32.o -MD -MP -MF $(DEPDIR)/tc-or32.Tpo -c -o tc-or32.o `test -f 'config/tc-or32.c' || echo '$(srcdir)/'`config/tc-or32.c 14594-@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or32.Tpo $(DEPDIR)/tc-or32.Po 14595-@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or32.c' object='tc-or32.o' libtool=no @AMDEPBACKSLASH@ 14596-@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14597-@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or32.o `test -f 'config/tc-or32.c' || echo '$(srcdir)/'`config/tc-or32.c 14598- 14599-tc-or32.obj: config/tc-or32.c 14600-@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or32.obj -MD -MP -MF $(DEPDIR)/tc-or32.Tpo -c -o tc-or32.obj `if test -f 'config/tc-or32.c'; then $(CYGPATH_W) 'config/tc-or32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or32.c'; fi` 14601-@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or32.Tpo $(DEPDIR)/tc-or32.Po 14602-@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or32.c' object='tc-or32.obj' libtool=no @AMDEPBACKSLASH@ 14603-@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14604-@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or32.obj `if test -f 'config/tc-or32.c'; then $(CYGPATH_W) 'config/tc-or32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or32.c'; fi` 14605+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or1k.obj `if test -f 'config/tc-or1k.c'; then $(CYGPATH_W) 'config/tc-or1k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or1k.c'; fi` 14606 14607 tc-pdp11.o: config/tc-pdp11.c 14608 @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-pdp11.o -MD -MP -MF $(DEPDIR)/tc-pdp11.Tpo -c -o tc-pdp11.o `test -f 'config/tc-pdp11.c' || echo '$(srcdir)/'`config/tc-pdp11.c 14609@@ -1517,6 +1503,20 @@ 14610 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14611 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi` 14612 14613+tc-riscv.o: config/tc-riscv.c 14614+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.o -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c 14615+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po 14616+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.o' libtool=no @AMDEPBACKSLASH@ 14617+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14618+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c 14619+ 14620+tc-riscv.obj: config/tc-riscv.c 14621+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.obj -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi` 14622+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po 14623+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.obj' libtool=no @AMDEPBACKSLASH@ 14624+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 14625+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi` 14626+ 14627 tc-rl78.o: config/tc-rl78.c 14628 @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rl78.o -MD -MP -MF $(DEPDIR)/tc-rl78.Tpo -c -o tc-rl78.o `test -f 'config/tc-rl78.c' || echo '$(srcdir)/'`config/tc-rl78.c 14629 @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-rl78.Tpo $(DEPDIR)/tc-rl78.Po 14630diff -rNU3 dist.orig/gas/atof-generic.c dist/gas/atof-generic.c 14631--- dist.orig/gas/atof-generic.c 2009-09-02 09:24:19.000000000 +0200 14632+++ dist/gas/atof-generic.c 2015-10-18 13:11:13.000000000 +0200 14633@@ -121,6 +121,32 @@ 14634 14635 switch (first_digit[0]) 14636 { 14637+ case 's': 14638+ case 'S': 14639+ if (!strncasecmp ("snan", first_digit, 4)) 14640+ { 14641+ address_of_generic_floating_point_number->sign = 0; 14642+ address_of_generic_floating_point_number->exponent = 0; 14643+ address_of_generic_floating_point_number->leader = 14644+ address_of_generic_floating_point_number->low; 14645+ *address_of_string_pointer = first_digit + 4; 14646+ return 0; 14647+ } 14648+ break; 14649+ 14650+ case 'q': 14651+ case 'Q': 14652+ if (!strncasecmp ("qnan", first_digit, 4)) 14653+ { 14654+ address_of_generic_floating_point_number->sign = 0; 14655+ address_of_generic_floating_point_number->exponent = 0; 14656+ address_of_generic_floating_point_number->leader = 14657+ address_of_generic_floating_point_number->low; 14658+ *address_of_string_pointer = first_digit + 4; 14659+ return 0; 14660+ } 14661+ break; 14662+ 14663 case 'n': 14664 case 'N': 14665 if (!strncasecmp ("nan", first_digit, 3)) 14666diff -rNU3 dist.orig/gas/config/atof-vax.c dist/gas/config/atof-vax.c 14667--- dist.orig/gas/config/atof-vax.c 2007-10-17 18:45:54.000000000 +0200 14668+++ dist/gas/config/atof-vax.c 2015-10-18 13:11:13.000000000 +0200 14669@@ -268,10 +268,27 @@ 14670 int exponent_skippage; 14671 LITTLENUM_TYPE word1; 14672 14673- /* JF: Deal with new Nan, +Inf and -Inf codes. */ 14674 if (f->sign != '-' && f->sign != '+') 14675 { 14676- make_invalid_floating_point_number (words); 14677+ if (f->sign == 0) 14678+ { 14679+ /* All NaNs are 0. */ 14680+ memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision); 14681+ } 14682+ else if (f->sign == 'P') 14683+ { 14684+ /* Positive Infinity. */ 14685+ memset (words, 0xff, sizeof (LITTLENUM_TYPE) * precision); 14686+ words[0] &= 0x7fff; 14687+ } 14688+ else if (f->sign == 'N') 14689+ { 14690+ /* Negative Infinity. */ 14691+ memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision); 14692+ words[0] = 0x0080; 14693+ } 14694+ else 14695+ make_invalid_floating_point_number (words); 14696 return return_value; 14697 } 14698 14699diff -rNU3 dist.orig/gas/config/obj-elf.c dist/gas/config/obj-elf.c 14700--- dist.orig/gas/config/obj-elf.c 2012-06-30 08:32:29.000000000 +0200 14701+++ dist/gas/config/obj-elf.c 2015-10-18 13:11:13.000000000 +0200 14702@@ -1705,12 +1705,14 @@ 14703 const struct elf_backend_data *bed; 14704 14705 bed = get_elf_backend_data (stdoutput); 14706+#if 0 14707 if (!(bed->elf_osabi == ELFOSABI_GNU 14708 || bed->elf_osabi == ELFOSABI_FREEBSD 14709 /* GNU is still using the default value 0. */ 14710 || bed->elf_osabi == ELFOSABI_NONE)) 14711 as_bad (_("symbol type \"%s\" is supported only by GNU and FreeBSD targets"), 14712 type_name); 14713+#endif 14714 type = BSF_FUNCTION | BSF_GNU_INDIRECT_FUNCTION; 14715 } 14716 else if (strcmp (type_name, "gnu_unique_object") == 0) 14717diff -rNU3 dist.orig/gas/config/tc-arm.c dist/gas/config/tc-arm.c 14718--- dist.orig/gas/config/tc-arm.c 2013-03-25 09:06:21.000000000 +0100 14719+++ dist/gas/config/tc-arm.c 2015-10-18 13:11:13.000000000 +0200 14720@@ -6936,7 +6936,7 @@ 14721 14722 /* Functions for operand encoding. ARM, then Thumb. */ 14723 14724-#define rotate_left(v, n) (v << n | v >> (32 - n)) 14725+#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) 14726 14727 /* If VAL can be encoded in the immediate field of an ARM instruction, 14728 return the encoded form. Otherwise, return FAIL. */ 14729@@ -17290,12 +17290,16 @@ 14730 asection *sect; 14731 14732 for (sect = stdoutput->sections; sect != NULL; sect = sect->next) 14733- if (seg_info (sect)->tc_segment_info_data.current_it.state 14734- == MANUAL_IT_BLOCK) 14735- { 14736- as_warn (_("section '%s' finished with an open IT block."), 14737- sect->name); 14738- } 14739+ { 14740+ segment_info_type *seginfo = seg_info (sect); 14741+ 14742+ if (seginfo && seginfo->tc_segment_info_data.current_it.state 14743+ == MANUAL_IT_BLOCK) 14744+ { 14745+ as_warn (_("section '%s' finished with an open IT block."), 14746+ sect->name); 14747+ } 14748+ } 14749 #else 14750 if (now_it.state == MANUAL_IT_BLOCK) 14751 as_warn (_("file finished with an open IT block.")); 14752diff -rNU3 dist.orig/gas/config/tc-m68k.c dist/gas/config/tc-m68k.c 14753--- dist.orig/gas/config/tc-m68k.c 2012-05-16 12:26:47.000000000 +0200 14754+++ dist/gas/config/tc-m68k.c 2015-10-18 13:11:13.000000000 +0200 14755@@ -7426,12 +7426,12 @@ 14756 } 14757 } 14758 14759- /* Remove 'm' or 'mc' prefix from 68k variants. */ 14760+ /* Remove 'm' or 'mc' prefix from 68k or coldfire variants. */ 14761 if (allow_m) 14762 { 14763 if (arg[0] == 'm') 14764 { 14765- if (arg[1] == '6') 14766+ if (arg[1] == '6' || arg[1] == '5') 14767 arg += 1; 14768 else if (arg[1] == 'c' && arg[2] == '6') 14769 arg += 2; 14770diff -rNU3 dist.orig/gas/config/tc-mips.c dist/gas/config/tc-mips.c 14771--- dist.orig/gas/config/tc-mips.c 2012-09-04 16:21:03.000000000 +0200 14772+++ dist/gas/config/tc-mips.c 2015-10-18 13:11:13.000000000 +0200 14773@@ -909,6 +909,9 @@ 14774 NUM_FIX_VR4120_CLASSES 14775 }; 14776 14777+/* ...likewise -mtrap-zero-jump. */ 14778+static bfd_boolean mips_trap_zero_jump; 14779+ 14780 /* ...likewise -mfix-loongson2f-jump. */ 14781 static bfd_boolean mips_fix_loongson2f_jump; 14782 14783@@ -941,6 +944,8 @@ 14784 efficient expansion. */ 14785 14786 static int mips_relax_branch; 14787+ 14788+static int mips_fix_loongson2f_btb; 14789 14790 /* The expansion of many macros depends on the type of symbol that 14791 they refer to. For example, when generating position-dependent code, 14792@@ -1316,6 +1321,7 @@ 14793 static void mips16_macro_build 14794 (expressionS *, const char *, const char *, va_list *); 14795 static void load_register (int, expressionS *, int); 14796+static void macro_build (expressionS *, const char *, const char *, ...); 14797 static void macro_start (void); 14798 static void macro_end (void); 14799 static void macro (struct mips_cl_insn * ip); 14800@@ -3626,6 +3632,35 @@ 14801 return nops; 14802 } 14803 14804+static void 14805+trap_zero_jump (struct mips_cl_insn * ip) 14806+{ 14807+ if (strcmp (ip->insn_mo->name, "j") == 0 14808+ || strcmp (ip->insn_mo->name, "jr") == 0 14809+ || strcmp (ip->insn_mo->name, "jalr") == 0) 14810+ { 14811+ int sreg; 14812+ 14813+ if (mips_opts.warn_about_macros) 14814+ return; 14815+ 14816+ sreg = EXTRACT_OPERAND (0, RS, *ip); 14817+ if (mips_opts.isa == ISA_MIPS32 14818+ || mips_opts.isa == ISA_MIPS32R2 14819+ || mips_opts.isa == ISA_MIPS64 14820+ || mips_opts.isa == ISA_MIPS64R2) 14821+ { 14822+ expressionS ep; 14823+ ep.X_op = O_constant; 14824+ ep.X_add_number = 4096; 14825+ macro_build (&ep, "tltiu", "s,j", sreg, BFD_RELOC_LO16); 14826+ } 14827+ else if (mips_opts.isa != ISA_UNKNOWN 14828+ && mips_opts.isa != ISA_MIPS1) 14829+ macro_build (NULL, "teq", "s,t", sreg, 0); 14830+ } 14831+} 14832+ 14833 /* Fix NOP issue: Replace nops by "or at,at,zero". */ 14834 14835 static void 14836@@ -3663,6 +3698,16 @@ 14837 ep.X_add_number = 0xffff; 14838 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); 14839 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); 14840+ /* Hide these three instructions to avoid getting a ``macro expanded into 14841+ multiple instructions'' warning. */ 14842+ if (mips_relax.sequence != 2) { 14843+ mips_macro_warning.sizes[0] -= 3 * 4; 14844+ mips_macro_warning.insns[0] -= 3; 14845+ } 14846+ if (mips_relax.sequence != 1) { 14847+ mips_macro_warning.sizes[1] -= 3 * 4; 14848+ mips_macro_warning.insns[1] -= 3; 14849+ } 14850 } 14851 } 14852 14853@@ -3718,6 +3763,11 @@ 14854 if (mips_opts.mips16 && history[0].fixp[0]) 14855 return FALSE; 14856 14857+ if (mips_fix_loongson2f) 14858+ fix_loongson2f (ip); 14859+ if (mips_trap_zero_jump) 14860+ trap_zero_jump (ip); 14861+ 14862 /* If the branch is itself the target of a branch, we can not swap. 14863 We cheat on this; all we check for is whether there is a label on 14864 this instruction. If there are any branches to anything other than 14865@@ -4764,6 +4814,45 @@ 14866 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); 14867 } 14868 14869+/* Fix jump through register issue on loongson2f processor for kernel code: 14870+ force a BTB clear before the jump to prevent it from being incorrectly 14871+ prefetched by the branch prediction engine. */ 14872+ 14873+static void 14874+macro_build_jrpatch (expressionS *ep, unsigned int sreg) 14875+{ 14876+ if (!mips_fix_loongson2f_btb) 14877+ return; 14878+ 14879+ if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == AT) 14880+ return; 14881+ 14882+ if (!mips_opts.at) 14883+ { 14884+ as_warn (_("unable to apply loongson2f BTB workaround when .set noat")); 14885+ return; 14886+ } 14887+ 14888+ /* li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE */ 14889+ ep->X_op = O_constant; 14890+ ep->X_add_number = 3; 14891+ macro_build (ep, "ori", "t,r,i", AT, ZERO, BFD_RELOC_LO16); 14892+ 14893+ /* dmtc0 $at, COP_0_DIAG */ 14894+ macro_build (NULL, "dmtc0", "t,G", AT, 22); 14895+ 14896+ /* Hide these two instructions to avoid getting a ``macro expanded into 14897+ multiple instructions'' warning. */ 14898+ if (mips_relax.sequence != 2) { 14899+ mips_macro_warning.sizes[0] -= 2 * 4; 14900+ mips_macro_warning.insns[0] -= 2; 14901+ } 14902+ if (mips_relax.sequence != 1) { 14903+ mips_macro_warning.sizes[1] -= 2 * 4; 14904+ mips_macro_warning.insns[1] -= 2; 14905+ } 14906+} 14907+ 14908 /* Build an instruction created by a macro expansion. This is passed 14909 a pointer to the count of instructions created so far, an 14910 expression, the name of the instruction to build, an operand format 14911@@ -7637,6 +7726,26 @@ 14912 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); 14913 break; 14914 14915+ case M_JR_S: 14916+ macro_build_jrpatch (&expr1, sreg); 14917+ macro_build (NULL, "jr", "s", sreg); 14918+ return; /* didn't modify $at */ 14919+ 14920+ case M_J_S: 14921+ macro_build_jrpatch (&expr1, sreg); 14922+ macro_build (NULL, "j", "s", sreg); 14923+ return; /* didn't modify $at */ 14924+ 14925+ case M_JALR_S: 14926+ macro_build_jrpatch (&expr1, sreg); 14927+ macro_build (NULL, "jalr", "s", sreg); 14928+ return; /* didn't modify $at */ 14929+ 14930+ case M_JALR_DS: 14931+ macro_build_jrpatch (&expr1, sreg); 14932+ macro_build (NULL, "jalr", "d,s", dreg, sreg); 14933+ return; /* didn't modify $at */ 14934+ 14935 case M_MSGSND: 14936 gas_assert (!mips_opts.micromips); 14937 { 14938@@ -9126,18 +9235,28 @@ 14939 14940 14941 case M_SAA_AB: 14942- ab = 1; 14943+ ab = (offset_expr.X_op != O_constant || offset_expr.X_add_number != 0); 14944 case M_SAA_OB: 14945 s = "saa"; 14946 off0 = 1; 14947 fmt = "t,(b)"; 14948+ if (!ab) 14949+ { 14950+ tempreg = AT; 14951+ goto ld_noat; 14952+ } 14953 goto ld_st; 14954 case M_SAAD_AB: 14955- ab = 1; 14956+ ab = (offset_expr.X_op != O_constant || offset_expr.X_add_number != 0); 14957 case M_SAAD_OB: 14958 s = "saad"; 14959 off0 = 1; 14960 fmt = "t,(b)"; 14961+ if (!ab) 14962+ { 14963+ tempreg = AT; 14964+ goto ld_noat; 14965+ } 14966 goto ld_st; 14967 14968 /* New code added to support COPZ instructions. 14969@@ -14350,6 +14469,8 @@ 14970 OPTION_SINGLE_FLOAT, 14971 OPTION_DOUBLE_FLOAT, 14972 OPTION_32, 14973+ OPTION_TRAP_ZERO_JUMP, 14974+ OPTION_NO_TRAP_ZERO_JUMP, 14975 #ifdef OBJ_ELF 14976 OPTION_CALL_SHARED, 14977 OPTION_CALL_NONPIC, 14978@@ -14364,6 +14485,8 @@ 14979 OPTION_NO_PDR, 14980 OPTION_MVXWORKS_PIC, 14981 #endif /* OBJ_ELF */ 14982+ OPTION_FIX_LOONGSON2F_BTB, 14983+ OPTION_NO_FIX_LOONGSON2F_BTB, 14984 OPTION_END_OF_ENUM 14985 }; 14986 14987@@ -14421,6 +14544,8 @@ 14988 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, 14989 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, 14990 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, 14991+ {"mfix-loongson2f-btb", no_argument, NULL, OPTION_FIX_LOONGSON2F_BTB}, 14992+ {"mno-fix-loongson2f-btb", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_BTB}, 14993 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 14994 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 14995 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, 14996@@ -14459,6 +14584,9 @@ 14997 make testing easier. */ 14998 {"32", no_argument, NULL, OPTION_32}, 14999 15000+ {"mtrap-zero-jump", no_argument, NULL, OPTION_TRAP_ZERO_JUMP}, 15001+ {"mno-trap-zero-jump", no_argument, NULL, OPTION_NO_TRAP_ZERO_JUMP}, 15002+ 15003 /* ELF-specific options. */ 15004 #ifdef OBJ_ELF 15005 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 15006@@ -14750,6 +14878,14 @@ 15007 mips_fix_vr4130 = 0; 15008 break; 15009 15010+ case OPTION_FIX_LOONGSON2F_BTB: 15011+ mips_fix_loongson2f_btb = 1; 15012+ break; 15013+ 15014+ case OPTION_NO_FIX_LOONGSON2F_BTB: 15015+ mips_fix_loongson2f_btb = 0; 15016+ break; 15017+ 15018 case OPTION_FIX_CN63XXP1: 15019 mips_fix_cn63xxp1 = TRUE; 15020 break; 15021@@ -14782,6 +14918,14 @@ 15022 mips_opts.sym32 = FALSE; 15023 break; 15024 15025+ case OPTION_TRAP_ZERO_JUMP: 15026+ mips_trap_zero_jump = TRUE; 15027+ break; 15028+ 15029+ case OPTION_NO_TRAP_ZERO_JUMP: 15030+ mips_trap_zero_jump = FALSE; 15031+ break; 15032+ 15033 #ifdef OBJ_ELF 15034 /* When generating ELF code, we permit -KPIC and -call_shared to 15035 select SVR4_PIC, and -non_shared to select no PIC. This is 15036@@ -19411,6 +19555,7 @@ 15037 fprintf (stream, _("\ 15038 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ 15039 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ 15040+-mfix-loongson2f-btb work around Loongson2F BTB errata\n\ 15041 -mfix-vr4120 work around certain VR4120 errata\n\ 15042 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ 15043 -mfix-24k insert a nop after ERET and DERET instructions\n\ 15044diff -rNU3 dist.orig/gas/config/tc-openrisc.c dist/gas/config/tc-openrisc.c 15045--- dist.orig/gas/config/tc-openrisc.c 2009-07-24 13:45:00.000000000 +0200 15046+++ dist/gas/config/tc-openrisc.c 1970-01-01 01:00:00.000000000 +0100 15047@@ -1,363 +0,0 @@ 15048-/* tc-openrisc.c -- Assembler for the OpenRISC family. 15049- Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2009 15050- Free Software Foundation. 15051- Contributed by Johan Rydberg, jrydberg@opencores.org 15052- 15053- This file is part of GAS, the GNU Assembler. 15054- 15055- GAS is free software; you can redistribute it and/or modify 15056- it under the terms of the GNU General Public License as published by 15057- the Free Software Foundation; either version 3, or (at your option) 15058- any later version. 15059- 15060- GAS is distributed in the hope that it will be useful, 15061- but WITHOUT ANY WARRANTY; without even the implied warranty of 15062- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15063- GNU General Public License for more details. 15064- 15065- You should have received a copy of the GNU General Public License 15066- along with GAS; see the file COPYING. If not, write to 15067- the Free Software Foundation, 51 Franklin Street - Fifth Floor, 15068- Boston, MA 02110-1301, USA. */ 15069- 15070-#include "as.h" 15071-#include "subsegs.h" 15072-#include "symcat.h" 15073-#include "opcodes/openrisc-desc.h" 15074-#include "opcodes/openrisc-opc.h" 15075-#include "cgen.h" 15076- 15077-/* Structure to hold all of the different components describing 15078- an individual instruction. */ 15079-typedef struct openrisc_insn openrisc_insn; 15080- 15081-struct openrisc_insn 15082-{ 15083- const CGEN_INSN * insn; 15084- const CGEN_INSN * orig_insn; 15085- CGEN_FIELDS fields; 15086-#if CGEN_INT_INSN_P 15087- CGEN_INSN_INT buffer [1]; 15088-#define INSN_VALUE(buf) (*(buf)) 15089-#else 15090- unsigned char buffer [CGEN_MAX_INSN_SIZE]; 15091-#define INSN_VALUE(buf) (buf) 15092-#endif 15093- char * addr; 15094- fragS * frag; 15095- int num_fixups; 15096- fixS * fixups [GAS_CGEN_MAX_FIXUPS]; 15097- int indices [MAX_OPERAND_INSTANCES]; 15098-}; 15099- 15100- 15101-const char comment_chars[] = "#"; 15102-const char line_comment_chars[] = "#"; 15103-const char line_separator_chars[] = ";"; 15104-const char EXP_CHARS[] = "eE"; 15105-const char FLT_CHARS[] = "dD"; 15106- 15107- 15108-#define OPENRISC_SHORTOPTS "m:" 15109-const char * md_shortopts = OPENRISC_SHORTOPTS; 15110- 15111-struct option md_longopts[] = 15112-{ 15113- {NULL, no_argument, NULL, 0} 15114-}; 15115-size_t md_longopts_size = sizeof (md_longopts); 15116- 15117-unsigned long openrisc_machine = 0; /* default */ 15118- 15119-int 15120-md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED) 15121-{ 15122- return 0; 15123-} 15124- 15125-void 15126-md_show_usage (FILE * stream ATTRIBUTE_UNUSED) 15127-{ 15128-} 15129- 15130-static void 15131-ignore_pseudo (int val ATTRIBUTE_UNUSED) 15132-{ 15133- discard_rest_of_line (); 15134-} 15135- 15136-const char openrisc_comment_chars [] = ";#"; 15137- 15138-/* The target specific pseudo-ops which we support. */ 15139-const pseudo_typeS md_pseudo_table[] = 15140-{ 15141- { "word", cons, 4 }, 15142- { "proc", ignore_pseudo, 0 }, 15143- { "endproc", ignore_pseudo, 0 }, 15144- { NULL, NULL, 0 } 15145-}; 15146- 15147- 15148- 15149-void 15150-md_begin (void) 15151-{ 15152- /* Initialize the `cgen' interface. */ 15153- 15154- /* Set the machine number and endian. */ 15155- gas_cgen_cpu_desc = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, 15156- CGEN_CPU_OPEN_ENDIAN, 15157- CGEN_ENDIAN_BIG, 15158- CGEN_CPU_OPEN_END); 15159- openrisc_cgen_init_asm (gas_cgen_cpu_desc); 15160- 15161- /* This is a callback from cgen to gas to parse operands. */ 15162- cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); 15163-} 15164- 15165-void 15166-md_assemble (char * str) 15167-{ 15168- static int last_insn_had_delay_slot = 0; 15169- openrisc_insn insn; 15170- char * errmsg; 15171- 15172- /* Initialize GAS's cgen interface for a new instruction. */ 15173- gas_cgen_init_parse (); 15174- 15175- insn.insn = openrisc_cgen_assemble_insn 15176- (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); 15177- 15178- if (!insn.insn) 15179- { 15180- as_bad ("%s", errmsg); 15181- return; 15182- } 15183- 15184- /* Doesn't really matter what we pass for RELAX_P here. */ 15185- gas_cgen_finish_insn (insn.insn, insn.buffer, 15186- CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); 15187- 15188- last_insn_had_delay_slot 15189- = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); 15190-} 15191- 15192- 15193-/* The syntax in the manual says constants begin with '#'. 15194- We just ignore it. */ 15195- 15196-void 15197-md_operand (expressionS * expressionP) 15198-{ 15199- if (* input_line_pointer == '#') 15200- { 15201- input_line_pointer ++; 15202- expression (expressionP); 15203- } 15204-} 15205- 15206-valueT 15207-md_section_align (segT segment, valueT size) 15208-{ 15209- int align = bfd_get_section_alignment (stdoutput, segment); 15210- return ((size + (1 << align) - 1) & (-1 << align)); 15211-} 15212- 15213-symbolS * 15214-md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 15215-{ 15216- return 0; 15217-} 15218- 15219- 15220-/* Interface to relax_segment. */ 15221- 15222-/* FIXME: Look through this. */ 15223- 15224-const relax_typeS md_relax_table[] = 15225-{ 15226-/* The fields are: 15227- 1) most positive reach of this state, 15228- 2) most negative reach of this state, 15229- 3) how many bytes this mode will add to the size of the current frag 15230- 4) which index into the table to try if we can't fit into this one. */ 15231- 15232- /* The first entry must be unused because an `rlx_more' value of zero ends 15233- each list. */ 15234- {1, 1, 0, 0}, 15235- 15236- /* The displacement used by GAS is from the end of the 2 byte insn, 15237- so we subtract 2 from the following. */ 15238- /* 16 bit insn, 8 bit disp -> 10 bit range. 15239- This doesn't handle a branch in the right slot at the border: 15240- the "& -4" isn't taken into account. It's not important enough to 15241- complicate things over it, so we subtract an extra 2 (or + 2 in -ve 15242- case). */ 15243- {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, 15244- /* 32 bit insn, 24 bit disp -> 26 bit range. */ 15245- {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, 15246- /* Same thing, but with leading nop for alignment. */ 15247- {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } 15248-}; 15249- 15250-/* Return an initial guess of the length by which a fragment must grow to 15251- hold a branch to reach its destination. 15252- Also updates fr_type/fr_subtype as necessary. 15253- 15254- Called just before doing relaxation. 15255- Any symbol that is now undefined will not become defined. 15256- The guess for fr_var is ACTUALLY the growth beyond fr_fix. 15257- Whatever we do to grow fr_fix or fr_var contributes to our returned value. 15258- Although it may not be explicit in the frag, pretend fr_var starts with a 15259- 0 value. */ 15260- 15261-int 15262-md_estimate_size_before_relax (fragS * fragP, segT segment) 15263-{ 15264- /* The only thing we have to handle here are symbols outside of the 15265- current segment. They may be undefined or in a different segment in 15266- which case linker scripts may place them anywhere. 15267- However, we can't finish the fragment here and emit the reloc as insn 15268- alignment requirements may move the insn about. */ 15269- 15270- if (S_GET_SEGMENT (fragP->fr_symbol) != segment) 15271- { 15272- /* The symbol is undefined in this segment. 15273- Change the relaxation subtype to the max allowable and leave 15274- all further handling to md_convert_frag. */ 15275- fragP->fr_subtype = 2; 15276- 15277- { 15278- const CGEN_INSN * insn; 15279- int i; 15280- 15281- /* Update the recorded insn. 15282- Fortunately we don't have to look very far. 15283- FIXME: Change this to record in the instruction the next higher 15284- relaxable insn to use. */ 15285- for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) 15286- { 15287- if ((strcmp (CGEN_INSN_MNEMONIC (insn), 15288- CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) 15289- == 0) 15290- && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) 15291- break; 15292- } 15293- if (i == 4) 15294- abort (); 15295- 15296- fragP->fr_cgen.insn = insn; 15297- return 2; 15298- } 15299- } 15300- 15301- return md_relax_table[fragP->fr_subtype].rlx_length; 15302-} 15303- 15304-/* *fragP has been relaxed to its final size, and now needs to have 15305- the bytes inside it modified to conform to the new size. 15306- 15307- Called after relaxation is finished. 15308- fragP->fr_type == rs_machine_dependent. 15309- fragP->fr_subtype is the subtype of what the address relaxed to. */ 15310- 15311-void 15312-md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, 15313- segT sec ATTRIBUTE_UNUSED, 15314- fragS * fragP ATTRIBUTE_UNUSED) 15315-{ 15316- /* FIXME */ 15317-} 15318- 15319- 15320-/* Functions concerning relocs. */ 15321- 15322-/* The location from which a PC relative jump should be calculated, 15323- given a PC relative reloc. */ 15324- 15325-long 15326-md_pcrel_from_section (fixS * fixP, segT sec) 15327-{ 15328- if (fixP->fx_addsy != (symbolS *) NULL 15329- && (! S_IS_DEFINED (fixP->fx_addsy) 15330- || S_GET_SEGMENT (fixP->fx_addsy) != sec)) 15331- /* The symbol is undefined (or is defined but not in this section). 15332- Let the linker figure it out. */ 15333- return 0; 15334- 15335- return (fixP->fx_frag->fr_address + fixP->fx_where) & ~1; 15336-} 15337- 15338- 15339-/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. 15340- Returns BFD_RELOC_NONE if no reloc type can be found. 15341- *FIXP may be modified if desired. */ 15342- 15343-bfd_reloc_code_real_type 15344-md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, 15345- const CGEN_OPERAND * operand, 15346- fixS * fixP) 15347-{ 15348- bfd_reloc_code_real_type type; 15349- 15350- switch (operand->type) 15351- { 15352- case OPENRISC_OPERAND_ABS_26: 15353- fixP->fx_pcrel = 0; 15354- type = BFD_RELOC_OPENRISC_ABS_26; 15355- goto emit; 15356- case OPENRISC_OPERAND_DISP_26: 15357- fixP->fx_pcrel = 1; 15358- type = BFD_RELOC_OPENRISC_REL_26; 15359- goto emit; 15360- 15361- case OPENRISC_OPERAND_HI16: 15362- type = BFD_RELOC_HI16; 15363- goto emit; 15364- 15365- case OPENRISC_OPERAND_LO16: 15366- type = BFD_RELOC_LO16; 15367- goto emit; 15368- 15369- emit: 15370- return type; 15371- 15372- default : /* avoid -Wall warning */ 15373- break; 15374- } 15375- 15376- return BFD_RELOC_NONE; 15377-} 15378- 15379-/* Write a value out to the object file, using the appropriate endianness. */ 15380- 15381-void 15382-md_number_to_chars (char * buf, valueT val, int n) 15383-{ 15384- number_to_chars_bigendian (buf, val, n); 15385-} 15386- 15387-/* Turn a string in input_line_pointer into a floating point constant of type 15388- type, and store the appropriate bytes in *litP. The number of LITTLENUMS 15389- emitted is stored in *sizeP . An error message is returned, or NULL on OK. 15390-*/ 15391- 15392-/* Equal to MAX_PRECISION in atof-ieee.c */ 15393-#define MAX_LITTLENUMS 6 15394- 15395-char * 15396-md_atof (int type, char * litP, int * sizeP) 15397-{ 15398- return ieee_md_atof (type, litP, sizeP, TRUE); 15399-} 15400- 15401-bfd_boolean 15402-openrisc_fix_adjustable (fixS * fixP) 15403-{ 15404- /* We need the symbol name for the VTABLE entries. */ 15405- if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 15406- || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 15407- return 0; 15408- 15409- return 1; 15410-} 15411diff -rNU3 dist.orig/gas/config/tc-openrisc.h dist/gas/config/tc-openrisc.h 15412--- dist.orig/gas/config/tc-openrisc.h 2007-07-03 13:01:04.000000000 +0200 15413+++ dist/gas/config/tc-openrisc.h 1970-01-01 01:00:00.000000000 +0100 15414@@ -1,61 +0,0 @@ 15415-/* tc-openrisc.h -- Header file for tc-openrisc.c. 15416- Copyright 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. 15417- 15418- This file is part of GAS, the GNU Assembler. 15419- 15420- GAS is free software; you can redistribute it and/or modify 15421- it under the terms of the GNU General Public License as published by 15422- the Free Software Foundation; either version 3, or (at your option) 15423- any later version. 15424- 15425- GAS is distributed in the hope that it will be useful, 15426- but WITHOUT ANY WARRANTY; without even the implied warranty of 15427- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15428- GNU General Public License for more details. 15429- 15430- You should have received a copy of the GNU General Public License 15431- along with GAS; see the file COPYING. If not, write to 15432- the Free Software Foundation, 51 Franklin Street - Fifth Floor, 15433- Boston, MA 02110-1301, USA. */ 15434- 15435-#define TC_OPENRISC 15436- 15437-#define LISTING_HEADER "OpenRISC GAS " 15438- 15439-/* The target BFD architecture. */ 15440-#define TARGET_ARCH bfd_arch_openrisc 15441- 15442-extern unsigned long openrisc_machine; 15443-#define TARGET_MACH (openrisc_machine) 15444- 15445-#define TARGET_FORMAT "elf32-openrisc" 15446-#define TARGET_BYTES_BIG_ENDIAN 1 15447- 15448-extern const char openrisc_comment_chars []; 15449-#define tc_comment_chars openrisc_comment_chars 15450- 15451-/* Permit temporary numeric labels. */ 15452-#define LOCAL_LABELS_FB 1 15453- 15454-#define DIFF_EXPR_OK 1 /* .-foo gets turned into PC relative relocs */ 15455- 15456-/* We don't need to handle .word strangely. */ 15457-#define WORKING_DOT_WORD 15458- 15459-/* Values passed to md_apply_fix don't include the symbol value. */ 15460-#define MD_APPLY_SYM_VALUE(FIX) 0 15461- 15462-#define md_apply_fix gas_cgen_md_apply_fix 15463- 15464-extern bfd_boolean openrisc_fix_adjustable (struct fix *); 15465-#define tc_fix_adjustable(FIX) openrisc_fix_adjustable (FIX) 15466- 15467-#define tc_gen_reloc gas_cgen_tc_gen_reloc 15468- 15469-/* Call md_pcrel_from_section(), not md_pcrel_from(). */ 15470-extern long md_pcrel_from_section (struct fix *, segT); 15471-#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC) 15472- 15473-/* For 8 vs 16 vs 32 bit branch selection. */ 15474-extern const struct relax_type md_relax_table[]; 15475-#define TC_GENERIC_RELAX_TABLE md_relax_table 15476diff -rNU3 dist.orig/gas/config/tc-or1k.c dist/gas/config/tc-or1k.c 15477--- dist.orig/gas/config/tc-or1k.c 1970-01-01 01:00:00.000000000 +0100 15478+++ dist/gas/config/tc-or1k.c 2015-10-18 13:11:13.000000000 +0200 15479@@ -0,0 +1,362 @@ 15480+/* tc-or1k.c -- Assembler for the OpenRISC family. 15481+ Copyright 2001-2014 Free Software Foundation. 15482+ Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 15483+ 15484+ This file is part of GAS, the GNU Assembler. 15485+ 15486+ GAS is free software; you can redistribute it and/or modify 15487+ it under the terms of the GNU General Public License as published by 15488+ the Free Software Foundation; either version 3, or (at your option) 15489+ any later version. 15490+ 15491+ GAS is distributed in the hope that it will be useful, 15492+ but WITHOUT ANY WARRANTY; without even the implied warranty of 15493+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15494+ GNU General Public License for more details. 15495+ 15496+ You should have received a copy of the GNU General Public License 15497+ along with this program; if not, see <http://www.gnu.org/licenses/> */ 15498+#include "as.h" 15499+#include "safe-ctype.h" 15500+#include "subsegs.h" 15501+#include "symcat.h" 15502+#include "opcodes/or1k-desc.h" 15503+#include "opcodes/or1k-opc.h" 15504+#include "cgen.h" 15505+#include "elf/or1k.h" 15506+#include "dw2gencfi.h" 15507+ 15508+/* Structure to hold all of the different components describing 15509+ an individual instruction. */ 15510+ 15511+typedef struct 15512+{ 15513+ const CGEN_INSN * insn; 15514+ const CGEN_INSN * orig_insn; 15515+ CGEN_FIELDS fields; 15516+#if CGEN_INT_INSN_P 15517+ CGEN_INSN_INT buffer [1]; 15518+#define INSN_VALUE(buf) (*(buf)) 15519+#else 15520+ unsigned char buffer [CGEN_MAX_INSN_SIZE]; 15521+#define INSN_VALUE(buf) (buf) 15522+#endif 15523+ char * addr; 15524+ fragS * frag; 15525+ int num_fixups; 15526+ fixS * fixups [GAS_CGEN_MAX_FIXUPS]; 15527+ int indices [MAX_OPERAND_INSTANCES]; 15528+} 15529+or1k_insn; 15530+ 15531+const char comment_chars[] = "#"; 15532+const char line_comment_chars[] = "#"; 15533+const char line_separator_chars[] = ";"; 15534+const char EXP_CHARS[] = "eE"; 15535+const char FLT_CHARS[] = "dD"; 15536+ 15537+#define OR1K_SHORTOPTS "m:" 15538+const char * md_shortopts = OR1K_SHORTOPTS; 15539+ 15540+struct option md_longopts[] = 15541+{ 15542+ {NULL, no_argument, NULL, 0} 15543+}; 15544+size_t md_longopts_size = sizeof (md_longopts); 15545+ 15546+unsigned long or1k_machine = 0; /* default */ 15547+ 15548+int 15549+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED) 15550+{ 15551+ return 0; 15552+} 15553+ 15554+void 15555+md_show_usage (FILE * stream ATTRIBUTE_UNUSED) 15556+{ 15557+} 15558+ 15559+static void 15560+ignore_pseudo (int val ATTRIBUTE_UNUSED) 15561+{ 15562+ discard_rest_of_line (); 15563+} 15564+ 15565+static bfd_boolean nodelay = FALSE; 15566+static void 15567+s_nodelay (int val ATTRIBUTE_UNUSED) 15568+{ 15569+ nodelay = TRUE; 15570+} 15571+ 15572+const char or1k_comment_chars [] = ";#"; 15573+ 15574+/* The target specific pseudo-ops which we support. */ 15575+const pseudo_typeS md_pseudo_table[] = 15576+{ 15577+ { "align", s_align_bytes, 0 }, 15578+ { "word", cons, 4 }, 15579+ { "proc", ignore_pseudo, 0 }, 15580+ { "endproc", ignore_pseudo, 0 }, 15581+ { "nodelay", s_nodelay, 0 }, 15582+ { NULL, NULL, 0 } 15583+}; 15584+ 15585+ 15586+void 15587+md_begin (void) 15588+{ 15589+ /* Initialize the `cgen' interface. */ 15590+ 15591+ /* Set the machine number and endian. */ 15592+ gas_cgen_cpu_desc = or1k_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, 15593+ CGEN_CPU_OPEN_ENDIAN, 15594+ CGEN_ENDIAN_BIG, 15595+ CGEN_CPU_OPEN_END); 15596+ or1k_cgen_init_asm (gas_cgen_cpu_desc); 15597+ 15598+ /* This is a callback from cgen to gas to parse operands. */ 15599+ cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); 15600+} 15601+ 15602+void 15603+md_assemble (char * str) 15604+{ 15605+ static int last_insn_had_delay_slot = 0; 15606+ or1k_insn insn; 15607+ char * errmsg; 15608+ 15609+ /* Initialize GAS's cgen interface for a new instruction. */ 15610+ gas_cgen_init_parse (); 15611+ 15612+ insn.insn = or1k_cgen_assemble_insn 15613+ (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); 15614+ 15615+ if (!insn.insn) 15616+ { 15617+ as_bad ("%s", errmsg); 15618+ return; 15619+ } 15620+ 15621+ /* Doesn't really matter what we pass for RELAX_P here. */ 15622+ gas_cgen_finish_insn (insn.insn, insn.buffer, 15623+ CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); 15624+ 15625+ last_insn_had_delay_slot 15626+ = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); 15627+ (void) last_insn_had_delay_slot; 15628+} 15629+ 15630+ 15631+/* The syntax in the manual says constants begin with '#'. 15632+ We just ignore it. */ 15633+ 15634+void 15635+md_operand (expressionS * expressionP) 15636+{ 15637+ if (* input_line_pointer == '#') 15638+ { 15639+ input_line_pointer ++; 15640+ expression (expressionP); 15641+ } 15642+} 15643+ 15644+valueT 15645+md_section_align (segT segment, valueT size) 15646+{ 15647+ int align = bfd_get_section_alignment (stdoutput, segment); 15648+ return ((size + (1 << align) - 1) & (-1 << align)); 15649+} 15650+ 15651+symbolS * 15652+md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 15653+{ 15654+ return 0; 15655+} 15656+ 15657+ 15658+/* Interface to relax_segment. */ 15659+ 15660+const relax_typeS md_relax_table[] = 15661+{ 15662+/* The fields are: 15663+ 1) most positive reach of this state, 15664+ 2) most negative reach of this state, 15665+ 3) how many bytes this mode will add to the size of the current frag 15666+ 4) which index into the table to try if we can't fit into this one. */ 15667+ 15668+ /* The first entry must be unused because an `rlx_more' value of zero ends 15669+ each list. */ 15670+ {1, 1, 0, 0}, 15671+ 15672+ /* The displacement used by GAS is from the end of the 4 byte insn, 15673+ so we subtract 4 from the following. */ 15674+ {(((1 << 25) - 1) << 2) - 4, -(1 << 25) - 4, 0, 0}, 15675+}; 15676+ 15677+int 15678+md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED) 15679+{ 15680+ return md_relax_table[fragP->fr_subtype].rlx_length; 15681+} 15682+ 15683+/* *fragP has been relaxed to its final size, and now needs to have 15684+ the bytes inside it modified to conform to the new size. 15685+ 15686+ Called after relaxation is finished. 15687+ fragP->fr_type == rs_machine_dependent. 15688+ fragP->fr_subtype is the subtype of what the address relaxed to. */ 15689+ 15690+void 15691+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, 15692+ segT sec ATTRIBUTE_UNUSED, 15693+ fragS * fragP ATTRIBUTE_UNUSED) 15694+{ 15695+ /* FIXME */ 15696+} 15697+ 15698+ 15699+/* Functions concerning relocs. */ 15700+ 15701+/* The location from which a PC relative jump should be calculated, 15702+ given a PC relative reloc. */ 15703+ 15704+long 15705+md_pcrel_from_section (fixS * fixP, segT sec) 15706+{ 15707+ if (fixP->fx_addsy != (symbolS *) NULL 15708+ && (! S_IS_DEFINED (fixP->fx_addsy) 15709+ || (S_GET_SEGMENT (fixP->fx_addsy) != sec) 15710+ || S_IS_EXTERNAL (fixP->fx_addsy) 15711+ || S_IS_WEAK (fixP->fx_addsy))) 15712+ { 15713+ /* The symbol is undefined (or is defined but not in this section). 15714+ Let the linker figure it out. */ 15715+ return 0; 15716+ } 15717+ 15718+ return fixP->fx_frag->fr_address + fixP->fx_where; 15719+} 15720+ 15721+ 15722+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. 15723+ Returns BFD_RELOC_NONE if no reloc type can be found. 15724+ *FIXP may be modified if desired. */ 15725+ 15726+bfd_reloc_code_real_type 15727+md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, 15728+ const CGEN_OPERAND * operand, 15729+ fixS * fixP) 15730+{ 15731+ if (fixP->fx_cgen.opinfo) 15732+ return fixP->fx_cgen.opinfo; 15733+ 15734+ switch (operand->type) 15735+ { 15736+ case OR1K_OPERAND_DISP26: 15737+ fixP->fx_pcrel = 1; 15738+ return BFD_RELOC_OR1K_REL_26; 15739+ 15740+ default: /* avoid -Wall warning */ 15741+ return BFD_RELOC_NONE; 15742+ } 15743+} 15744+ 15745+/* Write a value out to the object file, using the appropriate endianness. */ 15746+ 15747+void 15748+md_number_to_chars (char * buf, valueT val, int n) 15749+{ 15750+ number_to_chars_bigendian (buf, val, n); 15751+} 15752+ 15753+/* Turn a string in input_line_pointer into a floating point constant of type 15754+ type, and store the appropriate bytes in *litP. The number of LITTLENUMS 15755+ emitted is stored in *sizeP . An error message is returned, or NULL on OK. */ 15756+ 15757+/* Equal to MAX_PRECISION in atof-ieee.c. */ 15758+#define MAX_LITTLENUMS 6 15759+ 15760+char * 15761+md_atof (int type, char * litP, int * sizeP) 15762+{ 15763+ return ieee_md_atof (type, litP, sizeP, TRUE); 15764+} 15765+ 15766+bfd_boolean 15767+or1k_fix_adjustable (fixS * fixP) 15768+{ 15769+ /* We need the symbol name for the VTABLE entries. */ 15770+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 15771+ || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 15772+ return FALSE; 15773+ 15774+ return TRUE; 15775+} 15776+ 15777+#define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 15778+ 15779+arelent * 15780+tc_gen_reloc (asection *sec, fixS *fx) 15781+{ 15782+ bfd_reloc_code_real_type code = fx->fx_r_type; 15783+ 15784+ if (fx->fx_addsy != NULL 15785+ && strcmp (S_GET_NAME (fx->fx_addsy), GOT_NAME) == 0 15786+ && (code == BFD_RELOC_OR1K_GOTPC_HI16 15787+ || code == BFD_RELOC_OR1K_GOTPC_LO16)) 15788+ { 15789+ arelent * reloc; 15790+ 15791+ reloc = xmalloc (sizeof (* reloc)); 15792+ reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 15793+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy); 15794+ reloc->address = fx->fx_frag->fr_address + fx->fx_where; 15795+ reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type); 15796+ reloc->addend = fx->fx_offset; 15797+ return reloc; 15798+ } 15799+ 15800+ return gas_cgen_tc_gen_reloc (sec, fx); 15801+} 15802+ 15803+void 15804+or1k_apply_fix (struct fix *f, valueT *t, segT s) 15805+{ 15806+ gas_cgen_md_apply_fix (f, t, s); 15807+ 15808+ switch (f->fx_r_type) 15809+ { 15810+ case BFD_RELOC_OR1K_TLS_GD_HI16: 15811+ case BFD_RELOC_OR1K_TLS_GD_LO16: 15812+ case BFD_RELOC_OR1K_TLS_LDM_HI16: 15813+ case BFD_RELOC_OR1K_TLS_LDM_LO16: 15814+ case BFD_RELOC_OR1K_TLS_LDO_HI16: 15815+ case BFD_RELOC_OR1K_TLS_LDO_LO16: 15816+ case BFD_RELOC_OR1K_TLS_IE_HI16: 15817+ case BFD_RELOC_OR1K_TLS_IE_LO16: 15818+ case BFD_RELOC_OR1K_TLS_LE_HI16: 15819+ case BFD_RELOC_OR1K_TLS_LE_LO16: 15820+ S_SET_THREAD_LOCAL (f->fx_addsy); 15821+ break; 15822+ default: 15823+ break; 15824+ } 15825+} 15826+ 15827+void 15828+or1k_elf_final_processing (void) 15829+{ 15830+ if (nodelay) 15831+ elf_elfheader (stdoutput)->e_flags |= EF_OR1K_NODELAY; 15832+} 15833+ 15834+/* Standard calling conventions leave the CFA at SP on entry. */ 15835+ 15836+void 15837+or1k_cfi_frame_initial_instructions (void) 15838+{ 15839+ cfi_add_CFA_def_cfa_register (1); 15840+} 15841+ 15842diff -rNU3 dist.orig/gas/config/tc-or1k.h dist/gas/config/tc-or1k.h 15843--- dist.orig/gas/config/tc-or1k.h 1970-01-01 01:00:00.000000000 +0100 15844+++ dist/gas/config/tc-or1k.h 2015-10-18 13:11:13.000000000 +0200 15845@@ -0,0 +1,79 @@ 15846+/* tc-or1k.h -- Header file for tc-or1k.c. 15847+ Copyright 2001-2014 Free Software Foundation, Inc. 15848+ 15849+ This file is part of GAS, the GNU Assembler. 15850+ 15851+ GAS is free software; you can redistribute it and/or modify 15852+ it under the terms of the GNU General Public License as published by 15853+ the Free Software Foundation; either version 3, or (at your option) 15854+ any later version. 15855+ 15856+ GAS is distributed in the hope that it will be useful, 15857+ but WITHOUT ANY WARRANTY; without even the implied warranty of 15858+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15859+ GNU General Public License for more details. 15860+ 15861+ You should have received a copy of the GNU General Public License 15862+ along with this program; if not, see <http://www.gnu.org/licenses/> */ 15863+ 15864+#define TC_OR1K 15865+ 15866+#define LISTING_HEADER "Or1k GAS " 15867+ 15868+/* The target BFD architecture. */ 15869+#define TARGET_ARCH bfd_arch_or1k 15870+ 15871+extern unsigned long or1k_machine; 15872+#define TARGET_MACH (or1k_machine) 15873+ 15874+#define TARGET_FORMAT "elf32-or1k" 15875+#define TARGET_BYTES_BIG_ENDIAN 1 15876+ 15877+extern const char or1k_comment_chars []; 15878+#define tc_comment_chars or1k_comment_chars 15879+ 15880+/* Permit temporary numeric labels. */ 15881+#define LOCAL_LABELS_FB 1 15882+ 15883+#define DIFF_EXPR_OK 1 /* .-foo gets turned into PC relative relocs. */ 15884+ 15885+/* We don't need to handle .word strangely. */ 15886+#define WORKING_DOT_WORD 15887+ 15888+/* Values passed to md_apply_fix don't include the symbol value. */ 15889+#define MD_APPLY_SYM_VALUE(FIX) 0 15890+ 15891+#define md_apply_fix or1k_apply_fix 15892+extern void or1k_apply_fix (struct fix *, valueT *, segT); 15893+ 15894+extern bfd_boolean or1k_fix_adjustable (struct fix *); 15895+#define tc_fix_adjustable(FIX) or1k_fix_adjustable (FIX) 15896+ 15897+/* Call md_pcrel_from_section(), not md_pcrel_from(). */ 15898+extern long md_pcrel_from_section (struct fix *, segT); 15899+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC) 15900+ 15901+/* For 8 vs 16 vs 32 bit branch selection. */ 15902+extern const struct relax_type md_relax_table[]; 15903+#define TC_GENERIC_RELAX_TABLE md_relax_table 15904+ 15905+#define GAS_CGEN_PCREL_R_TYPE(r_type) gas_cgen_pcrel_r_type(r_type) 15906+ 15907+#define elf_tc_final_processing or1k_elf_final_processing 15908+void or1k_elf_final_processing (void); 15909+ 15910+/* Enable cfi directives. */ 15911+#define TARGET_USE_CFIPOP 1 15912+ 15913+/* Stack grows to lower addresses and wants 4 byte boundary. */ 15914+#define DWARF2_CIE_DATA_ALIGNMENT -4 15915+ 15916+/* Define the column that represents the PC. */ 15917+#define DWARF2_DEFAULT_RETURN_COLUMN 9 15918+ 15919+/* or1k instructions are 4 bytes long. */ 15920+#define DWARF2_LINE_MIN_INSN_LENGTH 4 15921+ 15922+#define tc_cfi_frame_initial_instructions \ 15923+ or1k_cfi_frame_initial_instructions 15924+extern void or1k_cfi_frame_initial_instructions (void); 15925diff -rNU3 dist.orig/gas/config/tc-or32.c dist/gas/config/tc-or32.c 15926--- dist.orig/gas/config/tc-or32.c 2012-05-17 17:13:16.000000000 +0200 15927+++ dist/gas/config/tc-or32.c 1970-01-01 01:00:00.000000000 +0100 15928@@ -1,967 +0,0 @@ 15929-/* Assembly backend for the OpenRISC 1000. 15930- Copyright (C) 2002, 2003, 2005, 2007, 2009, 2010, 2012 15931- Free Software Foundation, Inc. 15932- Contributed by Damjan Lampret <lampret@opencores.org>. 15933- Modified bu Johan Rydberg, <johan.rydberg@netinsight.se>. 15934- Based upon a29k port. 15935- 15936- This file is part of GAS, the GNU Assembler. 15937- 15938- GAS is free software; you can redistribute it and/or modify 15939- it under the terms of the GNU General Public License as published by 15940- the Free Software Foundation; either version 3, or (at your option) 15941- any later version. 15942- 15943- GAS is distributed in the hope that it will be useful, 15944- but WITHOUT ANY WARRANTY; without even the implied warranty of 15945- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15946- GNU General Public License for more details. 15947- 15948- You should have received a copy of the GNU General Public License 15949- along with GAS; see the file COPYING. If not, write to 15950- the Free Software Foundation, 51 Franklin Street - Fifth Floor, 15951- Boston, MA 02110-1301, USA. */ 15952- 15953-/* tc-a29k.c used as a template. */ 15954- 15955-#include "as.h" 15956-#include "safe-ctype.h" 15957-#include "opcode/or32.h" 15958-#include "elf/or32.h" 15959- 15960-#define DEBUG 0 15961- 15962-#ifndef REGISTER_PREFIX 15963-#define REGISTER_PREFIX '%' 15964-#endif 15965- 15966-/* Make it easier to clone this machine desc into another one. */ 15967-#define machine_opcode or32_opcode 15968-#define machine_opcodes or32_opcodes 15969-#define machine_ip or32_ip 15970-#define machine_it or32_it 15971- 15972-/* Handle of the OPCODE hash table. */ 15973-static struct hash_control *op_hash = NULL; 15974- 15975-struct machine_it 15976-{ 15977- char * error; 15978- unsigned long opcode; 15979- struct nlist * nlistp; 15980- expressionS exp; 15981- int pcrel; 15982- int reloc_offset; /* Offset of reloc within insn. */ 15983- int reloc; 15984-} 15985-the_insn; 15986- 15987-const pseudo_typeS md_pseudo_table[] = 15988-{ 15989- {"align", s_align_bytes, 4 }, 15990- {"space", s_space, 0 }, 15991- {"cputype", s_ignore, 0 }, 15992- {"reg", s_lsym, 0 }, /* Register equate, same as equ. */ 15993- {"sect", s_ignore, 0 }, /* Creation of coff sections. */ 15994- {"proc", s_ignore, 0 }, /* Start of a function. */ 15995- {"endproc", s_ignore, 0 }, /* Function end. */ 15996- {"word", cons, 4 }, 15997- {NULL, 0, 0 }, 15998-}; 15999- 16000-int md_short_jump_size = 4; 16001-int md_long_jump_size = 4; 16002- 16003-/* This array holds the chars that always start a comment. 16004- If the pre-processor is disabled, these aren't very useful. */ 16005-const char comment_chars[] = "#"; 16006- 16007-/* This array holds the chars that only start a comment at the beginning of 16008- a line. If the line seems to have the form '# 123 filename' 16009- .line and .file directives will appear in the pre-processed output. */ 16010-/* Note that input_file.c hand checks for '#' at the beginning of the 16011- first line of the input file. This is because the compiler outputs 16012- #NO_APP at the beginning of its output. */ 16013-/* Also note that comments like this one will always work. */ 16014-const char line_comment_chars[] = "#"; 16015- 16016-/* We needed an unused char for line separation to work around the 16017- lack of macros, using sed and such. */ 16018-const char line_separator_chars[] = ";"; 16019- 16020-/* Chars that can be used to separate mant from exp in floating point nums. */ 16021-const char EXP_CHARS[] = "eE"; 16022- 16023-/* Chars that mean this number is a floating point constant. 16024- As in 0f12.456 16025- or 0d1.2345e12. */ 16026-const char FLT_CHARS[] = "rRsSfFdDxXpP"; 16027- 16028-/* "l.jalr r9" precalculated opcode. */ 16029-static unsigned long jalr_r9_opcode; 16030- 16031-static void machine_ip (char *); 16032- 16033- 16034-/* Set bits in machine opcode according to insn->encoding 16035- description and passed operand. */ 16036- 16037-static void 16038-encode (const struct machine_opcode *insn, 16039- unsigned long *opcode, 16040- signed long param_val, 16041- char param_ch) 16042-{ 16043- int opc_pos = 0; 16044- int param_pos = 0; 16045- char *enc; 16046- 16047-#if DEBUG 16048- printf (" encode: opcode=%.8lx param_val=%.8lx abs=%.8lx param_ch=%c\n", 16049- *opcode, param_val, abs (param_val), param_ch); 16050-#endif 16051- for (enc = insn->encoding; *enc != '\0'; enc++) 16052- if (*enc == param_ch) 16053- { 16054- if (enc - 2 >= insn->encoding && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) 16055- continue; 16056- else 16057- param_pos ++; 16058- } 16059- 16060- opc_pos = 32; 16061- 16062- for (enc = insn->encoding; *enc != '\0';) 16063- { 16064- if ((*enc == '0') && (*(enc + 1) == 'x')) 16065- { 16066- int tmp = strtol (enc, NULL, 16); 16067- 16068- opc_pos -= 4; 16069- *opcode |= tmp << opc_pos; 16070- enc += 3; 16071- } 16072- else if ((*enc == '0') || (*enc == '-')) 16073- { 16074- opc_pos--; 16075- enc++; 16076- } 16077- else if (*enc == '1') 16078- { 16079- opc_pos--; 16080- *opcode |= 1 << opc_pos; 16081- enc++; 16082- } 16083- else if (*enc == param_ch) 16084- { 16085- opc_pos--; 16086- param_pos--; 16087- *opcode |= ((param_val >> param_pos) & 0x1) << opc_pos; 16088- enc++; 16089- } 16090- else if (ISALPHA (*enc)) 16091- { 16092- opc_pos--; 16093- enc++; 16094- } 16095- else 16096- enc++; 16097- } 16098- 16099-#if DEBUG 16100- printf (" opcode=%.8lx\n", *opcode); 16101-#endif 16102-} 16103- 16104-/* This function is called once, at assembler startup time. It should 16105- set up all the tables, etc., that the MD part of the assembler will 16106- need. */ 16107- 16108-void 16109-md_begin (void) 16110-{ 16111- const char *retval = NULL; 16112- int lose = 0; 16113- int skipnext = 0; 16114- unsigned int i; 16115- 16116- /* Hash up all the opcodes for fast use later. */ 16117- op_hash = hash_new (); 16118- 16119- for (i = 0; i < or32_num_opcodes; i++) 16120- { 16121- const char *name = machine_opcodes[i].name; 16122- 16123- if (skipnext) 16124- { 16125- skipnext = 0; 16126- continue; 16127- } 16128- 16129- retval = hash_insert (op_hash, name, (void *) &machine_opcodes[i]); 16130- if (retval != NULL) 16131- { 16132- fprintf (stderr, "internal error: can't hash `%s': %s\n", 16133- machine_opcodes[i].name, retval); 16134- lose = 1; 16135- } 16136- } 16137- 16138- if (lose) 16139- as_fatal (_("Broken assembler. No assembly attempted.")); 16140- 16141- encode (&machine_opcodes[insn_index ("l.jalr")], &jalr_r9_opcode, 9, 'B'); 16142-} 16143- 16144-/* Returns non zero if instruction is to be used. */ 16145- 16146-static int 16147-check_invalid_opcode (unsigned long opcode) 16148-{ 16149- return opcode == jalr_r9_opcode; 16150-} 16151- 16152-/* Assemble a single instruction. Its label has already been handled 16153- by the generic front end. We just parse opcode and operands, and 16154- produce the bytes of data and relocation. */ 16155- 16156-void 16157-md_assemble (char *str) 16158-{ 16159- char *toP; 16160- 16161-#if DEBUG 16162- printf ("NEW INSTRUCTION\n"); 16163-#endif 16164- 16165- know (str); 16166- machine_ip (str); 16167- toP = frag_more (4); 16168- 16169- /* Put out the opcode. */ 16170- md_number_to_chars (toP, the_insn.opcode, 4); 16171- 16172- /* Put out the symbol-dependent stuff. */ 16173- if (the_insn.reloc != BFD_RELOC_NONE) 16174- { 16175- fix_new_exp (frag_now, 16176- (toP - frag_now->fr_literal + the_insn.reloc_offset), 16177- 4, /* size */ 16178- &the_insn.exp, 16179- the_insn.pcrel, 16180- the_insn.reloc); 16181- } 16182-} 16183- 16184-/* This is true of the we have issued a "lo(" or "hi"(. */ 16185-static int waiting_for_shift = 0; 16186- 16187-static int mask_or_shift = 0; 16188- 16189-static char * 16190-parse_operand (char *s, expressionS *operandp, int opt) 16191-{ 16192- char *save = input_line_pointer; 16193- char *new_pointer; 16194- 16195-#if DEBUG 16196- printf (" PROCESS NEW OPERAND(%s) == %c (%d)\n", s, opt ? opt : '!', opt); 16197-#endif 16198- 16199- input_line_pointer = s; 16200- 16201- if (strncasecmp (s, "HI(", 3) == 0) 16202- { 16203- waiting_for_shift = 1; 16204- mask_or_shift = BFD_RELOC_HI16; 16205- 16206- input_line_pointer += 3; 16207- } 16208- else if (strncasecmp (s, "LO(", 3) == 0) 16209- { 16210- mask_or_shift = BFD_RELOC_LO16; 16211- 16212- input_line_pointer += 3; 16213- } 16214- else 16215- mask_or_shift = 0; 16216- 16217- if ((*s == '(') && (*(s+1) == 'r')) 16218- s++; 16219- 16220- if ((*s == 'r') && ISDIGIT (*(s + 1))) 16221- { 16222- operandp->X_add_number = strtol (s + 1, NULL, 10); 16223- operandp->X_op = O_register; 16224- for (; (*s != ',') && (*s != '\0');) 16225- s++; 16226- input_line_pointer = save; 16227- return s; 16228- } 16229- 16230- expression (operandp); 16231- 16232- if (operandp->X_op == O_absent) 16233- { 16234- if (! opt) 16235- as_bad (_("missing operand")); 16236- else 16237- { 16238- operandp->X_add_number = 0; 16239- operandp->X_op = O_constant; 16240- } 16241- } 16242- 16243- new_pointer = input_line_pointer; 16244- input_line_pointer = save; 16245- 16246-#if DEBUG 16247- printf (" %s=parse_operand(%s): operandp->X_op = %u\n", new_pointer, s, 16248- operandp->X_op); 16249-#endif 16250- 16251- return new_pointer; 16252-} 16253- 16254-/* Instruction parsing. Takes a string containing the opcode. 16255- Operands are at input_line_pointer. Output is in the_insn. 16256- Warnings or errors are generated. */ 16257- 16258-static void 16259-machine_ip (char *str) 16260-{ 16261- char *s; 16262- const char *args; 16263- const struct machine_opcode *insn; 16264- unsigned long opcode; 16265- expressionS the_operand; 16266- expressionS *operand = &the_operand; 16267- unsigned int regno; 16268- int reloc = BFD_RELOC_NONE; 16269- 16270-#if DEBUG 16271- printf ("machine_ip(%s)\n", str); 16272-#endif 16273- 16274- s = str; 16275- for (; ISALNUM (*s) || *s == '.'; ++s) 16276- if (ISUPPER (*s)) 16277- *s = TOLOWER (*s); 16278- 16279- switch (*s) 16280- { 16281- case '\0': 16282- break; 16283- 16284- case ' ': /* FIXME-SOMEDAY more whitespace. */ 16285- *s++ = '\0'; 16286- break; 16287- 16288- default: 16289- as_bad (_("unknown opcode1: `%s'"), str); 16290- return; 16291- } 16292- 16293- if ((insn = (struct machine_opcode *) hash_find (op_hash, str)) == NULL) 16294- { 16295- as_bad (_("unknown opcode2 `%s'."), str); 16296- return; 16297- } 16298- 16299- opcode = 0; 16300- memset (&the_insn, '\0', sizeof (the_insn)); 16301- the_insn.reloc = BFD_RELOC_NONE; 16302- 16303- reloc = BFD_RELOC_NONE; 16304- 16305- /* Build the opcode, checking as we go to make sure that the 16306- operands match. 16307- 16308- If an operand matches, we modify the_insn or opcode appropriately, 16309- and do a "continue". If an operand fails to match, we "break". */ 16310- if (insn->args[0] != '\0') 16311- /* Prime the pump. */ 16312- s = parse_operand (s, operand, insn->args[0] == 'I'); 16313- 16314- for (args = insn->args;; ++args) 16315- { 16316-#if DEBUG 16317- printf (" args = %s\n", args); 16318-#endif 16319- switch (*args) 16320- { 16321- case '\0': /* End of args. */ 16322- /* We have have 0 args, do the bazoooka! */ 16323- if (args == insn->args) 16324- encode (insn, &opcode, 0, 0); 16325- 16326- if (*s == '\0') 16327- { 16328- /* We are truly done. */ 16329- the_insn.opcode = opcode; 16330- if (check_invalid_opcode (opcode)) 16331- as_bad (_("instruction not allowed: %s"), str); 16332- return; 16333- } 16334- as_bad (_("too many operands: %s"), s); 16335- break; 16336- 16337- case ',': /* Must match a comma. */ 16338- if (*s++ == ',') 16339- { 16340- reloc = BFD_RELOC_NONE; 16341- 16342- /* Parse next operand. */ 16343- s = parse_operand (s, operand, args[1] == 'I'); 16344-#if DEBUG 16345- printf (" ',' case: operand->X_add_number = %d, *args = %s, *s = %s\n", 16346- operand->X_add_number, args, s); 16347-#endif 16348- continue; 16349- } 16350- break; 16351- 16352- case '(': /* Must match a (. */ 16353- s = parse_operand (s, operand, args[1] == 'I'); 16354- continue; 16355- 16356- case ')': /* Must match a ). */ 16357- continue; 16358- 16359- case 'r': /* A general register. */ 16360- args++; 16361- 16362- if (operand->X_op != O_register) 16363- break; /* Only registers. */ 16364- 16365- know (operand->X_add_symbol == 0); 16366- know (operand->X_op_symbol == 0); 16367- regno = operand->X_add_number; 16368- encode (insn, &opcode, regno, *args); 16369-#if DEBUG 16370- printf (" r: operand->X_op = %d\n", operand->X_op); 16371-#endif 16372- continue; 16373- 16374- default: 16375- /* if (! ISALPHA (*args)) 16376- break; */ /* Only immediate values. */ 16377- 16378- if (mask_or_shift) 16379- { 16380-#if DEBUG 16381- printf ("mask_or_shift = %d\n", mask_or_shift); 16382-#endif 16383- reloc = mask_or_shift; 16384- } 16385- mask_or_shift = 0; 16386- 16387- if (strncasecmp (args, "LO(", 3) == 0) 16388- { 16389-#if DEBUG 16390- printf ("reloc_const\n"); 16391-#endif 16392- reloc = BFD_RELOC_LO16; 16393- } 16394- else if (strncasecmp (args, "HI(", 3) == 0) 16395- { 16396-#if DEBUG 16397- printf ("reloc_consth\n"); 16398-#endif 16399- reloc = BFD_RELOC_HI16; 16400- } 16401- 16402- if (*s == '(') 16403- operand->X_op = O_constant; 16404- else if (*s == ')') 16405- s += 1; 16406-#if DEBUG 16407- printf (" default case: operand->X_add_number = %d, *args = %s, *s = %s\n", operand->X_add_number, args, s); 16408-#endif 16409- if (operand->X_op == O_constant) 16410- { 16411- if (reloc == BFD_RELOC_NONE) 16412- { 16413- bfd_vma v, mask; 16414- 16415- mask = 0x3ffffff; 16416- v = abs (operand->X_add_number) & ~ mask; 16417- if (v) 16418- as_bad (_("call/jmp target out of range (1)")); 16419- } 16420- 16421- if (reloc == BFD_RELOC_HI16) 16422- operand->X_add_number = ((operand->X_add_number >> 16) & 0xffff); 16423- 16424- the_insn.pcrel = 0; 16425- encode (insn, &opcode, operand->X_add_number, *args); 16426- /* the_insn.reloc = BFD_RELOC_NONE; */ 16427- continue; 16428- } 16429- 16430- if (reloc == BFD_RELOC_NONE) 16431- the_insn.reloc = BFD_RELOC_32_GOT_PCREL; 16432- else 16433- the_insn.reloc = reloc; 16434- 16435- /* the_insn.reloc = insn->reloc; */ 16436-#if DEBUG 16437- printf (" reloc sym=%d\n", the_insn.reloc); 16438- printf (" BFD_RELOC_NONE=%d\n", BFD_RELOC_NONE); 16439-#endif 16440- the_insn.exp = *operand; 16441- 16442- /* the_insn.reloc_offset = 1; */ 16443- the_insn.pcrel = 1; /* Assume PC-relative jump. */ 16444- 16445- /* FIXME-SOON, Do we figure out whether abs later, after 16446- know sym val? */ 16447- if (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_HI16) 16448- the_insn.pcrel = 0; 16449- 16450- encode (insn, &opcode, operand->X_add_number, *args); 16451- continue; 16452- } 16453- 16454- /* Types or values of args don't match. */ 16455- as_bad (_("invalid operands")); 16456- return; 16457- } 16458-} 16459- 16460-char * 16461-md_atof (int type, char * litP, int * sizeP) 16462-{ 16463- return ieee_md_atof (type, litP, sizeP, TRUE); 16464-} 16465- 16466-/* Write out big-endian. */ 16467- 16468-void 16469-md_number_to_chars (char *buf, valueT val, int n) 16470-{ 16471- number_to_chars_bigendian (buf, val, n); 16472-} 16473- 16474-void 16475-md_apply_fix (fixS * fixP, valueT * val, segT seg ATTRIBUTE_UNUSED) 16476-{ 16477- char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 16478- long t_val; 16479- 16480- t_val = (long) *val; 16481- 16482-#if DEBUG 16483- printf ("md_apply_fix val:%x\n", t_val); 16484-#endif 16485- 16486- fixP->fx_addnumber = t_val; /* Remember value for emit_reloc. */ 16487- 16488- switch (fixP->fx_r_type) 16489- { 16490- case BFD_RELOC_32: /* XXXXXXXX pattern in a word. */ 16491-#if DEBUG 16492- printf ("reloc_const: val=%x\n", t_val); 16493-#endif 16494- buf[0] = t_val >> 24; 16495- buf[1] = t_val >> 16; 16496- buf[2] = t_val >> 8; 16497- buf[3] = t_val; 16498- break; 16499- 16500- case BFD_RELOC_16: /* XXXX0000 pattern in a word. */ 16501-#if DEBUG 16502- printf ("reloc_const: val=%x\n", t_val); 16503-#endif 16504- buf[0] = t_val >> 8; 16505- buf[1] = t_val; 16506- break; 16507- 16508- case BFD_RELOC_8: /* XX000000 pattern in a word. */ 16509-#if DEBUG 16510- printf ("reloc_const: val=%x\n", t_val); 16511-#endif 16512- buf[0] = t_val; 16513- break; 16514- 16515- case BFD_RELOC_LO16: /* 0000XXXX pattern in a word. */ 16516-#if DEBUG 16517- printf ("reloc_const: val=%x\n", t_val); 16518-#endif 16519- buf[2] = t_val >> 8; /* Holds bits 0000XXXX. */ 16520- buf[3] = t_val; 16521- break; 16522- 16523- case BFD_RELOC_HI16: /* 0000XXXX pattern in a word. */ 16524-#if DEBUG 16525- printf ("reloc_consth: val=%x\n", t_val); 16526-#endif 16527- buf[2] = t_val >> 24; /* Holds bits XXXX0000. */ 16528- buf[3] = t_val >> 16; 16529- break; 16530- 16531- case BFD_RELOC_32_GOT_PCREL: /* 0000XXXX pattern in a word. */ 16532- if (!fixP->fx_done) 16533- ; 16534- else if (fixP->fx_pcrel) 16535- { 16536- long v = t_val >> 28; 16537- 16538- if (v != 0 && v != -1) 16539- as_bad_where (fixP->fx_file, fixP->fx_line, 16540- _("call/jmp target out of range (2)")); 16541- } 16542- else 16543- /* This case was supposed to be handled in machine_ip. */ 16544- abort (); 16545- 16546- buf[0] |= (t_val >> 26) & 0x03; /* Holds bits 0FFFFFFC of address. */ 16547- buf[1] = t_val >> 18; 16548- buf[2] = t_val >> 10; 16549- buf[3] = t_val >> 2; 16550- break; 16551- 16552- case BFD_RELOC_VTABLE_INHERIT: 16553- case BFD_RELOC_VTABLE_ENTRY: 16554- fixP->fx_done = 0; 16555- break; 16556- 16557- case BFD_RELOC_NONE: 16558- default: 16559- as_bad (_("bad relocation type: 0x%02x"), fixP->fx_r_type); 16560- break; 16561- } 16562- 16563- if (fixP->fx_addsy == (symbolS *) NULL) 16564- fixP->fx_done = 1; 16565-} 16566- 16567-/* Should never be called for or32. */ 16568- 16569-void 16570-md_create_short_jump (char * ptr ATTRIBUTE_UNUSED, 16571- addressT from_addr ATTRIBUTE_UNUSED, 16572- addressT to_addr ATTRIBUTE_UNUSED, 16573- fragS * frag ATTRIBUTE_UNUSED, 16574- symbolS * to_symbol ATTRIBUTE_UNUSED) 16575-{ 16576- as_fatal ("or32_create_short_jmp\n"); 16577-} 16578- 16579-/* Should never be called for or32. */ 16580- 16581-void 16582-md_convert_frag (bfd * headers ATTRIBUTE_UNUSED, 16583- segT seg ATTRIBUTE_UNUSED, 16584- fragS * fragP ATTRIBUTE_UNUSED) 16585-{ 16586- as_fatal ("or32_convert_frag\n"); 16587-} 16588- 16589-/* Should never be called for or32. */ 16590- 16591-void 16592-md_create_long_jump (char * ptr ATTRIBUTE_UNUSED, 16593- addressT from_addr ATTRIBUTE_UNUSED, 16594- addressT to_addr ATTRIBUTE_UNUSED, 16595- fragS * frag ATTRIBUTE_UNUSED, 16596- symbolS * to_symbol ATTRIBUTE_UNUSED) 16597-{ 16598- as_fatal ("or32_create_long_jump\n"); 16599-} 16600- 16601-/* Should never be called for or32. */ 16602- 16603-int 16604-md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, 16605- segT segtype ATTRIBUTE_UNUSED) 16606-{ 16607- as_fatal ("or32_estimate_size_before_relax\n"); 16608- return 0; 16609-} 16610- 16611-/* Translate internal representation of relocation info to target format. 16612- 16613- On sparc/29k: first 4 bytes are normal unsigned long address, next three 16614- bytes are index, most sig. byte first. Byte 7 is broken up with 16615- bit 7 as external, bits 6 & 5 unused, and the lower 16616- five bits as relocation type. Next 4 bytes are long addend. */ 16617-/* Thanx and a tip of the hat to Michael Bloom, mb@ttidca.tti.com. */ 16618- 16619-#ifdef OBJ_AOUT 16620-void 16621-tc_aout_fix_to_chars (char *where, 16622- fixS *fixP, 16623- relax_addressT segment_address_in_file) 16624-{ 16625- long r_symbolnum; 16626- 16627-#if DEBUG 16628- printf ("tc_aout_fix_to_chars\n"); 16629-#endif 16630- 16631- know (fixP->fx_r_type < BFD_RELOC_NONE); 16632- know (fixP->fx_addsy != NULL); 16633- 16634- md_number_to_chars 16635- (where, 16636- fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file, 16637- 4); 16638- 16639- r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) 16640- ? S_GET_TYPE (fixP->fx_addsy) 16641- : fixP->fx_addsy->sy_number); 16642- 16643- where[4] = (r_symbolnum >> 16) & 0x0ff; 16644- where[5] = (r_symbolnum >> 8) & 0x0ff; 16645- where[6] = r_symbolnum & 0x0ff; 16646- where[7] = (((!S_IS_DEFINED (fixP->fx_addsy)) << 7) & 0x80) | (0 & 0x60) | (fixP->fx_r_type & 0x1F); 16647- 16648- /* Also easy. */ 16649- md_number_to_chars (&where[8], fixP->fx_addnumber, 4); 16650-} 16651- 16652-#endif /* OBJ_AOUT */ 16653- 16654-const char *md_shortopts = ""; 16655- 16656-struct option md_longopts[] = 16657-{ 16658- { NULL, no_argument, NULL, 0 } 16659-}; 16660-size_t md_longopts_size = sizeof (md_longopts); 16661- 16662-int 16663-md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED) 16664-{ 16665- return 0; 16666-} 16667- 16668-void 16669-md_show_usage (FILE * stream ATTRIBUTE_UNUSED) 16670-{ 16671-} 16672- 16673-/* This is called when a line is unrecognized. This is used to handle 16674- definitions of or32 style local labels. */ 16675- 16676-int 16677-or32_unrecognized_line (int c) 16678-{ 16679- int lab; 16680- char *s; 16681- 16682- if (c != '$' 16683- || ! ISDIGIT ((unsigned char) input_line_pointer[0])) 16684- return 0; 16685- 16686- s = input_line_pointer; 16687- 16688- lab = 0; 16689- while (ISDIGIT ((unsigned char) *s)) 16690- { 16691- lab = lab * 10 + *s - '0'; 16692- ++s; 16693- } 16694- 16695- if (*s != ':') 16696- /* Not a label definition. */ 16697- return 0; 16698- 16699- if (dollar_label_defined (lab)) 16700- { 16701- as_bad (_("label \"$%d\" redefined"), lab); 16702- return 0; 16703- } 16704- 16705- define_dollar_label (lab); 16706- colon (dollar_label_name (lab, 0)); 16707- input_line_pointer = s + 1; 16708- 16709- return 1; 16710-} 16711- 16712-/* Default the values of symbols known that should be "predefined". We 16713- don't bother to predefine them unless you actually use one, since there 16714- are a lot of them. */ 16715- 16716-symbolS * 16717-md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 16718-{ 16719- return NULL; 16720-} 16721- 16722-/* Parse an operand that is machine-specific. */ 16723- 16724-void 16725-md_operand (expressionS *expressionP) 16726-{ 16727-#if DEBUG 16728- printf (" md_operand(input_line_pointer = %s)\n", input_line_pointer); 16729-#endif 16730- 16731- if (input_line_pointer[0] == REGISTER_PREFIX && input_line_pointer[1] == 'r') 16732- { 16733- /* We have a numeric register expression. No biggy. */ 16734- input_line_pointer += 2; /* Skip %r */ 16735- (void) expression (expressionP); 16736- 16737- if (expressionP->X_op != O_constant 16738- || expressionP->X_add_number > 255) 16739- as_bad (_("Invalid expression after %%%%\n")); 16740- expressionP->X_op = O_register; 16741- } 16742- else if (input_line_pointer[0] == '&') 16743- { 16744- /* We are taking the 'address' of a register...this one is not 16745- in the manual, but it *is* in traps/fpsymbol.h! What they 16746- seem to want is the register number, as an absolute number. */ 16747- input_line_pointer++; /* Skip & */ 16748- (void) expression (expressionP); 16749- 16750- if (expressionP->X_op != O_register) 16751- as_bad (_("invalid register in & expression")); 16752- else 16753- expressionP->X_op = O_constant; 16754- } 16755- else if (input_line_pointer[0] == '$' 16756- && ISDIGIT ((unsigned char) input_line_pointer[1])) 16757- { 16758- long lab; 16759- char *name; 16760- symbolS *sym; 16761- 16762- /* This is a local label. */ 16763- ++input_line_pointer; 16764- lab = (long) get_absolute_expression (); 16765- 16766- if (dollar_label_defined (lab)) 16767- { 16768- name = dollar_label_name (lab, 0); 16769- sym = symbol_find (name); 16770- } 16771- else 16772- { 16773- name = dollar_label_name (lab, 1); 16774- sym = symbol_find_or_make (name); 16775- } 16776- 16777- expressionP->X_op = O_symbol; 16778- expressionP->X_add_symbol = sym; 16779- expressionP->X_add_number = 0; 16780- } 16781- else if (input_line_pointer[0] == '$') 16782- { 16783- char *s; 16784- char type; 16785- int fieldnum, fieldlimit; 16786- LITTLENUM_TYPE floatbuf[8]; 16787- 16788- /* $float(), $doubleN(), or $extendN() convert floating values 16789- to integers. */ 16790- s = input_line_pointer; 16791- 16792- ++s; 16793- 16794- fieldnum = 0; 16795- if (strncmp (s, "double", sizeof "double" - 1) == 0) 16796- { 16797- s += sizeof "double" - 1; 16798- type = 'd'; 16799- fieldlimit = 2; 16800- } 16801- else if (strncmp (s, "float", sizeof "float" - 1) == 0) 16802- { 16803- s += sizeof "float" - 1; 16804- type = 'f'; 16805- fieldlimit = 1; 16806- } 16807- else if (strncmp (s, "extend", sizeof "extend" - 1) == 0) 16808- { 16809- s += sizeof "extend" - 1; 16810- type = 'x'; 16811- fieldlimit = 4; 16812- } 16813- else 16814- return; 16815- 16816- if (ISDIGIT (*s)) 16817- { 16818- fieldnum = *s - '0'; 16819- ++s; 16820- } 16821- if (fieldnum >= fieldlimit) 16822- return; 16823- 16824- SKIP_WHITESPACE (); 16825- if (*s != '(') 16826- return; 16827- ++s; 16828- SKIP_WHITESPACE (); 16829- 16830- s = atof_ieee (s, type, floatbuf); 16831- if (s == NULL) 16832- return; 16833- s = s; 16834- 16835- SKIP_WHITESPACE (); 16836- if (*s != ')') 16837- return; 16838- ++s; 16839- SKIP_WHITESPACE (); 16840- 16841- input_line_pointer = s; 16842- expressionP->X_op = O_constant; 16843- expressionP->X_unsigned = 1; 16844- expressionP->X_add_number = ((floatbuf[fieldnum * 2] 16845- << LITTLENUM_NUMBER_OF_BITS) 16846- + floatbuf[fieldnum * 2 + 1]); 16847- } 16848-} 16849- 16850-/* Round up a section size to the appropriate boundary. */ 16851- 16852-valueT 16853-md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size ATTRIBUTE_UNUSED) 16854-{ 16855- return size; /* Byte alignment is fine. */ 16856-} 16857- 16858-/* Exactly what point is a PC-relative offset relative TO? 16859- On the 29000, they're relative to the address of the instruction, 16860- which we have set up as the address of the fixup too. */ 16861- 16862-long 16863-md_pcrel_from (fixS *fixP) 16864-{ 16865- return fixP->fx_where + fixP->fx_frag->fr_address; 16866-} 16867- 16868-/* Generate a reloc for a fixup. */ 16869- 16870-arelent * 16871-tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 16872-{ 16873- arelent *reloc; 16874- 16875- reloc = xmalloc (sizeof (arelent)); 16876- reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 16877- *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 16878- reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 16879- /* reloc->address = fixp->fx_frag->fr_address + fixp->fx_where + fixp->fx_addnumber;*/ 16880- reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 16881- 16882- if (reloc->howto == (reloc_howto_type *) NULL) 16883- { 16884- as_bad_where (fixp->fx_file, fixp->fx_line, 16885- _("reloc %d not supported by object file format"), 16886- (int) fixp->fx_r_type); 16887- return NULL; 16888- } 16889- 16890- if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 16891- reloc->address = fixp->fx_offset; 16892- 16893- reloc->addend = fixp->fx_addnumber; 16894- return reloc; 16895-} 16896diff -rNU3 dist.orig/gas/config/tc-or32.h dist/gas/config/tc-or32.h 16897--- dist.orig/gas/config/tc-or32.h 2007-07-03 13:01:04.000000000 +0200 16898+++ dist/gas/config/tc-or32.h 1970-01-01 01:00:00.000000000 +0100 16899@@ -1,56 +0,0 @@ 16900-/* tc-or32.h -- Assemble for the OpenRISC 1000. 16901- Copyright (C) 2002, 2003. 2005, 2007 Free Software Foundation, Inc. 16902- Contributed by Damjan Lampret <lampret@opencores.org>. 16903- Based upon a29k port. 16904- 16905- This file is part of GAS, the GNU Assembler. 16906- 16907- GAS is free software; you can redistribute it and/or modify 16908- it under the terms of the GNU General Public License as published by 16909- the Free Software Foundation; either version 3, or (at your option) 16910- any later version. 16911- 16912- GAS is distributed in the hope that it will be useful, 16913- but WITHOUT ANY WARRANTY; without even the implied warranty of 16914- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16915- GNU General Public License for more details. 16916- 16917- You should have received a copy of the GNU General Public License 16918- along with GAS; see the file COPYING. If not, write to 16919- the Free Software Foundation, 51 Franklin Street - Fifth Floor, 16920- Boston, MA 02110-1301, USA. */ 16921- 16922-#define TC_OR32 16923- 16924-#define TARGET_BYTES_BIG_ENDIAN 1 16925- 16926-#define LEX_DOLLAR 1 16927- 16928-#ifdef OBJ_ELF 16929-#define TARGET_FORMAT "elf32-or32" 16930-#define TARGET_ARCH bfd_arch_or32 16931-#endif 16932- 16933-#ifdef OBJ_COFF 16934-#define TARGET_FORMAT "coff-or32-big" 16935-#define reloc_type int 16936-#endif 16937- 16938-#define tc_unrecognized_line(c) or32_unrecognized_line (c) 16939- 16940-extern int or32_unrecognized_line (int); 16941- 16942-#define tc_coff_symbol_emit_hook(a) ; /* Not used. */ 16943- 16944-#define COFF_MAGIC SIPFBOMAGIC 16945- 16946-/* No shared lib support, so we don't need to ensure externally 16947- visible symbols can be overridden. */ 16948-#define EXTERN_FORCE_RELOC 0 16949- 16950-#ifdef OBJ_ELF 16951-/* Values passed to md_apply_fix don't include the symbol value. */ 16952-#define MD_APPLY_SYM_VALUE(FIX) 0 16953-#endif 16954- 16955-#define ZERO_BASED_SEGMENTS 16956diff -rNU3 dist.orig/gas/config/tc-riscv.c dist/gas/config/tc-riscv.c 16957--- dist.orig/gas/config/tc-riscv.c 1970-01-01 01:00:00.000000000 +0100 16958+++ dist/gas/config/tc-riscv.c 2015-10-18 13:11:13.000000000 +0200 16959@@ -0,0 +1,2225 @@ 16960+/* tc-riscv.c -- RISC-V assembler 16961+ Copyright 2011-2014 Free Software Foundation, Inc. 16962+ 16963+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 16964+ Based on MIPS target. 16965+ 16966+ This file is part of GAS. 16967+ 16968+ GAS is free software; you can redistribute it and/or modify 16969+ it under the terms of the GNU General Public License as published by 16970+ the Free Software Foundation; either version 3, or (at your option) 16971+ any later version. 16972+ 16973+ GAS is distributed in the hope that it will be useful, 16974+ but WITHOUT ANY WARRANTY; without even the implied warranty of 16975+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16976+ GNU General Public License for more details. 16977+ 16978+ You should have received a copy of the GNU General Public License 16979+ along with GAS; see the file COPYING. If not, write to the Free 16980+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 16981+ 02110-1301, USA. */ 16982+ 16983+#include "as.h" 16984+#include "config.h" 16985+#include "subsegs.h" 16986+#include "safe-ctype.h" 16987+ 16988+#include "itbl-ops.h" 16989+#include "dwarf2dbg.h" 16990+#include "dw2gencfi.h" 16991+ 16992+#include "elf/riscv.h" 16993+#include "opcode/riscv.h" 16994+ 16995+#include <execinfo.h> 16996+#include <stdint.h> 16997+ 16998+/* Information about an instruction, including its format, operands 16999+ and fixups. */ 17000+struct riscv_cl_insn 17001+{ 17002+ /* The opcode's entry in riscv_opcodes. */ 17003+ const struct riscv_opcode *insn_mo; 17004+ 17005+ /* The encoded instruction bits. */ 17006+ insn_t insn_opcode; 17007+ 17008+ /* The frag that contains the instruction. */ 17009+ struct frag *frag; 17010+ 17011+ /* The offset into FRAG of the first instruction byte. */ 17012+ long where; 17013+ 17014+ /* The relocs associated with the instruction, if any. */ 17015+ fixS *fixp; 17016+}; 17017+ 17018+bfd_boolean rv64 = TRUE; /* RV64 (true) or RV32 (false) */ 17019+#define LOAD_ADDRESS_INSN (rv64 ? "ld" : "lw") 17020+#define ADD32_INSN (rv64 ? "addiw" : "addi") 17021+ 17022+struct riscv_subset 17023+{ 17024+ const char* name; 17025+ int version_major; 17026+ int version_minor; 17027+ 17028+ struct riscv_subset* next; 17029+}; 17030+ 17031+static struct riscv_subset* riscv_subsets; 17032+ 17033+static int 17034+riscv_subset_supports(const char* feature) 17035+{ 17036+ struct riscv_subset* s; 17037+ bfd_boolean rv64_insn; 17038+ 17039+ if ((rv64_insn = !strncmp(feature, "64", 2)) || !strncmp(feature, "32", 2)) 17040+ { 17041+ if (rv64 != rv64_insn) 17042+ return 0; 17043+ feature += 2; 17044+ } 17045+ 17046+ for (s = riscv_subsets; s != NULL; s = s->next) 17047+ if (strcmp(s->name, feature) == 0) 17048+ /* FIXME: once we support version numbers: 17049+ return major == s->version_major && minor <= s->version_minor; */ 17050+ return 1; 17051+ 17052+ return 0; 17053+} 17054+ 17055+static void 17056+riscv_add_subset(const char* subset) 17057+{ 17058+ struct riscv_subset* s = xmalloc(sizeof(struct riscv_subset)); 17059+ s->name = xstrdup(subset); 17060+ s->version_major = 1; 17061+ s->version_minor = 0; 17062+ s->next = riscv_subsets; 17063+ riscv_subsets = s; 17064+} 17065+ 17066+static void 17067+riscv_set_arch(const char* arg) 17068+{ 17069+ /* Formally, ISA subset names begin with RV, RV32, or RV64, but we allow the 17070+ prefix to be omitted. We also allow all-lowercase names if version 17071+ numbers and eXtensions are omitted (i.e. only some combination of imafd 17072+ is supported in this case). 17073+ 17074+ FIXME: Version numbers are not supported yet. */ 17075+ const char* subsets = "IMAFD"; 17076+ const char* p; 17077+ 17078+ for (p = arg; *p; p++) 17079+ if (!ISLOWER(*p) || strchr(subsets, TOUPPER(*p)) == NULL) 17080+ break; 17081+ 17082+ if (!*p) 17083+ { 17084+ /* Legal all-lowercase name. */ 17085+ for (p = arg; *p; p++) 17086+ { 17087+ char subset[2] = {TOUPPER(*p), 0}; 17088+ riscv_add_subset(subset); 17089+ } 17090+ return; 17091+ } 17092+ 17093+ if (strncmp(arg, "RV32", 4) == 0) 17094+ { 17095+ rv64 = FALSE; 17096+ arg += 4; 17097+ } 17098+ else if (strncmp(arg, "RV64", 4) == 0) 17099+ { 17100+ rv64 = TRUE; 17101+ arg += 4; 17102+ } 17103+ else if (strncmp(arg, "RV", 2) == 0) 17104+ arg += 2; 17105+ 17106+ if (*arg && *arg != 'I') 17107+ as_fatal("`I' must be the first ISA subset name specified (got %c)", *arg); 17108+ 17109+ for (p = arg; *p; p++) 17110+ { 17111+ if (*p == 'X') 17112+ { 17113+ const char* q = p+1; 17114+ while (ISLOWER(*q)) 17115+ q++; 17116+ 17117+ char subset[q-p+1]; 17118+ memcpy(subset, p, q-p); 17119+ subset[q-p] = 0; 17120+ 17121+ riscv_add_subset(subset); 17122+ p = q-1; 17123+ } 17124+ else if (strchr(subsets, *p) != NULL) 17125+ { 17126+ char subset[2] = {*p, 0}; 17127+ riscv_add_subset(subset); 17128+ } 17129+ else 17130+ as_fatal("unsupported ISA subset %c", *p); 17131+ } 17132+} 17133+ 17134+/* This is the set of options which may be modified by the .set 17135+ pseudo-op. We use a struct so that .set push and .set pop are more 17136+ reliable. */ 17137+ 17138+struct riscv_set_options 17139+{ 17140+ /* Generate position-independent code. */ 17141+ int pic; 17142+ /* Generate RVC code. */ 17143+ int rvc; 17144+}; 17145+ 17146+static struct riscv_set_options riscv_opts = 17147+{ 17148+ 0, /* pic */ 17149+ 0, /* rvc */ 17150+}; 17151+ 17152+/* handle of the OPCODE hash table */ 17153+static struct hash_control *op_hash = NULL; 17154+ 17155+/* This array holds the chars that always start a comment. If the 17156+ pre-processor is disabled, these aren't very useful */ 17157+const char comment_chars[] = "#"; 17158+ 17159+/* This array holds the chars that only start a comment at the beginning of 17160+ a line. If the line seems to have the form '# 123 filename' 17161+ .line and .file directives will appear in the pre-processed output */ 17162+/* Note that input_file.c hand checks for '#' at the beginning of the 17163+ first line of the input file. This is because the compiler outputs 17164+ #NO_APP at the beginning of its output. */ 17165+/* Also note that C style comments are always supported. */ 17166+const char line_comment_chars[] = "#"; 17167+ 17168+/* This array holds machine specific line separator characters. */ 17169+const char line_separator_chars[] = ";"; 17170+ 17171+/* Chars that can be used to separate mant from exp in floating point nums */ 17172+const char EXP_CHARS[] = "eE"; 17173+ 17174+/* Chars that mean this number is a floating point constant */ 17175+/* As in 0f12.456 */ 17176+/* or 0d1.2345e12 */ 17177+const char FLT_CHARS[] = "rRsSfFdDxXpP"; 17178+ 17179+/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 17180+ changed in read.c . Ideally it shouldn't have to know about it at all, 17181+ but nothing is ideal around here. 17182+ */ 17183+ 17184+static char *insn_error; 17185+ 17186+#define RELAX_BRANCH_ENCODE(uncond, toofar) \ 17187+ ((relax_substateT) \ 17188+ (0xc0000000 \ 17189+ | ((toofar) ? 1 : 0) \ 17190+ | ((uncond) ? 2 : 0))) 17191+#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 17192+#define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) 17193+#define RELAX_BRANCH_UNCOND(i) (((i) & 2) != 0) 17194+ 17195+/* Is the given value a sign-extended 32-bit value? */ 17196+#define IS_SEXT_32BIT_NUM(x) \ 17197+ (((x) &~ (offsetT) 0x7fffffff) == 0 \ 17198+ || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 17199+ 17200+#define IS_SEXT_NBIT_NUM(x,n) \ 17201+ ({ int64_t __tmp = (x); \ 17202+ __tmp = (__tmp << (64-(n))) >> (64-(n)); \ 17203+ __tmp == (x); }) 17204+ 17205+/* Is the given value a zero-extended 32-bit value? Or a negated one? */ 17206+#define IS_ZEXT_32BIT_NUM(x) \ 17207+ (((x) &~ (offsetT) 0xffffffff) == 0 \ 17208+ || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 17209+ 17210+/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in 17211+ VALUE << SHIFT. VALUE is evaluated exactly once. */ 17212+#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ 17213+ (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \ 17214+ | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) 17215+ 17216+/* Extract bits MASK << SHIFT from STRUCT and shift them right 17217+ SHIFT places. */ 17218+#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ 17219+ (((STRUCT) >> (SHIFT)) & (MASK)) 17220+ 17221+/* Change INSN's opcode so that the operand given by FIELD has value VALUE. 17222+ INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ 17223+#define INSERT_OPERAND(FIELD, INSN, VALUE) \ 17224+ INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) 17225+ 17226+/* Extract the operand given by FIELD from riscv_cl_insn INSN. */ 17227+#define EXTRACT_OPERAND(FIELD, INSN) \ 17228+ EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) 17229+ 17230+/* Determine if an instruction matches an opcode. */ 17231+#define OPCODE_MATCHES(OPCODE, OP) \ 17232+ (((OPCODE) & MASK_##OP) == MATCH_##OP) 17233+ 17234+#define INSN_MATCHES(INSN, OP) \ 17235+ (((INSN).insn_opcode & MASK_##OP) == MATCH_##OP) 17236+ 17237+/* Prototypes for static functions. */ 17238+ 17239+#define internalError() \ 17240+ as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) 17241+ 17242+static char *expr_end; 17243+ 17244+/* Expressions which appear in instructions. These are set by 17245+ riscv_ip. */ 17246+ 17247+static expressionS imm_expr; 17248+static expressionS offset_expr; 17249+ 17250+/* Relocs associated with imm_expr and offset_expr. */ 17251+ 17252+static bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; 17253+static bfd_reloc_code_real_type offset_reloc = BFD_RELOC_UNUSED; 17254+ 17255+/* The default target format to use. */ 17256+ 17257+const char * 17258+riscv_target_format (void) 17259+{ 17260+ return rv64 ? "elf64-littleriscv" : "elf32-littleriscv"; 17261+} 17262+ 17263+/* Return the length of instruction INSN. */ 17264+ 17265+static inline unsigned int 17266+insn_length (const struct riscv_cl_insn *insn) 17267+{ 17268+ return riscv_insn_length (insn->insn_opcode); 17269+} 17270+ 17271+/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 17272+ 17273+static void 17274+create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) 17275+{ 17276+ insn->insn_mo = mo; 17277+ insn->insn_opcode = mo->match; 17278+ insn->frag = NULL; 17279+ insn->where = 0; 17280+ insn->fixp = NULL; 17281+} 17282+ 17283+/* Install INSN at the location specified by its "frag" and "where" fields. */ 17284+ 17285+static void 17286+install_insn (const struct riscv_cl_insn *insn) 17287+{ 17288+ char *f = insn->frag->fr_literal + insn->where; 17289+ md_number_to_chars (f, insn->insn_opcode, insn_length(insn)); 17290+} 17291+ 17292+/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 17293+ and install the opcode in the new location. */ 17294+ 17295+static void 17296+move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) 17297+{ 17298+ insn->frag = frag; 17299+ insn->where = where; 17300+ if (insn->fixp != NULL) 17301+ { 17302+ insn->fixp->fx_frag = frag; 17303+ insn->fixp->fx_where = where; 17304+ } 17305+ install_insn (insn); 17306+} 17307+ 17308+/* Add INSN to the end of the output. */ 17309+ 17310+static void 17311+add_fixed_insn (struct riscv_cl_insn *insn) 17312+{ 17313+ char *f = frag_more (insn_length (insn)); 17314+ move_insn (insn, frag_now, f - frag_now->fr_literal); 17315+} 17316+ 17317+static void 17318+add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, 17319+ relax_substateT subtype, symbolS *symbol, offsetT offset) 17320+{ 17321+ frag_grow (max_chars); 17322+ move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 17323+ frag_var (rs_machine_dependent, max_chars, var, 17324+ subtype, symbol, offset, NULL); 17325+} 17326+ 17327+/* Compute the length of a branch sequence, and adjust the 17328+ RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 17329+ worst-case length is computed. */ 17330+static int 17331+relaxed_branch_length (fragS *fragp, asection *sec, int update) 17332+{ 17333+ bfd_boolean toofar = TRUE; 17334+ 17335+ if (fragp) 17336+ { 17337+ bfd_boolean uncond = RELAX_BRANCH_UNCOND (fragp->fr_subtype); 17338+ 17339+ if (S_IS_DEFINED (fragp->fr_symbol) 17340+ && sec == S_GET_SEGMENT (fragp->fr_symbol)) 17341+ { 17342+ offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17343+ bfd_vma range; 17344+ val -= fragp->fr_address + fragp->fr_fix; 17345+ 17346+ if (uncond) 17347+ range = RISCV_JUMP_REACH; 17348+ else 17349+ range = RISCV_BRANCH_REACH; 17350+ toofar = (bfd_vma)(val + range/2) >= range; 17351+ } 17352+ 17353+ if (update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 17354+ fragp->fr_subtype = RELAX_BRANCH_ENCODE (uncond, toofar); 17355+ } 17356+ 17357+ return toofar ? 8 : 4; 17358+} 17359+ 17360+struct regname { 17361+ const char *name; 17362+ unsigned int num; 17363+}; 17364+ 17365+enum reg_class { 17366+ RCLASS_GPR, 17367+ RCLASS_FPR, 17368+ RCLASS_CSR, 17369+ RCLASS_VEC_GPR, 17370+ RCLASS_VEC_FPR, 17371+ RCLASS_MAX 17372+}; 17373+ 17374+static struct hash_control *reg_names_hash = NULL; 17375+ 17376+#define ENCODE_REG_HASH(cls, n) (void*)(uintptr_t)((n)*RCLASS_MAX + (cls) + 1) 17377+#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) 17378+#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) 17379+ 17380+static void 17381+hash_reg_name (enum reg_class class, const char *name, unsigned n) 17382+{ 17383+ void *hash = ENCODE_REG_HASH (class, n); 17384+ const char *retval = hash_insert (reg_names_hash, name, hash); 17385+ if (retval != NULL) 17386+ as_fatal (_("internal error: can't hash `%s': %s"), name, retval); 17387+} 17388+ 17389+static void 17390+hash_reg_names (enum reg_class class, const char * const names[], unsigned n) 17391+{ 17392+ unsigned i; 17393+ for (i = 0; i < n; i++) 17394+ hash_reg_name (class, names[i], i); 17395+} 17396+ 17397+static unsigned int 17398+reg_lookup_internal (const char *s, enum reg_class class) 17399+{ 17400+ struct regname *r = (struct regname *) hash_find (reg_names_hash, s); 17401+ if (r == NULL || DECODE_REG_CLASS (r) != class) 17402+ return -1; 17403+ return DECODE_REG_NUM (r); 17404+} 17405+ 17406+static int 17407+reg_lookup (char **s, enum reg_class class, unsigned int *regnop) 17408+{ 17409+ char *e; 17410+ char save_c; 17411+ int reg = -1; 17412+ 17413+ /* Find end of name. */ 17414+ e = *s; 17415+ if (is_name_beginner (*e)) 17416+ ++e; 17417+ while (is_part_of_name (*e)) 17418+ ++e; 17419+ 17420+ /* Terminate name. */ 17421+ save_c = *e; 17422+ *e = '\0'; 17423+ 17424+ /* Look for the register. Advance to next token if one was recognized. */ 17425+ if ((reg = reg_lookup_internal (*s, class)) >= 0) 17426+ *s = e; 17427+ 17428+ *e = save_c; 17429+ if (regnop) 17430+ *regnop = reg; 17431+ return reg >= 0; 17432+} 17433+ 17434+static int 17435+arg_lookup(char **s, const char* const* array, size_t size, unsigned *regnop) 17436+{ 17437+ const char *p = strchr(*s, ','); 17438+ size_t i, len = p ? (size_t)(p - *s) : strlen(*s); 17439+ 17440+ for (i = 0; i < size; i++) 17441+ if (array[i] != NULL && strncmp(array[i], *s, len) == 0) 17442+ { 17443+ *regnop = i; 17444+ *s += len; 17445+ return 1; 17446+ } 17447+ 17448+ return 0; 17449+} 17450+ 17451+/* For consistency checking, verify that all bits are specified either 17452+ by the match/mask part of the instruction definition, or by the 17453+ operand list. */ 17454+static int 17455+validate_riscv_insn (const struct riscv_opcode *opc) 17456+{ 17457+ const char *p = opc->args; 17458+ char c; 17459+ insn_t required_bits, used_bits = opc->mask; 17460+ 17461+ if ((used_bits & opc->match) != opc->match) 17462+ { 17463+ as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), 17464+ opc->name, opc->args); 17465+ return 0; 17466+ } 17467+ required_bits = ((insn_t)1 << (8 * riscv_insn_length (opc->match))) - 1; 17468+ /* Work around for undefined behavior of uint64_t << 64 */ 17469+ if(riscv_insn_length (opc->match) == 8) 17470+ required_bits = 0xffffffffffffffff; 17471+ 17472+#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) 17473+ while (*p) 17474+ switch (c = *p++) 17475+ { 17476+ /* Xcustom */ 17477+ case '^': 17478+ switch (c = *p++) 17479+ { 17480+ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 17481+ case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 17482+ case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; 17483+ case 'j': USE_BITS (OP_MASK_CUSTOM_IMM, OP_SH_CUSTOM_IMM); break; 17484+ } 17485+ break; 17486+ /* Xhwacha */ 17487+ case '#': 17488+ switch (c = *p++) 17489+ { 17490+ case 'g': USE_BITS (OP_MASK_IMMNGPR, OP_SH_IMMNGPR); break; 17491+ case 'f': USE_BITS (OP_MASK_IMMNFPR, OP_SH_IMMNFPR); break; 17492+ case 'n': USE_BITS (OP_MASK_IMMSEGNELM, OP_SH_IMMSEGNELM); break; 17493+ case 'd': USE_BITS (OP_MASK_VRD, OP_SH_VRD); break; 17494+ case 's': USE_BITS (OP_MASK_VRS, OP_SH_VRS); break; 17495+ case 't': USE_BITS (OP_MASK_VRT, OP_SH_VRT); break; 17496+ case 'r': USE_BITS (OP_MASK_VRR, OP_SH_VRR); break; 17497+ case 'D': USE_BITS (OP_MASK_VFD, OP_SH_VFD); break; 17498+ case 'S': USE_BITS (OP_MASK_VFS, OP_SH_VFS); break; 17499+ case 'T': USE_BITS (OP_MASK_VFT, OP_SH_VFT); break; 17500+ case 'R': USE_BITS (OP_MASK_VFR, OP_SH_VFR); break; 17501+ 17502+ default: 17503+ as_bad (_("internal: bad RISC-V opcode (unknown extension operand type `#%c'): %s %s"), 17504+ c, opc->name, opc->args); 17505+ return 0; 17506+ } 17507+ break; 17508+ case ',': break; 17509+ case '(': break; 17510+ case ')': break; 17511+ case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; 17512+ case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 17513+ case 'A': break; 17514+ case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 17515+ case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 17516+ case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; 17517+ case 'I': break; 17518+ case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; 17519+ case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 17520+ case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ 17521+ case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; 17522+ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 17523+ case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; 17524+ case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 17525+ case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; 17526+ case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; 17527+ case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; 17528+ case 'o': 17529+ case 'j': used_bits |= ENCODE_ITYPE_IMM(-1U); break; 17530+ case 'a': used_bits |= ENCODE_UJTYPE_IMM(-1U); break; 17531+ case 'p': used_bits |= ENCODE_SBTYPE_IMM(-1U); break; 17532+ case 'q': used_bits |= ENCODE_STYPE_IMM(-1U); break; 17533+ case 'u': used_bits |= ENCODE_UTYPE_IMM(-1U); break; 17534+ case '[': break; 17535+ case ']': break; 17536+ case '0': break; 17537+ default: 17538+ as_bad (_("internal: bad RISC-V opcode (unknown operand type `%c'): %s %s"), 17539+ c, opc->name, opc->args); 17540+ return 0; 17541+ } 17542+#undef USE_BITS 17543+ if (used_bits != required_bits) 17544+ { 17545+ as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), 17546+ ~(long)(used_bits & required_bits), opc->name, opc->args); 17547+ return 0; 17548+ } 17549+ return 1; 17550+} 17551+ 17552+struct percent_op_match 17553+{ 17554+ const char *str; 17555+ bfd_reloc_code_real_type reloc; 17556+}; 17557+ 17558+/* This function is called once, at assembler startup time. It should set up 17559+ all the tables, etc. that the MD part of the assembler will need. */ 17560+ 17561+void 17562+md_begin (void) 17563+{ 17564+ const char *retval = NULL; 17565+ int i = 0; 17566+ 17567+ if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, 0)) 17568+ as_warn (_("Could not set architecture and machine")); 17569+ 17570+ op_hash = hash_new (); 17571+ 17572+ for (i = 0; i < NUMOPCODES;) 17573+ { 17574+ const char *name = riscv_opcodes[i].name; 17575+ 17576+ if (riscv_subset_supports(riscv_opcodes[i].subset)) 17577+ retval = hash_insert (op_hash, name, (void *) &riscv_opcodes[i]); 17578+ 17579+ if (retval != NULL) 17580+ { 17581+ fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 17582+ riscv_opcodes[i].name, retval); 17583+ /* Probably a memory allocation problem? Give up now. */ 17584+ as_fatal (_("Broken assembler. No assembly attempted.")); 17585+ } 17586+ do 17587+ { 17588+ if (riscv_opcodes[i].pinfo != INSN_MACRO) 17589+ { 17590+ if (!validate_riscv_insn (&riscv_opcodes[i])) 17591+ as_fatal (_("Broken assembler. No assembly attempted.")); 17592+ } 17593+ ++i; 17594+ } 17595+ while ((i < NUMOPCODES) && !strcmp (riscv_opcodes[i].name, name)); 17596+ } 17597+ 17598+ reg_names_hash = hash_new (); 17599+ hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); 17600+ hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); 17601+ hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); 17602+ hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); 17603+ hash_reg_names (RCLASS_VEC_GPR, riscv_vec_gpr_names, NVGPR); 17604+ hash_reg_names (RCLASS_VEC_FPR, riscv_vec_fpr_names, NVFPR); 17605+ 17606+#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); 17607+#include "opcode/riscv-opc.h" 17608+#undef DECLARE_CSR 17609+ 17610+ /* set the default alignment for the text section (2**2) */ 17611+ record_alignment (text_section, 2); 17612+} 17613+ 17614+/* Output an instruction. IP is the instruction information. 17615+ ADDRESS_EXPR is an operand of the instruction to be used with 17616+ RELOC_TYPE. */ 17617+ 17618+static void 17619+append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, 17620+ bfd_reloc_code_real_type reloc_type) 17621+{ 17622+#ifdef OBJ_ELF 17623+ dwarf2_emit_insn (0); 17624+#endif 17625+ 17626+ gas_assert(reloc_type <= BFD_RELOC_UNUSED); 17627+ 17628+ if (address_expr != NULL) 17629+ { 17630+ if (address_expr->X_op == O_constant) 17631+ { 17632+ switch (reloc_type) 17633+ { 17634+ case BFD_RELOC_32: 17635+ ip->insn_opcode |= address_expr->X_add_number; 17636+ break; 17637+ 17638+ case BFD_RELOC_RISCV_HI20: 17639+ ip->insn_opcode |= ENCODE_UTYPE_IMM ( 17640+ RISCV_CONST_HIGH_PART (address_expr->X_add_number)); 17641+ break; 17642+ 17643+ case BFD_RELOC_RISCV_LO12_S: 17644+ ip->insn_opcode |= ENCODE_STYPE_IMM (address_expr->X_add_number); 17645+ break; 17646+ 17647+ case BFD_RELOC_UNUSED: 17648+ case BFD_RELOC_RISCV_LO12_I: 17649+ ip->insn_opcode |= ENCODE_ITYPE_IMM (address_expr->X_add_number); 17650+ break; 17651+ 17652+ default: 17653+ internalError (); 17654+ } 17655+ reloc_type = BFD_RELOC_UNUSED; 17656+ } 17657+ else if (reloc_type == BFD_RELOC_12_PCREL) 17658+ { 17659+ add_relaxed_insn (ip, relaxed_branch_length (NULL, NULL, 0), 4, 17660+ RELAX_BRANCH_ENCODE (0, 0), 17661+ address_expr->X_add_symbol, 17662+ address_expr->X_add_number); 17663+ return; 17664+ } 17665+ else if (reloc_type < BFD_RELOC_UNUSED) 17666+ { 17667+ reloc_howto_type *howto; 17668+ 17669+ howto = bfd_reloc_type_lookup (stdoutput, reloc_type); 17670+ if (howto == NULL) 17671+ as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); 17672+ 17673+ ip->fixp = fix_new_exp (ip->frag, ip->where, 17674+ bfd_get_reloc_size (howto), 17675+ address_expr, 17676+ reloc_type == BFD_RELOC_12_PCREL || 17677+ reloc_type == BFD_RELOC_RISCV_CALL || 17678+ reloc_type == BFD_RELOC_RISCV_JMP, 17679+ reloc_type); 17680+ 17681+ /* These relocations can have an addend that won't fit in 17682+ 4 octets for 64bit assembly. */ 17683+ if (rv64 17684+ && ! howto->partial_inplace 17685+ && (reloc_type == BFD_RELOC_32 17686+ || reloc_type == BFD_RELOC_64 17687+ || reloc_type == BFD_RELOC_CTOR 17688+ || reloc_type == BFD_RELOC_RISCV_HI20 17689+ || reloc_type == BFD_RELOC_RISCV_LO12_I 17690+ || reloc_type == BFD_RELOC_RISCV_LO12_S)) 17691+ ip->fixp->fx_no_overflow = 1; 17692+ } 17693+ } 17694+ 17695+ add_fixed_insn (ip); 17696+ 17697+ install_insn (ip); 17698+} 17699+ 17700+/* Build an instruction created by a macro expansion. This is passed 17701+ a pointer to the count of instructions created so far, an 17702+ expression, the name of the instruction to build, an operand format 17703+ string, and corresponding arguments. */ 17704+ 17705+static void 17706+macro_build (expressionS *ep, const char *name, const char *fmt, ...) 17707+{ 17708+ const struct riscv_opcode *mo; 17709+ struct riscv_cl_insn insn; 17710+ bfd_reloc_code_real_type r; 17711+ va_list args; 17712+ 17713+ va_start (args, fmt); 17714+ 17715+ r = BFD_RELOC_UNUSED; 17716+ mo = (struct riscv_opcode *) hash_find (op_hash, name); 17717+ gas_assert (mo); 17718+ gas_assert (strcmp (name, mo->name) == 0); 17719+ 17720+ create_insn (&insn, mo); 17721+ for (;;) 17722+ { 17723+ switch (*fmt++) 17724+ { 17725+ case 'd': 17726+ INSERT_OPERAND (RD, insn, va_arg (args, int)); 17727+ continue; 17728+ 17729+ case 's': 17730+ INSERT_OPERAND (RS1, insn, va_arg (args, int)); 17731+ continue; 17732+ 17733+ case 't': 17734+ INSERT_OPERAND (RS2, insn, va_arg (args, int)); 17735+ continue; 17736+ 17737+ case '>': 17738+ INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); 17739+ continue; 17740+ 17741+ case 'j': 17742+ case 'u': 17743+ case 'q': 17744+ gas_assert (ep != NULL); 17745+ r = va_arg (args, int); 17746+ continue; 17747+ 17748+ case '\0': 17749+ break; 17750+ case ',': 17751+ continue; 17752+ default: 17753+ internalError (); 17754+ } 17755+ break; 17756+ } 17757+ va_end (args); 17758+ gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 17759+ 17760+ append_insn (&insn, ep, r); 17761+} 17762+ 17763+/* 17764+ * Sign-extend 32-bit mode constants that have bit 31 set and all 17765+ * higher bits unset. 17766+ */ 17767+static void 17768+normalize_constant_expr (expressionS *ex) 17769+{ 17770+ if (rv64) 17771+ return; 17772+ if ((ex->X_op == O_constant || ex->X_op == O_symbol) 17773+ && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 17774+ ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 17775+ - 0x80000000); 17776+} 17777+ 17778+static symbolS * 17779+make_internal_label (void) 17780+{ 17781+ return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, 17782+ (valueT) frag_now_fix(), frag_now); 17783+} 17784+ 17785+/* Load an entry from the GOT. */ 17786+static void 17787+pcrel_access (int destreg, int tempreg, expressionS *ep, 17788+ const char* lo_insn, const char* lo_pattern, 17789+ bfd_reloc_code_real_type hi_reloc, 17790+ bfd_reloc_code_real_type lo_reloc) 17791+{ 17792+ expressionS ep2; 17793+ ep2.X_op = O_symbol; 17794+ ep2.X_add_symbol = make_internal_label (); 17795+ ep2.X_add_number = 0; 17796+ 17797+ macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); 17798+ macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); 17799+} 17800+ 17801+static void 17802+pcrel_load (int destreg, int tempreg, expressionS *ep, const char* lo_insn, 17803+ bfd_reloc_code_real_type hi_reloc, 17804+ bfd_reloc_code_real_type lo_reloc) 17805+{ 17806+ pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); 17807+} 17808+ 17809+static void 17810+pcrel_store (int srcreg, int tempreg, expressionS *ep, const char* lo_insn, 17811+ bfd_reloc_code_real_type hi_reloc, 17812+ bfd_reloc_code_real_type lo_reloc) 17813+{ 17814+ pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); 17815+} 17816+ 17817+/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ 17818+static void 17819+riscv_call (int destreg, int tempreg, expressionS *ep, 17820+ bfd_reloc_code_real_type reloc) 17821+{ 17822+ macro_build (ep, "auipc", "d,u", tempreg, reloc); 17823+ macro_build (NULL, "jalr", "d,s", destreg, tempreg); 17824+} 17825+ 17826+/* Warn if an expression is not a constant. */ 17827+ 17828+static void 17829+check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex) 17830+{ 17831+ if (ex->X_op == O_big) 17832+ as_bad (_("unsupported large constant")); 17833+ else if (ex->X_op != O_constant) 17834+ as_bad (_("Instruction %s requires absolute expression"), 17835+ ip->insn_mo->name); 17836+ normalize_constant_expr (ex); 17837+} 17838+ 17839+/* Load an integer constant into a register. */ 17840+ 17841+static void 17842+load_const (int reg, expressionS *ep) 17843+{ 17844+ int shift = RISCV_IMM_BITS; 17845+ expressionS upper = *ep, lower = *ep; 17846+ lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift); 17847+ upper.X_add_number -= lower.X_add_number; 17848+ 17849+ gas_assert (ep->X_op == O_constant); 17850+ 17851+ if (rv64 && !IS_SEXT_32BIT_NUM(ep->X_add_number)) 17852+ { 17853+ /* Reduce to a signed 32-bit constant using SLLI and ADDI, which 17854+ is not optimal but also not so bad. */ 17855+ while (((upper.X_add_number >> shift) & 1) == 0) 17856+ shift++; 17857+ 17858+ upper.X_add_number = (int64_t) upper.X_add_number >> shift; 17859+ load_const(reg, &upper); 17860+ 17861+ macro_build (NULL, "slli", "d,s,>", reg, reg, shift); 17862+ if (lower.X_add_number != 0) 17863+ macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I); 17864+ } 17865+ else 17866+ { 17867+ int hi_reg = 0; 17868+ 17869+ if (upper.X_add_number != 0) 17870+ { 17871+ macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20); 17872+ hi_reg = reg; 17873+ } 17874+ 17875+ if (lower.X_add_number != 0 || hi_reg == 0) 17876+ macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg, 17877+ BFD_RELOC_RISCV_LO12_I); 17878+ } 17879+} 17880+ 17881+/* Expand RISC-V assembly macros into one or more instructions. */ 17882+static void 17883+macro (struct riscv_cl_insn *ip) 17884+{ 17885+ int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; 17886+ int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; 17887+ int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; 17888+ int mask = ip->insn_mo->mask; 17889+ 17890+ switch (mask) 17891+ { 17892+ case M_LI: 17893+ load_const (rd, &imm_expr); 17894+ break; 17895+ 17896+ case M_LA: 17897+ case M_LLA: 17898+ /* Load the address of a symbol into a register. */ 17899+ if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 17900+ as_bad(_("offset too large")); 17901+ 17902+ if (offset_expr.X_op == O_constant) 17903+ load_const (rd, &offset_expr); 17904+ else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ 17905+ pcrel_load (rd, rd, &offset_expr, LOAD_ADDRESS_INSN, 17906+ BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17907+ else /* Local PIC symbol, or any non-PIC symbol */ 17908+ pcrel_load (rd, rd, &offset_expr, "addi", 17909+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17910+ break; 17911+ 17912+ case M_LA_TLS_GD: 17913+ pcrel_load (rd, rd, &offset_expr, "addi", 17914+ BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17915+ break; 17916+ 17917+ case M_LA_TLS_IE: 17918+ pcrel_load (rd, rd, &offset_expr, LOAD_ADDRESS_INSN, 17919+ BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17920+ break; 17921+ 17922+ case M_LB: 17923+ pcrel_load (rd, rd, &offset_expr, "lb", 17924+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17925+ break; 17926+ 17927+ case M_LBU: 17928+ pcrel_load (rd, rd, &offset_expr, "lbu", 17929+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17930+ break; 17931+ 17932+ case M_LH: 17933+ pcrel_load (rd, rd, &offset_expr, "lh", 17934+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17935+ break; 17936+ 17937+ case M_LHU: 17938+ pcrel_load (rd, rd, &offset_expr, "lhu", 17939+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17940+ break; 17941+ 17942+ case M_LW: 17943+ pcrel_load (rd, rd, &offset_expr, "lw", 17944+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17945+ break; 17946+ 17947+ case M_LWU: 17948+ pcrel_load (rd, rd, &offset_expr, "lwu", 17949+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17950+ break; 17951+ 17952+ case M_LD: 17953+ pcrel_load (rd, rd, &offset_expr, "ld", 17954+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17955+ break; 17956+ 17957+ case M_FLW: 17958+ pcrel_load (rd, rs1, &offset_expr, "flw", 17959+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17960+ break; 17961+ 17962+ case M_FLD: 17963+ pcrel_load (rd, rs1, &offset_expr, "fld", 17964+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 17965+ break; 17966+ 17967+ case M_SB: 17968+ pcrel_store (rs2, rs1, &offset_expr, "sb", 17969+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 17970+ break; 17971+ 17972+ case M_SH: 17973+ pcrel_store (rs2, rs1, &offset_expr, "sh", 17974+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 17975+ break; 17976+ 17977+ case M_SW: 17978+ pcrel_store (rs2, rs1, &offset_expr, "sw", 17979+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 17980+ break; 17981+ 17982+ case M_SD: 17983+ pcrel_store (rs2, rs1, &offset_expr, "sd", 17984+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 17985+ break; 17986+ 17987+ case M_FSW: 17988+ pcrel_store (rs2, rs1, &offset_expr, "fsw", 17989+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 17990+ break; 17991+ 17992+ case M_FSD: 17993+ pcrel_store (rs2, rs1, &offset_expr, "fsd", 17994+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 17995+ break; 17996+ 17997+ case M_VF: 17998+ pcrel_access (0, rs1, &offset_expr, "vf", "s,s,q", 17999+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 18000+ break; 18001+ 18002+ case M_CALL: 18003+ riscv_call (rd, rs1, &offset_expr, offset_reloc); 18004+ break; 18005+ 18006+ default: 18007+ as_bad (_("Macro %s not implemented"), ip->insn_mo->name); 18008+ break; 18009+ } 18010+} 18011+ 18012+static const struct percent_op_match percent_op_utype[] = 18013+{ 18014+ {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, 18015+ {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, 18016+ {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, 18017+ {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, 18018+ {"%hi", BFD_RELOC_RISCV_HI20}, 18019+ {0, 0} 18020+}; 18021+ 18022+static const struct percent_op_match percent_op_itype[] = 18023+{ 18024+ {"%lo", BFD_RELOC_RISCV_LO12_I}, 18025+ {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, 18026+ {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, 18027+ {0, 0} 18028+}; 18029+ 18030+static const struct percent_op_match percent_op_stype[] = 18031+{ 18032+ {"%lo", BFD_RELOC_RISCV_LO12_S}, 18033+ {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, 18034+ {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, 18035+ {0, 0} 18036+}; 18037+ 18038+static const struct percent_op_match percent_op_rtype[] = 18039+{ 18040+ {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, 18041+ {0, 0} 18042+}; 18043+ 18044+/* Return true if *STR points to a relocation operator. When returning true, 18045+ move *STR over the operator and store its relocation code in *RELOC. 18046+ Leave both *STR and *RELOC alone when returning false. */ 18047+ 18048+static bfd_boolean 18049+parse_relocation (char **str, bfd_reloc_code_real_type *reloc, 18050+ const struct percent_op_match *percent_op) 18051+{ 18052+ for ( ; percent_op->str; percent_op++) 18053+ if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) 18054+ { 18055+ int len = strlen (percent_op->str); 18056+ 18057+ if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 18058+ continue; 18059+ 18060+ *str += strlen (percent_op->str); 18061+ *reloc = percent_op->reloc; 18062+ 18063+ /* Check whether the output BFD supports this relocation. 18064+ If not, issue an error and fall back on something safe. */ 18065+ if (!bfd_reloc_type_lookup (stdoutput, percent_op->reloc)) 18066+ { 18067+ as_bad ("relocation %s isn't supported by the current ABI", 18068+ percent_op->str); 18069+ *reloc = BFD_RELOC_UNUSED; 18070+ } 18071+ return TRUE; 18072+ } 18073+ return FALSE; 18074+} 18075+ 18076+static void 18077+my_getExpression (expressionS *ep, char *str) 18078+{ 18079+ char *save_in; 18080+ 18081+ save_in = input_line_pointer; 18082+ input_line_pointer = str; 18083+ expression (ep); 18084+ expr_end = input_line_pointer; 18085+ input_line_pointer = save_in; 18086+} 18087+ 18088+/* Parse string STR as a 16-bit relocatable operand. Store the 18089+ expression in *EP and the relocation, if any, in RELOC. 18090+ Return the number of relocation operators used (0 or 1). 18091+ 18092+ On exit, EXPR_END points to the first character after the expression. */ 18093+ 18094+static size_t 18095+my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 18096+ char *str, const struct percent_op_match *percent_op) 18097+{ 18098+ size_t reloc_index; 18099+ int crux_depth, str_depth; 18100+ char *crux; 18101+ 18102+ /* Search for the start of the main expression. 18103+ End the loop with CRUX pointing to the start 18104+ of the main expression and with CRUX_DEPTH containing the number 18105+ of open brackets at that point. */ 18106+ reloc_index = -1; 18107+ str_depth = 0; 18108+ do 18109+ { 18110+ reloc_index++; 18111+ crux = str; 18112+ crux_depth = str_depth; 18113+ 18114+ /* Skip over whitespace and brackets, keeping count of the number 18115+ of brackets. */ 18116+ while (*str == ' ' || *str == '\t' || *str == '(') 18117+ if (*str++ == '(') 18118+ str_depth++; 18119+ } 18120+ while (*str == '%' 18121+ && reloc_index < 1 18122+ && parse_relocation (&str, reloc, percent_op)); 18123+ 18124+ my_getExpression (ep, crux); 18125+ str = expr_end; 18126+ 18127+ /* Match every open bracket. */ 18128+ while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 18129+ if (*str++ == ')') 18130+ crux_depth--; 18131+ 18132+ if (crux_depth > 0) 18133+ as_bad ("unclosed '('"); 18134+ 18135+ expr_end = str; 18136+ 18137+ return reloc_index; 18138+} 18139+ 18140+/* This routine assembles an instruction into its binary format. As a 18141+ side effect, it sets one of the global variables imm_reloc or 18142+ offset_reloc to the type of relocation to do if one of the operands 18143+ is an address expression. */ 18144+ 18145+static void 18146+riscv_ip (char *str, struct riscv_cl_insn *ip) 18147+{ 18148+ char *s; 18149+ const char *args; 18150+ char c = 0; 18151+ struct riscv_opcode *insn; 18152+ char *argsStart; 18153+ unsigned int regno; 18154+ char save_c = 0; 18155+ int argnum; 18156+ const struct percent_op_match *p; 18157+ 18158+ insn_error = NULL; 18159+ 18160+ /* If the instruction contains a '.', we first try to match an instruction 18161+ including the '.'. Then we try again without the '.'. */ 18162+ insn = NULL; 18163+ for (s = str; *s != '\0' && !ISSPACE (*s); ++s) 18164+ continue; 18165+ 18166+ /* If we stopped on whitespace, then replace the whitespace with null for 18167+ the call to hash_find. Save the character we replaced just in case we 18168+ have to re-parse the instruction. */ 18169+ if (ISSPACE (*s)) 18170+ { 18171+ save_c = *s; 18172+ *s++ = '\0'; 18173+ } 18174+ 18175+ insn = (struct riscv_opcode *) hash_find (op_hash, str); 18176+ 18177+ /* If we didn't find the instruction in the opcode table, try again, but 18178+ this time with just the instruction up to, but not including the 18179+ first '.'. */ 18180+ if (insn == NULL) 18181+ { 18182+ /* Restore the character we overwrite above (if any). */ 18183+ if (save_c) 18184+ *(--s) = save_c; 18185+ 18186+ /* Scan up to the first '.' or whitespace. */ 18187+ for (s = str; 18188+ *s != '\0' && *s != '.' && !ISSPACE (*s); 18189+ ++s) 18190+ continue; 18191+ 18192+ /* If we did not find a '.', then we can quit now. */ 18193+ if (*s != '.') 18194+ { 18195+ insn_error = "unrecognized opcode"; 18196+ return; 18197+ } 18198+ 18199+ /* Lookup the instruction in the hash table. */ 18200+ *s++ = '\0'; 18201+ if ((insn = (struct riscv_opcode *) hash_find (op_hash, str)) == NULL) 18202+ { 18203+ insn_error = "unrecognized opcode"; 18204+ return; 18205+ } 18206+ } 18207+ 18208+ argsStart = s; 18209+ for (;;) 18210+ { 18211+ bfd_boolean ok = TRUE; 18212+ gas_assert (strcmp (insn->name, str) == 0); 18213+ 18214+ create_insn (ip, insn); 18215+ insn_error = NULL; 18216+ argnum = 1; 18217+ for (args = insn->args;; ++args) 18218+ { 18219+ s += strspn (s, " \t"); 18220+ switch (*args) 18221+ { 18222+ case '\0': /* end of args */ 18223+ if (*s == '\0') 18224+ return; 18225+ break; 18226+ /* Xcustom */ 18227+ case '^': 18228+ { 18229+ unsigned long max = OP_MASK_RD; 18230+ my_getExpression (&imm_expr, s); 18231+ check_absolute_expr (ip, &imm_expr); 18232+ switch (*++args) 18233+ { 18234+ case 'j': 18235+ max = OP_MASK_CUSTOM_IMM; 18236+ INSERT_OPERAND (CUSTOM_IMM, *ip, imm_expr.X_add_number); 18237+ break; 18238+ case 'd': 18239+ INSERT_OPERAND (RD, *ip, imm_expr.X_add_number); 18240+ break; 18241+ case 's': 18242+ INSERT_OPERAND (RS1, *ip, imm_expr.X_add_number); 18243+ break; 18244+ case 't': 18245+ INSERT_OPERAND (RS2, *ip, imm_expr.X_add_number); 18246+ break; 18247+ } 18248+ imm_expr.X_op = O_absent; 18249+ s = expr_end; 18250+ if ((unsigned long) imm_expr.X_add_number > max) 18251+ as_warn ("Bad custom immediate (%lu), must be at most %lu", 18252+ (unsigned long)imm_expr.X_add_number, max); 18253+ continue; 18254+ } 18255+ 18256+ /* Xhwacha */ 18257+ case '#': 18258+ switch ( *++args ) 18259+ { 18260+ case 'g': 18261+ my_getExpression( &imm_expr, s ); 18262+ /* check_absolute_expr( ip, &imm_expr ); */ 18263+ if ((unsigned long) imm_expr.X_add_number > 32 ) 18264+ as_warn( _( "Improper ngpr amount (%lu)" ), 18265+ (unsigned long) imm_expr.X_add_number ); 18266+ INSERT_OPERAND( IMMNGPR, *ip, imm_expr.X_add_number ); 18267+ imm_expr.X_op = O_absent; 18268+ s = expr_end; 18269+ continue; 18270+ case 'f': 18271+ my_getExpression( &imm_expr, s ); 18272+ /* check_absolute_expr( ip, &imm_expr ); */ 18273+ if ((unsigned long) imm_expr.X_add_number > 32 ) 18274+ as_warn( _( "Improper nfpr amount (%lu)" ), 18275+ (unsigned long) imm_expr.X_add_number ); 18276+ INSERT_OPERAND( IMMNFPR, *ip, imm_expr.X_add_number ); 18277+ imm_expr.X_op = O_absent; 18278+ s = expr_end; 18279+ continue; 18280+ case 'n': 18281+ my_getExpression( &imm_expr, s ); 18282+ /* check_absolute_expr( ip, &imm_expr ); */ 18283+ if ((unsigned long) imm_expr.X_add_number > 8 ) 18284+ as_warn( _( "Improper nelm amount (%lu)" ), 18285+ (unsigned long) imm_expr.X_add_number ); 18286+ INSERT_OPERAND( IMMSEGNELM, *ip, imm_expr.X_add_number - 1 ); 18287+ imm_expr.X_op = O_absent; 18288+ s = expr_end; 18289+ continue; 18290+ case 'd': 18291+ ok = reg_lookup( &s, RCLASS_VEC_GPR, ®no ); 18292+ if ( !ok ) 18293+ as_bad( _( "Invalid vector register" ) ); 18294+ INSERT_OPERAND( VRD, *ip, regno ); 18295+ continue; 18296+ case 's': 18297+ ok = reg_lookup( &s, RCLASS_VEC_GPR, ®no ); 18298+ if ( !ok ) 18299+ as_bad( _( "Invalid vector register" ) ); 18300+ INSERT_OPERAND( VRS, *ip, regno ); 18301+ continue; 18302+ case 't': 18303+ ok = reg_lookup( &s, RCLASS_VEC_GPR, ®no ); 18304+ if ( !ok ) 18305+ as_bad( _( "Invalid vector register" ) ); 18306+ INSERT_OPERAND( VRT, *ip, regno ); 18307+ continue; 18308+ case 'r': 18309+ ok = reg_lookup( &s, RCLASS_VEC_GPR, ®no ); 18310+ if ( !ok ) 18311+ as_bad( _( "Invalid vector register" ) ); 18312+ INSERT_OPERAND( VRR, *ip, regno ); 18313+ continue; 18314+ case 'D': 18315+ ok = reg_lookup( &s, RCLASS_VEC_FPR, ®no ); 18316+ if ( !ok ) 18317+ as_bad( _( "Invalid vector register" ) ); 18318+ INSERT_OPERAND( VFD, *ip, regno ); 18319+ continue; 18320+ case 'S': 18321+ ok = reg_lookup( &s, RCLASS_VEC_FPR, ®no ); 18322+ if ( !ok ) 18323+ as_bad( _( "Invalid vector register" ) ); 18324+ INSERT_OPERAND( VFS, *ip, regno ); 18325+ continue; 18326+ case 'T': 18327+ ok = reg_lookup( &s, RCLASS_VEC_FPR, ®no ); 18328+ if ( !ok ) 18329+ as_bad( _( "Invalid vector register" ) ); 18330+ INSERT_OPERAND( VFT, *ip, regno ); 18331+ continue; 18332+ case 'R': 18333+ ok = reg_lookup( &s, RCLASS_VEC_FPR, ®no ); 18334+ if ( !ok ) 18335+ as_bad( _( "Invalid vector register" ) ); 18336+ INSERT_OPERAND( VFR, *ip, regno ); 18337+ continue; 18338+ } 18339+ break; 18340+ 18341+ case ',': 18342+ ++argnum; 18343+ if (*s++ == *args) 18344+ continue; 18345+ s--; 18346+ break; 18347+ 18348+ case '(': 18349+ case ')': 18350+ case '[': 18351+ case ']': 18352+ if (*s++ == *args) 18353+ continue; 18354+ break; 18355+ 18356+ case '<': /* shift amount, 0 - 31 */ 18357+ my_getExpression (&imm_expr, s); 18358+ check_absolute_expr (ip, &imm_expr); 18359+ if ((unsigned long) imm_expr.X_add_number > 31) 18360+ as_warn (_("Improper shift amount (%lu)"), 18361+ (unsigned long) imm_expr.X_add_number); 18362+ INSERT_OPERAND (SHAMTW, *ip, imm_expr.X_add_number); 18363+ imm_expr.X_op = O_absent; 18364+ s = expr_end; 18365+ continue; 18366+ 18367+ case '>': /* shift amount, 0 - (XLEN-1) */ 18368+ my_getExpression (&imm_expr, s); 18369+ check_absolute_expr (ip, &imm_expr); 18370+ if ((unsigned long) imm_expr.X_add_number > (rv64 ? 63 : 31)) 18371+ as_warn (_("Improper shift amount (%lu)"), 18372+ (unsigned long) imm_expr.X_add_number); 18373+ INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); 18374+ imm_expr.X_op = O_absent; 18375+ s = expr_end; 18376+ continue; 18377+ 18378+ case 'Z': /* CSRRxI immediate */ 18379+ my_getExpression (&imm_expr, s); 18380+ check_absolute_expr (ip, &imm_expr); 18381+ if ((unsigned long) imm_expr.X_add_number > 31) 18382+ as_warn (_("Improper CSRxI immediate (%lu)"), 18383+ (unsigned long) imm_expr.X_add_number); 18384+ INSERT_OPERAND (RS1, *ip, imm_expr.X_add_number); 18385+ imm_expr.X_op = O_absent; 18386+ s = expr_end; 18387+ continue; 18388+ 18389+ case 'E': /* Control register. */ 18390+ ok = reg_lookup (&s, RCLASS_CSR, ®no); 18391+ if (ok) 18392+ INSERT_OPERAND (CSR, *ip, regno); 18393+ else 18394+ { 18395+ my_getExpression (&imm_expr, s); 18396+ check_absolute_expr (ip, &imm_expr); 18397+ if ((unsigned long) imm_expr.X_add_number > 0xfff) 18398+ as_warn(_("Improper CSR address (%lu)"), 18399+ (unsigned long) imm_expr.X_add_number); 18400+ INSERT_OPERAND (CSR, *ip, imm_expr.X_add_number); 18401+ imm_expr.X_op = O_absent; 18402+ s = expr_end; 18403+ } 18404+ continue; 18405+ 18406+ case 'm': /* rounding mode */ 18407+ if (arg_lookup (&s, riscv_rm, ARRAY_SIZE(riscv_rm), ®no)) 18408+ { 18409+ INSERT_OPERAND (RM, *ip, regno); 18410+ continue; 18411+ } 18412+ break; 18413+ 18414+ case 'P': 18415+ case 'Q': /* fence predecessor/successor */ 18416+ if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ), ®no)) 18417+ { 18418+ if (*args == 'P') 18419+ INSERT_OPERAND(PRED, *ip, regno); 18420+ else 18421+ INSERT_OPERAND(SUCC, *ip, regno); 18422+ continue; 18423+ } 18424+ break; 18425+ 18426+ case 'd': /* destination register */ 18427+ case 's': /* source register */ 18428+ case 't': /* target register */ 18429+ ok = reg_lookup (&s, RCLASS_GPR, ®no); 18430+ if (ok) 18431+ { 18432+ c = *args; 18433+ if (*s == ' ') 18434+ ++s; 18435+ 18436+ /* Now that we have assembled one operand, we use the args string 18437+ * to figure out where it goes in the instruction. */ 18438+ switch (c) 18439+ { 18440+ case 's': 18441+ INSERT_OPERAND (RS1, *ip, regno); 18442+ break; 18443+ case 'd': 18444+ INSERT_OPERAND (RD, *ip, regno); 18445+ break; 18446+ case 't': 18447+ INSERT_OPERAND (RS2, *ip, regno); 18448+ break; 18449+ } 18450+ continue; 18451+ } 18452+ break; 18453+ 18454+ case 'D': /* floating point rd */ 18455+ case 'S': /* floating point rs1 */ 18456+ case 'T': /* floating point rs2 */ 18457+ case 'U': /* floating point rs1 and rs2 */ 18458+ case 'R': /* floating point rs3 */ 18459+ if (reg_lookup (&s, RCLASS_FPR, ®no)) 18460+ { 18461+ c = *args; 18462+ if (*s == ' ') 18463+ ++s; 18464+ switch (c) 18465+ { 18466+ case 'D': 18467+ INSERT_OPERAND (RD, *ip, regno); 18468+ break; 18469+ case 'S': 18470+ INSERT_OPERAND (RS1, *ip, regno); 18471+ break; 18472+ case 'U': 18473+ INSERT_OPERAND (RS1, *ip, regno); 18474+ /* fallthru */ 18475+ case 'T': 18476+ INSERT_OPERAND (RS2, *ip, regno); 18477+ break; 18478+ case 'R': 18479+ INSERT_OPERAND (RS3, *ip, regno); 18480+ break; 18481+ } 18482+ continue; 18483+ } 18484+ 18485+ break; 18486+ 18487+ case 'I': 18488+ my_getExpression (&imm_expr, s); 18489+ if (imm_expr.X_op != O_big 18490+ && imm_expr.X_op != O_constant) 18491+ insn_error = _("absolute expression required"); 18492+ normalize_constant_expr (&imm_expr); 18493+ s = expr_end; 18494+ continue; 18495+ 18496+ case 'A': 18497+ my_getExpression (&offset_expr, s); 18498+ normalize_constant_expr (&offset_expr); 18499+ imm_reloc = BFD_RELOC_32; 18500+ s = expr_end; 18501+ continue; 18502+ 18503+ case 'j': /* sign-extended immediate */ 18504+ imm_reloc = BFD_RELOC_RISCV_LO12_I; 18505+ p = percent_op_itype; 18506+ goto alu_op; 18507+ case 'q': /* store displacement */ 18508+ p = percent_op_stype; 18509+ offset_reloc = BFD_RELOC_RISCV_LO12_S; 18510+ goto load_store; 18511+ case 'o': /* load displacement */ 18512+ p = percent_op_itype; 18513+ offset_reloc = BFD_RELOC_RISCV_LO12_I; 18514+ goto load_store; 18515+ case '0': /* AMO "displacement," which must be zero */ 18516+ p = percent_op_rtype; 18517+ offset_reloc = BFD_RELOC_UNUSED; 18518+load_store: 18519+ /* Check whether there is only a single bracketed expression 18520+ left. If so, it must be the base register and the 18521+ constant must be zero. */ 18522+ offset_expr.X_op = O_constant; 18523+ offset_expr.X_add_number = 0; 18524+ if (*s == '(' && strchr (s + 1, '(') == 0) 18525+ continue; 18526+alu_op: 18527+ /* If this value won't fit into a 16 bit offset, then go 18528+ find a macro that will generate the 32 bit offset 18529+ code pattern. */ 18530+ if (!my_getSmallExpression (&offset_expr, &offset_reloc, s, p)) 18531+ { 18532+ normalize_constant_expr (&offset_expr); 18533+ if (offset_expr.X_op != O_constant 18534+ || (*args == '0' && offset_expr.X_add_number != 0) 18535+ || offset_expr.X_add_number >= (signed)RISCV_IMM_REACH/2 18536+ || offset_expr.X_add_number < -(signed)RISCV_IMM_REACH/2) 18537+ break; 18538+ } 18539+ 18540+ s = expr_end; 18541+ continue; 18542+ 18543+ case 'p': /* pc relative offset */ 18544+ offset_reloc = BFD_RELOC_12_PCREL; 18545+ my_getExpression (&offset_expr, s); 18546+ s = expr_end; 18547+ continue; 18548+ 18549+ case 'u': /* upper 20 bits */ 18550+ p = percent_op_utype; 18551+ if (!my_getSmallExpression (&imm_expr, &imm_reloc, s, p) 18552+ && imm_expr.X_op == O_constant) 18553+ { 18554+ if (imm_expr.X_add_number < 0 18555+ || imm_expr.X_add_number >= (signed)RISCV_BIGIMM_REACH) 18556+ as_bad (_("lui expression not in range 0..1048575")); 18557+ 18558+ imm_reloc = BFD_RELOC_RISCV_HI20; 18559+ imm_expr.X_add_number <<= RISCV_IMM_BITS; 18560+ } 18561+ s = expr_end; 18562+ continue; 18563+ 18564+ case 'a': /* 26 bit address */ 18565+ my_getExpression (&offset_expr, s); 18566+ s = expr_end; 18567+ offset_reloc = BFD_RELOC_RISCV_JMP; 18568+ continue; 18569+ 18570+ case 'c': 18571+ my_getExpression (&offset_expr, s); 18572+ s = expr_end; 18573+ offset_reloc = BFD_RELOC_RISCV_CALL; 18574+ if (*s == '@') 18575+ offset_reloc = BFD_RELOC_RISCV_CALL_PLT, s++; 18576+ continue; 18577+ 18578+ default: 18579+ as_bad (_("bad char = '%c'\n"), *args); 18580+ internalError (); 18581+ } 18582+ break; 18583+ } 18584+ /* Args don't match. */ 18585+ if (insn + 1 < &riscv_opcodes[NUMOPCODES] && 18586+ !strcmp (insn->name, insn[1].name)) 18587+ { 18588+ ++insn; 18589+ s = argsStart; 18590+ insn_error = _("illegal operands"); 18591+ continue; 18592+ } 18593+ if (save_c) 18594+ *(--argsStart) = save_c; 18595+ insn_error = _("illegal operands"); 18596+ return; 18597+ } 18598+} 18599+ 18600+void 18601+md_assemble (char *str) 18602+{ 18603+ struct riscv_cl_insn insn; 18604+ 18605+ imm_expr.X_op = O_absent; 18606+ offset_expr.X_op = O_absent; 18607+ imm_reloc = BFD_RELOC_UNUSED; 18608+ offset_reloc = BFD_RELOC_UNUSED; 18609+ 18610+ riscv_ip (str, &insn); 18611+ 18612+ if (insn_error) 18613+ { 18614+ as_bad ("%s `%s'", insn_error, str); 18615+ return; 18616+ } 18617+ 18618+ if (insn.insn_mo->pinfo == INSN_MACRO) 18619+ macro (&insn); 18620+ else 18621+ { 18622+ if (imm_expr.X_op != O_absent) 18623+ append_insn (&insn, &imm_expr, imm_reloc); 18624+ else if (offset_expr.X_op != O_absent) 18625+ append_insn (&insn, &offset_expr, offset_reloc); 18626+ else 18627+ append_insn (&insn, NULL, BFD_RELOC_UNUSED); 18628+ } 18629+} 18630+ 18631+char * 18632+md_atof (int type, char *litP, int *sizeP) 18633+{ 18634+ return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); 18635+} 18636+ 18637+void 18638+md_number_to_chars (char *buf, valueT val, int n) 18639+{ 18640+ number_to_chars_littleendian (buf, val, n); 18641+} 18642+ 18643+const char *md_shortopts = "O::g::G:"; 18644+ 18645+enum options 18646+ { 18647+ OPTION_M32 = OPTION_MD_BASE, 18648+ OPTION_M64, 18649+ OPTION_MARCH, 18650+ OPTION_PIC, 18651+ OPTION_NO_PIC, 18652+ OPTION_MRVC, 18653+ OPTION_MNO_RVC, 18654+ OPTION_END_OF_ENUM 18655+ }; 18656+ 18657+struct option md_longopts[] = 18658+{ 18659+ {"m32", no_argument, NULL, OPTION_M32}, 18660+ {"m64", no_argument, NULL, OPTION_M64}, 18661+ {"march", required_argument, NULL, OPTION_MARCH}, 18662+ {"fPIC", no_argument, NULL, OPTION_PIC}, 18663+ {"fpic", no_argument, NULL, OPTION_PIC}, 18664+ {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, 18665+ {"mrvc", no_argument, NULL, OPTION_MRVC}, 18666+ {"mno-rvc", no_argument, NULL, OPTION_MNO_RVC}, 18667+ 18668+ {NULL, no_argument, NULL, 0} 18669+}; 18670+size_t md_longopts_size = sizeof (md_longopts); 18671+ 18672+int 18673+md_parse_option (int c, char *arg) 18674+{ 18675+ switch (c) 18676+ { 18677+ case OPTION_MRVC: 18678+ riscv_opts.rvc = 1; 18679+ break; 18680+ 18681+ case OPTION_MNO_RVC: 18682+ riscv_opts.rvc = 0; 18683+ break; 18684+ 18685+ case OPTION_M32: 18686+ rv64 = FALSE; 18687+ break; 18688+ 18689+ case OPTION_M64: 18690+ rv64 = TRUE; 18691+ break; 18692+ 18693+ case OPTION_MARCH: 18694+ riscv_set_arch(arg); 18695+ 18696+ case OPTION_NO_PIC: 18697+ riscv_opts.pic = FALSE; 18698+ break; 18699+ 18700+ case OPTION_PIC: 18701+ riscv_opts.pic = TRUE; 18702+ break; 18703+ 18704+ default: 18705+ return 0; 18706+ } 18707+ 18708+ return 1; 18709+} 18710+ 18711+void 18712+riscv_after_parse_args (void) 18713+{ 18714+ if (riscv_subsets == NULL) 18715+ riscv_set_arch("RVIMAFDXcustom"); 18716+} 18717+ 18718+void 18719+riscv_init_after_args (void) 18720+{ 18721+ /* initialize opcodes */ 18722+ bfd_riscv_num_opcodes = bfd_riscv_num_builtin_opcodes; 18723+ riscv_opcodes = (struct riscv_opcode *) riscv_builtin_opcodes; 18724+} 18725+ 18726+long 18727+md_pcrel_from (fixS *fixP) 18728+{ 18729+ return fixP->fx_where + fixP->fx_frag->fr_address; 18730+} 18731+ 18732+/* Apply a fixup to the object file. */ 18733+ 18734+void 18735+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 18736+{ 18737+ bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); 18738+ 18739+ /* Remember value for tc_gen_reloc. */ 18740+ fixP->fx_addnumber = *valP; 18741+ 18742+ switch (fixP->fx_r_type) 18743+ { 18744+ case BFD_RELOC_RISCV_TLS_GOT_HI20: 18745+ case BFD_RELOC_RISCV_TLS_GD_HI20: 18746+ case BFD_RELOC_RISCV_TLS_DTPREL32: 18747+ case BFD_RELOC_RISCV_TLS_DTPREL64: 18748+ case BFD_RELOC_RISCV_TPREL_HI20: 18749+ case BFD_RELOC_RISCV_TPREL_LO12_I: 18750+ case BFD_RELOC_RISCV_TPREL_LO12_S: 18751+ case BFD_RELOC_RISCV_TPREL_ADD: 18752+ S_SET_THREAD_LOCAL (fixP->fx_addsy); 18753+ /* fall through */ 18754+ 18755+ case BFD_RELOC_RISCV_GOT_HI20: 18756+ case BFD_RELOC_RISCV_PCREL_HI20: 18757+ case BFD_RELOC_RISCV_HI20: 18758+ case BFD_RELOC_RISCV_LO12_I: 18759+ case BFD_RELOC_RISCV_LO12_S: 18760+ case BFD_RELOC_RISCV_ADD8: 18761+ case BFD_RELOC_RISCV_ADD16: 18762+ case BFD_RELOC_RISCV_ADD32: 18763+ case BFD_RELOC_RISCV_ADD64: 18764+ case BFD_RELOC_RISCV_SUB8: 18765+ case BFD_RELOC_RISCV_SUB16: 18766+ case BFD_RELOC_RISCV_SUB32: 18767+ case BFD_RELOC_RISCV_SUB64: 18768+ gas_assert (fixP->fx_addsy != NULL); 18769+ /* Nothing needed to do. The value comes from the reloc entry. */ 18770+ break; 18771+ 18772+ case BFD_RELOC_64: 18773+ case BFD_RELOC_32: 18774+ case BFD_RELOC_16: 18775+ case BFD_RELOC_8: 18776+ if (fixP->fx_addsy && fixP->fx_subsy) 18777+ { 18778+ fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); 18779+ fixP->fx_next->fx_addsy = fixP->fx_subsy; 18780+ fixP->fx_next->fx_subsy = NULL; 18781+ fixP->fx_next->fx_offset = 0; 18782+ fixP->fx_subsy = NULL; 18783+ 18784+ if (fixP->fx_r_type == BFD_RELOC_64) 18785+ fixP->fx_r_type = BFD_RELOC_RISCV_ADD64, 18786+ fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; 18787+ else if (fixP->fx_r_type == BFD_RELOC_32) 18788+ fixP->fx_r_type = BFD_RELOC_RISCV_ADD32, 18789+ fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; 18790+ else if (fixP->fx_r_type == BFD_RELOC_16) 18791+ fixP->fx_r_type = BFD_RELOC_RISCV_ADD16, 18792+ fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; 18793+ else 18794+ fixP->fx_r_type = BFD_RELOC_RISCV_ADD8, 18795+ fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; 18796+ } 18797+ /* fall through */ 18798+ 18799+ case BFD_RELOC_RVA: 18800+ /* If we are deleting this reloc entry, we must fill in the 18801+ value now. This can happen if we have a .word which is not 18802+ resolved when it appears but is later defined. */ 18803+ if (fixP->fx_addsy == NULL) 18804+ { 18805+ gas_assert (fixP->fx_size <= sizeof (valueT)); 18806+ md_number_to_chars ((char *) buf, *valP, fixP->fx_size); 18807+ fixP->fx_done = 1; 18808+ } 18809+ break; 18810+ 18811+ case BFD_RELOC_RISCV_JMP: 18812+ if (fixP->fx_addsy) 18813+ { 18814+ /* Fill in a tentative value to improve objdump readability. */ 18815+ bfd_vma delta = ENCODE_UJTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP); 18816+ bfd_putl32 (bfd_getl32 (buf) | delta, buf); 18817+ } 18818+ break; 18819+ 18820+ case BFD_RELOC_12_PCREL: 18821+ if (fixP->fx_addsy) 18822+ { 18823+ /* Fill in a tentative value to improve objdump readability. */ 18824+ bfd_vma delta = ENCODE_SBTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP); 18825+ bfd_putl32 (bfd_getl32 (buf) | delta, buf); 18826+ } 18827+ break; 18828+ 18829+ case BFD_RELOC_RISCV_PCREL_LO12_S: 18830+ case BFD_RELOC_RISCV_PCREL_LO12_I: 18831+ case BFD_RELOC_RISCV_CALL: 18832+ case BFD_RELOC_RISCV_CALL_PLT: 18833+ case BFD_RELOC_RISCV_ALIGN: 18834+ break; 18835+ 18836+ default: 18837+ /* We ignore generic BFD relocations we don't know about. */ 18838+ if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) 18839+ internalError (); 18840+ } 18841+} 18842+ 18843+/* This structure is used to hold a stack of .set values. */ 18844+ 18845+struct riscv_option_stack 18846+{ 18847+ struct riscv_option_stack *next; 18848+ struct riscv_set_options options; 18849+}; 18850+ 18851+static struct riscv_option_stack *riscv_opts_stack; 18852+ 18853+/* Handle the .set pseudo-op. */ 18854+ 18855+static void 18856+s_riscv_option (int x ATTRIBUTE_UNUSED) 18857+{ 18858+ char *name = input_line_pointer, ch; 18859+ 18860+ while (!is_end_of_line[(unsigned char) *input_line_pointer]) 18861+ ++input_line_pointer; 18862+ ch = *input_line_pointer; 18863+ *input_line_pointer = '\0'; 18864+ 18865+ if (strcmp (name, "rvc") == 0) 18866+ riscv_opts.rvc = 1; 18867+ else if (strcmp (name, "norvc") == 0) 18868+ riscv_opts.rvc = 0; 18869+ else if (strcmp (name, "push") == 0) 18870+ { 18871+ struct riscv_option_stack *s; 18872+ 18873+ s = (struct riscv_option_stack *) xmalloc (sizeof *s); 18874+ s->next = riscv_opts_stack; 18875+ s->options = riscv_opts; 18876+ riscv_opts_stack = s; 18877+ } 18878+ else if (strcmp (name, "pop") == 0) 18879+ { 18880+ struct riscv_option_stack *s; 18881+ 18882+ s = riscv_opts_stack; 18883+ if (s == NULL) 18884+ as_bad (_(".option pop with no .option push")); 18885+ else 18886+ { 18887+ riscv_opts = s->options; 18888+ riscv_opts_stack = s->next; 18889+ free (s); 18890+ } 18891+ } 18892+ else 18893+ { 18894+ as_warn (_("Unrecognized .option directive: %s\n"), name); 18895+ } 18896+ *input_line_pointer = ch; 18897+ demand_empty_rest_of_line (); 18898+} 18899+ 18900+/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate 18901+ a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for 18902+ use in DWARF debug information. */ 18903+ 18904+static void 18905+s_dtprel (int bytes) 18906+{ 18907+ expressionS ex; 18908+ char *p; 18909+ 18910+ expression (&ex); 18911+ 18912+ if (ex.X_op != O_symbol) 18913+ { 18914+ as_bad (_("Unsupported use of %s"), (bytes == 8 18915+ ? ".dtpreldword" 18916+ : ".dtprelword")); 18917+ ignore_rest_of_line (); 18918+ } 18919+ 18920+ p = frag_more (bytes); 18921+ md_number_to_chars (p, 0, bytes); 18922+ fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, 18923+ (bytes == 8 18924+ ? BFD_RELOC_RISCV_TLS_DTPREL64 18925+ : BFD_RELOC_RISCV_TLS_DTPREL32)); 18926+ 18927+ demand_empty_rest_of_line (); 18928+} 18929+ 18930+/* Handle the .bss pseudo-op. */ 18931+ 18932+static void 18933+s_bss (int ignore ATTRIBUTE_UNUSED) 18934+{ 18935+ subseg_set (bss_section, 0); 18936+ demand_empty_rest_of_line (); 18937+} 18938+ 18939+/* Align to a given power of two. */ 18940+ 18941+static void 18942+s_align (int x ATTRIBUTE_UNUSED) 18943+{ 18944+ int alignment, fill_value = 0, fill_value_specified = 0; 18945+ 18946+ alignment = get_absolute_expression (); 18947+ if (alignment < 0 || alignment > 31) 18948+ as_bad (_("unsatisfiable alignment: %d"), alignment); 18949+ 18950+ if (*input_line_pointer == ',') 18951+ { 18952+ ++input_line_pointer; 18953+ fill_value = get_absolute_expression (); 18954+ fill_value_specified = 1; 18955+ } 18956+ 18957+ if (!fill_value_specified && subseg_text_p (now_seg) && alignment > 2) 18958+ { 18959+ /* Emit the worst-case NOP string. The linker will delete any 18960+ unnecessary NOPs. This allows us to support code alignment 18961+ in spite of linker relaxations. */ 18962+ bfd_vma i, worst_case_nop_bytes = (1L << alignment) - 4; 18963+ char *nops = frag_more (worst_case_nop_bytes); 18964+ for (i = 0; i < worst_case_nop_bytes; i += 4) 18965+ md_number_to_chars (nops + i, RISCV_NOP, 4); 18966+ 18967+ expressionS ex; 18968+ ex.X_op = O_constant; 18969+ ex.X_add_number = worst_case_nop_bytes; 18970+ 18971+ fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, 18972+ &ex, TRUE, BFD_RELOC_RISCV_ALIGN); 18973+ } 18974+ else if (alignment) 18975+ frag_align (alignment, fill_value, 0); 18976+ 18977+ record_alignment (now_seg, alignment); 18978+ 18979+ demand_empty_rest_of_line (); 18980+} 18981+ 18982+int 18983+md_estimate_size_before_relax (fragS *fragp, asection *segtype) 18984+{ 18985+ return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); 18986+} 18987+ 18988+/* Translate internal representation of relocation info to BFD target 18989+ format. */ 18990+ 18991+arelent * 18992+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 18993+{ 18994+ arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); 18995+ 18996+ reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 18997+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 18998+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 18999+ 19000+ if (fixp->fx_pcrel) 19001+ /* At this point, fx_addnumber is "symbol offset - pcrel address". 19002+ Relocations want only the symbol offset. */ 19003+ reloc->addend = fixp->fx_addnumber + reloc->address; 19004+ else 19005+ reloc->addend = fixp->fx_addnumber; 19006+ 19007+ reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 19008+ if (reloc->howto == NULL) 19009+ { 19010+ if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) 19011+ && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) 19012+ { 19013+ /* We don't have R_RISCV_8/16, but for this special case, 19014+ we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ 19015+ return reloc; 19016+ } 19017+ 19018+ as_bad_where (fixp->fx_file, fixp->fx_line, 19019+ _("cannot represent %s relocation in object file"), 19020+ bfd_get_reloc_code_name (fixp->fx_r_type)); 19021+ return NULL; 19022+ } 19023+ 19024+ return reloc; 19025+} 19026+ 19027+int 19028+riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) 19029+{ 19030+ if (RELAX_BRANCH_P (fragp->fr_subtype)) 19031+ { 19032+ offsetT old_var = fragp->fr_var; 19033+ fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 19034+ return fragp->fr_var - old_var; 19035+ } 19036+ 19037+ return 0; 19038+} 19039+ 19040+/* Convert a machine dependent frag. */ 19041+ 19042+static void 19043+md_convert_frag_branch (fragS *fragp) 19044+{ 19045+ bfd_byte *buf; 19046+ insn_t insn; 19047+ expressionS exp; 19048+ fixS *fixp; 19049+ 19050+ buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; 19051+ 19052+ exp.X_op = O_symbol; 19053+ exp.X_add_symbol = fragp->fr_symbol; 19054+ exp.X_add_number = fragp->fr_offset; 19055+ 19056+ if (RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 19057+ { 19058+ gas_assert (fragp->fr_var == 8); 19059+ /* We could relax JAL to AUIPC/JALR, but we don't do this yet. */ 19060+ gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); 19061+ 19062+ /* Invert the branch condition. Branch over the jump. */ 19063+ insn = bfd_getl32 (buf); 19064+ insn ^= MATCH_BEQ ^ MATCH_BNE; 19065+ insn |= ENCODE_SBTYPE_IMM (8); 19066+ md_number_to_chars ((char *) buf, insn, 4); 19067+ buf += 4; 19068+ 19069+ /* Jump to the target. */ 19070+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 19071+ 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); 19072+ md_number_to_chars ((char *) buf, MATCH_JAL, 4); 19073+ buf += 4; 19074+ } 19075+ else 19076+ { 19077+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 19078+ 4, &exp, FALSE, BFD_RELOC_12_PCREL); 19079+ buf += 4; 19080+ } 19081+ 19082+ fixp->fx_file = fragp->fr_file; 19083+ fixp->fx_line = fragp->fr_line; 19084+ fixp->fx_pcrel = 1; 19085+ 19086+ gas_assert (buf == (bfd_byte *)fragp->fr_literal 19087+ + fragp->fr_fix + fragp->fr_var); 19088+ 19089+ fragp->fr_fix += fragp->fr_var; 19090+} 19091+ 19092+/* Relax a machine dependent frag. This returns the amount by which 19093+ the current size of the frag should change. */ 19094+ 19095+void 19096+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, 19097+ fragS *fragp) 19098+{ 19099+ gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); 19100+ md_convert_frag_branch (fragp); 19101+} 19102+ 19103+void 19104+md_show_usage (FILE *stream) 19105+{ 19106+ fprintf (stream, _("\ 19107+RISC-V options:\n\ 19108+ -m32 assemble RV32 code\n\ 19109+ -m64 assemble RV64 code (default)\n\ 19110+ -fpic generate position-independent code\n\ 19111+ -fno-pic don't generate position-independent code (default)\n\ 19112+")); 19113+} 19114+ 19115+/* Standard calling conventions leave the CFA at SP on entry. */ 19116+void 19117+riscv_cfi_frame_initial_instructions (void) 19118+{ 19119+ cfi_add_CFA_def_cfa_register (X_SP); 19120+} 19121+ 19122+int 19123+tc_riscv_regname_to_dw2regnum (char *regname) 19124+{ 19125+ int reg; 19126+ 19127+ if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) 19128+ return reg; 19129+ 19130+ if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) 19131+ return reg + 32; 19132+ 19133+ as_bad (_("unknown register `%s'"), regname); 19134+ return -1; 19135+} 19136+ 19137+void 19138+riscv_elf_final_processing (void) 19139+{ 19140+ struct riscv_subset* s; 19141+ 19142+ unsigned int Xlen = 0; 19143+ for (s = riscv_subsets; s != NULL; s = s->next) 19144+ if (s->name[0] == 'X') 19145+ Xlen += strlen(s->name); 19146+ 19147+ char extension[Xlen]; 19148+ extension[0] = 0; 19149+ for (s = riscv_subsets; s != NULL; s = s->next) 19150+ if (s->name[0] == 'X') 19151+ strcat(extension, s->name); 19152+ 19153+ EF_SET_RISCV_EXT(elf_elfheader (stdoutput)->e_flags, 19154+ riscv_elf_name_to_flag (extension)); 19155+} 19156+ 19157+/* Pseudo-op table. */ 19158+ 19159+static const pseudo_typeS riscv_pseudo_table[] = 19160+{ 19161+ /* RISC-V-specific pseudo-ops. */ 19162+ {"option", s_riscv_option, 0}, 19163+ {"half", cons, 2}, 19164+ {"word", cons, 4}, 19165+ {"dword", cons, 8}, 19166+ {"dtprelword", s_dtprel, 4}, 19167+ {"dtpreldword", s_dtprel, 8}, 19168+ {"bss", s_bss, 0}, 19169+ {"align", s_align, 0}, 19170+ 19171+ /* leb128 doesn't work with relaxation; disallow it */ 19172+ {"uleb128", s_err, 0}, 19173+ {"sleb128", s_err, 0}, 19174+ 19175+ { NULL, NULL, 0 }, 19176+}; 19177+ 19178+void 19179+riscv_pop_insert (void) 19180+{ 19181+ extern void pop_insert (const pseudo_typeS *); 19182+ 19183+ pop_insert (riscv_pseudo_table); 19184+} 19185diff -rNU3 dist.orig/gas/config/tc-riscv.h dist/gas/config/tc-riscv.h 19186--- dist.orig/gas/config/tc-riscv.h 1970-01-01 01:00:00.000000000 +0100 19187+++ dist/gas/config/tc-riscv.h 2015-10-18 13:11:13.000000000 +0200 19188@@ -0,0 +1,102 @@ 19189+/* tc-riscv.h -- header file for tc-riscv.c. 19190+ Copyright 2011-2014 Free Software Foundation, Inc. 19191+ 19192+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 19193+ Based on MIPS target. 19194+ 19195+ This file is part of GAS. 19196+ 19197+ GAS is free software; you can redistribute it and/or modify 19198+ it under the terms of the GNU General Public License as published by 19199+ the Free Software Foundation; either version 3, or (at your option) 19200+ any later version. 19201+ 19202+ GAS is distributed in the hope that it will be useful, 19203+ but WITHOUT ANY WARRANTY; without even the implied warranty of 19204+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19205+ GNU General Public License for more details. 19206+ 19207+ You should have received a copy of the GNU General Public License 19208+ along with GAS; see the file COPYING. If not, write to the Free 19209+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19210+ 02110-1301, USA. */ 19211+ 19212+#ifndef TC_RISCV 19213+#define TC_RISCV 19214+ 19215+#include "opcode/riscv.h" 19216+ 19217+struct frag; 19218+struct expressionS; 19219+ 19220+#define TARGET_BYTES_BIG_ENDIAN 0 19221+ 19222+#define TARGET_ARCH bfd_arch_riscv 19223+ 19224+#define WORKING_DOT_WORD 1 19225+#define OLD_FLOAT_READS 19226+#define REPEAT_CONS_EXPRESSIONS 19227+#define LOCAL_LABELS_FB 1 19228+#define FAKE_LABEL_NAME ".L0 " 19229+ 19230+#define md_relax_frag(segment, fragp, stretch) \ 19231+ riscv_relax_frag(segment, fragp, stretch) 19232+extern int riscv_relax_frag (asection *, struct frag *, long); 19233+ 19234+#define md_section_align(seg,size) (size) 19235+#define md_undefined_symbol(name) (0) 19236+#define md_operand(x) 19237+ 19238+#define MAX_MEM_FOR_RS_ALIGN_CODE (1 + 2) 19239+ 19240+#define TC_SYMFIELD_TYPE int 19241+ 19242+/* The ISA of the target may change based on command-line arguments. */ 19243+#define TARGET_FORMAT riscv_target_format() 19244+extern const char *riscv_target_format (void); 19245+ 19246+#define md_after_parse_args() riscv_after_parse_args() 19247+extern void riscv_after_parse_args (void); 19248+ 19249+#define tc_init_after_args() riscv_init_after_args() 19250+extern void riscv_init_after_args (void); 19251+ 19252+#define md_parse_long_option(arg) riscv_parse_long_option (arg) 19253+extern int riscv_parse_long_option (const char *); 19254+ 19255+/* Let the linker resolve all the relocs due to relaxation. */ 19256+#define tc_fix_adjustable(fixp) 0 19257+#define md_allow_local_subtract(l,r,s) 0 19258+ 19259+/* Values passed to md_apply_fix don't include symbol values. */ 19260+#define MD_APPLY_SYM_VALUE(FIX) 0 19261+ 19262+/* Global syms must not be resolved, to support ELF shared libraries. */ 19263+#define EXTERN_FORCE_RELOC \ 19264+ (OUTPUT_FLAVOR == bfd_target_elf_flavour) 19265+ 19266+#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) ((SEG)->flags & SEC_CODE) 19267+#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 19268+#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 19269+#define TC_FORCE_RELOCATION_LOCAL(FIX) 1 19270+#define DIFF_EXPR_OK 1 19271+ 19272+extern void riscv_pop_insert (void); 19273+#define md_pop_insert() riscv_pop_insert() 19274+ 19275+#define TARGET_USE_CFIPOP 1 19276+ 19277+#define tc_cfi_frame_initial_instructions riscv_cfi_frame_initial_instructions 19278+extern void riscv_cfi_frame_initial_instructions (void); 19279+ 19280+#define tc_regname_to_dw2regnum tc_riscv_regname_to_dw2regnum 19281+extern int tc_riscv_regname_to_dw2regnum (char *regname); 19282+ 19283+extern bfd_boolean rv64; 19284+#define DWARF2_DEFAULT_RETURN_COLUMN X_RA 19285+#define DWARF2_CIE_DATA_ALIGNMENT (rv64 ? 8 : 4) 19286+ 19287+#define elf_tc_final_processing riscv_elf_final_processing 19288+extern void riscv_elf_final_processing (void); 19289+ 19290+#endif /* TC_RISCV */ 19291diff -rNU3 dist.orig/gas/config/tc-vax.c dist/gas/config/tc-vax.c 19292--- dist.orig/gas/config/tc-vax.c 2010-06-28 16:06:57.000000000 +0200 19293+++ dist/gas/config/tc-vax.c 2015-10-18 13:11:13.000000000 +0200 19294@@ -24,6 +24,7 @@ 19295 19296 #include "vax-inst.h" 19297 #include "obstack.h" /* For FRAG_APPEND_1_CHAR macro in "frags.h" */ 19298+#include "dw2gencfi.h" 19299 #include "subsegs.h" 19300 #include "safe-ctype.h" 19301 19302@@ -392,6 +393,9 @@ 19303 && (PLT_symbol == NULL || fragP->fr_symbol != PLT_symbol) 19304 && fragP->fr_symbol != NULL 19305 && flag_want_pic 19306+#ifdef OBJ_ELF 19307+ && ELF_ST_VISIBILITY (S_GET_OTHER (fragP->fr_symbol)) != STV_HIDDEN 19308+#endif 19309 && (!S_IS_DEFINED (fragP->fr_symbol) 19310 || S_IS_WEAK (fragP->fr_symbol) 19311 || S_IS_EXTERNAL (fragP->fr_symbol))) 19312@@ -1073,6 +1077,154 @@ 19313 return retval; 19314 } 19315 19316+#ifdef OBJ_AOUT 19317+#ifndef BFD_ASSEMBLER 19318+void 19319+tc_aout_fix_to_chars (where, fixP, segment_address_in_file) 19320+ char *where; 19321+ fixS *fixP; 19322+ relax_addressT segment_address_in_file; 19323+{ 19324+ /* 19325+ * In: length of relocation (or of address) in chars: 1, 2 or 4. 19326+ * Out: GNU LD relocation length code: 0, 1, or 2. 19327+ */ 19328+ 19329+ static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; 19330+ int r_symbolnum; 19331+ int r_flags; 19332+ 19333+ know (fixP->fx_addsy != NULL); 19334+ 19335+ md_number_to_chars (where, 19336+ fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file, 19337+ 4); 19338+ 19339+ r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) 19340+ ? S_GET_TYPE (fixP->fx_addsy) 19341+ : fixP->fx_addsy->sy_number); 19342+ r_flags = (fixP->fx_pcrel ? 1 : 0) 19343+ | (!S_IS_DEFINED (fixP->fx_addsy) ? 8 : 0) /* extern */ 19344+ | ((nbytes_r_length[fixP->fx_size] & 3) << 1); 19345+ 19346+#if 0 19347+ r_flags |= ((!S_IS_DEFINED(fixP->fx_addsy) 19348+ && fixP->fx_pcrel 19349+ && fixP->fx_addsy != GOT_symbol 19350+ && fixP->fx_addsy != PLT_symbol 19351+ && flags_want_pic) ? 0x10 : 0); 19352+#endif 19353+ 19354+ switch (fixP->fx_r_type) { 19355+ case NO_RELOC: 19356+ break; 19357+ case NO_RELOC2: 19358+ if (r_flags & 8) 19359+ r_flags |= 0x80; /* setting the copy bit */ 19360+ /* says we can convert */ 19361+ /* to gotslot if needed */ 19362+ break; 19363+ case RELOC_32: 19364+ if (flag_want_pic && S_IS_EXTERNAL(fixP->fx_addsy)) { 19365+ r_symbolnum = fixP->fx_addsy->sy_number; 19366+ r_flags |= 8; /* set extern bit */ 19367+ } 19368+ break; 19369+ case RELOC_JMP_SLOT: 19370+ if (flag_want_pic) { 19371+ r_flags |= 0x20; /* set jmptable */ 19372+ r_flags &= ~0x08; /* clear extern bit */ 19373+ } 19374+ break; 19375+ case RELOC_JMP_TBL: 19376+ if (flag_want_pic) { 19377+ r_flags |= 0x20; /* set jmptable */ 19378+ r_flags |= 0x08; /* set extern bit */ 19379+ } 19380+ break; 19381+ case RELOC_GLOB_DAT: 19382+ if (flag_want_pic) { 19383+ r_flags |= 0x10; /* set baserel bit */ 19384+ r_symbolnum = fixP->fx_addsy->sy_number; 19385+ if (S_IS_EXTERNAL(fixP->fx_addsy)) 19386+ r_flags |= 8; /* set extern bit */ 19387+ } 19388+ break; 19389+ } 19390+ 19391+ where[4] = (r_symbolnum >> 0) & 0xff; 19392+ where[5] = (r_symbolnum >> 8) & 0xff; 19393+ where[6] = (r_symbolnum >> 16) & 0xff; 19394+ where[7] = r_flags; 19395+} 19396+#endif /* !BFD_ASSEMBLER */ 19397+#endif /* OBJ_AOUT */ 19398+ 19399+/* 19400+ * BUGS, GRIPES, APOLOGIA, etc. 19401+ * 19402+ * The opcode table 'votstrs' needs to be sorted on opcode frequency. 19403+ * That is, AFTER we hash it with hash_...(), we want most-used opcodes 19404+ * to come out of the hash table faster. 19405+ * 19406+ * I am sorry to inflict yet another VAX assembler on the world, but 19407+ * RMS says we must do everything from scratch, to prevent pin-heads 19408+ * restricting this software. 19409+ */ 19410+ 19411+/* 19412+ * This is a vaguely modular set of routines in C to parse VAX 19413+ * assembly code using DEC mnemonics. It is NOT un*x specific. 19414+ * 19415+ * The idea here is that the assembler has taken care of all: 19416+ * labels 19417+ * macros 19418+ * listing 19419+ * pseudo-ops 19420+ * line continuation 19421+ * comments 19422+ * condensing any whitespace down to exactly one space 19423+ * and all we have to do is parse 1 line into a vax instruction 19424+ * partially formed. We will accept a line, and deliver: 19425+ * an error message (hopefully empty) 19426+ * a skeleton VAX instruction (tree structure) 19427+ * textual pointers to all the operand expressions 19428+ * a warning message that notes a silly operand (hopefully empty) 19429+ */ 19430+ 19431+/* 19432+ * E D I T H I S T O R Y 19433+ * 19434+ * 17may86 Dean Elsner. Bug if line ends immediately after opcode. 19435+ * 30apr86 Dean Elsner. New vip_op() uses arg block so change call. 19436+ * 6jan86 Dean Elsner. Crock vip_begin() to call vip_op_defaults(). 19437+ * 2jan86 Dean Elsner. Invent synthetic opcodes. 19438+ * Widen vax_opcodeT to 32 bits. Use a bit for VIT_OPCODE_SYNTHETIC, 19439+ * which means this is not a real opcode, it is like a macro; it will 19440+ * be relax()ed into 1 or more instructions. 19441+ * Use another bit for VIT_OPCODE_SPECIAL if the op-code is not optimised 19442+ * like a regular branch instruction. Option added to vip_begin(): 19443+ * exclude synthetic opcodes. Invent synthetic_votstrs[]. 19444+ * 31dec85 Dean Elsner. Invent vit_opcode_nbytes. 19445+ * Also make vit_opcode into a char[]. We now have n-byte vax opcodes, 19446+ * so caller's don't have to know the difference between a 1-byte & a 19447+ * 2-byte op-code. Still need vax_opcodeT concept, so we know how 19448+ * big an object must be to hold an op.code. 19449+ * 30dec85 Dean Elsner. Widen typedef vax_opcodeT in "vax-inst.h" 19450+ * because vax opcodes may be 16 bits. Our crufty C compiler was 19451+ * happily initialising 8-bit vot_codes with 16-bit numbers! 19452+ * (Wouldn't the 'phone company like to compress data so easily!) 19453+ * 29dec85 Dean Elsner. New static table vax_operand_width_size[]. 19454+ * Invented so we know hw many bytes a "I^#42" needs in its immediate 19455+ * operand. Revised struct vop in "vax-inst.h": explicitly include 19456+ * byte length of each operand, and it's letter-code datum type. 19457+ * 17nov85 Dean Elsner. Name Change. 19458+ * Due to ar(1) truncating names, we learned the hard way that 19459+ * "vax-inst-parse.c" -> "vax-inst-parse." dropping the "o" off 19460+ * the archived object name. SO... we shortened the name of this 19461+ * source file, and changed the makefile. 19462+ */ 19463+ 19464 /* Parse a vax operand in DEC assembler notation. 19465 For speed, expect a string of whitespace to be reduced to a single ' '. 19466 This is the case for GNU AS, and is easy for other DEC-compatible 19467@@ -3150,7 +3302,7 @@ 19468 if (flag_want_pic && operandP->vop_mode == 8 19469 && this_add_symbol != NULL) 19470 { 19471- as_warn (_("Symbol %s used as immediate operand in PIC mode."), 19472+ as_warn (_("Symbol '%s' used as immediate operand in PIC mode."), 19473 S_GET_NAME (this_add_symbol)); 19474 } 19475 #endif 19476@@ -3226,7 +3378,15 @@ 19477 length = 4; 19478 } 19479 } 19480+#ifdef OBJ_ELF 19481+ if (flag_want_pic && this_add_symbol != NULL) 19482+ { 19483+ as_warn (_("Symbol '%s' used as displacement in PIC mode."), 19484+ S_GET_NAME (this_add_symbol)); 19485+ } 19486+#endif 19487 p = frag_more (1 + length); 19488+ know (operandP->vop_reg != 0xf); 19489 know (operandP->vop_reg >= 0); 19490 p[0] = operandP->vop_reg 19491 | ((at | "?\12\14?\16"[length]) << 4); 19492@@ -3411,3 +3571,38 @@ 19493 { 19494 return vax_md_atof (type, litP, sizeP); 19495 } 19496+ 19497+void 19498+vax_cfi_frame_initial_instructions (void) 19499+{ 19500+ cfi_add_CFA_def_cfa (14, 0); 19501+} 19502+ 19503+int 19504+tc_vax_regname_to_dw2regnum (char *regname) 19505+{ 19506+ unsigned int i; 19507+ static const struct { char *name; int dw2regnum; } regnames[] = 19508+ { 19509+ { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 }, 19510+ { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, 19511+ { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, 19512+ { "ap", 12 }, { "fp", 13 }, { "sp", 14 }, { "pc", 15 }, 19513+ { "psw", 16 }, 19514+ }; 19515+ 19516+ for (i = 0; i < ARRAY_SIZE (regnames); ++i) 19517+ if (strcmp (regnames[i].name, regname) == 0) 19518+ return regnames[i].dw2regnum; 19519+ 19520+ return -1; 19521+} 19522+ 19523+void 19524+vax_cfi_emit_pcrel_expr (expressionS *expP, unsigned int nbytes) 19525+{ 19526+ vax_cons_special_reloc = "pcrel"; 19527+ expP->X_add_number += nbytes; 19528+ emit_expr (expP, nbytes); 19529+ vax_cons_special_reloc = NULL; 19530+} 19531diff -rNU3 dist.orig/gas/config/tc-vax.h dist/gas/config/tc-vax.h 19532--- dist.orig/gas/config/tc-vax.h 2007-07-03 13:01:05.000000000 +0200 19533+++ dist/gas/config/tc-vax.h 2015-10-18 13:11:13.000000000 +0200 19534@@ -71,9 +71,17 @@ 19535 == S_GET_SEGMENT ((FIX)->fx_addsy))) \ 19536 || S_IS_LOCAL ((FIX)->fx_addsy))) 19537 19538-/* 19539- * Local Variables: 19540- * comment-column: 0 19541- * fill-column: 131 19542- * End: 19543- */ 19544+#define TARGET_USE_CFIPOP 1 19545+ 19546+#define tc_cfi_frame_initial_instructions vax_cfi_frame_initial_instructions 19547+extern void vax_cfi_frame_initial_instructions (void); 19548+ 19549+#define tc_regname_to_dw2regnum tc_vax_regname_to_dw2regnum 19550+extern int tc_vax_regname_to_dw2regnum (char *); 19551+ 19552+#define tc_cfi_emit_pcrel_expr vax_cfi_emit_pcrel_expr 19553+extern void vax_cfi_emit_pcrel_expr (expressionS *, unsigned int); 19554+ 19555+#define DWARF2_LINE_MIN_INSN_LENGTH 1 19556+#define DWARF2_DEFAULT_RETURN_COLUMN 15 19557+#define DWARF2_CIE_DATA_ALIGNMENT -4 19558diff -rNU3 dist.orig/gas/config/te-armnbsd.h dist/gas/config/te-armnbsd.h 19559--- dist.orig/gas/config/te-armnbsd.h 1970-01-01 01:00:00.000000000 +0100 19560+++ dist/gas/config/te-armnbsd.h 2015-10-18 13:11:13.000000000 +0200 19561@@ -0,0 +1,22 @@ 19562+/* Copyright 2004, 2005, 2007, 2009 Free Software Foundation, Inc. 19563+ 19564+ This file is part of GAS, the GNU Assembler. 19565+ 19566+ GAS is free software; you can redistribute it and/or modify 19567+ it under the terms of the GNU General Public License as 19568+ published by the Free Software Foundation; either version 3, 19569+ or (at your option) any later version. 19570+ 19571+ GAS is distributed in the hope that it will be useful, but 19572+ WITHOUT ANY WARRANTY; without even the implied warranty of 19573+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 19574+ the GNU General Public License for more details. 19575+ 19576+ You should have received a copy of the GNU General Public License 19577+ along with GAS; see the file COPYING. If not, write to the Free 19578+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19579+ 02110-1301, USA. */ 19580+ 19581+#include "te-nbsd.h" 19582+ 19583+#define CPU_DEFAULT ARM_ARCH_V4 19584diff -rNU3 dist.orig/gas/config/te-armnbsdeabi.h dist/gas/config/te-armnbsdeabi.h 19585--- dist.orig/gas/config/te-armnbsdeabi.h 1970-01-01 01:00:00.000000000 +0100 19586+++ dist/gas/config/te-armnbsdeabi.h 2015-10-18 13:11:13.000000000 +0200 19587@@ -0,0 +1,25 @@ 19588+/* Copyright 2004, 2005, 2007, 2009 Free Software Foundation, Inc. 19589+ 19590+ This file is part of GAS, the GNU Assembler. 19591+ 19592+ GAS is free software; you can redistribute it and/or modify 19593+ it under the terms of the GNU General Public License as 19594+ published by the Free Software Foundation; either version 3, 19595+ or (at your option) any later version. 19596+ 19597+ GAS is distributed in the hope that it will be useful, but 19598+ WITHOUT ANY WARRANTY; without even the implied warranty of 19599+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 19600+ the GNU General Public License for more details. 19601+ 19602+ You should have received a copy of the GNU General Public License 19603+ along with GAS; see the file COPYING. If not, write to the Free 19604+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19605+ 02110-1301, USA. */ 19606+ 19607+#include "te-nbsd.h" 19608+ 19609+/* The EABI requires the use of VFP. */ 19610+#define CPU_DEFAULT ARM_ARCH_V5TEJ 19611+#define FPU_DEFAULT FPU_ARCH_VFP 19612+#define EABI_DEFAULT EF_ARM_EABI_VER5 19613diff -rNU3 dist.orig/gas/config/te-armnbsdeabihf.h dist/gas/config/te-armnbsdeabihf.h 19614--- dist.orig/gas/config/te-armnbsdeabihf.h 1970-01-01 01:00:00.000000000 +0100 19615+++ dist/gas/config/te-armnbsdeabihf.h 2015-10-18 13:11:13.000000000 +0200 19616@@ -0,0 +1,25 @@ 19617+/* Copyright 2004, 2005, 2007, 2009 Free Software Foundation, Inc. 19618+ 19619+ This file is part of GAS, the GNU Assembler. 19620+ 19621+ GAS is free software; you can redistribute it and/or modify 19622+ it under the terms of the GNU General Public License as 19623+ published by the Free Software Foundation; either version 3, 19624+ or (at your option) any later version. 19625+ 19626+ GAS is distributed in the hope that it will be useful, but 19627+ WITHOUT ANY WARRANTY; without even the implied warranty of 19628+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 19629+ the GNU General Public License for more details. 19630+ 19631+ You should have received a copy of the GNU General Public License 19632+ along with GAS; see the file COPYING. If not, write to the Free 19633+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19634+ 02110-1301, USA. */ 19635+ 19636+#include "te-nbsd.h" 19637+ 19638+/* The EABI requires the use of VFP. */ 19639+#define CPU_DEFAULT ARM_ARCH_V5TEJ 19640+#define FPU_DEFAULT FPU_ARCH_VFP_V2 19641+#define EABI_DEFAULT EF_ARM_EABI_VER5 19642diff -rNU3 dist.orig/gas/config/vax-inst.h dist/gas/config/vax-inst.h 19643--- dist.orig/gas/config/vax-inst.h 2009-09-02 09:24:21.000000000 +0200 19644+++ dist/gas/config/vax-inst.h 2015-10-18 13:11:13.000000000 +0200 19645@@ -66,6 +66,8 @@ 19646 #define VAX_WIDEN_WORD (0x20) /* Add this to byte branch to get word br. */ 19647 #define VAX_WIDEN_LONG (0x6) /* Add this to byte branch to get long jmp.*/ 19648 /* Needs VAX_PC_RELATIVE_MODE byte after it*/ 19649+#define VAX_CALLS (0xFB) /* Call with arg list on stack */ 19650+#define VAX_CALLG (0xFA) /* Call with arg list in memory */ 19651 19652 struct vit /* vax instruction tree */ 19653 { 19654diff -rNU3 dist.orig/gas/configure dist/gas/configure 19655--- dist.orig/gas/configure 2012-06-18 06:43:06.000000000 +0200 19656+++ dist/gas/configure 2015-10-18 13:11:13.000000000 +0200 19657@@ -12146,7 +12146,7 @@ 19658 fi 19659 ;; 19660 19661- epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc) 19662+ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k | or1knd) 19663 using_cgen=yes 19664 ;; 19665 19666@@ -12340,6 +12340,8 @@ 19667 cgen_cpu_prefix="" 19668 if test $using_cgen = yes ; then 19669 case ${target_cpu} in 19670+ or1knd) 19671+ cgen_cpu_prefix=or1k ;; 19672 *) cgen_cpu_prefix=${target_cpu} ;; 19673 esac 19674 19675diff -rNU3 dist.orig/gas/configure.in dist/gas/configure.in 19676--- dist.orig/gas/configure.in 2012-11-05 17:27:44.000000000 +0100 19677+++ dist/gas/configure.in 2015-10-18 13:11:13.000000000 +0200 19678@@ -314,7 +314,7 @@ 19679 fi 19680 ;; 19681 19682- epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc) 19683+ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k | or1knd) 19684 using_cgen=yes 19685 ;; 19686 19687@@ -504,6 +504,8 @@ 19688 cgen_cpu_prefix="" 19689 if test $using_cgen = yes ; then 19690 case ${target_cpu} in 19691+ or1knd) 19692+ cgen_cpu_prefix=or1k ;; 19693 *) cgen_cpu_prefix=${target_cpu} ;; 19694 esac 19695 AC_SUBST(cgen_cpu_prefix) 19696diff -rNU3 dist.orig/gas/configure.tgt dist/gas/configure.tgt 19697--- dist.orig/gas/configure.tgt 2012-09-04 14:53:45.000000000 +0200 19698+++ dist/gas/configure.tgt 2015-10-18 13:11:13.000000000 +0200 19699@@ -51,7 +51,7 @@ 19700 m32c) cpu_type=m32c endian=little ;; 19701 m32r) cpu_type=m32r endian=big ;; 19702 m32rle) cpu_type=m32r endian=little ;; 19703- m5200) cpu_type=m68k ;; 19704+ m5200|m5407) cpu_type=m68k ;; 19705 m68008) cpu_type=m68k ;; 19706 m680[012346]0) cpu_type=m68k ;; 19707 m6811|m6812|m68hc12) cpu_type=m68hc11 ;; 19708@@ -61,11 +61,13 @@ 19709 mips*el) cpu_type=mips endian=little ;; 19710 mips*) cpu_type=mips endian=big ;; 19711 mt) cpu_type=mt endian=big ;; 19712- or32*) cpu_type=or32 endian=big ;; 19713+ or1k*) cpu_type=or1k endian=big ;; 19714 pjl*) cpu_type=pj endian=little ;; 19715 pj*) cpu_type=pj endian=big ;; 19716 powerpc*le*) cpu_type=ppc endian=little ;; 19717 powerpc*) cpu_type=ppc endian=big ;; 19718+ riscv*eb) cpu_type=riscv endian=big ;; 19719+ riscv*) cpu_type=riscv endian=little ;; 19720 rs6000*) cpu_type=ppc ;; 19721 rl78*) cpu_type=rl78 ;; 19722 rx) cpu_type=rx ;; 19723@@ -100,6 +102,7 @@ 19724 case ${generic_target} in 19725 aarch64*-*-elf) fmt=elf;; 19726 aarch64*-*-linux*) fmt=elf em=linux ;; 19727+ aarch64*-*-netbsd*) fmt=elf em=nbsd ;; 19728 19729 alpha-*-*vms*) fmt=evax ;; 19730 alpha-*-osf*) fmt=ecoff ;; 19731@@ -111,9 +114,11 @@ 19732 arc-*-elf*) fmt=elf ;; 19733 19734 arm-*-aout) fmt=aout ;; 19735- arm-*-coff) fmt=coff ;; 19736- arm-*-rtems*) fmt=elf ;; 19737- arm-*-elf) fmt=elf ;; 19738+ arm-*-coff | thumb-*-coff) fmt=coff ;; 19739+ arm-*-rtems* | thumb-*-rtems*) fmt=elf ;; 19740+ arm-*-elf | thumb-*-elf) fmt=elf ;; 19741+ arm-*-netbsdelf*-*eabihf*) fmt=elf em=armnbsdeabihf ;; 19742+ arm-*-netbsdelf*-*eabi*) fmt=elf em=armnbsdeabi ;; 19743 arm-*-eabi*) fmt=elf em=armeabi ;; 19744 arm-*-symbianelf*) fmt=elf em=symbian ;; 19745 arm-*-kaos*) fmt=elf ;; 19746@@ -124,8 +129,8 @@ 19747 arm-*-uclinux*eabi*) fmt=elf em=armlinuxeabi ;; 19748 arm-*-uclinux*) fmt=elf em=linux ;; 19749 arm-*-nacl*) fmt=elf em=nacl ;; 19750- arm-*-netbsdelf*) fmt=elf em=nbsd ;; 19751- arm-*-*n*bsd*) fmt=aout em=nbsd ;; 19752+ arm-*-netbsdelf*) fmt=elf em=armnbsd ;; 19753+ arm-*-*n*bsd*) fmt=aout em=armnbsd ;; 19754 arm-*-nto*) fmt=elf ;; 19755 arm-epoc-pe) fmt=coff em=epoc-pe ;; 19756 arm-wince-pe | arm-*-wince | arm*-*-mingw32ce* | arm*-*-cegcc*) 19757@@ -334,10 +339,9 @@ 19758 ns32k-pc532-lites*) fmt=aout em=nbsd532 ;; 19759 ns32k-*-*n*bsd*) fmt=aout em=nbsd532 ;; 19760 19761- openrisc-*-*) fmt=elf ;; 19762- 19763- or32-*-rtems*) fmt=elf ;; 19764- or32-*-elf) fmt=elf ;; 19765+ or1k-*-elf) fmt=elf ;; 19766+ or1k-*-linux*) fmt=elf em=linux ;; 19767+ or1k-*-netbsd*) fmt=elf em=nbsd ;; 19768 19769 pj*) fmt=elf ;; 19770 19771@@ -357,6 +361,11 @@ 19772 ppc-*-kaos*) fmt=elf ;; 19773 ppc-*-lynxos*) fmt=elf em=lynx ;; 19774 19775+ riscv*eb-*-linux*) fmt=elf endian=big em=linux ;; 19776+ riscv*eb-*-netbsd*) fmt=elf endian=big em=nbsd ;; 19777+ riscv*-*-linux*) fmt=elf endian=little em=linux ;; 19778+ riscv*-*-netbsd*) fmt=elf endian=little em=nbsd ;; 19779+ 19780 s390-*-linux-*) fmt=elf em=linux ;; 19781 s390-*-tpf*) fmt=elf ;; 19782 19783@@ -451,7 +460,7 @@ 19784 esac 19785 19786 case ${cpu_type} in 19787- aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k) 19788+ aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | riscv | sparc | z80 | z8k) 19789 bfd_gas=yes 19790 ;; 19791 esac 19792diff -rNU3 dist.orig/gas/doc/Makefile.am dist/gas/doc/Makefile.am 19793--- dist.orig/gas/doc/Makefile.am 2012-09-04 14:53:45.000000000 +0200 19794+++ dist/gas/doc/Makefile.am 2015-10-18 13:11:13.000000000 +0200 19795@@ -24,6 +24,8 @@ 19796 -I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc 19797 19798 asconfig.texi: $(CONFIG).texi 19799+ @echo "NOT REBUILDING $@" 19800+NetBSD_DISABLED_asconfig.text: 19801 rm -f asconfig.texi 19802 cp $(srcdir)/$(CONFIG).texi ./asconfig.texi 19803 chmod u+w ./asconfig.texi 19804@@ -103,6 +105,8 @@ 19805 # The sed command removes the no-adjust Nroff command so that 19806 # the man output looks standard. 19807 as.1: $(srcdir)/as.texinfo asconfig.texi $(CPU_DOCS) 19808+ @echo "NOT REBUILDING $@" 19809+NetBSD_DISABLED_as.1: 19810 touch $@ 19811 -$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod 19812 -($(POD2MAN) as.pod | \ 19813diff -rNU3 dist.orig/gas/doc/Makefile.in dist/gas/doc/Makefile.in 19814--- dist.orig/gas/doc/Makefile.in 2012-09-04 14:53:45.000000000 +0200 19815+++ dist/gas/doc/Makefile.in 2015-10-18 13:11:13.000000000 +0200 19816@@ -374,6 +374,8 @@ 19817 -rm -rf .libs _libs 19818 19819 as.info: as.texinfo $(as_TEXINFOS) 19820+ @echo "NOT REBUILDING $@" 19821+NetBSD_DISABLED_as.info: as.texinfo $(as_TEXINFOS) 19822 restore=: && backupdir="$(am__leading_dot)am$$$$" && \ 19823 rm -rf $$backupdir && mkdir $$backupdir && \ 19824 if ($(MAKEINFO) --version) >/dev/null 2>&1; then \ 19825@@ -756,6 +758,8 @@ 19826 19827 19828 asconfig.texi: $(CONFIG).texi 19829+ @echo "NOT REBUILDING $@" 19830+NetBSD_DISABLED_asconfig.texi: 19831 rm -f asconfig.texi 19832 cp $(srcdir)/$(CONFIG).texi ./asconfig.texi 19833 chmod u+w ./asconfig.texi 19834@@ -773,6 +777,8 @@ 19835 # The sed command removes the no-adjust Nroff command so that 19836 # the man output looks standard. 19837 as.1: $(srcdir)/as.texinfo asconfig.texi $(CPU_DOCS) 19838+ @echo "NOT REBUILDING $@" 19839+NetBSD_DISABLED_as.1: 19840 touch $@ 19841 -$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod 19842 -($(POD2MAN) as.pod | \ 19843diff -rNU3 dist.orig/gas/doc/as.info dist/gas/doc/as.info 19844--- dist.orig/gas/doc/as.info 2013-03-25 10:10:23.000000000 +0100 19845+++ dist/gas/doc/as.info 2015-10-18 13:11:13.000000000 +0200 19846@@ -22275,8 +22275,8 @@ 19847 * -g command line option, Alpha: Alpha Options. (line 47) 19848 * -G command line option, Alpha: Alpha Options. (line 53) 19849 * -G option (MIPS): MIPS Opts. (line 8) 19850-* -H option, VAX/VMS: VAX-Opts. (line 81) 19851 * -h option, VAX/VMS: VAX-Opts. (line 45) 19852+* -H option, VAX/VMS: VAX-Opts. (line 81) 19853 * -I PATH: I. (line 6) 19854 * -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 19855 * -Ip option, M32RX: M32R-Opts. (line 97) 19856@@ -22876,8 +22876,8 @@ 19857 * BSD syntax: PDP-11-Syntax. (line 6) 19858 * bss directive, i960: Directives-i960. (line 6) 19859 * bss directive, TIC54X: TIC54X-Directives. (line 29) 19860-* bss section <1>: bss. (line 6) 19861-* bss section: Ld Sections. (line 20) 19862+* bss section <1>: Ld Sections. (line 20) 19863+* bss section: bss. (line 6) 19864 * bug criteria: Bug Criteria. (line 6) 19865 * bug reports: Bug Reporting. (line 6) 19866 * bugs in assembler: Reporting Bugs. (line 6) 19867diff -rNU3 dist.orig/gas/doc/c-mips.texi dist/gas/doc/c-mips.texi 19868--- dist.orig/gas/doc/c-mips.texi 2012-09-04 16:16:07.000000000 +0200 19869+++ dist/gas/doc/c-mips.texi 2015-10-18 13:11:13.000000000 +0200 19870@@ -210,6 +210,14 @@ 19871 @itemx -mno-fix-vr4130 19872 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 19873 19874+@item -mfix-loongson2f-btb 19875+@itemx -mno-fix-loongson2f-btb 19876+Clear the Branch Target Buffer before any jump through a register. This 19877+option is intended to be used on kernel code for the Loongson 2F processor 19878+only; userland code compiled with this option will fault, and kernel code 19879+compiled with this option run on another processor than Loongson 2F will 19880+yield unpredictable results. 19881+ 19882 @item -mfix-24k 19883 @itemx -mno-fix-24k 19884 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. 19885diff -rNU3 dist.orig/gas/remap.c dist/gas/remap.c 19886--- dist.orig/gas/remap.c 2011-03-11 15:18:24.000000000 +0100 19887+++ dist/gas/remap.c 2015-10-18 13:11:13.000000000 +0200 19888@@ -84,8 +84,8 @@ 19889 return xstrdup (filename); 19890 name = filename + map->old_len; 19891 name_len = strlen (name) + 1; 19892- s = (char *) alloca (name_len + map->new_len); 19893+ s = (char *) xmalloc (name_len + map->new_len); 19894 memcpy (s, map->new_prefix, map->new_len); 19895 memcpy (s + map->new_len, name, name_len); 19896- return xstrdup (s); 19897+ return s; 19898 } 19899diff -rNU3 dist.orig/gprof/corefile.c dist/gprof/corefile.c 19900--- dist.orig/gprof/corefile.c 2012-03-06 14:54:59.000000000 +0100 19901+++ dist/gprof/corefile.c 2015-10-18 13:11:17.000000000 +0200 19902@@ -30,6 +30,8 @@ 19903 #include "corefile.h" 19904 #include "safe-ctype.h" 19905 19906+#include <stdlib.h> 19907+ 19908 bfd *core_bfd; 19909 static int core_num_syms; 19910 static asymbol **core_syms; 19911diff -rNU3 dist.orig/gprof/gprof.c dist/gprof/gprof.c 19912--- dist.orig/gprof/gprof.c 2009-06-12 17:33:30.000000000 +0200 19913+++ dist/gprof/gprof.c 2015-10-18 13:11:17.000000000 +0200 19914@@ -47,6 +47,8 @@ 19915 19916 static void usage (FILE *, int) ATTRIBUTE_NORETURN; 19917 19918+#include <stdlib.h> 19919+ 19920 const char * whoami; 19921 const char * function_mapping_file; 19922 static const char * external_symbol_table; 19923diff -rNU3 dist.orig/gprof/gprof.info dist/gprof/gprof.info 19924--- dist.orig/gprof/gprof.info 2012-11-13 15:19:35.000000000 +0100 19925+++ dist/gprof/gprof.info 2015-10-18 13:11:17.000000000 +0200 19926@@ -2441,34 +2441,34 @@ 19927 19928 Tag Table: 19929 Node: Top777 19930-Node: Introduction2102 19931-Node: Compiling4594 19932-Node: Executing8650 19933-Node: Invoking11438 19934-Node: Output Options12853 19935-Node: Analysis Options19942 19936-Node: Miscellaneous Options23640 19937-Node: Deprecated Options24895 19938-Node: Symspecs26964 19939-Node: Output28790 19940-Node: Flat Profile29830 19941-Node: Call Graph34783 19942-Node: Primary38015 19943-Node: Callers40603 19944-Node: Subroutines42720 19945-Node: Cycles44561 19946-Node: Line-by-line51338 19947-Node: Annotated Source55411 19948-Node: Inaccuracy58410 19949-Node: Sampling Error58668 19950-Node: Assumptions61572 19951-Node: How do I?63042 19952-Node: Incompatibilities64596 19953-Node: Details66090 19954-Node: Implementation66483 19955-Node: File Format72380 19956-Node: Internals76670 19957-Node: Debugging85165 19958-Node: GNU Free Documentation License86766 19959+Node: Introduction2103 19960+Node: Compiling4595 19961+Node: Executing8651 19962+Node: Invoking11439 19963+Node: Output Options12854 19964+Node: Analysis Options19943 19965+Node: Miscellaneous Options23641 19966+Node: Deprecated Options24896 19967+Node: Symspecs26965 19968+Node: Output28791 19969+Node: Flat Profile29831 19970+Node: Call Graph34784 19971+Node: Primary38016 19972+Node: Callers40604 19973+Node: Subroutines42721 19974+Node: Cycles44562 19975+Node: Line-by-line51339 19976+Node: Annotated Source55412 19977+Node: Inaccuracy58411 19978+Node: Sampling Error58669 19979+Node: Assumptions61573 19980+Node: How do I?63043 19981+Node: Incompatibilities64597 19982+Node: Details66091 19983+Node: Implementation66484 19984+Node: File Format72381 19985+Node: Internals76671 19986+Node: Debugging85166 19987+Node: GNU Free Documentation License86767 19988 19989 End Tag Table 19990diff -rNU3 dist.orig/include/bfdlink.h dist/include/bfdlink.h 19991--- dist.orig/include/bfdlink.h 2012-04-09 18:27:18.000000000 +0200 19992+++ dist/include/bfdlink.h 2015-10-18 13:11:17.000000000 +0200 19993@@ -435,6 +435,10 @@ 19994 option). If this is NULL, no symbols are being wrapped. */ 19995 struct bfd_hash_table *wrap_hash; 19996 19997+ /* Hash table of symbols which may be left unresolved during 19998+ a link. If this is NULL, no symbols can be left unresolved. */ 19999+ struct bfd_hash_table *ignore_hash; 20000+ 20001 /* The output BFD. */ 20002 bfd *output_bfd; 20003 20004diff -rNU3 dist.orig/include/dis-asm.h dist/include/dis-asm.h 20005--- dist.orig/include/dis-asm.h 2012-09-04 14:53:46.000000000 +0200 20006+++ dist/include/dis-asm.h 2015-10-18 13:11:17.000000000 +0200 20007@@ -226,7 +226,6 @@ 20008 extern int print_insn_bfin (bfd_vma, disassemble_info *); 20009 extern int print_insn_big_arm (bfd_vma, disassemble_info *); 20010 extern int print_insn_big_mips (bfd_vma, disassemble_info *); 20011-extern int print_insn_big_or32 (bfd_vma, disassemble_info *); 20012 extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); 20013 extern int print_insn_big_score (bfd_vma, disassemble_info *); 20014 extern int print_insn_cr16 (bfd_vma, disassemble_info *); 20015@@ -253,7 +252,6 @@ 20016 extern int print_insn_iq2000 (bfd_vma, disassemble_info *); 20017 extern int print_insn_little_arm (bfd_vma, disassemble_info *); 20018 extern int print_insn_little_mips (bfd_vma, disassemble_info *); 20019-extern int print_insn_little_or32 (bfd_vma, disassemble_info *); 20020 extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); 20021 extern int print_insn_little_score (bfd_vma, disassemble_info *); 20022 extern int print_insn_lm32 (bfd_vma, disassemble_info *); 20023@@ -275,9 +273,10 @@ 20024 extern int print_insn_msp430 (bfd_vma, disassemble_info *); 20025 extern int print_insn_mt (bfd_vma, disassemble_info *); 20026 extern int print_insn_ns32k (bfd_vma, disassemble_info *); 20027-extern int print_insn_openrisc (bfd_vma, disassemble_info *); 20028+extern int print_insn_or1k (bfd_vma, disassemble_info *); 20029 extern int print_insn_pdp11 (bfd_vma, disassemble_info *); 20030 extern int print_insn_pj (bfd_vma, disassemble_info *); 20031+extern int print_insn_riscv (bfd_vma, disassemble_info *); 20032 extern int print_insn_rs6000 (bfd_vma, disassemble_info *); 20033 extern int print_insn_s390 (bfd_vma, disassemble_info *); 20034 extern int print_insn_sh (bfd_vma, disassemble_info *); 20035diff -rNU3 dist.orig/include/elf/common.h dist/include/elf/common.h 20036--- dist.orig/include/elf/common.h 2012-09-04 14:53:47.000000000 +0200 20037+++ dist/include/elf/common.h 2015-10-18 13:11:17.000000000 +0200 20038@@ -194,7 +194,7 @@ 20039 #define EM_MN10300 89 /* Matsushita MN10300 */ 20040 #define EM_MN10200 90 /* Matsushita MN10200 */ 20041 #define EM_PJ 91 /* picoJava */ 20042-#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ 20043+#define EM_OR1K 92 /* OpenRISC 1000 32-bit embedded processor */ 20044 #define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ 20045 #define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ 20046 #define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor */ 20047@@ -298,6 +298,7 @@ 20048 #define EM_TILEGX 191 /* Tilera TILE-Gx multicore architecture family */ 20049 #define EM_RL78 197 /* Renesas RL78 family. */ 20050 #define EM_78K0R 199 /* Renesas 78K0R. */ 20051+#define EM_RISCV 243 /* RISC-V */ 20052 20053 /* If it is necessary to assign new unofficial EM_* values, please pick large 20054 random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision 20055@@ -357,9 +358,6 @@ 20056 /* Ubicom IP2xxx; Written in the absense of an ABI. */ 20057 #define EM_IP2K_OLD 0x8217 20058 20059-/* (Deprecated) Temporary number for the OpenRISC processor. */ 20060-#define EM_OR32 0x8472 20061- 20062 /* Cygnus PowerPC ELF backend. Written in the absence of an ABI. */ 20063 #define EM_CYGNUS_POWERPC 0x9025 20064 20065@@ -607,6 +605,16 @@ 20066 /* Values for NetBSD .note.netbsd.ident notes. Note name is "NetBSD". */ 20067 20068 #define NT_NETBSD_IDENT 1 20069+#define NT_NETBSD_MARCH 5 20070+ 20071+/* Values for NetBSD .note.netbsd.ident notes. Note name is "PaX". */ 20072+#define NT_NETBSD_PAX 3 20073+#define NT_NETBSD_PAX_MPROTECT 0x01 /* Force enable Mprotect */ 20074+#define NT_NETBSD_PAX_NOMPROTECT 0x02 /* Force disable Mprotect */ 20075+#define NT_NETBSD_PAX_GUARD 0x04 /* Force enable Segvguard */ 20076+#define NT_NETBSD_PAX_NOGUARD 0x08 /* Force disable Servguard */ 20077+#define NT_NETBSD_PAX_ASLR 0x10 /* Force enable ASLR */ 20078+#define NT_NETBSD_PAX_NOASLR 0x20 /* Force disable ASLR */ 20079 20080 /* Values for OpenBSD .note.openbsd.ident notes. Note name is "OpenBSD". */ 20081 20082diff -rNU3 dist.orig/include/elf/openrisc.h dist/include/elf/openrisc.h 20083--- dist.orig/include/elf/openrisc.h 2010-04-15 12:26:08.000000000 +0200 20084+++ dist/include/elf/openrisc.h 1970-01-01 01:00:00.000000000 +0100 20085@@ -1,39 +0,0 @@ 20086-/* OpenRISC ELF support for BFD. 20087- Copyright 2001, 2010 Free Software Foundation, Inc. 20088- 20089- This file is part of BFD, the Binary File Descriptor library. 20090- 20091- This program is free software; you can redistribute it and/or modify 20092- it under the terms of the GNU General Public License as published by 20093- the Free Software Foundation; either version 3 of the License, or 20094- (at your option) any later version. 20095- 20096- This program is distributed in the hope that it will be useful, 20097- but WITHOUT ANY WARRANTY; without even the implied warranty of 20098- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20099- GNU General Public License for more details. 20100- 20101- You should have received a copy of the GNU General Public License 20102- along with this program; if not, write to the Free Software Foundation, 20103- Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 20104- 20105-#ifndef _ELF_OPENRISC_H 20106-#define _ELF_OPENRISC_H 20107- 20108-#include "elf/reloc-macros.h" 20109- 20110-/* Relocations. */ 20111-START_RELOC_NUMBERS (elf_openrisc_reloc_type) 20112- RELOC_NUMBER (R_OPENRISC_NONE, 0) 20113- RELOC_NUMBER (R_OPENRISC_INSN_REL_26, 1) 20114- RELOC_NUMBER (R_OPENRISC_INSN_ABS_26, 2) 20115- RELOC_NUMBER (R_OPENRISC_LO_16_IN_INSN, 3) 20116- RELOC_NUMBER (R_OPENRISC_HI_16_IN_INSN, 4) 20117- RELOC_NUMBER (R_OPENRISC_8, 5) 20118- RELOC_NUMBER (R_OPENRISC_16, 6) 20119- RELOC_NUMBER (R_OPENRISC_32, 7) 20120- RELOC_NUMBER (R_OPENRISC_GNU_VTINHERIT, 8) 20121- RELOC_NUMBER (R_OPENRISC_GNU_VTENTRY, 9) 20122-END_RELOC_NUMBERS (R_OPENRISC_max) 20123- 20124-#endif /* _ELF_OPENRISC_H */ 20125diff -rNU3 dist.orig/include/elf/or1k.h dist/include/elf/or1k.h 20126--- dist.orig/include/elf/or1k.h 1970-01-01 01:00:00.000000000 +0100 20127+++ dist/include/elf/or1k.h 2015-10-18 13:11:17.000000000 +0200 20128@@ -0,0 +1,65 @@ 20129+/* Or1k ELF support for BFD. 20130+ Copyright 2001-2014 Free Software Foundation, Inc. 20131+ 20132+ This file is part of BFD, the Binary File Descriptor library. 20133+ 20134+ This program is free software; you can redistribute it and/or modify 20135+ it under the terms of the GNU General Public License as published by 20136+ the Free Software Foundation; either version 3 of the License, or 20137+ (at your option) any later version. 20138+ 20139+ This program is distributed in the hope that it will be useful, 20140+ but WITHOUT ANY WARRANTY; without even the implied warranty of 20141+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20142+ GNU General Public License for more details. 20143+ 20144+ You should have received a copy of the GNU General Public License 20145+ along with this program; if not, see <http://www.gnu.org/licenses/> */ 20146+ 20147+#ifndef _ELF_OR1K_H 20148+#define _ELF_OR1K_H 20149+ 20150+#include "elf/reloc-macros.h" 20151+ 20152+/* Relocations. */ 20153+START_RELOC_NUMBERS (elf_or1k_reloc_type) 20154+ RELOC_NUMBER (R_OR1K_NONE, 0) 20155+ RELOC_NUMBER (R_OR1K_32, 1) 20156+ RELOC_NUMBER (R_OR1K_16, 2) 20157+ RELOC_NUMBER (R_OR1K_8, 3) 20158+ RELOC_NUMBER (R_OR1K_LO_16_IN_INSN, 4) 20159+ RELOC_NUMBER (R_OR1K_HI_16_IN_INSN, 5) 20160+ RELOC_NUMBER (R_OR1K_INSN_REL_26, 6) 20161+ RELOC_NUMBER (R_OR1K_GNU_VTENTRY, 7) 20162+ RELOC_NUMBER (R_OR1K_GNU_VTINHERIT, 8) 20163+ RELOC_NUMBER (R_OR1K_32_PCREL, 9) 20164+ RELOC_NUMBER (R_OR1K_16_PCREL, 10) 20165+ RELOC_NUMBER (R_OR1K_8_PCREL, 11) 20166+ RELOC_NUMBER (R_OR1K_GOTPC_HI16, 12) 20167+ RELOC_NUMBER (R_OR1K_GOTPC_LO16, 13) 20168+ RELOC_NUMBER (R_OR1K_GOT16, 14) 20169+ RELOC_NUMBER (R_OR1K_PLT26, 15) 20170+ RELOC_NUMBER (R_OR1K_GOTOFF_HI16, 16) 20171+ RELOC_NUMBER (R_OR1K_GOTOFF_LO16, 17) 20172+ RELOC_NUMBER (R_OR1K_COPY, 18) 20173+ RELOC_NUMBER (R_OR1K_GLOB_DAT, 19) 20174+ RELOC_NUMBER (R_OR1K_JMP_SLOT, 20) 20175+ RELOC_NUMBER (R_OR1K_RELATIVE, 21) 20176+ RELOC_NUMBER (R_OR1K_TLS_GD_HI16, 22) 20177+ RELOC_NUMBER (R_OR1K_TLS_GD_LO16, 23) 20178+ RELOC_NUMBER (R_OR1K_TLS_LDM_HI16, 24) 20179+ RELOC_NUMBER (R_OR1K_TLS_LDM_LO16, 25) 20180+ RELOC_NUMBER (R_OR1K_TLS_LDO_HI16, 26) 20181+ RELOC_NUMBER (R_OR1K_TLS_LDO_LO16, 27) 20182+ RELOC_NUMBER (R_OR1K_TLS_IE_HI16, 28) 20183+ RELOC_NUMBER (R_OR1K_TLS_IE_LO16, 29) 20184+ RELOC_NUMBER (R_OR1K_TLS_LE_HI16, 30) 20185+ RELOC_NUMBER (R_OR1K_TLS_LE_LO16, 31) 20186+ RELOC_NUMBER (R_OR1K_TLS_TPOFF, 32) 20187+ RELOC_NUMBER (R_OR1K_TLS_DTPOFF, 33) 20188+ RELOC_NUMBER (R_OR1K_TLS_DTPMOD, 34) 20189+END_RELOC_NUMBERS (R_OR1K_max) 20190+ 20191+#define EF_OR1K_NODELAY (1UL << 0) 20192+ 20193+#endif /* _ELF_OR1K_H */ 20194diff -rNU3 dist.orig/include/elf/or32.h dist/include/elf/or32.h 20195--- dist.orig/include/elf/or32.h 2010-05-18 05:31:06.000000000 +0200 20196+++ dist/include/elf/or32.h 1970-01-01 01:00:00.000000000 +0100 20197@@ -1,56 +0,0 @@ 20198-/* OR1K ELF support for BFD. Derived from ppc.h. 20199- Copyright (C) 2002, 2010 Free Software Foundation, Inc. 20200- Contributed by Ivan Guzvinec <ivang@opencores.org> 20201- 20202- This file is part of BFD, the Binary File Descriptor library. 20203- 20204- This program is free software; you can redistribute it and/or modify 20205- it under the terms of the GNU General Public License as published by 20206- the Free Software Foundation; either version 3 of the License, or 20207- (at your option) any later version. 20208- 20209- This program is distributed in the hope that it will be useful, 20210- but WITHOUT ANY WARRANTY; without even the implied warranty of 20211- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20212- GNU General Public License for more details. 20213- 20214- You should have received a copy of the GNU General Public License 20215- along with this program; if not, write to the Free Software 20216- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20217- MA 02110-1301, USA. */ 20218- 20219-#ifndef _ELF_OR1K_H 20220-#define _ELF_OR1K_H 20221- 20222-#include "elf/reloc-macros.h" 20223- 20224-/* Relocations. */ 20225-START_RELOC_NUMBERS (elf_or32_reloc_type) 20226- RELOC_NUMBER (R_OR32_NONE, 0) 20227- RELOC_NUMBER (R_OR32_32, 1) 20228- RELOC_NUMBER (R_OR32_16, 2) 20229- RELOC_NUMBER (R_OR32_8, 3) 20230- RELOC_NUMBER (R_OR32_CONST, 4) 20231- RELOC_NUMBER (R_OR32_CONSTH, 5) 20232- RELOC_NUMBER (R_OR32_JUMPTARG, 6) 20233- RELOC_NUMBER (R_OR32_GNU_VTENTRY, 7) 20234- RELOC_NUMBER (R_OR32_GNU_VTINHERIT, 8) 20235-END_RELOC_NUMBERS (R_OR32_max) 20236- 20237-/* Four bit OR32 machine type field. */ 20238-#define EF_OR32_MACH 0x0000000f 20239- 20240-/* Various CPU types. */ 20241-#define E_OR32_MACH_BASE 0x00000000 20242-#define E_OR32_MACH_UNUSED1 0x00000001 20243-#define E_OR32_MACH_UNUSED2 0x00000002 20244-#define E_OR32_MACH_UNUSED4 0x00000003 20245- 20246-/* Processor specific section headers, sh_type field */ 20247-#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ 20248- entries in this section \ 20249- based on the address \ 20250- specified in the associated \ 20251- symbol table entry. */ 20252- 20253-#endif /* _ELF_OR1K_H */ 20254diff -rNU3 dist.orig/include/elf/riscv.h dist/include/elf/riscv.h 20255--- dist.orig/include/elf/riscv.h 1970-01-01 01:00:00.000000000 +0100 20256+++ dist/include/elf/riscv.h 2015-10-18 13:11:17.000000000 +0200 20257@@ -0,0 +1,138 @@ 20258+/* RISC-V ELF support for BFD. 20259+ Copyright 2011-2014 Free Software Foundation, Inc. 20260+ 20261+ Contributed by Andrw Waterman <waterman@cs.berkeley.edu> at UC Berkeley. 20262+ Based on MIPS ELF support for BFD, by Ian Lance Taylor. 20263+ 20264+ This file is part of BFD, the Binary File Descriptor library. 20265+ 20266+ This program is free software; you can redistribute it and/or modify 20267+ it under the terms of the GNU General Public License as published by 20268+ the Free Software Foundation; either version 3 of the License, or 20269+ (at your option) any later version. 20270+ 20271+ This program is distributed in the hope that it will be useful, 20272+ but WITHOUT ANY WARRANTY; without even the implied warranty of 20273+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20274+ GNU General Public License for more details. 20275+ 20276+ You should have received a copy of the GNU General Public License 20277+ along with this program; if not, write to the Free Software 20278+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20279+ MA 02110-1301, USA. */ 20280+ 20281+/* This file holds definitions specific to the RISCV ELF ABI. Note 20282+ that most of this is not actually implemented by BFD. */ 20283+ 20284+#ifndef _ELF_RISCV_H 20285+#define _ELF_RISCV_H 20286+ 20287+#include "elf/reloc-macros.h" 20288+ 20289+/* Relocation types. */ 20290+START_RELOC_NUMBERS (elf_riscv_reloc_type) 20291+ /* Relocation types used by the dynamic linker. */ 20292+ RELOC_NUMBER (R_RISCV_NONE, 0) 20293+ RELOC_NUMBER (R_RISCV_32, 1) 20294+ RELOC_NUMBER (R_RISCV_64, 2) 20295+ RELOC_NUMBER (R_RISCV_RELATIVE, 3) 20296+ RELOC_NUMBER (R_RISCV_COPY, 4) 20297+ RELOC_NUMBER (R_RISCV_JUMP_SLOT, 5) 20298+ RELOC_NUMBER (R_RISCV_TLS_DTPMOD32, 6) 20299+ RELOC_NUMBER (R_RISCV_TLS_DTPMOD64, 7) 20300+ RELOC_NUMBER (R_RISCV_TLS_DTPREL32, 8) 20301+ RELOC_NUMBER (R_RISCV_TLS_DTPREL64, 9) 20302+ RELOC_NUMBER (R_RISCV_TLS_TPREL32, 10) 20303+ RELOC_NUMBER (R_RISCV_TLS_TPREL64, 11) 20304+ 20305+ /* Relocation types not used by the dynamic linker. */ 20306+ RELOC_NUMBER (R_RISCV_BRANCH, 16) 20307+ RELOC_NUMBER (R_RISCV_JAL, 17) 20308+ RELOC_NUMBER (R_RISCV_CALL, 18) 20309+ RELOC_NUMBER (R_RISCV_CALL_PLT, 19) 20310+ RELOC_NUMBER (R_RISCV_GOT_HI20, 20) 20311+ RELOC_NUMBER (R_RISCV_TLS_GOT_HI20, 21) 20312+ RELOC_NUMBER (R_RISCV_TLS_GD_HI20, 22) 20313+ RELOC_NUMBER (R_RISCV_PCREL_HI20, 23) 20314+ RELOC_NUMBER (R_RISCV_PCREL_LO12_I, 24) 20315+ RELOC_NUMBER (R_RISCV_PCREL_LO12_S, 25) 20316+ RELOC_NUMBER (R_RISCV_HI20, 26) 20317+ RELOC_NUMBER (R_RISCV_LO12_I, 27) 20318+ RELOC_NUMBER (R_RISCV_LO12_S, 28) 20319+ RELOC_NUMBER (R_RISCV_TPREL_HI20, 29) 20320+ RELOC_NUMBER (R_RISCV_TPREL_LO12_I, 30) 20321+ RELOC_NUMBER (R_RISCV_TPREL_LO12_S, 31) 20322+ RELOC_NUMBER (R_RISCV_TPREL_ADD, 32) 20323+ RELOC_NUMBER (R_RISCV_ADD8, 33) 20324+ RELOC_NUMBER (R_RISCV_ADD16, 34) 20325+ RELOC_NUMBER (R_RISCV_ADD32, 35) 20326+ RELOC_NUMBER (R_RISCV_ADD64, 36) 20327+ RELOC_NUMBER (R_RISCV_SUB8, 37) 20328+ RELOC_NUMBER (R_RISCV_SUB16, 38) 20329+ RELOC_NUMBER (R_RISCV_SUB32, 39) 20330+ RELOC_NUMBER (R_RISCV_SUB64, 40) 20331+ RELOC_NUMBER (R_RISCV_GNU_VTINHERIT, 41) 20332+ RELOC_NUMBER (R_RISCV_GNU_VTENTRY, 42) 20333+ RELOC_NUMBER (R_RISCV_ALIGN, 43) 20334+END_RELOC_NUMBERS (R_RISCV_max) 20335+ 20336+/* Processor specific flags for the ELF header e_flags field. */ 20337+ 20338+/* Custom flag definitions. */ 20339+ 20340+#define EF_RISCV_EXT_MASK 0xffff 20341+#define EF_RISCV_EXT_SH 16 20342+#define E_RISCV_EXT_Xcustom 0x0000 20343+#define E_RISCV_EXT_Xhwacha 0x0001 20344+#define E_RISCV_EXT_RESERVED 0xffff 20345+ 20346+#define EF_GET_RISCV_EXT(x) \ 20347+ ((x >> EF_RISCV_EXT_SH) & EF_RISCV_EXT_MASK) 20348+ 20349+#define EF_SET_RISCV_EXT(x, ext) \ 20350+ do { x |= ((ext & EF_RISCV_EXT_MASK) << EF_RISCV_EXT_SH); } while (0) 20351+ 20352+#define EF_IS_RISCV_EXT_Xcustom(x) \ 20353+ (EF_GET_RISCV_EXT(x) == E_RISCV_EXT_Xcustom) 20354+ 20355+/* A mapping from extension names to elf flags */ 20356+ 20357+struct riscv_extension_entry 20358+{ 20359+ const char* name; 20360+ unsigned int flag; 20361+}; 20362+ 20363+static const struct riscv_extension_entry riscv_extension_map[] = 20364+{ 20365+ {"Xcustom", E_RISCV_EXT_Xcustom}, 20366+ {"Xhwacha", E_RISCV_EXT_Xhwacha}, 20367+}; 20368+ 20369+/* Given an extension name, return an elf flag. */ 20370+ 20371+static inline const char* riscv_elf_flag_to_name(unsigned int flag) 20372+{ 20373+ unsigned int i; 20374+ 20375+ for (i=0; i<sizeof(riscv_extension_map)/sizeof(riscv_extension_map[0]); i++) 20376+ if (riscv_extension_map[i].flag == flag) 20377+ return riscv_extension_map[i].name; 20378+ 20379+ return NULL; 20380+} 20381+ 20382+/* Given an elf flag, return an extension name. */ 20383+ 20384+static inline unsigned int riscv_elf_name_to_flag(const char* name) 20385+{ 20386+ unsigned int i; 20387+ 20388+ for (i=0; i<sizeof(riscv_extension_map)/sizeof(riscv_extension_map[0]); i++) 20389+ if (strcmp(riscv_extension_map[i].name, name) == 0) 20390+ return riscv_extension_map[i].flag; 20391+ 20392+ return E_RISCV_EXT_Xcustom; 20393+} 20394+ 20395+#endif /* _ELF_RISCV_H */ 20396diff -rNU3 dist.orig/include/objalloc.h dist/include/objalloc.h 20397--- dist.orig/include/objalloc.h 2005-05-10 12:21:08.000000000 +0200 20398+++ dist/include/objalloc.h 2015-10-18 13:11:17.000000000 +0200 20399@@ -1,5 +1,5 @@ 20400 /* objalloc.h -- routines to allocate memory for objects 20401- Copyright 1997, 2001 Free Software Foundation, Inc. 20402+ Copyright 1997-2012 Free Software Foundation, Inc. 20403 Written by Ian Lance Taylor, Cygnus Solutions. 20404 20405 This program is free software; you can redistribute it and/or modify it 20406@@ -91,7 +91,7 @@ 20407 if (__len == 0) \ 20408 __len = 1; \ 20409 __len = (__len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1); \ 20410- (__len <= __o->current_space \ 20411+ (__len != 0 && __len <= __o->current_space \ 20412 ? (__o->current_ptr += __len, \ 20413 __o->current_space -= __len, \ 20414 (void *) (__o->current_ptr - __len)) \ 20415diff -rNU3 dist.orig/include/opcode/mips.h dist/include/opcode/mips.h 20416--- dist.orig/include/opcode/mips.h 2012-09-04 16:21:05.000000000 +0200 20417+++ dist/include/opcode/mips.h 2015-10-18 13:11:17.000000000 +0200 20418@@ -1035,7 +1035,11 @@ 20419 M_DSUB_I, 20420 M_DSUBU_I, 20421 M_DSUBU_I_2, 20422+ M_JR_S, 20423+ M_J_S, 20424 M_J_A, 20425+ M_JALR_S, 20426+ M_JALR_DS, 20427 M_JAL_1, 20428 M_JAL_2, 20429 M_JAL_A, 20430diff -rNU3 dist.orig/include/opcode/riscv-opc.h dist/include/opcode/riscv-opc.h 20431--- dist.orig/include/opcode/riscv-opc.h 1970-01-01 01:00:00.000000000 +0100 20432+++ dist/include/opcode/riscv-opc.h 2015-10-18 13:11:17.000000000 +0200 20433@@ -0,0 +1,1234 @@ 20434+/* Automatically generated by parse-opcodes */ 20435+#ifndef RISCV_ENCODING_H 20436+#define RISCV_ENCODING_H 20437+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 20438+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f 20439+#define MATCH_VLSEGSTWU 0xc00305b 20440+#define MASK_VLSEGSTWU 0x1e00707f 20441+#define MATCH_C_LW0 0x12 20442+#define MASK_C_LW0 0x801f 20443+#define MATCH_FMV_D_X 0xf2000053 20444+#define MASK_FMV_D_X 0xfff0707f 20445+#define MATCH_VLH 0x200205b 20446+#define MASK_VLH 0xfff0707f 20447+#define MATCH_C_LI 0x0 20448+#define MASK_C_LI 0x1f 20449+#define MATCH_FADD_D 0x2000053 20450+#define MASK_FADD_D 0xfe00007f 20451+#define MATCH_C_LD 0x9 20452+#define MASK_C_LD 0x1f 20453+#define MATCH_VLD 0x600205b 20454+#define MASK_VLD 0xfff0707f 20455+#define MATCH_FADD_S 0x53 20456+#define MASK_FADD_S 0xfe00007f 20457+#define MATCH_C_LW 0xa 20458+#define MASK_C_LW 0x1f 20459+#define MATCH_VLW 0x400205b 20460+#define MASK_VLW 0xfff0707f 20461+#define MATCH_VSSEGSTW 0x400307b 20462+#define MASK_VSSEGSTW 0x1e00707f 20463+#define MATCH_UTIDX 0x6077 20464+#define MASK_UTIDX 0xfffff07f 20465+#define MATCH_C_FLW 0x14 20466+#define MASK_C_FLW 0x1f 20467+#define MATCH_FSUB_D 0xa000053 20468+#define MASK_FSUB_D 0xfe00007f 20469+#define MATCH_VSSEGSTD 0x600307b 20470+#define MASK_VSSEGSTD 0x1e00707f 20471+#define MATCH_VSSEGSTB 0x307b 20472+#define MASK_VSSEGSTB 0x1e00707f 20473+#define MATCH_DIV 0x2004033 20474+#define MASK_DIV 0xfe00707f 20475+#define MATCH_FMV_H_X 0xf4000053 20476+#define MASK_FMV_H_X 0xfff0707f 20477+#define MATCH_C_FLD 0x15 20478+#define MASK_C_FLD 0x1f 20479+#define MATCH_FRRM 0x202073 20480+#define MASK_FRRM 0xfffff07f 20481+#define MATCH_VFMSV_S 0x1000202b 20482+#define MASK_VFMSV_S 0xfff0707f 20483+#define MATCH_C_LWSP 0x5 20484+#define MASK_C_LWSP 0x1f 20485+#define MATCH_FENCE 0xf 20486+#define MASK_FENCE 0x707f 20487+#define MATCH_FNMSUB_S 0x4b 20488+#define MASK_FNMSUB_S 0x600007f 20489+#define MATCH_FLE_S 0xa0000053 20490+#define MASK_FLE_S 0xfe00707f 20491+#define MATCH_FNMSUB_H 0x400004b 20492+#define MASK_FNMSUB_H 0x600007f 20493+#define MATCH_FLE_H 0xbc000053 20494+#define MASK_FLE_H 0xfe00707f 20495+#define MATCH_FLW 0x2007 20496+#define MASK_FLW 0x707f 20497+#define MATCH_VSETVL 0x600b 20498+#define MASK_VSETVL 0xfff0707f 20499+#define MATCH_VFMSV_D 0x1200202b 20500+#define MASK_VFMSV_D 0xfff0707f 20501+#define MATCH_FLE_D 0xa2000053 20502+#define MASK_FLE_D 0xfe00707f 20503+#define MATCH_FENCE_I 0x100f 20504+#define MASK_FENCE_I 0x707f 20505+#define MATCH_FNMSUB_D 0x200004b 20506+#define MASK_FNMSUB_D 0x600007f 20507+#define MATCH_ADDW 0x3b 20508+#define MASK_ADDW 0xfe00707f 20509+#define MATCH_XOR 0x4033 20510+#define MASK_XOR 0xfe00707f 20511+#define MATCH_SUB 0x40000033 20512+#define MASK_SUB 0xfe00707f 20513+#define MATCH_VSSTW 0x400307b 20514+#define MASK_VSSTW 0xfe00707f 20515+#define MATCH_VSSTH 0x200307b 20516+#define MASK_VSSTH 0xfe00707f 20517+#define MATCH_SC_W 0x1800202f 20518+#define MASK_SC_W 0xf800707f 20519+#define MATCH_VSSTB 0x307b 20520+#define MASK_VSSTB 0xfe00707f 20521+#define MATCH_VSSTD 0x600307b 20522+#define MASK_VSSTD 0xfe00707f 20523+#define MATCH_ADDI 0x13 20524+#define MASK_ADDI 0x707f 20525+#define MATCH_RDTIMEH 0xc8102073 20526+#define MASK_RDTIMEH 0xfffff07f 20527+#define MATCH_MULH 0x2001033 20528+#define MASK_MULH 0xfe00707f 20529+#define MATCH_CSRRSI 0x6073 20530+#define MASK_CSRRSI 0x707f 20531+#define MATCH_FCVT_D_WU 0xd2100053 20532+#define MASK_FCVT_D_WU 0xfff0007f 20533+#define MATCH_MULW 0x200003b 20534+#define MASK_MULW 0xfe00707f 20535+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 20536+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f 20537+#define MATCH_VENQIMM1 0xc00302b 20538+#define MASK_VENQIMM1 0xfe007fff 20539+#define MATCH_VENQIMM2 0xe00302b 20540+#define MASK_VENQIMM2 0xfe007fff 20541+#define MATCH_RDINSTRET 0xc0202073 20542+#define MASK_RDINSTRET 0xfffff07f 20543+#define MATCH_C_SWSP 0x8 20544+#define MASK_C_SWSP 0x1f 20545+#define MATCH_VLSTW 0x400305b 20546+#define MASK_VLSTW 0xfe00707f 20547+#define MATCH_VLSTH 0x200305b 20548+#define MASK_VLSTH 0xfe00707f 20549+#define MATCH_VLSTB 0x305b 20550+#define MASK_VLSTB 0xfe00707f 20551+#define MATCH_VLSTD 0x600305b 20552+#define MASK_VLSTD 0xfe00707f 20553+#define MATCH_ANDI 0x7013 20554+#define MASK_ANDI 0x707f 20555+#define MATCH_FMV_X_S 0xe0000053 20556+#define MASK_FMV_X_S 0xfff0707f 20557+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 20558+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f 20559+#define MATCH_FNMADD_S 0x4f 20560+#define MASK_FNMADD_S 0x600007f 20561+#define MATCH_LWU 0x6003 20562+#define MASK_LWU 0x707f 20563+#define MATCH_CUSTOM0_RS1 0x200b 20564+#define MASK_CUSTOM0_RS1 0x707f 20565+#define MATCH_VLSEGSTBU 0x800305b 20566+#define MASK_VLSEGSTBU 0x1e00707f 20567+#define MATCH_FNMADD_D 0x200004f 20568+#define MASK_FNMADD_D 0x600007f 20569+#define MATCH_FCVT_W_S 0xc0000053 20570+#define MASK_FCVT_W_S 0xfff0007f 20571+#define MATCH_C_SRAI 0x1019 20572+#define MASK_C_SRAI 0x1c1f 20573+#define MATCH_MULHSU 0x2002033 20574+#define MASK_MULHSU 0xfe00707f 20575+#define MATCH_FCVT_D_LU 0xd2300053 20576+#define MASK_FCVT_D_LU 0xfff0007f 20577+#define MATCH_FCVT_W_D 0xc2000053 20578+#define MASK_FCVT_W_D 0xfff0007f 20579+#define MATCH_FSUB_H 0xc000053 20580+#define MASK_FSUB_H 0xfe00007f 20581+#define MATCH_DIVUW 0x200503b 20582+#define MASK_DIVUW 0xfe00707f 20583+#define MATCH_SLTI 0x2013 20584+#define MASK_SLTI 0x707f 20585+#define MATCH_VLSTBU 0x800305b 20586+#define MASK_VLSTBU 0xfe00707f 20587+#define MATCH_SLTU 0x3033 20588+#define MASK_SLTU 0xfe00707f 20589+#define MATCH_FLH 0x1007 20590+#define MASK_FLH 0x707f 20591+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 20592+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f 20593+#define MATCH_FLD 0x3007 20594+#define MASK_FLD 0x707f 20595+#define MATCH_FSUB_S 0x8000053 20596+#define MASK_FSUB_S 0xfe00007f 20597+#define MATCH_FCVT_H_LU 0x6c000053 20598+#define MASK_FCVT_H_LU 0xfff0007f 20599+#define MATCH_CUSTOM0 0xb 20600+#define MASK_CUSTOM0 0x707f 20601+#define MATCH_CUSTOM1 0x2b 20602+#define MASK_CUSTOM1 0x707f 20603+#define MATCH_CUSTOM2 0x5b 20604+#define MASK_CUSTOM2 0x707f 20605+#define MATCH_CUSTOM3 0x7b 20606+#define MASK_CUSTOM3 0x707f 20607+#define MATCH_VXCPTSAVE 0x302b 20608+#define MASK_VXCPTSAVE 0xfff07fff 20609+#define MATCH_VMSV 0x200202b 20610+#define MASK_VMSV 0xfff0707f 20611+#define MATCH_FCVT_LU_S 0xc0300053 20612+#define MASK_FCVT_LU_S 0xfff0007f 20613+#define MATCH_AUIPC 0x17 20614+#define MASK_AUIPC 0x7f 20615+#define MATCH_FRFLAGS 0x102073 20616+#define MASK_FRFLAGS 0xfffff07f 20617+#define MATCH_FCVT_LU_D 0xc2300053 20618+#define MASK_FCVT_LU_D 0xfff0007f 20619+#define MATCH_CSRRWI 0x5073 20620+#define MASK_CSRRWI 0x707f 20621+#define MATCH_FADD_H 0x4000053 20622+#define MASK_FADD_H 0xfe00007f 20623+#define MATCH_FSQRT_S 0x58000053 20624+#define MASK_FSQRT_S 0xfff0007f 20625+#define MATCH_VXCPTKILL 0x400302b 20626+#define MASK_VXCPTKILL 0xffffffff 20627+#define MATCH_STOP 0x5077 20628+#define MASK_STOP 0xffffffff 20629+#define MATCH_FSGNJN_S 0x20001053 20630+#define MASK_FSGNJN_S 0xfe00707f 20631+#define MATCH_FSGNJN_H 0x34000053 20632+#define MASK_FSGNJN_H 0xfe00707f 20633+#define MATCH_FSQRT_D 0x5a000053 20634+#define MASK_FSQRT_D 0xfff0007f 20635+#define MATCH_XORI 0x4013 20636+#define MASK_XORI 0x707f 20637+#define MATCH_DIVU 0x2005033 20638+#define MASK_DIVU 0xfe00707f 20639+#define MATCH_FSGNJN_D 0x22001053 20640+#define MASK_FSGNJN_D 0xfe00707f 20641+#define MATCH_FSQRT_H 0x24000053 20642+#define MASK_FSQRT_H 0xfff0007f 20643+#define MATCH_VSSEGSTH 0x200307b 20644+#define MASK_VSSEGSTH 0x1e00707f 20645+#define MATCH_SW 0x2023 20646+#define MASK_SW 0x707f 20647+#define MATCH_VLSTWU 0xc00305b 20648+#define MASK_VLSTWU 0xfe00707f 20649+#define MATCH_VFSSEGW 0x1400207b 20650+#define MASK_VFSSEGW 0x1ff0707f 20651+#define MATCH_LHU 0x5003 20652+#define MASK_LHU 0x707f 20653+#define MATCH_SH 0x1023 20654+#define MASK_SH 0x707f 20655+#define MATCH_FMSUB_H 0x4000047 20656+#define MASK_FMSUB_H 0x600007f 20657+#define MATCH_VXCPTAUX 0x200402b 20658+#define MASK_VXCPTAUX 0xfffff07f 20659+#define MATCH_FMSUB_D 0x2000047 20660+#define MASK_FMSUB_D 0x600007f 20661+#define MATCH_VFSSEGD 0x1600207b 20662+#define MASK_VFSSEGD 0x1ff0707f 20663+#define MATCH_VLSEGHU 0xa00205b 20664+#define MASK_VLSEGHU 0x1ff0707f 20665+#define MATCH_MOVN 0x2007077 20666+#define MASK_MOVN 0xfe00707f 20667+#define MATCH_CUSTOM1_RS1 0x202b 20668+#define MASK_CUSTOM1_RS1 0x707f 20669+#define MATCH_VLSTHU 0xa00305b 20670+#define MASK_VLSTHU 0xfe00707f 20671+#define MATCH_MOVZ 0x7077 20672+#define MASK_MOVZ 0xfe00707f 20673+#define MATCH_CSRRW 0x1073 20674+#define MASK_CSRRW 0x707f 20675+#define MATCH_LD 0x3003 20676+#define MASK_LD 0x707f 20677+#define MATCH_LB 0x3 20678+#define MASK_LB 0x707f 20679+#define MATCH_VLWU 0xc00205b 20680+#define MASK_VLWU 0xfff0707f 20681+#define MATCH_LH 0x1003 20682+#define MASK_LH 0x707f 20683+#define MATCH_LW 0x2003 20684+#define MASK_LW 0x707f 20685+#define MATCH_CSRRC 0x3073 20686+#define MASK_CSRRC 0x707f 20687+#define MATCH_FCVT_LU_H 0x4c000053 20688+#define MASK_FCVT_LU_H 0xfff0007f 20689+#define MATCH_FCVT_S_D 0x40100053 20690+#define MASK_FCVT_S_D 0xfff0007f 20691+#define MATCH_BGEU 0x7063 20692+#define MASK_BGEU 0x707f 20693+#define MATCH_VFLSTD 0x1600305b 20694+#define MASK_VFLSTD 0xfe00707f 20695+#define MATCH_FCVT_S_L 0xd0200053 20696+#define MASK_FCVT_S_L 0xfff0007f 20697+#define MATCH_FCVT_S_H 0x84000053 20698+#define MASK_FCVT_S_H 0xfff0007f 20699+#define MATCH_FSCSR 0x301073 20700+#define MASK_FSCSR 0xfff0707f 20701+#define MATCH_FCVT_S_W 0xd0000053 20702+#define MASK_FCVT_S_W 0xfff0007f 20703+#define MATCH_VFLSTW 0x1400305b 20704+#define MASK_VFLSTW 0xfe00707f 20705+#define MATCH_VXCPTEVAC 0x600302b 20706+#define MASK_VXCPTEVAC 0xfff07fff 20707+#define MATCH_AMOMINU_D 0xc000302f 20708+#define MASK_AMOMINU_D 0xf800707f 20709+#define MATCH_FSFLAGS 0x101073 20710+#define MASK_FSFLAGS 0xfff0707f 20711+#define MATCH_SRLI 0x5013 20712+#define MASK_SRLI 0xfc00707f 20713+#define MATCH_C_SRLI 0x819 20714+#define MASK_C_SRLI 0x1c1f 20715+#define MATCH_AMOMINU_W 0xc000202f 20716+#define MASK_AMOMINU_W 0xf800707f 20717+#define MATCH_SRLW 0x503b 20718+#define MASK_SRLW 0xfe00707f 20719+#define MATCH_VFLSEGW 0x1400205b 20720+#define MASK_VFLSEGW 0x1ff0707f 20721+#define MATCH_C_LD0 0x8012 20722+#define MASK_C_LD0 0x801f 20723+#define MATCH_VLSEGBU 0x800205b 20724+#define MASK_VLSEGBU 0x1ff0707f 20725+#define MATCH_JALR 0x67 20726+#define MASK_JALR 0x707f 20727+#define MATCH_BLT 0x4063 20728+#define MASK_BLT 0x707f 20729+#define MATCH_CUSTOM2_RD_RS1 0x605b 20730+#define MASK_CUSTOM2_RD_RS1 0x707f 20731+#define MATCH_FCLASS_S 0xe0001053 20732+#define MASK_FCLASS_S 0xfff0707f 20733+#define MATCH_SFENCE_VM 0x10100073 20734+#define MASK_SFENCE_VM 0xfff07fff 20735+#define MATCH_REM 0x2006033 20736+#define MASK_REM 0xfe00707f 20737+#define MATCH_FCLASS_D 0xe2001053 20738+#define MASK_FCLASS_D 0xfff0707f 20739+#define MATCH_FMUL_S 0x10000053 20740+#define MASK_FMUL_S 0xfe00007f 20741+#define MATCH_RDCYCLEH 0xc8002073 20742+#define MASK_RDCYCLEH 0xfffff07f 20743+#define MATCH_VLSEGSTHU 0xa00305b 20744+#define MASK_VLSEGSTHU 0x1e00707f 20745+#define MATCH_FMUL_D 0x12000053 20746+#define MASK_FMUL_D 0xfe00007f 20747+#define MATCH_ORI 0x6013 20748+#define MASK_ORI 0x707f 20749+#define MATCH_FMUL_H 0x14000053 20750+#define MASK_FMUL_H 0xfe00007f 20751+#define MATCH_VFLSEGD 0x1600205b 20752+#define MASK_VFLSEGD 0x1ff0707f 20753+#define MATCH_FEQ_S 0xa0002053 20754+#define MASK_FEQ_S 0xfe00707f 20755+#define MATCH_FSGNJX_D 0x22002053 20756+#define MASK_FSGNJX_D 0xfe00707f 20757+#define MATCH_SRAIW 0x4000501b 20758+#define MASK_SRAIW 0xfe00707f 20759+#define MATCH_FSGNJX_H 0x3c000053 20760+#define MASK_FSGNJX_H 0xfe00707f 20761+#define MATCH_FSGNJX_S 0x20002053 20762+#define MASK_FSGNJX_S 0xfe00707f 20763+#define MATCH_FEQ_D 0xa2002053 20764+#define MASK_FEQ_D 0xfe00707f 20765+#define MATCH_CUSTOM1_RD_RS1 0x602b 20766+#define MASK_CUSTOM1_RD_RS1 0x707f 20767+#define MATCH_FEQ_H 0xac000053 20768+#define MASK_FEQ_H 0xfe00707f 20769+#define MATCH_AMOMAXU_D 0xe000302f 20770+#define MASK_AMOMAXU_D 0xf800707f 20771+#define MATCH_DIVW 0x200403b 20772+#define MASK_DIVW 0xfe00707f 20773+#define MATCH_AMOMAXU_W 0xe000202f 20774+#define MASK_AMOMAXU_W 0xf800707f 20775+#define MATCH_SRAI_RV32 0x40005013 20776+#define MASK_SRAI_RV32 0xfe00707f 20777+#define MATCH_C_SRLI32 0xc19 20778+#define MASK_C_SRLI32 0x1c1f 20779+#define MATCH_VFSSTW 0x1400307b 20780+#define MASK_VFSSTW 0xfe00707f 20781+#define MATCH_CUSTOM0_RD 0x400b 20782+#define MASK_CUSTOM0_RD 0x707f 20783+#define MATCH_C_BEQ 0x10 20784+#define MASK_C_BEQ 0x1f 20785+#define MATCH_VFSSTD 0x1600307b 20786+#define MASK_VFSSTD 0xfe00707f 20787+#define MATCH_CUSTOM3_RD_RS1 0x607b 20788+#define MASK_CUSTOM3_RD_RS1 0x707f 20789+#define MATCH_LR_D 0x1000302f 20790+#define MASK_LR_D 0xf9f0707f 20791+#define MATCH_LR_W 0x1000202f 20792+#define MASK_LR_W 0xf9f0707f 20793+#define MATCH_FCVT_H_WU 0x7c000053 20794+#define MASK_FCVT_H_WU 0xfff0007f 20795+#define MATCH_VMVV 0x200002b 20796+#define MASK_VMVV 0xfff0707f 20797+#define MATCH_SLLW 0x103b 20798+#define MASK_SLLW 0xfe00707f 20799+#define MATCH_SLLI 0x1013 20800+#define MASK_SLLI 0xfc00707f 20801+#define MATCH_BEQ 0x63 20802+#define MASK_BEQ 0x707f 20803+#define MATCH_AND 0x7033 20804+#define MASK_AND 0xfe00707f 20805+#define MATCH_LBU 0x4003 20806+#define MASK_LBU 0x707f 20807+#define MATCH_FSGNJ_S 0x20000053 20808+#define MASK_FSGNJ_S 0xfe00707f 20809+#define MATCH_FMSUB_S 0x47 20810+#define MASK_FMSUB_S 0x600007f 20811+#define MATCH_C_SUB3 0x11c 20812+#define MASK_C_SUB3 0x31f 20813+#define MATCH_FSGNJ_H 0x2c000053 20814+#define MASK_FSGNJ_H 0xfe00707f 20815+#define MATCH_VLB 0x205b 20816+#define MASK_VLB 0xfff0707f 20817+#define MATCH_C_ADDIW 0x1d 20818+#define MASK_C_ADDIW 0x1f 20819+#define MATCH_CUSTOM3_RS1_RS2 0x307b 20820+#define MASK_CUSTOM3_RS1_RS2 0x707f 20821+#define MATCH_FSGNJ_D 0x22000053 20822+#define MASK_FSGNJ_D 0xfe00707f 20823+#define MATCH_VLSEGWU 0xc00205b 20824+#define MASK_VLSEGWU 0x1ff0707f 20825+#define MATCH_FCVT_S_WU 0xd0100053 20826+#define MASK_FCVT_S_WU 0xfff0007f 20827+#define MATCH_CUSTOM3_RS1 0x207b 20828+#define MASK_CUSTOM3_RS1 0x707f 20829+#define MATCH_SC_D 0x1800302f 20830+#define MASK_SC_D 0xf800707f 20831+#define MATCH_VFSW 0x1400207b 20832+#define MASK_VFSW 0xfff0707f 20833+#define MATCH_AMOSWAP_D 0x800302f 20834+#define MASK_AMOSWAP_D 0xf800707f 20835+#define MATCH_SB 0x23 20836+#define MASK_SB 0x707f 20837+#define MATCH_AMOSWAP_W 0x800202f 20838+#define MASK_AMOSWAP_W 0xf800707f 20839+#define MATCH_VFSD 0x1600207b 20840+#define MASK_VFSD 0xfff0707f 20841+#define MATCH_CUSTOM2_RS1 0x205b 20842+#define MASK_CUSTOM2_RS1 0x707f 20843+#define MATCH_SD 0x3023 20844+#define MASK_SD 0x707f 20845+#define MATCH_FMV_S_X 0xf0000053 20846+#define MASK_FMV_S_X 0xfff0707f 20847+#define MATCH_REMUW 0x200703b 20848+#define MASK_REMUW 0xfe00707f 20849+#define MATCH_JAL 0x6f 20850+#define MASK_JAL 0x7f 20851+#define MATCH_C_FSD 0x18 20852+#define MASK_C_FSD 0x1f 20853+#define MATCH_RDCYCLE 0xc0002073 20854+#define MASK_RDCYCLE 0xfffff07f 20855+#define MATCH_C_BNE 0x11 20856+#define MASK_C_BNE 0x1f 20857+#define MATCH_C_ADD 0x1a 20858+#define MASK_C_ADD 0x801f 20859+#define MATCH_VXCPTCAUSE 0x402b 20860+#define MASK_VXCPTCAUSE 0xfffff07f 20861+#define MATCH_VGETCFG 0x400b 20862+#define MASK_VGETCFG 0xfffff07f 20863+#define MATCH_LUI 0x37 20864+#define MASK_LUI 0x7f 20865+#define MATCH_VSETCFG 0x200b 20866+#define MASK_VSETCFG 0x7fff 20867+#define MATCH_C_SDSP 0x6 20868+#define MASK_C_SDSP 0x1f 20869+#define MATCH_C_LDSP 0x4 20870+#define MASK_C_LDSP 0x1f 20871+#define MATCH_FNMADD_H 0x400004f 20872+#define MASK_FNMADD_H 0x600007f 20873+#define MATCH_CUSTOM0_RS1_RS2 0x300b 20874+#define MASK_CUSTOM0_RS1_RS2 0x707f 20875+#define MATCH_SLLI_RV32 0x1013 20876+#define MASK_SLLI_RV32 0xfe00707f 20877+#define MATCH_MUL 0x2000033 20878+#define MASK_MUL 0xfe00707f 20879+#define MATCH_CSRRCI 0x7073 20880+#define MASK_CSRRCI 0x707f 20881+#define MATCH_C_SRAI32 0x1419 20882+#define MASK_C_SRAI32 0x1c1f 20883+#define MATCH_FLT_H 0xb4000053 20884+#define MASK_FLT_H 0xfe00707f 20885+#define MATCH_SRAI 0x40005013 20886+#define MASK_SRAI 0xfc00707f 20887+#define MATCH_AMOAND_D 0x6000302f 20888+#define MASK_AMOAND_D 0xf800707f 20889+#define MATCH_FLT_D 0xa2001053 20890+#define MASK_FLT_D 0xfe00707f 20891+#define MATCH_SRAW 0x4000503b 20892+#define MASK_SRAW 0xfe00707f 20893+#define MATCH_CSRRS 0x2073 20894+#define MASK_CSRRS 0x707f 20895+#define MATCH_FLT_S 0xa0001053 20896+#define MASK_FLT_S 0xfe00707f 20897+#define MATCH_ADDIW 0x1b 20898+#define MASK_ADDIW 0x707f 20899+#define MATCH_AMOAND_W 0x6000202f 20900+#define MASK_AMOAND_W 0xf800707f 20901+#define MATCH_CUSTOM2_RD 0x405b 20902+#define MASK_CUSTOM2_RD 0x707f 20903+#define MATCH_MRTS 0x30500073 20904+#define MASK_MRTS 0xffffffff 20905+#define MATCH_FCVT_WU_D 0xc2100053 20906+#define MASK_FCVT_WU_D 0xfff0007f 20907+#define MATCH_AMOXOR_W 0x2000202f 20908+#define MASK_AMOXOR_W 0xf800707f 20909+#define MATCH_FCVT_D_L 0xd2200053 20910+#define MASK_FCVT_D_L 0xfff0007f 20911+#define MATCH_FCVT_WU_H 0x5c000053 20912+#define MASK_FCVT_WU_H 0xfff0007f 20913+#define MATCH_C_SLLI 0x19 20914+#define MASK_C_SLLI 0x1c1f 20915+#define MATCH_AMOXOR_D 0x2000302f 20916+#define MASK_AMOXOR_D 0xf800707f 20917+#define MATCH_FCVT_WU_S 0xc0100053 20918+#define MASK_FCVT_WU_S 0xfff0007f 20919+#define MATCH_CUSTOM3_RD 0x407b 20920+#define MASK_CUSTOM3_RD 0x707f 20921+#define MATCH_FMAX_H 0xcc000053 20922+#define MASK_FMAX_H 0xfe00707f 20923+#define MATCH_VENQCNT 0x1000302b 20924+#define MASK_VENQCNT 0xfe007fff 20925+#define MATCH_VLBU 0x800205b 20926+#define MASK_VLBU 0xfff0707f 20927+#define MATCH_VLHU 0xa00205b 20928+#define MASK_VLHU 0xfff0707f 20929+#define MATCH_C_SW 0xd 20930+#define MASK_C_SW 0x1f 20931+#define MATCH_C_SD 0xc 20932+#define MASK_C_SD 0x1f 20933+#define MATCH_C_OR3 0x21c 20934+#define MASK_C_OR3 0x31f 20935+#define MATCH_C_AND3 0x31c 20936+#define MASK_C_AND3 0x31f 20937+#define MATCH_VFSSEGSTW 0x1400307b 20938+#define MASK_VFSSEGSTW 0x1e00707f 20939+#define MATCH_SLT 0x2033 20940+#define MASK_SLT 0xfe00707f 20941+#define MATCH_AMOOR_D 0x4000302f 20942+#define MASK_AMOOR_D 0xf800707f 20943+#define MATCH_REMU 0x2007033 20944+#define MASK_REMU 0xfe00707f 20945+#define MATCH_REMW 0x200603b 20946+#define MASK_REMW 0xfe00707f 20947+#define MATCH_SLL 0x1033 20948+#define MASK_SLL 0xfe00707f 20949+#define MATCH_VFSSEGSTD 0x1600307b 20950+#define MASK_VFSSEGSTD 0x1e00707f 20951+#define MATCH_AMOOR_W 0x4000202f 20952+#define MASK_AMOOR_W 0xf800707f 20953+#define MATCH_CUSTOM2_RS1_RS2 0x305b 20954+#define MASK_CUSTOM2_RS1_RS2 0x707f 20955+#define MATCH_VF 0x10202b 20956+#define MASK_VF 0x1f0707f 20957+#define MATCH_VFMVV 0x1000002b 20958+#define MASK_VFMVV 0xfff0707f 20959+#define MATCH_VFLSEGSTW 0x1400305b 20960+#define MASK_VFLSEGSTW 0x1e00707f 20961+#define MATCH_VXCPTRESTORE 0x200302b 20962+#define MASK_VXCPTRESTORE 0xfff07fff 20963+#define MATCH_VXCPTHOLD 0x800302b 20964+#define MASK_VXCPTHOLD 0xfff07fff 20965+#define MATCH_SLTIU 0x3013 20966+#define MASK_SLTIU 0x707f 20967+#define MATCH_VFLSEGSTD 0x1600305b 20968+#define MASK_VFLSEGSTD 0x1e00707f 20969+#define MATCH_VFLD 0x1600205b 20970+#define MASK_VFLD 0xfff0707f 20971+#define MATCH_FMADD_S 0x43 20972+#define MASK_FMADD_S 0x600007f 20973+#define MATCH_VFLW 0x1400205b 20974+#define MASK_VFLW 0xfff0707f 20975+#define MATCH_FMADD_D 0x2000043 20976+#define MASK_FMADD_D 0x600007f 20977+#define MATCH_FMADD_H 0x4000043 20978+#define MASK_FMADD_H 0x600007f 20979+#define MATCH_SRET 0x10000073 20980+#define MASK_SRET 0xffffffff 20981+#define MATCH_VSSEGW 0x400207b 20982+#define MASK_VSSEGW 0x1ff0707f 20983+#define MATCH_CUSTOM0_RD_RS1 0x600b 20984+#define MASK_CUSTOM0_RD_RS1 0x707f 20985+#define MATCH_VSSEGH 0x200207b 20986+#define MASK_VSSEGH 0x1ff0707f 20987+#define MATCH_FRCSR 0x302073 20988+#define MASK_FRCSR 0xfffff07f 20989+#define MATCH_VSSEGD 0x600207b 20990+#define MASK_VSSEGD 0x1ff0707f 20991+#define MATCH_VSSEGB 0x207b 20992+#define MASK_VSSEGB 0x1ff0707f 20993+#define MATCH_FMIN_H 0xc4000053 20994+#define MASK_FMIN_H 0xfe00707f 20995+#define MATCH_FMIN_D 0x2a000053 20996+#define MASK_FMIN_D 0xfe00707f 20997+#define MATCH_BLTU 0x6063 20998+#define MASK_BLTU 0x707f 20999+#define MATCH_FMIN_S 0x28000053 21000+#define MASK_FMIN_S 0xfe00707f 21001+#define MATCH_SRLI_RV32 0x5013 21002+#define MASK_SRLI_RV32 0xfe00707f 21003+#define MATCH_SLLIW 0x101b 21004+#define MASK_SLLIW 0xfe00707f 21005+#define MATCH_FMAX_S 0x28001053 21006+#define MASK_FMAX_S 0xfe00707f 21007+#define MATCH_FCVT_D_H 0x8c000053 21008+#define MASK_FCVT_D_H 0xfff0007f 21009+#define MATCH_FCVT_D_W 0xd2000053 21010+#define MASK_FCVT_D_W 0xfff0007f 21011+#define MATCH_ADD 0x33 21012+#define MASK_ADD 0xfe00707f 21013+#define MATCH_FCVT_D_S 0x42000053 21014+#define MASK_FCVT_D_S 0xfff0007f 21015+#define MATCH_FMAX_D 0x2a001053 21016+#define MASK_FMAX_D 0xfe00707f 21017+#define MATCH_BNE 0x1063 21018+#define MASK_BNE 0x707f 21019+#define MATCH_CUSTOM1_RD 0x402b 21020+#define MASK_CUSTOM1_RD 0x707f 21021+#define MATCH_FSRM 0x201073 21022+#define MASK_FSRM 0xfff0707f 21023+#define MATCH_FDIV_D 0x1a000053 21024+#define MASK_FDIV_D 0xfe00007f 21025+#define MATCH_VSW 0x400207b 21026+#define MASK_VSW 0xfff0707f 21027+#define MATCH_FCVT_L_S 0xc0200053 21028+#define MASK_FCVT_L_S 0xfff0007f 21029+#define MATCH_FDIV_H 0x1c000053 21030+#define MASK_FDIV_H 0xfe00007f 21031+#define MATCH_VSB 0x207b 21032+#define MASK_VSB 0xfff0707f 21033+#define MATCH_FDIV_S 0x18000053 21034+#define MASK_FDIV_S 0xfe00007f 21035+#define MATCH_FSRMI 0x205073 21036+#define MASK_FSRMI 0xfff0707f 21037+#define MATCH_FCVT_L_H 0x44000053 21038+#define MASK_FCVT_L_H 0xfff0007f 21039+#define MATCH_VSH 0x200207b 21040+#define MASK_VSH 0xfff0707f 21041+#define MATCH_FCVT_L_D 0xc2200053 21042+#define MASK_FCVT_L_D 0xfff0007f 21043+#define MATCH_FCVT_H_S 0x90000053 21044+#define MASK_FCVT_H_S 0xfff0007f 21045+#define MATCH_SCALL 0x73 21046+#define MASK_SCALL 0xffffffff 21047+#define MATCH_FSFLAGSI 0x105073 21048+#define MASK_FSFLAGSI 0xfff0707f 21049+#define MATCH_FCVT_H_W 0x74000053 21050+#define MASK_FCVT_H_W 0xfff0007f 21051+#define MATCH_FCVT_H_L 0x64000053 21052+#define MASK_FCVT_H_L 0xfff0007f 21053+#define MATCH_SRLIW 0x501b 21054+#define MASK_SRLIW 0xfe00707f 21055+#define MATCH_FCVT_S_LU 0xd0300053 21056+#define MASK_FCVT_S_LU 0xfff0007f 21057+#define MATCH_FCVT_H_D 0x92000053 21058+#define MASK_FCVT_H_D 0xfff0007f 21059+#define MATCH_SBREAK 0x100073 21060+#define MASK_SBREAK 0xffffffff 21061+#define MATCH_RDINSTRETH 0xc8202073 21062+#define MASK_RDINSTRETH 0xfffff07f 21063+#define MATCH_SRA 0x40005033 21064+#define MASK_SRA 0xfe00707f 21065+#define MATCH_BGE 0x5063 21066+#define MASK_BGE 0x707f 21067+#define MATCH_SRL 0x5033 21068+#define MASK_SRL 0xfe00707f 21069+#define MATCH_VENQCMD 0xa00302b 21070+#define MASK_VENQCMD 0xfe007fff 21071+#define MATCH_OR 0x6033 21072+#define MASK_OR 0xfe00707f 21073+#define MATCH_SUBW 0x4000003b 21074+#define MASK_SUBW 0xfe00707f 21075+#define MATCH_FMV_X_D 0xe2000053 21076+#define MASK_FMV_X_D 0xfff0707f 21077+#define MATCH_RDTIME 0xc0102073 21078+#define MASK_RDTIME 0xfffff07f 21079+#define MATCH_AMOADD_D 0x302f 21080+#define MASK_AMOADD_D 0xf800707f 21081+#define MATCH_AMOMAX_W 0xa000202f 21082+#define MASK_AMOMAX_W 0xf800707f 21083+#define MATCH_C_MOVE 0x2 21084+#define MASK_C_MOVE 0x801f 21085+#define MATCH_FMOVN 0x6007077 21086+#define MASK_FMOVN 0xfe00707f 21087+#define MATCH_C_FSW 0x16 21088+#define MASK_C_FSW 0x1f 21089+#define MATCH_AMOADD_W 0x202f 21090+#define MASK_AMOADD_W 0xf800707f 21091+#define MATCH_AMOMAX_D 0xa000302f 21092+#define MASK_AMOMAX_D 0xf800707f 21093+#define MATCH_FMOVZ 0x4007077 21094+#define MASK_FMOVZ 0xfe00707f 21095+#define MATCH_CUSTOM1_RS1_RS2 0x302b 21096+#define MASK_CUSTOM1_RS1_RS2 0x707f 21097+#define MATCH_FMV_X_H 0xe4000053 21098+#define MASK_FMV_X_H 0xfff0707f 21099+#define MATCH_VSD 0x600207b 21100+#define MASK_VSD 0xfff0707f 21101+#define MATCH_VLSEGSTW 0x400305b 21102+#define MASK_VLSEGSTW 0x1e00707f 21103+#define MATCH_C_ADDI 0x1 21104+#define MASK_C_ADDI 0x1f 21105+#define MATCH_C_SLLIW 0x1819 21106+#define MASK_C_SLLIW 0x1c1f 21107+#define MATCH_VLSEGSTB 0x305b 21108+#define MASK_VLSEGSTB 0x1e00707f 21109+#define MATCH_VLSEGSTD 0x600305b 21110+#define MASK_VLSEGSTD 0x1e00707f 21111+#define MATCH_VLSEGSTH 0x200305b 21112+#define MASK_VLSEGSTH 0x1e00707f 21113+#define MATCH_MULHU 0x2003033 21114+#define MASK_MULHU 0xfe00707f 21115+#define MATCH_AMOMIN_W 0x8000202f 21116+#define MASK_AMOMIN_W 0xf800707f 21117+#define MATCH_C_SLLI32 0x419 21118+#define MASK_C_SLLI32 0x1c1f 21119+#define MATCH_C_ADD3 0x1c 21120+#define MASK_C_ADD3 0x31f 21121+#define MATCH_VGETVL 0x200400b 21122+#define MASK_VGETVL 0xfffff07f 21123+#define MATCH_AMOMIN_D 0x8000302f 21124+#define MASK_AMOMIN_D 0xf800707f 21125+#define MATCH_FCVT_W_H 0x54000053 21126+#define MASK_FCVT_W_H 0xfff0007f 21127+#define MATCH_VLSEGB 0x205b 21128+#define MASK_VLSEGB 0x1ff0707f 21129+#define MATCH_FSD 0x3027 21130+#define MASK_FSD 0x707f 21131+#define MATCH_VLSEGD 0x600205b 21132+#define MASK_VLSEGD 0x1ff0707f 21133+#define MATCH_FSH 0x1027 21134+#define MASK_FSH 0x707f 21135+#define MATCH_VLSEGH 0x200205b 21136+#define MASK_VLSEGH 0x1ff0707f 21137+#define MATCH_C_SUB 0x801a 21138+#define MASK_C_SUB 0x801f 21139+#define MATCH_VLSEGW 0x400205b 21140+#define MASK_VLSEGW 0x1ff0707f 21141+#define MATCH_FSW 0x2027 21142+#define MASK_FSW 0x707f 21143+#define MATCH_C_J 0x8002 21144+#define MASK_C_J 0x801f 21145+#define CSR_FFLAGS 0x1 21146+#define CSR_FRM 0x2 21147+#define CSR_FCSR 0x3 21148+#define CSR_CYCLE 0xc00 21149+#define CSR_TIME 0xc01 21150+#define CSR_INSTRET 0xc02 21151+#define CSR_STATS 0xc0 21152+#define CSR_UARCH0 0xcc0 21153+#define CSR_UARCH1 0xcc1 21154+#define CSR_UARCH2 0xcc2 21155+#define CSR_UARCH3 0xcc3 21156+#define CSR_UARCH4 0xcc4 21157+#define CSR_UARCH5 0xcc5 21158+#define CSR_UARCH6 0xcc6 21159+#define CSR_UARCH7 0xcc7 21160+#define CSR_UARCH8 0xcc8 21161+#define CSR_UARCH9 0xcc9 21162+#define CSR_UARCH10 0xcca 21163+#define CSR_UARCH11 0xccb 21164+#define CSR_UARCH12 0xccc 21165+#define CSR_UARCH13 0xccd 21166+#define CSR_UARCH14 0xcce 21167+#define CSR_UARCH15 0xccf 21168+#define CSR_SSTATUS 0x100 21169+#define CSR_STVEC 0x101 21170+#define CSR_STIMECMP 0x121 21171+#define CSR_SSCRATCH 0x140 21172+#define CSR_SEPC 0x141 21173+#define CSR_SPTBR 0x188 21174+#define CSR_SASID 0x189 21175+#define CSR_SCYCLE 0x900 21176+#define CSR_STIME 0x901 21177+#define CSR_SINSTRET 0x902 21178+#define CSR_SCAUSE 0xd40 21179+#define CSR_SBADADDR 0xd41 21180+#define CSR_MSTATUS 0x300 21181+#define CSR_MSCRATCH 0x340 21182+#define CSR_MEPC 0x341 21183+#define CSR_MCAUSE 0x342 21184+#define CSR_MBADADDR 0x343 21185+#define CSR_RESET 0x780 21186+#define CSR_TOHOST 0x781 21187+#define CSR_FROMHOST 0x782 21188+#define CSR_SEND_IPI 0x783 21189+#define CSR_HARTID 0xfc0 21190+#define CSR_CYCLEH 0xc80 21191+#define CSR_TIMEH 0xc81 21192+#define CSR_INSTRETH 0xc82 21193+#define CSR_SCYCLEH 0x980 21194+#define CSR_STIMEH 0x981 21195+#define CSR_SINSTRETH 0x982 21196+#define CAUSE_MISALIGNED_FETCH 0x0 21197+#define CAUSE_FAULT_FETCH 0x1 21198+#define CAUSE_ILLEGAL_INSTRUCTION 0x2 21199+#define CAUSE_MISALIGNED_LOAD 0x4 21200+#define CAUSE_FAULT_LOAD 0x5 21201+#define CAUSE_MISALIGNED_STORE 0x6 21202+#define CAUSE_FAULT_STORE 0x7 21203+#define CAUSE_ECALL 0x8 21204+#define CAUSE_BREAKPOINT 0x9 21205+#endif 21206+#ifdef DECLARE_INSN 21207+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) 21208+DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU) 21209+DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0) 21210+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 21211+DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH) 21212+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 21213+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 21214+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 21215+DECLARE_INSN(vld, MATCH_VLD, MASK_VLD) 21216+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 21217+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 21218+DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW) 21219+DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW) 21220+DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX) 21221+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 21222+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 21223+DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD) 21224+DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB) 21225+DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 21226+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) 21227+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 21228+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) 21229+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S) 21230+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 21231+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 21232+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 21233+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 21234+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) 21235+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) 21236+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 21237+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) 21238+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D) 21239+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 21240+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 21241+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 21242+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 21243+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 21244+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 21245+DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW) 21246+DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH) 21247+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 21248+DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB) 21249+DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD) 21250+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 21251+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) 21252+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 21253+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 21254+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 21255+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 21256+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) 21257+DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1) 21258+DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2) 21259+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) 21260+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 21261+DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW) 21262+DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH) 21263+DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB) 21264+DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD) 21265+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 21266+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) 21267+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) 21268+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 21269+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 21270+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 21271+DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU) 21272+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 21273+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 21274+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 21275+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 21276+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 21277+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 21278+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) 21279+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 21280+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 21281+DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU) 21282+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 21283+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) 21284+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) 21285+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 21286+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 21287+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) 21288+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 21289+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 21290+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 21291+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 21292+DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE) 21293+DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV) 21294+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 21295+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 21296+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) 21297+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 21298+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 21299+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) 21300+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 21301+DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL) 21302+DECLARE_INSN(stop, MATCH_STOP, MASK_STOP) 21303+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 21304+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) 21305+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 21306+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 21307+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 21308+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 21309+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) 21310+DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH) 21311+DECLARE_INSN(sw, MATCH_SW, MASK_SW) 21312+DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU) 21313+DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW) 21314+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 21315+DECLARE_INSN(sh, MATCH_SH, MASK_SH) 21316+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) 21317+DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX) 21318+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 21319+DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD) 21320+DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU) 21321+DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN) 21322+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 21323+DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU) 21324+DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ) 21325+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 21326+DECLARE_INSN(ld, MATCH_LD, MASK_LD) 21327+DECLARE_INSN(lb, MATCH_LB, MASK_LB) 21328+DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU) 21329+DECLARE_INSN(lh, MATCH_LH, MASK_LH) 21330+DECLARE_INSN(lw, MATCH_LW, MASK_LW) 21331+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 21332+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) 21333+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 21334+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 21335+DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD) 21336+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 21337+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) 21338+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) 21339+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 21340+DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW) 21341+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC) 21342+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 21343+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) 21344+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 21345+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 21346+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 21347+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 21348+DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW) 21349+DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0) 21350+DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU) 21351+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 21352+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 21353+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 21354+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 21355+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) 21356+DECLARE_INSN(rem, MATCH_REM, MASK_REM) 21357+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 21358+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 21359+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) 21360+DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU) 21361+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 21362+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 21363+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) 21364+DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD) 21365+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 21366+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 21367+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 21368+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) 21369+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 21370+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 21371+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 21372+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) 21373+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 21374+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 21375+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 21376+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) 21377+DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32) 21378+DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW) 21379+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 21380+DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ) 21381+DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD) 21382+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 21383+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 21384+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 21385+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) 21386+DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV) 21387+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 21388+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 21389+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 21390+DECLARE_INSN(and, MATCH_AND, MASK_AND) 21391+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 21392+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 21393+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 21394+DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3) 21395+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) 21396+DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB) 21397+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 21398+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 21399+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 21400+DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU) 21401+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 21402+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 21403+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 21404+DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW) 21405+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 21406+DECLARE_INSN(sb, MATCH_SB, MASK_SB) 21407+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 21408+DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD) 21409+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 21410+DECLARE_INSN(sd, MATCH_SD, MASK_SD) 21411+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) 21412+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 21413+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 21414+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 21415+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) 21416+DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE) 21417+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 21418+DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE) 21419+DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG) 21420+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 21421+DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG) 21422+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 21423+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 21424+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) 21425+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 21426+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) 21427+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 21428+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 21429+DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32) 21430+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) 21431+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 21432+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 21433+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 21434+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 21435+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 21436+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 21437+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 21438+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 21439+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 21440+DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS) 21441+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 21442+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 21443+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 21444+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) 21445+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 21446+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 21447+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 21448+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 21449+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) 21450+DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT) 21451+DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU) 21452+DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU) 21453+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 21454+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 21455+DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3) 21456+DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3) 21457+DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW) 21458+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 21459+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 21460+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 21461+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 21462+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 21463+DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD) 21464+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 21465+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 21466+DECLARE_INSN(vf, MATCH_VF, MASK_VF) 21467+DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV) 21468+DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW) 21469+DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE) 21470+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD) 21471+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 21472+DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD) 21473+DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD) 21474+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 21475+DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW) 21476+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 21477+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) 21478+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 21479+DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW) 21480+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 21481+DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH) 21482+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) 21483+DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD) 21484+DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB) 21485+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) 21486+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 21487+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 21488+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 21489+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) 21490+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 21491+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 21492+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) 21493+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 21494+DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 21495+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 21496+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 21497+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 21498+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 21499+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) 21500+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 21501+DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW) 21502+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 21503+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) 21504+DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB) 21505+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 21506+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) 21507+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) 21508+DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH) 21509+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 21510+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) 21511+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) 21512+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) 21513+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) 21514+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) 21515+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 21516+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 21517+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) 21518+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) 21519+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) 21520+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 21521+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 21522+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 21523+DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD) 21524+DECLARE_INSN(or, MATCH_OR, MASK_OR) 21525+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 21526+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 21527+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) 21528+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 21529+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 21530+DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE) 21531+DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN) 21532+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 21533+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 21534+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 21535+DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ) 21536+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 21537+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) 21538+DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD) 21539+DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW) 21540+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 21541+DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW) 21542+DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB) 21543+DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD) 21544+DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH) 21545+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 21546+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 21547+DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32) 21548+DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3) 21549+DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL) 21550+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 21551+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) 21552+DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB) 21553+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 21554+DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD) 21555+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) 21556+DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH) 21557+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 21558+DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW) 21559+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 21560+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 21561+#endif 21562+#ifdef DECLARE_CSR 21563+DECLARE_CSR(fflags, CSR_FFLAGS) 21564+DECLARE_CSR(frm, CSR_FRM) 21565+DECLARE_CSR(fcsr, CSR_FCSR) 21566+DECLARE_CSR(cycle, CSR_CYCLE) 21567+DECLARE_CSR(time, CSR_TIME) 21568+DECLARE_CSR(instret, CSR_INSTRET) 21569+DECLARE_CSR(stats, CSR_STATS) 21570+DECLARE_CSR(uarch0, CSR_UARCH0) 21571+DECLARE_CSR(uarch1, CSR_UARCH1) 21572+DECLARE_CSR(uarch2, CSR_UARCH2) 21573+DECLARE_CSR(uarch3, CSR_UARCH3) 21574+DECLARE_CSR(uarch4, CSR_UARCH4) 21575+DECLARE_CSR(uarch5, CSR_UARCH5) 21576+DECLARE_CSR(uarch6, CSR_UARCH6) 21577+DECLARE_CSR(uarch7, CSR_UARCH7) 21578+DECLARE_CSR(uarch8, CSR_UARCH8) 21579+DECLARE_CSR(uarch9, CSR_UARCH9) 21580+DECLARE_CSR(uarch10, CSR_UARCH10) 21581+DECLARE_CSR(uarch11, CSR_UARCH11) 21582+DECLARE_CSR(uarch12, CSR_UARCH12) 21583+DECLARE_CSR(uarch13, CSR_UARCH13) 21584+DECLARE_CSR(uarch14, CSR_UARCH14) 21585+DECLARE_CSR(uarch15, CSR_UARCH15) 21586+DECLARE_CSR(sstatus, CSR_SSTATUS) 21587+DECLARE_CSR(stvec, CSR_STVEC) 21588+DECLARE_CSR(stimecmp, CSR_STIMECMP) 21589+DECLARE_CSR(sscratch, CSR_SSCRATCH) 21590+DECLARE_CSR(sepc, CSR_SEPC) 21591+DECLARE_CSR(sptbr, CSR_SPTBR) 21592+DECLARE_CSR(sasid, CSR_SASID) 21593+DECLARE_CSR(scycle, CSR_SCYCLE) 21594+DECLARE_CSR(stime, CSR_STIME) 21595+DECLARE_CSR(sinstret, CSR_SINSTRET) 21596+DECLARE_CSR(scause, CSR_SCAUSE) 21597+DECLARE_CSR(sbadaddr, CSR_SBADADDR) 21598+DECLARE_CSR(mstatus, CSR_MSTATUS) 21599+DECLARE_CSR(mscratch, CSR_MSCRATCH) 21600+DECLARE_CSR(mepc, CSR_MEPC) 21601+DECLARE_CSR(mcause, CSR_MCAUSE) 21602+DECLARE_CSR(mbadaddr, CSR_MBADADDR) 21603+DECLARE_CSR(reset, CSR_RESET) 21604+DECLARE_CSR(tohost, CSR_TOHOST) 21605+DECLARE_CSR(fromhost, CSR_FROMHOST) 21606+DECLARE_CSR(send_ipi, CSR_SEND_IPI) 21607+DECLARE_CSR(hartid, CSR_HARTID) 21608+DECLARE_CSR(cycleh, CSR_CYCLEH) 21609+DECLARE_CSR(timeh, CSR_TIMEH) 21610+DECLARE_CSR(instreth, CSR_INSTRETH) 21611+DECLARE_CSR(scycleh, CSR_SCYCLEH) 21612+DECLARE_CSR(stimeh, CSR_STIMEH) 21613+DECLARE_CSR(sinstreth, CSR_SINSTRETH) 21614+#endif 21615+#ifdef DECLARE_CAUSE 21616+DECLARE_CAUSE("fflags", CAUSE_FFLAGS) 21617+DECLARE_CAUSE("frm", CAUSE_FRM) 21618+DECLARE_CAUSE("fcsr", CAUSE_FCSR) 21619+DECLARE_CAUSE("cycle", CAUSE_CYCLE) 21620+DECLARE_CAUSE("time", CAUSE_TIME) 21621+DECLARE_CAUSE("instret", CAUSE_INSTRET) 21622+DECLARE_CAUSE("stats", CAUSE_STATS) 21623+DECLARE_CAUSE("uarch0", CAUSE_UARCH0) 21624+DECLARE_CAUSE("uarch1", CAUSE_UARCH1) 21625+DECLARE_CAUSE("uarch2", CAUSE_UARCH2) 21626+DECLARE_CAUSE("uarch3", CAUSE_UARCH3) 21627+DECLARE_CAUSE("uarch4", CAUSE_UARCH4) 21628+DECLARE_CAUSE("uarch5", CAUSE_UARCH5) 21629+DECLARE_CAUSE("uarch6", CAUSE_UARCH6) 21630+DECLARE_CAUSE("uarch7", CAUSE_UARCH7) 21631+DECLARE_CAUSE("uarch8", CAUSE_UARCH8) 21632+DECLARE_CAUSE("uarch9", CAUSE_UARCH9) 21633+DECLARE_CAUSE("uarch10", CAUSE_UARCH10) 21634+DECLARE_CAUSE("uarch11", CAUSE_UARCH11) 21635+DECLARE_CAUSE("uarch12", CAUSE_UARCH12) 21636+DECLARE_CAUSE("uarch13", CAUSE_UARCH13) 21637+DECLARE_CAUSE("uarch14", CAUSE_UARCH14) 21638+DECLARE_CAUSE("uarch15", CAUSE_UARCH15) 21639+DECLARE_CAUSE("sstatus", CAUSE_SSTATUS) 21640+DECLARE_CAUSE("stvec", CAUSE_STVEC) 21641+DECLARE_CAUSE("stimecmp", CAUSE_STIMECMP) 21642+DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH) 21643+DECLARE_CAUSE("sepc", CAUSE_SEPC) 21644+DECLARE_CAUSE("sptbr", CAUSE_SPTBR) 21645+DECLARE_CAUSE("sasid", CAUSE_SASID) 21646+DECLARE_CAUSE("scycle", CAUSE_SCYCLE) 21647+DECLARE_CAUSE("stime", CAUSE_STIME) 21648+DECLARE_CAUSE("sinstret", CAUSE_SINSTRET) 21649+DECLARE_CAUSE("scause", CAUSE_SCAUSE) 21650+DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR) 21651+DECLARE_CAUSE("mstatus", CAUSE_MSTATUS) 21652+DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH) 21653+DECLARE_CAUSE("mepc", CAUSE_MEPC) 21654+DECLARE_CAUSE("mcause", CAUSE_MCAUSE) 21655+DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR) 21656+DECLARE_CAUSE("reset", CAUSE_RESET) 21657+DECLARE_CAUSE("tohost", CAUSE_TOHOST) 21658+DECLARE_CAUSE("fromhost", CAUSE_FROMHOST) 21659+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI) 21660+DECLARE_CAUSE("hartid", CAUSE_HARTID) 21661+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH) 21662+DECLARE_CAUSE("timeh", CAUSE_TIMEH) 21663+DECLARE_CAUSE("instreth", CAUSE_INSTRETH) 21664+DECLARE_CAUSE("scycleh", CAUSE_SCYCLEH) 21665+DECLARE_CAUSE("stimeh", CAUSE_STIMEH) 21666+DECLARE_CAUSE("sinstreth", CAUSE_SINSTRETH) 21667+#endif 21668diff -rNU3 dist.orig/include/opcode/riscv.h dist/include/opcode/riscv.h 21669--- dist.orig/include/opcode/riscv.h 1970-01-01 01:00:00.000000000 +0100 21670+++ dist/include/opcode/riscv.h 2015-10-18 13:11:17.000000000 +0200 21671@@ -0,0 +1,320 @@ 21672+/* riscv.h. RISC-V opcode list for GDB, the GNU debugger. 21673+ Copyright 2011 21674+ Free Software Foundation, Inc. 21675+ Contributed by Andrew Waterman 21676+ 21677+This file is part of GDB, GAS, and the GNU binutils. 21678+ 21679+GDB, GAS, and the GNU binutils are free software; you can redistribute 21680+them and/or modify them under the terms of the GNU General Public 21681+License as published by the Free Software Foundation; either version 21682+1, or (at your option) any later version. 21683+ 21684+GDB, GAS, and the GNU binutils are distributed in the hope that they 21685+will be useful, but WITHOUT ANY WARRANTY; without even the implied 21686+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 21687+the GNU General Public License for more details. 21688+ 21689+You should have received a copy of the GNU General Public License 21690+along with this file; see the file COPYING. If not, write to the Free 21691+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21692+ 21693+#ifndef _RISCV_H_ 21694+#define _RISCV_H_ 21695+ 21696+#include "riscv-opc.h" 21697+#include <stdlib.h> 21698+#include <stdint.h> 21699+ 21700+/* RVC fields */ 21701+ 21702+#define OP_MASK_CRD 0x1f 21703+#define OP_SH_CRD 5 21704+#define OP_MASK_CRS2 0x1f 21705+#define OP_SH_CRS2 5 21706+#define OP_MASK_CRS1 0x1f 21707+#define OP_SH_CRS1 10 21708+#define OP_MASK_CRDS 0x7 21709+#define OP_SH_CRDS 13 21710+#define OP_MASK_CRS2S 0x7 21711+#define OP_SH_CRS2S 13 21712+#define OP_MASK_CRS2BS 0x7 21713+#define OP_SH_CRS2BS 5 21714+#define OP_MASK_CRS1S 0x7 21715+#define OP_SH_CRS1S 10 21716+#define OP_MASK_CIMM6 0x3f 21717+#define OP_SH_CIMM6 10 21718+#define OP_MASK_CIMM5 0x1f 21719+#define OP_SH_CIMM5 5 21720+#define OP_MASK_CIMM10 0x3ff 21721+#define OP_SH_CIMM10 5 21722+ 21723+static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 }; 21724+#define rvc_rd_regmap rvc_rs1_regmap 21725+#define rvc_rs2b_regmap rvc_rs1_regmap 21726+static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 }; 21727+ 21728+typedef uint64_t insn_t; 21729+ 21730+static inline unsigned int riscv_insn_length (insn_t insn) 21731+{ 21732+ if ((insn & 0x3) != 3) /* RVC */ 21733+ return 2; 21734+ if ((insn & 0x1f) != 0x1f) /* base ISA and extensions in 32-bit space */ 21735+ return 4; 21736+ if ((insn & 0x3f) == 0x1f) /* 48-bit extensions */ 21737+ return 6; 21738+ if ((insn & 0x7f) == 0x3f) /* 64-bit extensions */ 21739+ return 8; 21740+ /* longer instructions not supported at the moment */ 21741+ return 2; 21742+} 21743+ 21744+static const char * const riscv_rm[8] = { 21745+ "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" 21746+}; 21747+static const char* const riscv_pred_succ[16] = { 21748+ 0, "w", "r", "rw", "o", "ow", "or", "orw", 21749+ "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw", 21750+}; 21751+ 21752+#define RVC_JUMP_BITS 10 21753+#define RVC_JUMP_ALIGN_BITS 1 21754+#define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS) 21755+#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RVC_JUMP_ALIGN) 21756+ 21757+#define RVC_BRANCH_BITS 5 21758+#define RVC_BRANCH_ALIGN_BITS RVC_JUMP_ALIGN_BITS 21759+#define RVC_BRANCH_ALIGN (1 << RVC_BRANCH_ALIGN_BITS) 21760+#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RVC_BRANCH_ALIGN) 21761+ 21762+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) 21763+#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) 21764+ 21765+#define EXTRACT_ITYPE_IMM(x) \ 21766+ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) 21767+#define EXTRACT_STYPE_IMM(x) \ 21768+ (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) 21769+#define EXTRACT_SBTYPE_IMM(x) \ 21770+ ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) 21771+#define EXTRACT_UTYPE_IMM(x) \ 21772+ ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) 21773+#define EXTRACT_UJTYPE_IMM(x) \ 21774+ ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) 21775+ 21776+#define ENCODE_ITYPE_IMM(x) \ 21777+ (RV_X(x, 0, 12) << 20) 21778+#define ENCODE_STYPE_IMM(x) \ 21779+ ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) 21780+#define ENCODE_SBTYPE_IMM(x) \ 21781+ ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) 21782+#define ENCODE_UTYPE_IMM(x) \ 21783+ (RV_X(x, 12, 20) << 12) 21784+#define ENCODE_UJTYPE_IMM(x) \ 21785+ ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) 21786+ 21787+#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) 21788+#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) 21789+#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) 21790+#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) 21791+#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) 21792+ 21793+#define RISCV_RTYPE(insn, rd, rs1, rs2) \ 21794+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) 21795+#define RISCV_ITYPE(insn, rd, rs1, imm) \ 21796+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) 21797+#define RISCV_STYPE(insn, rs1, rs2, imm) \ 21798+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) 21799+#define RISCV_SBTYPE(insn, rs1, rs2, target) \ 21800+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target)) 21801+#define RISCV_UTYPE(insn, rd, bigimm) \ 21802+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) 21803+#define RISCV_UJTYPE(insn, rd, target) \ 21804+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) 21805+ 21806+#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) 21807+ 21808+#define RISCV_CONST_HIGH_PART(VALUE) \ 21809+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) 21810+#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) 21811+#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) 21812+#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) 21813+ 21814+/* RV fields */ 21815+ 21816+#define OP_MASK_OP 0x7f 21817+#define OP_SH_OP 0 21818+#define OP_MASK_RS2 0x1f 21819+#define OP_SH_RS2 20 21820+#define OP_MASK_RS1 0x1f 21821+#define OP_SH_RS1 15 21822+#define OP_MASK_RS3 0x1f 21823+#define OP_SH_RS3 27 21824+#define OP_MASK_RD 0x1f 21825+#define OP_SH_RD 7 21826+#define OP_MASK_SHAMT 0x3f 21827+#define OP_SH_SHAMT 20 21828+#define OP_MASK_SHAMTW 0x1f 21829+#define OP_SH_SHAMTW 20 21830+#define OP_MASK_RM 0x7 21831+#define OP_SH_RM 12 21832+#define OP_MASK_PRED 0xf 21833+#define OP_SH_PRED 24 21834+#define OP_MASK_SUCC 0xf 21835+#define OP_SH_SUCC 20 21836+#define OP_MASK_AQ 0x1 21837+#define OP_SH_AQ 26 21838+#define OP_MASK_RL 0x1 21839+#define OP_SH_RL 25 21840+ 21841+#define OP_MASK_VRD 0x1f 21842+#define OP_SH_VRD 7 21843+#define OP_MASK_VRS 0x1f 21844+#define OP_SH_VRS 15 21845+#define OP_MASK_VRT 0x1f 21846+#define OP_SH_VRT 20 21847+#define OP_MASK_VRR 0x1f 21848+#define OP_SH_VRR 27 21849+ 21850+#define OP_MASK_VFD 0x1f 21851+#define OP_SH_VFD 7 21852+#define OP_MASK_VFS 0x1f 21853+#define OP_SH_VFS 15 21854+#define OP_MASK_VFT 0x1f 21855+#define OP_SH_VFT 20 21856+#define OP_MASK_VFR 0x1f 21857+#define OP_SH_VFR 27 21858+ 21859+#define OP_MASK_IMMNGPR 0x3f 21860+#define OP_SH_IMMNGPR 20 21861+#define OP_MASK_IMMNFPR 0x3f 21862+#define OP_SH_IMMNFPR 26 21863+#define OP_MASK_IMMSEGNELM 0x7 21864+#define OP_SH_IMMSEGNELM 29 21865+#define OP_MASK_CUSTOM_IMM 0x7f 21866+#define OP_SH_CUSTOM_IMM 25 21867+#define OP_MASK_CSR 0xfff 21868+#define OP_SH_CSR 20 21869+ 21870+#define X_RA 1 21871+#define X_SP 2 21872+#define X_GP 3 21873+#define X_TP 4 21874+#define X_T0 5 21875+#define X_T1 6 21876+#define X_T2 7 21877+#define X_T3 28 21878+ 21879+#define NGPR 32 21880+#define NFPR 32 21881+#define NVGPR 32 21882+#define NVFPR 32 21883+ 21884+#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS 21885+#define RISCV_JUMP_ALIGN_BITS 1 21886+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) 21887+#define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN) 21888+ 21889+#define RISCV_IMM_BITS 12 21890+#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS) 21891+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS) 21892+#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS) 21893+#define RISCV_BRANCH_BITS RISCV_IMM_BITS 21894+#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS 21895+#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) 21896+#define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN) 21897+ 21898+/* This structure holds information for a particular instruction. */ 21899+ 21900+struct riscv_opcode 21901+{ 21902+ /* The name of the instruction. */ 21903+ const char *name; 21904+ /* The ISA subset name (I, M, A, F, D, Xextension). */ 21905+ const char *subset; 21906+ /* A string describing the arguments for this instruction. */ 21907+ const char *args; 21908+ /* The basic opcode for the instruction. When assembling, this 21909+ opcode is modified by the arguments to produce the actual opcode 21910+ that is used. If pinfo is INSN_MACRO, then this is 0. */ 21911+ insn_t match; 21912+ /* If pinfo is not INSN_MACRO, then this is a bit mask for the 21913+ relevant portions of the opcode when disassembling. If the 21914+ actual opcode anded with the match field equals the opcode field, 21915+ then we have found the correct instruction. If pinfo is 21916+ INSN_MACRO, then this field is the macro identifier. */ 21917+ insn_t mask; 21918+ /* A function to determine if a word corresponds to this instruction. 21919+ Usually, this computes ((word & mask) == match). */ 21920+ int (*match_func)(const struct riscv_opcode *op, insn_t word); 21921+ /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 21922+ of bits describing the instruction, notably any relevant hazard 21923+ information. */ 21924+ unsigned long pinfo; 21925+}; 21926+ 21927+#define INSN_WRITE_GPR_D 0x00000001 21928+#define INSN_WRITE_GPR_RA 0x00000004 21929+#define INSN_WRITE_FPR_D 0x00000008 21930+#define INSN_READ_GPR_S 0x00000040 21931+#define INSN_READ_GPR_T 0x00000080 21932+#define INSN_READ_FPR_S 0x00000100 21933+#define INSN_READ_FPR_T 0x00000200 21934+#define INSN_READ_FPR_R 0x00000400 21935+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 21936+#define INSN_ALIAS 0x00001000 21937+/* Instruction is actually a macro. It should be ignored by the 21938+ disassembler, and requires special treatment by the assembler. */ 21939+#define INSN_MACRO 0xffffffff 21940+ 21941+/* This is a list of macro expanded instructions. 21942+ 21943+ _I appended means immediate 21944+ _A appended means address 21945+ _AB appended means address with base register 21946+ _D appended means 64 bit floating point constant 21947+ _S appended means 32 bit floating point constant. */ 21948+ 21949+enum 21950+{ 21951+ M_LA, 21952+ M_LLA, 21953+ M_LA_TLS_GD, 21954+ M_LA_TLS_IE, 21955+ M_LB, 21956+ M_LBU, 21957+ M_LH, 21958+ M_LHU, 21959+ M_LW, 21960+ M_LWU, 21961+ M_LD, 21962+ M_SB, 21963+ M_SH, 21964+ M_SW, 21965+ M_SD, 21966+ M_FLW, 21967+ M_FLD, 21968+ M_FSW, 21969+ M_FSD, 21970+ M_CALL, 21971+ M_J, 21972+ M_LI, 21973+ M_VF, 21974+ M_NUM_MACROS 21975+}; 21976+ 21977+ 21978+extern const char * const riscv_gpr_names_numeric[NGPR]; 21979+extern const char * const riscv_gpr_names_abi[NGPR]; 21980+extern const char * const riscv_fpr_names_numeric[NFPR]; 21981+extern const char * const riscv_fpr_names_abi[NFPR]; 21982+extern const char * const riscv_vec_gpr_names[NVGPR]; 21983+extern const char * const riscv_vec_fpr_names[NVFPR]; 21984+ 21985+extern const struct riscv_opcode riscv_builtin_opcodes[]; 21986+extern const int bfd_riscv_num_builtin_opcodes; 21987+extern struct riscv_opcode *riscv_opcodes; 21988+extern int bfd_riscv_num_opcodes; 21989+#define NUMOPCODES bfd_riscv_num_opcodes 21990+ 21991+#endif /* _RISCV_H_ */ 21992diff -rNU3 dist.orig/ld/Makefile.am dist/ld/Makefile.am 21993--- dist.orig/ld/Makefile.am 2013-03-25 09:06:23.000000000 +0100 21994+++ dist/ld/Makefile.am 2015-10-18 13:11:17.000000000 +0200 21995@@ -145,12 +145,16 @@ 21996 earmelf_linux_eabi.c \ 21997 earmelf_nacl.c \ 21998 earmelf_nbsd.c \ 21999+ earmelf_nbsd_eabi.c \ 22000+ earmelf_nbsd_eabihf.c \ 22001 earmelf_vxworks.c \ 22002 earmelfb.c \ 22003 earmelfb_linux.c \ 22004 earmelfb_linux_eabi.c \ 22005 earmelfb_nacl.c \ 22006 earmelfb_nbsd.c \ 22007+ earmelfb_nbsd_eabi.c \ 22008+ earmelfb_nbsd_eabihf.c \ 22009 earmnbsd.c \ 22010 earmnto.c \ 22011 earmpe.c \ 22012@@ -228,6 +232,7 @@ 22013 eelf32lppc.c \ 22014 eelf32lppcnto.c \ 22015 eelf32lppcsim.c \ 22016+ eelf32lriscv.c \ 22017 eelf32lsmip.c \ 22018 eelf32ltsmip.c \ 22019 eelf32ltsmip_fbsd.c \ 22020@@ -241,9 +246,12 @@ 22021 eelf32mipswindiss.c \ 22022 eelf32moxie.c \ 22023 eelf32mt.c \ 22024- eelf32openrisc.c \ 22025+ eelf32or1k.c \ 22026+ eelf32or1k_linux.c \ 22027+ eelf32or1k_nbsd.c \ 22028 eelf32ppc.c \ 22029 eelf32ppc_fbsd.c \ 22030+ eelf32ppc_nbsd.c \ 22031 eelf32ppclinux.c \ 22032 eelf32ppcnto.c \ 22033 eelf32ppcsim.c \ 22034@@ -402,8 +410,6 @@ 22035 emsp430xW427.c \ 22036 enews.c \ 22037 ens32knbsd.c \ 22038- eor32.c \ 22039- eor32elf.c \ 22040 epc532macha.c \ 22041 epdp11.c \ 22042 epjelf.c \ 22043@@ -469,6 +475,8 @@ 22044 eaarch64elfb.c \ 22045 eaarch64linux.c \ 22046 eaarch64linuxb.c \ 22047+ eaarch64nbsd.c \ 22048+ eaarch64nbsdb.c \ 22049 eelf32_x86_64.c \ 22050 eelf32_x86_64_nacl.c \ 22051 eelf64_aix.c \ 22052@@ -487,6 +495,7 @@ 22053 eelf64btsmip_fbsd.c \ 22054 eelf64hppa.c \ 22055 eelf64lppc.c \ 22056+ eelf64lriscv.c \ 22057 eelf64ltsmip.c \ 22058 eelf64ltsmip_fbsd.c \ 22059 eelf64mmix.c \ 22060@@ -731,6 +740,18 @@ 22061 $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22062 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22063 ${GENSCRIPTS} armelf_nbsd "$(tdir_armelf_nbsd)" 22064+earmelf_nbsd_eabi.c: $(srcdir)/emulparams/armelf_nbsd_eabi.sh \ 22065+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22066+ $(srcdir)/emulparams/armelf.sh \ 22067+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22068+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22069+ ${GENSCRIPTS} armelf_nbsd_eabi "$(tdir_armelf_nbsd_eabi)" 22070+earmelf_nbsd_eabihf.c: $(srcdir)/emulparams/armelf_nbsd_eabihf.sh \ 22071+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22072+ $(srcdir)/emulparams/armelf.sh \ 22073+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22074+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22075+ ${GENSCRIPTS} armelf_nbsd_eabihf "$(tdir_armelf_nbsd_eabihf)" 22076 earmelf_vxworks.c: $(srcdir)/emulparams/armelf_vxworks.sh \ 22077 $(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/armelf.sh \ 22078 $(ELF_DEPS) $(srcdir)/emultempl/vxworks.em \ 22079@@ -766,6 +787,19 @@ 22080 $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22081 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22082 ${GENSCRIPTS} armelfb_nbsd "$(tdir_armelfb_nbsd)" 22083+earmelfb_nbsd_eabi.c: $(srcdir)/emulparams/armelfb_nbsd_eabi.sh \ 22084+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22085+ $(srcdir)/emulparams/armelf.sh \ 22086+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22087+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22088+ ${GENSCRIPTS} armelfb_nbsd_eabi "$(tdir_armelfb_nbsd_eabi)" 22089+earmelfb_nbsd_eabihf.c: $(srcdir)/emulparams/armelfb_nbsd_eabihf.sh \ 22090+ $(srcdir)/emulparams/armelf_nbsd_eabi.sh \ 22091+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22092+ $(srcdir)/emulparams/armelf.sh \ 22093+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22094+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22095+ ${GENSCRIPTS} armelfb_nbsd_eabihf "$(tdir_armelfb_nbsd_eabihf)" 22096 earmnbsd.c: $(srcdir)/emulparams/armnbsd.sh \ 22097 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} 22098 ${GENSCRIPTS} armnbsd "$(tdir_armnbsd)" 22099@@ -1080,6 +1114,10 @@ 22100 ldemul-list.h \ 22101 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22102 ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)" 22103+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ 22104+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ 22105+ $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22106+ ${GENSCRIPTS} elf32lriscv "$(tdir_elf32lriscv)" 22107 eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ 22108 $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ 22109 $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ 22110@@ -1130,9 +1168,17 @@ 22111 eelf32mt.c: $(srcdir)/emulparams/elf32mt.sh \ 22112 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22113 ${GENSCRIPTS} elf32mt "$(tdir_mt)" 22114-eelf32openrisc.c: $(srcdir)/emulparams/elf32openrisc.sh \ 22115+eelf32or1k.c: $(srcdir)/emulparams/elf32or1k.sh \ 22116+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22117+ ${GENSCRIPTS} elf32or1k "$(tdir_or1k)" 22118+eelf32or1k_linux.c: $(srcdir)/emulparams/elf32or1k_linux.sh \ 22119+ $(srcdir)/emulparams/elf32or1k.sh \ 22120 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22121- ${GENSCRIPTS} elf32openrisc "$(tdir_openrisc)" 22122+ ${GENSCRIPTS} elf32or1k_linux "$(tdir_or1k_linux)" 22123+eelf32or1k_nbsd.c: $(srcdir)/emulparams/elf32or1k_nbsd.sh \ 22124+ $(srcdir)/emulparams/elf32or1k.sh \ 22125+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22126+ ${GENSCRIPTS} elf32or1k_nbsd "$(tdir_or1k_nbsd)" 22127 eelf32ppc.c: $(srcdir)/emulparams/elf32ppc.sh \ 22128 $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ 22129 ldemul-list.h \ 22130@@ -1144,6 +1190,12 @@ 22131 ldemul-list.h \ 22132 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22133 ${GENSCRIPTS} elf32ppc_fbsd "$(tdir_elf32ppc_fbsd)" 22134+eelf32ppc_nbsd.c: $(srcdir)/emulparams/elf32ppc_nbsd.sh \ 22135+ $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ 22136+ $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ 22137+ ldemul-list.h \ 22138+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22139+ ${GENSCRIPTS} elf32ppc_nbsd "$(tdir_elf32ppc_nbsd)" 22140 eelf32ppclinux.c: $(srcdir)/emulparams/elf32ppclinux.sh \ 22141 $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ 22142 $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ 22143@@ -1741,6 +1793,14 @@ 22144 $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ 22145 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22146 ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)" 22147+eaarch64nbsd.c: $(srcdir)/emulparams/aarch64nbsd.sh \ 22148+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ 22149+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22150+ ${GENSCRIPTS} aarch64nbsd "$(tdir_aarch64nbsd)" 22151+eaarch64nbsdb.c: $(srcdir)/emulparams/aarch64nbsdb.sh $(srcdir)/emulparams/aarch64nbsd.sh \ 22152+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ 22153+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22154+ ${GENSCRIPTS} aarch64nbsdb "$(tdir_aarch64nbsdb)" 22155 eor32.c: $(srcdir)/emulparams/or32.sh \ 22156 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS} 22157 ${GENSCRIPTS} or32 "$(tdir_or32)" 22158@@ -2029,6 +2089,11 @@ 22159 ldemul-list.h \ 22160 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22161 ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)" 22162+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ 22163+ $(srcdir)/emulparams/elf64lriscv-defs.sh \ 22164+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ 22165+ $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22166+ ${GENSCRIPTS} elf64lriscv "$(tdir_elf64lriscv)" 22167 eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ 22168 $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ 22169 $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ 22170@@ -2219,6 +2284,8 @@ 22171 # because almost all configs use "gen" version of manual. 22172 # Set DOCVER above to change. 22173 configdoc.texi: ${DOCVER}-doc.texi 22174+ @echo "NOT REBUILDING $@" 22175+NetBSD_DISABLED_configdoc.texi: 22176 cp ${srcdir}/${DOCVER}-doc.texi ./configdoc.texi 22177 chmod u+w ./configdoc.texi 22178 22179@@ -2226,6 +2293,8 @@ 22180 # The sed command removes the no-adjust Nroff command so that 22181 # the man output looks standard. 22182 ld.1: $(srcdir)/ld.texinfo configdoc.texi 22183+ @echo "NOT REBUILDING $@" 22184+NetBSD_DISABLED_ld.1: 22185 touch $@ 22186 -$(TEXI2POD) $(MANCONF) < $(srcdir)/ld.texinfo > ld.pod 22187 -($(POD2MAN) ld.pod | \ 22188diff -rNU3 dist.orig/ld/Makefile.in dist/ld/Makefile.in 22189--- dist.orig/ld/Makefile.in 2013-03-25 09:06:23.000000000 +0100 22190+++ dist/ld/Makefile.in 2015-10-18 13:11:17.000000000 +0200 22191@@ -452,12 +452,16 @@ 22192 earmelf_linux_eabi.c \ 22193 earmelf_nacl.c \ 22194 earmelf_nbsd.c \ 22195+ earmelf_nbsd_eabi.c \ 22196+ earmelf_nbsd_eabihf.c \ 22197 earmelf_vxworks.c \ 22198 earmelfb.c \ 22199 earmelfb_linux.c \ 22200 earmelfb_linux_eabi.c \ 22201 earmelfb_nacl.c \ 22202 earmelfb_nbsd.c \ 22203+ earmelfb_nbsd_eabi.c \ 22204+ earmelfb_nbsd_eabihf.c \ 22205 earmnbsd.c \ 22206 earmnto.c \ 22207 earmpe.c \ 22208@@ -535,6 +539,7 @@ 22209 eelf32lppc.c \ 22210 eelf32lppcnto.c \ 22211 eelf32lppcsim.c \ 22212+ eelf32lriscv.c \ 22213 eelf32lsmip.c \ 22214 eelf32ltsmip.c \ 22215 eelf32ltsmip_fbsd.c \ 22216@@ -548,9 +553,12 @@ 22217 eelf32mipswindiss.c \ 22218 eelf32moxie.c \ 22219 eelf32mt.c \ 22220- eelf32openrisc.c \ 22221+ eelf32or1k.c \ 22222+ eelf32or1k_linux.c \ 22223+ eelf32or1k_nbsd.c \ 22224 eelf32ppc.c \ 22225 eelf32ppc_fbsd.c \ 22226+ eelf32ppc_nbsd.c \ 22227 eelf32ppclinux.c \ 22228 eelf32ppcnto.c \ 22229 eelf32ppcsim.c \ 22230@@ -709,8 +717,6 @@ 22231 emsp430xW427.c \ 22232 enews.c \ 22233 ens32knbsd.c \ 22234- eor32.c \ 22235- eor32elf.c \ 22236 epc532macha.c \ 22237 epdp11.c \ 22238 epjelf.c \ 22239@@ -775,6 +781,8 @@ 22240 eaarch64elfb.c \ 22241 eaarch64linux.c \ 22242 eaarch64linuxb.c \ 22243+ eaarch64nbsd.c \ 22244+ eaarch64nbsdb.c \ 22245 eelf32_x86_64.c \ 22246 eelf32_x86_64_nacl.c \ 22247 eelf64_aix.c \ 22248@@ -793,6 +801,7 @@ 22249 eelf64btsmip_fbsd.c \ 22250 eelf64hppa.c \ 22251 eelf64lppc.c \ 22252+ eelf64lriscv.c \ 22253 eelf64ltsmip.c \ 22254 eelf64ltsmip_fbsd.c \ 22255 eelf64mmix.c \ 22256@@ -1060,6 +1069,8 @@ 22257 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64elfb.Po@am__quote@ 22258 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64linux.Po@am__quote@ 22259 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64linuxb.Po@am__quote@ 22260+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64nbsd.Po@am__quote@ 22261+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaarch64nbsdb.Po@am__quote@ 22262 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaix5ppc.Po@am__quote@ 22263 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaix5rs6.Po@am__quote@ 22264 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixppc.Po@am__quote@ 22265@@ -1078,12 +1089,16 @@ 22266 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_linux_eabi.Po@am__quote@ 22267 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_nacl.Po@am__quote@ 22268 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_nbsd.Po@am__quote@ 22269+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_nbsd_eabi.Po@am__quote@ 22270+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_nbsd_eabihf.Po@am__quote@ 22271 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_vxworks.Po@am__quote@ 22272 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb.Po@am__quote@ 22273 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_linux.Po@am__quote@ 22274 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_linux_eabi.Po@am__quote@ 22275 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_nacl.Po@am__quote@ 22276 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_nbsd.Po@am__quote@ 22277+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_nbsd_eabi.Po@am__quote@ 22278+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelfb_nbsd_eabihf.Po@am__quote@ 22279 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmnbsd.Po@am__quote@ 22280 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmnto.Po@am__quote@ 22281 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmpe.Po@am__quote@ 22282@@ -1156,6 +1171,7 @@ 22283 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppc.Po@am__quote@ 22284 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcnto.Po@am__quote@ 22285 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@ 22286+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Po@am__quote@ 22287 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@ 22288 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmip.Po@am__quote@ 22289 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmip_fbsd.Po@am__quote@ 22290@@ -1169,9 +1185,12 @@ 22291 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Po@am__quote@ 22292 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32moxie.Po@am__quote@ 22293 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mt.Po@am__quote@ 22294-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32openrisc.Po@am__quote@ 22295+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32or1k.Po@am__quote@ 22296+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32or1k_linux.Po@am__quote@ 22297+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32or1k_nbsd.Po@am__quote@ 22298 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppc.Po@am__quote@ 22299 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppc_fbsd.Po@am__quote@ 22300+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppc_nbsd.Po@am__quote@ 22301 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppclinux.Po@am__quote@ 22302 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppcnto.Po@am__quote@ 22303 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppcsim.Po@am__quote@ 22304@@ -1204,6 +1223,7 @@ 22305 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@ 22306 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@ 22307 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@ 22308+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@ 22309 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@ 22310 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@ 22311 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@ 22312@@ -1363,8 +1383,6 @@ 22313 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW427.Po@am__quote@ 22314 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/enews.Po@am__quote@ 22315 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ens32knbsd.Po@am__quote@ 22316-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32.Po@am__quote@ 22317-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32elf.Po@am__quote@ 22318 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epc532macha.Po@am__quote@ 22319 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epdp11.Po@am__quote@ 22320 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epjelf.Po@am__quote@ 22321@@ -1490,6 +1508,8 @@ 22322 -rm -f libtool config.lt 22323 22324 ld.info: ld.texinfo $(ld_TEXINFOS) 22325+ @echo "NOT REBUILDING $@" 22326+NetBSD_DISABLED_ld.info: ld.texinfo $(ld_TEXINFOS) 22327 restore=: && backupdir="$(am__leading_dot)am$$$$" && \ 22328 rm -rf $$backupdir && mkdir $$backupdir && \ 22329 if ($(MAKEINFO) --version) >/dev/null 2>&1; then \ 22330@@ -2201,6 +2221,18 @@ 22331 $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22332 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22333 ${GENSCRIPTS} armelf_nbsd "$(tdir_armelf_nbsd)" 22334+earmelf_nbsd_eabi.c: $(srcdir)/emulparams/armelf_nbsd_eabi.sh \ 22335+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22336+ $(srcdir)/emulparams/armelf.sh \ 22337+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22338+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22339+ ${GENSCRIPTS} armelf_nbsd_eabi "$(tdir_armelf_nbsd_eabi)" 22340+earmelf_nbsd_eabihf.c: $(srcdir)/emulparams/armelf_nbsd_eabihf.sh \ 22341+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22342+ $(srcdir)/emulparams/armelf.sh \ 22343+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22344+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22345+ ${GENSCRIPTS} armelf_nbsd_eabihf "$(tdir_armelf_nbsd_eabihf)" 22346 earmelf_vxworks.c: $(srcdir)/emulparams/armelf_vxworks.sh \ 22347 $(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/armelf.sh \ 22348 $(ELF_DEPS) $(srcdir)/emultempl/vxworks.em \ 22349@@ -2236,6 +2268,20 @@ 22350 $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22351 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22352 ${GENSCRIPTS} armelfb_nbsd "$(tdir_armelfb_nbsd)" 22353+earmelfb_nbsd_eabi.c: $(srcdir)/emulparams/armelfb_nbsd_eabi.sh \ 22354+ $(srcdir)/emulparams/armelf_nbsd_eabi.sh \ 22355+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22356+ $(srcdir)/emulparams/armelf.sh \ 22357+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22358+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22359+ ${GENSCRIPTS} armelfb_nbsd_eabi "$(tdir_armelfb_nbsd_eabi)" 22360+earmelfb_nbsd_eabihf.c: $(srcdir)/emulparams/armelfb_nbsd_eabihf.sh \ 22361+ $(srcdir)/emulparams/armelf_nbsd_eabihf.sh \ 22362+ $(srcdir)/emulparams/armelf_nbsd.sh \ 22363+ $(srcdir)/emulparams/armelf.sh \ 22364+ $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ 22365+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22366+ ${GENSCRIPTS} armelfb_nbsd_eabihf "$(tdir_armelfb_nbsd_eabihf)" 22367 earmnbsd.c: $(srcdir)/emulparams/armnbsd.sh \ 22368 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} 22369 ${GENSCRIPTS} armnbsd "$(tdir_armnbsd)" 22370@@ -2550,6 +2596,10 @@ 22371 ldemul-list.h \ 22372 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22373 ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)" 22374+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ 22375+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ 22376+ $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22377+ ${GENSCRIPTS} elf32lriscv "$(tdir_elf32lriscv)" 22378 eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ 22379 $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ 22380 $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ 22381@@ -2600,9 +2650,17 @@ 22382 eelf32mt.c: $(srcdir)/emulparams/elf32mt.sh \ 22383 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22384 ${GENSCRIPTS} elf32mt "$(tdir_mt)" 22385-eelf32openrisc.c: $(srcdir)/emulparams/elf32openrisc.sh \ 22386+eelf32or1k.c: $(srcdir)/emulparams/elf32or1k.sh \ 22387+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22388+ ${GENSCRIPTS} elf32or1k "$(tdir_or1k)" 22389+eelf32or1k_linux.c: $(srcdir)/emulparams/elf32or1k_linux.sh \ 22390+ $(srcdir)/emulparams/elf32or1k.sh \ 22391+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22392+ ${GENSCRIPTS} elf32or1k_linux "$(tdir_or1k_linux)" 22393+eelf32or1k_nbsd.c: $(srcdir)/emulparams/elf32or1k_nbsd.sh \ 22394+ $(srcdir)/emulparams/elf32or1k.sh \ 22395 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22396- ${GENSCRIPTS} elf32openrisc "$(tdir_openrisc)" 22397+ ${GENSCRIPTS} elf32or1k_nbsd "$(tdir_or1k_nbsd)" 22398 eelf32ppc.c: $(srcdir)/emulparams/elf32ppc.sh \ 22399 $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ 22400 ldemul-list.h \ 22401@@ -2614,6 +2672,12 @@ 22402 ldemul-list.h \ 22403 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22404 ${GENSCRIPTS} elf32ppc_fbsd "$(tdir_elf32ppc_fbsd)" 22405+eelf32ppc_nbsd.c: $(srcdir)/emulparams/elf32ppc_nbsd.sh \ 22406+ $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ 22407+ $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ 22408+ ldemul-list.h \ 22409+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22410+ ${GENSCRIPTS} elf32ppc_nbsd "$(tdir_elf32ppc_nbsd)" 22411 eelf32ppclinux.c: $(srcdir)/emulparams/elf32ppclinux.sh \ 22412 $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ 22413 $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ 22414@@ -3211,12 +3275,14 @@ 22415 $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ 22416 $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22417 ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)" 22418-eor32.c: $(srcdir)/emulparams/or32.sh \ 22419- $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS} 22420- ${GENSCRIPTS} or32 "$(tdir_or32)" 22421-eor32elf.c: $(srcdir)/emulparams/or32elf.sh \ 22422- $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22423- ${GENSCRIPTS} or32elf "$(tdir_or32elf)" 22424+eaarch64nbsd.c: $(srcdir)/emulparams/aarch64nbsd.sh \ 22425+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ 22426+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22427+ ${GENSCRIPTS} aarch64nbsd "$(tdir_aarch64nbsd)" 22428+eaarch64nbsdb.c: $(srcdir)/emulparams/aarch64nbsdb.sh $(srcdir)/emulparams/aarch64nbsd.sh \ 22429+ $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ 22430+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22431+ ${GENSCRIPTS} aarch64nbsdb "$(tdir_aarch64nbsdb)" 22432 epc532macha.c: $(srcdir)/emulparams/pc532macha.sh \ 22433 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} 22434 ${GENSCRIPTS} pc532macha "$(tdir_pc532macha)" 22435@@ -3499,6 +3565,11 @@ 22436 ldemul-list.h \ 22437 $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22438 ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)" 22439+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ 22440+ $(srcdir)/emulparams/elf64lriscv-defs.sh \ 22441+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ 22442+ $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} 22443+ ${GENSCRIPTS} elf64lriscv "$(tdir_elf64lriscv)" 22444 eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ 22445 $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ 22446 $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ 22447@@ -3632,6 +3703,8 @@ 22448 # because almost all configs use "gen" version of manual. 22449 # Set DOCVER above to change. 22450 configdoc.texi: ${DOCVER}-doc.texi 22451+ @echo "NOT REBUILDING $@" 22452+NetBSD_DISABLED_configdoc.texi: 22453 cp ${srcdir}/${DOCVER}-doc.texi ./configdoc.texi 22454 chmod u+w ./configdoc.texi 22455 22456@@ -3639,6 +3712,8 @@ 22457 # The sed command removes the no-adjust Nroff command so that 22458 # the man output looks standard. 22459 ld.1: $(srcdir)/ld.texinfo configdoc.texi 22460+ @echo "NOT REBUILDING $@" 22461+NetBSD_DISABLED_ld.1: 22462 touch $@ 22463 -$(TEXI2POD) $(MANCONF) < $(srcdir)/ld.texinfo > ld.pod 22464 -($(POD2MAN) ld.pod | \ 22465diff -rNU3 dist.orig/ld/configdoc.texi dist/ld/configdoc.texi 22466--- dist.orig/ld/configdoc.texi 2012-11-13 15:19:33.000000000 +0100 22467+++ dist/ld/configdoc.texi 1970-01-01 01:00:00.000000000 +0100 22468@@ -1,27 +0,0 @@ 22469-@c ------------------------------ CONFIGURATION VARS: 22470-@c 1. Inclusiveness of this manual 22471-@set GENERIC 22472- 22473-@c 2. Specific target machines 22474-@set ARM 22475-@set C6X 22476-@set H8300 22477-@set HPPA 22478-@set I960 22479-@set M68HC11 22480-@set M68K 22481-@set MMIX 22482-@set MSP430 22483-@set POWERPC 22484-@set POWERPC64 22485-@set Renesas 22486-@set SPU 22487-@set TICOFF 22488-@set WIN32 22489-@set XTENSA 22490- 22491-@c 3. Properties of this configuration 22492-@clear SingleFormat 22493-@set UsesEnvVars 22494-@c ------------------------------ end CONFIGURATION VARS 22495- 22496diff -rNU3 dist.orig/ld/configure.tgt dist/ld/configure.tgt 22497--- dist.orig/ld/configure.tgt 2012-09-04 14:53:47.000000000 +0200 22498+++ dist/ld/configure.tgt 2015-10-18 13:11:17.000000000 +0200 22499@@ -35,6 +35,10 @@ 22500 targ_extra_emuls="aarch64linux aarch64elfb aarch64elf armelfb_linux_eabi armelf_linux_eabi armelfb armelf" ;; 22501 aarch64-*-linux*) targ_emul=aarch64linux 22502 targ_extra_emuls="aarch64linuxb aarch64elf aarch64elfb armelf_linux_eabi armelfb_linux_eabi armelf armelfb" ;; 22503+aarch64_be-*-netbsd*) targ_emul=aarch64nbsdb 22504+ targ_extra_emuls="aarch64nbsd aarch64elfb aarch64elf armelfb_nbsd_eabihf armelf_nbsd_eabihf armelfb_nbsd_eabi armelf_nbsd_eabi armelfb_nbsd armelf_nbsd armelf armelfb" ;; 22505+aarch64-*-netbsd*) targ_emul=aarch64nbsd 22506+ targ_extra_emuls="aarch64nbsdb aarch64elf aarch64elfb armelf_nbsd_eabihf armelfb_nbsd_eabihf armelf_nbsd_eabi armelfb_nbsd_eabi armelf_nbsd armelfb_nbsd armelf armelfb" ;; 22507 alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu) 22508 targ_emul=elf64alpha_fbsd 22509 targ_extra_emuls="elf64alpha alpha" 22510@@ -64,7 +68,19 @@ 22511 arm-*-freebsd* | arm-*-kfreebsd*-gnu) 22512 targ_emul=armelf_fbsd 22513 targ_extra_emuls="armelf" ;; 22514-armeb-*-netbsdelf*) targ_emul=armelfb_nbsd; 22515+arm*eb-*-netbsdelf*-*eabihf*) 22516+ targ_emul=armelfb_nbsd_eabihf; 22517+ targ_extra_emuls="armelf_nbsd_eabihf armelf_nbsd_eabi armelfb_nbsd_eabi armelf_nbsd armelfb_nbsd armelf armnbsd" ;; 22518+arm*eb-*-netbsdelf*-*eabi*) 22519+ targ_emul=armelfb_nbsd_eabi; 22520+ targ_extra_emuls="armelf_nbsd_eabi armelf_nbsd_eabihf armelfb_nbsd_eabihf armelf_nbsd armelfb_nbsd armelf armnbsd" ;; 22521+arm*-*-netbsdelf*-*eabihf*) 22522+ targ_emul=armelf_nbsd_eabihf; 22523+ targ_extra_emuls="armelfb_nbsd_eabihf armelf_nbsd_eabi armelfb_nbsd_eabi armelf_nbsd armelfb_nbsd armelf armnbsd" ;; 22524+arm*-*-netbsdelf*-*eabi*) 22525+ targ_emul=armelf_nbsd_eabi; 22526+ targ_extra_emuls="armelfb_nbsd_eabi armelf_nbsd_eabihf armelfb_nbsd_eabihf armelf_nbsd armelfb_nbsd armelf armnbsd" ;; 22527+arm*eb-*-netbsdelf*) targ_emul=armelfb_nbsd; 22528 targ_extra_emuls="armelf_nbsd armelf armnbsd" ;; 22529 arm-*-netbsdelf*) targ_emul=armelf_nbsd; 22530 targ_extra_emuls="armelfb_nbsd armelf armnbsd" ;; 22531@@ -379,7 +395,8 @@ 22532 m68*-*-gnu*) targ_emul=m68kelf ;; 22533 m68*-*-netbsd*4k*) targ_emul=m68k4knbsd 22534 targ_extra_emuls="m68knbsd m68kelfnbsd" ;; 22535-m68*-*-netbsdelf*) targ_emul=m68kelfnbsd 22536+m68*-*-netbsdelf* | m5407*-*-netbsdelf*) 22537+ targ_emul=m68kelfnbsd 22538 targ_extra_emuls="m68knbsd m68k4knbsd" ;; 22539 m68*-*-netbsdaout* | m68*-*-netbsd*) 22540 targ_emul=m68knbsd 22541@@ -409,12 +426,18 @@ 22542 mips*-sgi-irix*) targ_emul=mipsbig ;; 22543 mips*el-*-ecoff*) targ_emul=mipsidtl ;; 22544 mips*-*-ecoff*) targ_emul=mipsidt ;; 22545+mips64*el-*-netbsd*) targ_emul=elf32ltsmipn32 22546+ targ_extra_emuls="elf64btsmip elf64ltsmip elf32ltsmip elf32btsmipn32 elf32btsmip" 22547+ ;; 22548+mips64*-*-netbsd*) targ_emul=elf32btsmipn32 22549+ targ_extra_emuls="elf64ltsmip elf64btsmip elf32btsmip elf32ltsmipn32 elf32ltsmip" 22550+ ;; 22551 mips*el-*-netbsd*) targ_emul=elf32ltsmip 22552 targ_extra_emuls="elf32btsmip elf64ltsmip elf64btsmip" 22553 ;; 22554 mips*-*-netbsd*) targ_emul=elf32btsmip 22555 targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" 22556- ;; 22557+ ;; 22558 mips*-*-bsd*) targ_emul=mipsbig ;; 22559 mips*vr4300el-*-elf*) targ_emul=elf32l4300 ;; 22560 mips*vr4300-*-elf*) targ_emul=elf32b4300 ;; 22561@@ -481,11 +504,11 @@ 22562 ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;; 22563 ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd 22564 ;; 22565-openrisc-*-*) targ_emul=elf32openrisc ;; 22566-or32-*-coff) targ_emul=or32 ;; 22567-or32-*-elf) targ_emul=or32elf ;; 22568-or32-*-rtems*) targ_emul=or32elf 22569- ;; 22570+or1k-*-elf | or1knd-*-elf) targ_emul=elf32or1k ;; 22571+or1k-*-linux* | or1knd-*-linux*) targ_emul=elf32or1k_linux ;; 22572+or1k-*-netbsd* | or1knd-*-netbsd*) targ_emul=elf32or1k_nbsd ;; 22573+or1k-*-rtems* | or1knd-*-rtems*) targ_emul=elf32or1k ;; 22574+ 22575 pdp11-*-*) targ_emul=pdp11 22576 ;; 22577 pjl*-*-*) targ_emul=pjlelf ; targ_extra_emuls="elf_i386" ;; 22578@@ -529,8 +552,18 @@ 22579 *) targ_emul=elf32lppc 22580 targ_extra_emuls="elf32ppcsim" ;; 22581 esac ;; 22582+powerpc64*-*-netbsd*) 22583+ targ_emul=elf64ppc 22584+ targ_extra_emuls="elf32ppc elf32ppc_nbsd elf32ppcsim" 22585+ tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'` 22586+ tdir_elf32ppc_nbsd=$tdir_elf32ppc 22587+ tdir_elf32ppcsim=$tdir_elf32ppc 22588+ ;; 22589+powerpc*-*-netbsd*) 22590+ targ_emul=elf32ppc_nbsd 22591+ targ_extra_emuls="elf32ppc elf32ppcsim" ;; 22592 powerpc*-*-elf* | powerpc*-*-eabi* | powerpc*-*-sysv* \ 22593- | powerpc*-*-netbsd* | powerpc-*-openbsd* | powerpc*-*-kaos*) 22594+ | powerpc-*-openbsd* | powerpc*-*-kaos*) 22595 case "${targ}" in 22596 *64*) targ_emul=elf64ppc 22597 targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim" 22598@@ -557,6 +590,12 @@ 22599 powerpc-*-beos*) targ_emul=aixppc ;; 22600 powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;; 22601 powerpc-*-lynxos*) targ_emul=ppclynx ;; 22602+riscv32-*-*) targ_emul=elf32lriscv 22603+ targ_extra_emuls="elf64lriscv" 22604+ targ_extra_libpath=$targ_extra_emuls ;; 22605+riscv*-*-*) targ_emul=elf64lriscv 22606+ targ_extra_emuls="elf32lriscv" 22607+ targ_extra_libpath=$targ_extra_emuls ;; 22608 rs6000-*-aix[5-9]*) targ_emul=aix5rs6 ;; 22609 rs6000-*-aix*) targ_emul=aixrs6 22610 ;; 22611@@ -654,10 +693,15 @@ 22612 tdir_sparclinux=${targ_alias}aout 22613 tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'` 22614 tdir_sun4=sparc-sun-sunos4 ;; 22615-sparc64-*-netbsd* | sparc64-*-openbsd*) 22616- targ_emul=elf64_sparc 22617- targ_extra_emuls="elf32_sparc" ;; 22618-sparc*-*-netbsd*elf*) targ_emul=elf32_sparc ;; 22619+sparc64-*-netbsd*) targ_emul=elf64_sparc 22620+ targ_extra_emuls="elf32_sparc sparcnbsd" 22621+ ;; 22622+sparc64-*-openbsd*) targ_emul=elf64_sparc 22623+ targ_extra_emuls="elf32_sparc" 22624+ ;; 22625+sparc*-*-netbsd*elf*) targ_emul=elf32_sparc 22626+ targ_extra_emuls=sparcnbsd 22627+ ;; 22628 sparc*-*-netbsd*) targ_emul=sparcnbsd ;; 22629 sparc-*-solaris2.[0-6] | sparc-*-solaris2.[0-6].*) 22630 targ_emul=elf32_sparc_sol2 22631diff -rNU3 dist.orig/ld/emulparams/aarch64nbsd.sh dist/ld/emulparams/aarch64nbsd.sh 22632--- dist.orig/ld/emulparams/aarch64nbsd.sh 1970-01-01 01:00:00.000000000 +0100 22633+++ dist/ld/emulparams/aarch64nbsd.sh 2015-10-18 13:11:17.000000000 +0200 22634@@ -0,0 +1,36 @@ 22635+ARCH=aarch64 22636+MACHINE= 22637+NOP=0 22638+ 22639+SCRIPT_NAME=elf 22640+OUTPUT_FORMAT="elf64-littleaarch64" 22641+BIG_OUTPUT_FORMAT="elf64-bigaarch64" 22642+LITTLE_OUTPUT_FORMAT="elf64-littleaarch64" 22643+NO_REL_RELOCS=yes 22644+ 22645+TEMPLATE_NAME=elf32 22646+EXTRA_EM_FILE=aarch64elf 22647+ 22648+GENERATE_SHLIB_SCRIPT=yes 22649+GENERATE_PIE_SCRIPT=yes 22650+ 22651+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" 22652+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" 22653+SEPARATE_GOTPLT=24 22654+IREL_IN_PLT= 22655+ 22656+TEXT_START_ADDR=0x200100000 22657+ 22658+DATA_START_SYMBOLS='PROVIDE (__data_start = .);'; 22659+ 22660+# AArch64 does not support .s* sections. 22661+NO_SMALL_DATA=yes 22662+ 22663+OTHER_BSS_SYMBOLS='__bss_start__ = .;' 22664+OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ;' 22665+OTHER_END_SYMBOLS='__end__ = . ;' 22666+ 22667+OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }' 22668+ATTRS_SECTIONS='.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }' 22669+# Ensure each PLT entry is aligned to a cache line. 22670+PLT=".plt ${RELOCATING-0} : ALIGN(16) { *(.plt)${IREL_IN_PLT+ *(.iplt)} }" 22671diff -rNU3 dist.orig/ld/emulparams/aarch64nbsdb.sh dist/ld/emulparams/aarch64nbsdb.sh 22672--- dist.orig/ld/emulparams/aarch64nbsdb.sh 1970-01-01 01:00:00.000000000 +0100 22673+++ dist/ld/emulparams/aarch64nbsdb.sh 2015-10-18 13:11:17.000000000 +0200 22674@@ -0,0 +1,2 @@ 22675+. ${srcdir}/emulparams/aarch64nbsd.sh 22676+OUTPUT_FORMAT="elf64-bigaarch64" 22677diff -rNU3 dist.orig/ld/emulparams/armelf_nbsd.sh dist/ld/emulparams/armelf_nbsd.sh 22678--- dist.orig/ld/emulparams/armelf_nbsd.sh 2006-05-30 18:45:32.000000000 +0200 22679+++ dist/ld/emulparams/armelf_nbsd.sh 2015-10-18 13:11:17.000000000 +0200 22680@@ -1,7 +1,14 @@ 22681 . ${srcdir}/emulparams/armelf.sh 22682 MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" 22683-TEXT_START_ADDR=0x00008000 22684+TEXT_START_ADDR=0x00010000 22685 TARGET2_TYPE=got-rel 22686 22687+unset DATA_START_SYMBOLS 22688 unset STACK_ADDR 22689 unset EMBEDDED 22690+ 22691+case "$target" in 22692+ aarch64*-*-netbsd* | arm*-*-netbsdelf*-*eabi*) 22693+ LIB_PATH='=/usr/lib/oabi' 22694+ ;; 22695+esac 22696diff -rNU3 dist.orig/ld/emulparams/armelf_nbsd_eabi.sh dist/ld/emulparams/armelf_nbsd_eabi.sh 22697--- dist.orig/ld/emulparams/armelf_nbsd_eabi.sh 1970-01-01 01:00:00.000000000 +0100 22698+++ dist/ld/emulparams/armelf_nbsd_eabi.sh 2015-10-18 13:11:17.000000000 +0200 22699@@ -0,0 +1,20 @@ 22700+. ${srcdir}/emulparams/armelf_nbsd.sh 22701+ 22702+# Use the ARM ABI-compliant exception-handling sections. 22703+OTHER_READONLY_SECTIONS=" 22704+ .ARM.extab ${RELOCATING-0} : { *(.ARM.extab${RELOCATING+* .gnu.linkonce.armextab.*}) } 22705+ ${RELOCATING+ PROVIDE_HIDDEN (__exidx_start = .); } 22706+ .ARM.exidx ${RELOCATING-0} : { *(.ARM.exidx${RELOCATING+* .gnu.linkonce.armexidx.*}) } 22707+ ${RELOCATING+ PROVIDE_HIDDEN (__exidx_end = .); }" 22708+ 22709+case "$target" in 22710+ arm*-*-netbsdelf*-*eabihf*) 22711+ LIB_PATH='=/usr/lib/eabi' 22712+ ;; 22713+ arm*-*-netbsdelf*-*eabi*) 22714+ LIB_PATH='=/usr/lib' 22715+ ;; 22716+ aarch64*-*-netbsd* | arm*-*-netbsdelf*) 22717+ LIB_PATH='=/usr/lib/eabi' 22718+ ;; 22719+esac 22720diff -rNU3 dist.orig/ld/emulparams/armelf_nbsd_eabihf.sh dist/ld/emulparams/armelf_nbsd_eabihf.sh 22721--- dist.orig/ld/emulparams/armelf_nbsd_eabihf.sh 1970-01-01 01:00:00.000000000 +0100 22722+++ dist/ld/emulparams/armelf_nbsd_eabihf.sh 2015-10-18 13:11:17.000000000 +0200 22723@@ -0,0 +1,17 @@ 22724+. ${srcdir}/emulparams/armelf_nbsd.sh 22725+ 22726+# Use the ARM ABI-compliant exception-handling sections. 22727+OTHER_READONLY_SECTIONS=" 22728+ .ARM.extab ${RELOCATING-0} : { *(.ARM.extab${RELOCATING+* .gnu.linkonce.armextab.*}) } 22729+ ${RELOCATING+ PROVIDE_HIDDEN (__exidx_start = .); } 22730+ .ARM.exidx ${RELOCATING-0} : { *(.ARM.exidx${RELOCATING+* .gnu.linkonce.armexidx.*}) } 22731+ ${RELOCATING+ PROVIDE_HIDDEN (__exidx_end = .); }" 22732+ 22733+case "$target" in 22734+ arm*-*-netbsdelf*-*eabihf*) 22735+ LIB_PATH='=/usr/lib' 22736+ ;; 22737+ aarch64*-*-netbsd* | arm*-*-netbsdelf*) 22738+ LIB_PATH='=/usr/lib/eabihf' 22739+ ;; 22740+esac 22741diff -rNU3 dist.orig/ld/emulparams/armelfb_nbsd_eabi.sh dist/ld/emulparams/armelfb_nbsd_eabi.sh 22742--- dist.orig/ld/emulparams/armelfb_nbsd_eabi.sh 1970-01-01 01:00:00.000000000 +0100 22743+++ dist/ld/emulparams/armelfb_nbsd_eabi.sh 2015-10-18 13:11:17.000000000 +0200 22744@@ -0,0 +1,2 @@ 22745+. ${srcdir}/emulparams/armelf_nbsd_eabi.sh 22746+OUTPUT_FORMAT="elf32-bigarm" 22747diff -rNU3 dist.orig/ld/emulparams/armelfb_nbsd_eabihf.sh dist/ld/emulparams/armelfb_nbsd_eabihf.sh 22748--- dist.orig/ld/emulparams/armelfb_nbsd_eabihf.sh 1970-01-01 01:00:00.000000000 +0100 22749+++ dist/ld/emulparams/armelfb_nbsd_eabihf.sh 2015-10-18 13:11:17.000000000 +0200 22750@@ -0,0 +1,2 @@ 22751+. ${srcdir}/emulparams/armelf_nbsd_eabihf.sh 22752+OUTPUT_FORMAT="elf32-bigarm" 22753diff -rNU3 dist.orig/ld/emulparams/elf32_sparc.sh dist/ld/emulparams/elf32_sparc.sh 22754--- dist.orig/ld/emulparams/elf32_sparc.sh 2010-09-20 20:41:15.000000000 +0200 22755+++ dist/ld/emulparams/elf32_sparc.sh 2015-10-18 13:11:17.000000000 +0200 22756@@ -13,6 +13,13 @@ 22757 TEMPLATE_NAME=elf32 22758 DATA_PLT= 22759 GENERATE_SHLIB_SCRIPT=yes 22760+#ELFSIZE=32 22761 GENERATE_PIE_SCRIPT=yes 22762 NOP=0x01000000 22763 NO_SMALL_DATA=yes 22764+ 22765+case "$target" in 22766+ sparc64-*-netbsd*) 22767+ LIB_PATH='=/usr/lib/sparc' 22768+ ;; 22769+esac 22770diff -rNU3 dist.orig/ld/emulparams/elf32bmipn32-defs.sh dist/ld/emulparams/elf32bmipn32-defs.sh 22771--- dist.orig/ld/emulparams/elf32bmipn32-defs.sh 2012-09-04 16:14:28.000000000 +0200 22772+++ dist/ld/emulparams/elf32bmipn32-defs.sh 2015-10-18 13:11:17.000000000 +0200 22773@@ -6,6 +6,7 @@ 22774 22775 # Handle both big- and little-ended 32-bit MIPS objects. 22776 ARCH=mips 22777+MACHINE= 22778 OUTPUT_FORMAT="elf32-bigmips" 22779 BIG_OUTPUT_FORMAT="elf32-bigmips" 22780 LITTLE_OUTPUT_FORMAT="elf32-littlemips" 22781diff -rNU3 dist.orig/ld/emulparams/elf32lriscv-defs.sh dist/ld/emulparams/elf32lriscv-defs.sh 22782--- dist.orig/ld/emulparams/elf32lriscv-defs.sh 1970-01-01 01:00:00.000000000 +0100 22783+++ dist/ld/emulparams/elf32lriscv-defs.sh 2015-10-18 13:11:17.000000000 +0200 22784@@ -0,0 +1,39 @@ 22785+# This is an ELF platform. 22786+SCRIPT_NAME=elf 22787+ARCH=riscv 22788+OUTPUT_FORMAT="elf32-littleriscv" 22789+NO_REL_RELOCS=yes 22790+ 22791+TEMPLATE_NAME=elf32 22792+EXTRA_EM_FILE=riscvelf 22793+ 22794+case "$EMULATION_NAME" in 22795+elf32*) ELFSIZE=32; LIBPATH_SUFFIX=32 ;; 22796+elf64*) ELFSIZE=64; LIBPATH_SUFFIX= ;; 22797+*) echo $0: unhandled emulation $EMULATION_NAME >&2; exit 1 ;; 22798+esac 22799+ 22800+if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then 22801+ case " $EMULATION_LIBPATH " in 22802+ *" ${EMULATION_NAME} "*) 22803+ NATIVE=yes 22804+ ;; 22805+ esac 22806+fi 22807+ 22808+GENERATE_SHLIB_SCRIPT=yes 22809+GENERATE_PIE_SCRIPT=yes 22810+ 22811+TEXT_START_ADDR=0x800000 22812+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" 22813+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" 22814+ 22815+INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" 22816+SDATA_START_SYMBOLS="_gp = . + 0x800; 22817+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)" 22818+if test -n "${CREATE_SHLIB}"; then 22819+ INITIAL_READONLY_SECTIONS= 22820+ SDATA_START_SYMBOLS= 22821+ OTHER_READONLY_SECTIONS=".srodata ${RELOCATING-0} : { *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) }" 22822+ unset GOT 22823+fi 22824diff -rNU3 dist.orig/ld/emulparams/elf32lriscv.sh dist/ld/emulparams/elf32lriscv.sh 22825--- dist.orig/ld/emulparams/elf32lriscv.sh 1970-01-01 01:00:00.000000000 +0100 22826+++ dist/ld/emulparams/elf32lriscv.sh 2015-10-18 13:11:17.000000000 +0200 22827@@ -0,0 +1,2 @@ 22828+. ${srcdir}/emulparams/elf32lriscv-defs.sh 22829+OUTPUT_FORMAT="elf32-littleriscv" 22830diff -rNU3 dist.orig/ld/emulparams/elf32openrisc.sh dist/ld/emulparams/elf32openrisc.sh 22831--- dist.orig/ld/emulparams/elf32openrisc.sh 2008-10-22 07:20:44.000000000 +0200 22832+++ dist/ld/emulparams/elf32openrisc.sh 1970-01-01 01:00:00.000000000 +0100 22833@@ -1,11 +0,0 @@ 22834-MACHINE= 22835-SCRIPT_NAME=elf 22836-OUTPUT_FORMAT="elf32-openrisc" 22837-NO_RELA_RELOCS=yes 22838-TEXT_START_ADDR=0x10000 22839-ARCH=openrisc 22840-MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" 22841-ENTRY=_start 22842-EMBEDDED=yes 22843-NOP=0x15000000 22844- 22845diff -rNU3 dist.orig/ld/emulparams/elf32or1k.sh dist/ld/emulparams/elf32or1k.sh 22846--- dist.orig/ld/emulparams/elf32or1k.sh 1970-01-01 01:00:00.000000000 +0100 22847+++ dist/ld/emulparams/elf32or1k.sh 2015-10-18 13:11:17.000000000 +0200 22848@@ -0,0 +1,14 @@ 22849+SCRIPT_NAME=elf 22850+MACHINE= 22851+TEMPLATE_NAME=elf32 22852+OUTPUT_FORMAT="elf32-or1k" 22853+NOP=0x15000000 22854+TEXT_START_ADDR=0x0000 22855+TARGET_PAGE_SIZE=0x2000 22856+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" 22857+EMBEDDED=yes 22858+ARCH=or1k 22859+ELFSIZE=32 22860+INITIAL_READONLY_SECTIONS=".vectors ${RELOCATING-0} : { KEEP (*(.vectors)) }" 22861+NO_REL_RELOCS=yes 22862+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" 22863diff -rNU3 dist.orig/ld/emulparams/elf32or1k_linux.sh dist/ld/emulparams/elf32or1k_linux.sh 22864--- dist.orig/ld/emulparams/elf32or1k_linux.sh 1970-01-01 01:00:00.000000000 +0100 22865+++ dist/ld/emulparams/elf32or1k_linux.sh 2015-10-18 13:11:17.000000000 +0200 22866@@ -0,0 +1,6 @@ 22867+. ${srcdir}/emulparams/elf32or1k.sh 22868+unset EMBEDDED 22869+GENERATE_SHLIB_SCRIPT=yes 22870+GENERATE_PIE_SCRIPT=yes 22871+GENERATE_COMBRELOC_SCRIPT=yes 22872+TEXT_START_ADDR=0x00002000 22873diff -rNU3 dist.orig/ld/emulparams/elf32or1k_nbsd.sh dist/ld/emulparams/elf32or1k_nbsd.sh 22874--- dist.orig/ld/emulparams/elf32or1k_nbsd.sh 1970-01-01 01:00:00.000000000 +0100 22875+++ dist/ld/emulparams/elf32or1k_nbsd.sh 2015-10-18 13:11:17.000000000 +0200 22876@@ -0,0 +1,6 @@ 22877+. ${srcdir}/emulparams/elf32or1k.sh 22878+unset EMBEDDED 22879+GENERATE_SHLIB_SCRIPT=yes 22880+GENERATE_PIE_SCRIPT=yes 22881+GENERATE_COMBRELOC_SCRIPT=yes 22882+TEXT_START_ADDR=0x00002000 22883diff -rNU3 dist.orig/ld/emulparams/elf32ppc_nbsd.sh dist/ld/emulparams/elf32ppc_nbsd.sh 22884--- dist.orig/ld/emulparams/elf32ppc_nbsd.sh 1970-01-01 01:00:00.000000000 +0100 22885+++ dist/ld/emulparams/elf32ppc_nbsd.sh 2015-10-18 13:11:17.000000000 +0200 22886@@ -0,0 +1,7 @@ 22887+. ${srcdir}/emulparams/elf32ppc.sh 22888+ 22889+case "$target" in 22890+ powerpc64*-*-netbsd*) 22891+ LIB_PATH='=/usr/lib/powerpc' 22892+ ;; 22893+esac 22894diff -rNU3 dist.orig/ld/emulparams/elf64alpha_nbsd.sh dist/ld/emulparams/elf64alpha_nbsd.sh 22895--- dist.orig/ld/emulparams/elf64alpha_nbsd.sh 2001-12-18 00:54:58.000000000 +0100 22896+++ dist/ld/emulparams/elf64alpha_nbsd.sh 2015-10-18 13:11:17.000000000 +0200 22897@@ -1,2 +1,8 @@ 22898 . ${srcdir}/emulparams/elf64alpha.sh 22899 ENTRY=__start 22900+ 22901+NOP=0x47ff041f 22902+# XXX binutils 2.13 22903+# Note that the number is always big-endian, thus we have to 22904+# reverse the digit string. 22905+#NOP=0x0000fe2f1f04ff47 # unop; nop 22906diff -rNU3 dist.orig/ld/emulparams/elf64lriscv-defs.sh dist/ld/emulparams/elf64lriscv-defs.sh 22907--- dist.orig/ld/emulparams/elf64lriscv-defs.sh 1970-01-01 01:00:00.000000000 +0100 22908+++ dist/ld/emulparams/elf64lriscv-defs.sh 2015-10-18 13:11:17.000000000 +0200 22909@@ -0,0 +1 @@ 22910+. ${srcdir}/emulparams/elf32lriscv-defs.sh 22911diff -rNU3 dist.orig/ld/emulparams/elf64lriscv.sh dist/ld/emulparams/elf64lriscv.sh 22912--- dist.orig/ld/emulparams/elf64lriscv.sh 1970-01-01 01:00:00.000000000 +0100 22913+++ dist/ld/emulparams/elf64lriscv.sh 2015-10-18 13:11:17.000000000 +0200 22914@@ -0,0 +1,2 @@ 22915+. ${srcdir}/emulparams/elf64lriscv-defs.sh 22916+OUTPUT_FORMAT="elf64-littleriscv" 22917diff -rNU3 dist.orig/ld/emulparams/elf_i386.sh dist/ld/emulparams/elf_i386.sh 22918--- dist.orig/ld/emulparams/elf_i386.sh 2012-06-11 15:23:50.000000000 +0200 22919+++ dist/ld/emulparams/elf_i386.sh 2015-10-18 13:11:17.000000000 +0200 22920@@ -9,7 +9,14 @@ 22921 MACHINE= 22922 TEMPLATE_NAME=elf32 22923 GENERATE_SHLIB_SCRIPT=yes 22924+#ELFSIZE=32 22925 GENERATE_PIE_SCRIPT=yes 22926 NO_SMALL_DATA=yes 22927 SEPARATE_GOTPLT="SIZEOF (.got.plt) >= 12 ? 12 : 0" 22928 IREL_IN_PLT= 22929+ 22930+case "$target" in 22931+ x86_64-*-netbsd*) 22932+ LIB_PATH='=/usr/lib/i386' 22933+ ;; 22934+esac 22935diff -rNU3 dist.orig/ld/emulparams/hppalinux.sh dist/ld/emulparams/hppalinux.sh 22936--- dist.orig/ld/emulparams/hppalinux.sh 2011-02-18 19:20:29.000000000 +0100 22937+++ dist/ld/emulparams/hppalinux.sh 2015-10-18 13:11:17.000000000 +0200 22938@@ -1,5 +1,5 @@ 22939 # If you change this file, please also look at files which source this one: 22940-# hppanbsd.sh 22941+# hppanbsd.sh hppaobsd.sh 22942 22943 SCRIPT_NAME=elf 22944 ELFSIZE=32 22945diff -rNU3 dist.orig/ld/emulparams/hppaobsd.sh dist/ld/emulparams/hppaobsd.sh 22946--- dist.orig/ld/emulparams/hppaobsd.sh 2006-05-30 18:45:32.000000000 +0200 22947+++ dist/ld/emulparams/hppaobsd.sh 2015-10-18 13:11:17.000000000 +0200 22948@@ -1,4 +1,4 @@ 22949-. ${srcdir}/emulparams/hppanbsd.sh 22950+. ${srcdir}/emulparams/hppalinux.sh 22951 22952 OUTPUT_FORMAT="elf32-hppa" 22953 TEXT_START_ADDR=0x1000 22954diff -rNU3 dist.orig/ld/emulparams/m68kelf.sh dist/ld/emulparams/m68kelf.sh 22955--- dist.orig/ld/emulparams/m68kelf.sh 2009-09-29 18:28:52.000000000 +0200 22956+++ dist/ld/emulparams/m68kelf.sh 2015-10-18 13:11:17.000000000 +0200 22957@@ -10,5 +10,6 @@ 22958 TEMPLATE_NAME=elf32 22959 EXTRA_EM_FILE=m68kelf 22960 GENERATE_SHLIB_SCRIPT=yes 22961+ELFSIZE=32 22962 GENERATE_PIE_SCRIPT=yes 22963 NO_SMALL_DATA=yes 22964diff -rNU3 dist.orig/ld/emulparams/m68kelfnbsd.sh dist/ld/emulparams/m68kelfnbsd.sh 22965--- dist.orig/ld/emulparams/m68kelfnbsd.sh 2001-12-18 14:26:26.000000000 +0100 22966+++ dist/ld/emulparams/m68kelfnbsd.sh 2015-10-18 13:11:17.000000000 +0200 22967@@ -1,4 +1,4 @@ 22968 . ${srcdir}/emulparams/m68kelf.sh 22969 TEXT_START_ADDR=0x2000 22970 TARGET_PAGE_SIZE=0x2000 22971-MACHINE= 22972+NONPAGED_TEXT_START_ADDR=${TEXT_START_ADDR} 22973diff -rNU3 dist.orig/ld/emulparams/or32.sh dist/ld/emulparams/or32.sh 22974--- dist.orig/ld/emulparams/or32.sh 2006-06-20 04:22:14.000000000 +0200 22975+++ dist/ld/emulparams/or32.sh 1970-01-01 01:00:00.000000000 +0100 22976@@ -1,5 +0,0 @@ 22977-SCRIPT_NAME=or32 22978-OUTPUT_FORMAT="coff-or32-big" 22979-TEXT_START_ADDR=0x1000000 22980-TARGET_PAGE_SIZE=0x1000000 22981-ARCH=or32 22982diff -rNU3 dist.orig/ld/emulparams/or32elf.sh dist/ld/emulparams/or32elf.sh 22983--- dist.orig/ld/emulparams/or32elf.sh 2008-10-22 07:20:44.000000000 +0200 22984+++ dist/ld/emulparams/or32elf.sh 1970-01-01 01:00:00.000000000 +0100 22985@@ -1,9 +0,0 @@ 22986-SCRIPT_NAME=elf 22987-TEMPLATE_NAME=generic 22988-EXTRA_EM_FILE=genelf 22989-OUTPUT_FORMAT="elf32-or32" 22990-NO_RELA_RELOCS=yes 22991-TEXT_START_ADDR=0x1000000 22992-TARGET_PAGE_SIZE=0x1000000 22993-MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" 22994-ARCH=or32 22995diff -rNU3 dist.orig/ld/emulparams/sh.sh dist/ld/emulparams/sh.sh 22996--- dist.orig/ld/emulparams/sh.sh 2001-11-22 10:08:04.000000000 +0100 22997+++ dist/ld/emulparams/sh.sh 2015-10-18 13:11:17.000000000 +0200 22998@@ -3,6 +3,6 @@ 22999 23000 SCRIPT_NAME=sh 23001 OUTPUT_FORMAT="coff-sh" 23002-TEXT_START_ADDR=0x8000 23003-TARGET_PAGE_SIZE=128 23004+TEXT_START_ADDR=0x1000 23005+TARGET_PAGE_SIZE=0x1000 23006 ARCH=sh 23007diff -rNU3 dist.orig/ld/emulparams/shelf_nbsd.sh dist/ld/emulparams/shelf_nbsd.sh 23008--- dist.orig/ld/emulparams/shelf_nbsd.sh 2008-01-16 00:05:46.000000000 +0100 23009+++ dist/ld/emulparams/shelf_nbsd.sh 2015-10-18 13:11:17.000000000 +0200 23010@@ -9,7 +9,11 @@ 23011 23012 DATA_START_SYMBOLS='PROVIDE (__data_start = .);'; 23013 23014-ENTRY=_start 23015+ENTRY=__start 23016 23017 unset EMBEDDED 23018 unset OTHER_SECTIONS 23019+ 23020+OTHER_READWRITE_SECTIONS=' 23021+ .note.ABI-tag : { *(.note.ABI-tag) } 23022+' 23023diff -rNU3 dist.orig/ld/emultempl/aarch64elf.em dist/ld/emultempl/aarch64elf.em 23024--- dist.orig/ld/emultempl/aarch64elf.em 2013-03-25 09:06:23.000000000 +0100 23025+++ dist/ld/emultempl/aarch64elf.em 2015-10-18 13:11:17.000000000 +0200 23026@@ -38,6 +38,7 @@ 23027 ldfile_set_output_arch ("`echo ${ARCH}`", bfd_arch_unknown); 23028 #endif /* not TARGET_ */ 23029 input_flags.dynamic = ${DYNAMIC_LINK-TRUE}; 23030+ input_flags.add_DT_NEEDED_for_dynamic = TRUE; 23031 config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`; 23032 config.separate_code = `if test "x${SEPARATE_CODE}" = xyes ; then echo TRUE ; else echo FALSE ; fi`; 23033 } 23034diff -rNU3 dist.orig/ld/emultempl/armelf.em dist/ld/emultempl/armelf.em 23035--- dist.orig/ld/emultempl/armelf.em 2013-03-25 09:06:23.000000000 +0100 23036+++ dist/ld/emultempl/armelf.em 2015-10-18 13:11:17.000000000 +0200 23037@@ -51,6 +51,7 @@ 23038 ldfile_set_output_arch ("`echo ${ARCH}`", bfd_arch_unknown); 23039 #endif /* not TARGET_ */ 23040 input_flags.dynamic = ${DYNAMIC_LINK-TRUE}; 23041+ input_flags.add_DT_NEEDED_for_dynamic = TRUE; 23042 config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`; 23043 config.separate_code = `if test "x${SEPARATE_CODE}" = xyes ; then echo TRUE ; else echo FALSE ; fi`; 23044 } 23045diff -rNU3 dist.orig/ld/emultempl/elf32.em dist/ld/emultempl/elf32.em 23046--- dist.orig/ld/emultempl/elf32.em 2013-03-25 09:06:23.000000000 +0100 23047+++ dist/ld/emultempl/elf32.em 2015-10-18 13:11:17.000000000 +0200 23048@@ -72,6 +72,9 @@ 23049 23050 if [ "x${USE_LIBPATH}" = xyes ] ; then 23051 case ${target} in 23052+ *-*-netbsd*) 23053+ ;; 23054+ 23055 *-*-linux-* | *-*-k*bsd*-* | *-*-gnu*) 23056 fragment <<EOF 23057 #ifdef HAVE_GLOB 23058@@ -103,6 +106,7 @@ 23059 { 23060 ldfile_set_output_arch ("${OUTPUT_ARCH}", bfd_arch_`echo ${ARCH} | sed -e 's/:.*//'`); 23061 input_flags.dynamic = ${DYNAMIC_LINK-TRUE}; 23062+ input_flags.add_DT_NEEDED_for_dynamic = TRUE; 23063 config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`; 23064 config.separate_code = `if test "x${SEPARATE_CODE}" = xyes ; then echo TRUE ; else echo FALSE ; fi`; 23065 } 23066@@ -375,6 +379,9 @@ 23067 23068 EOF 23069 case ${target} in 23070+ *-*-netbsd*) 23071+ ;; 23072+ 23073 *-*-linux-* | *-*-k*bsd*-* | *-*-gnu*) 23074 fragment <<EOF 23075 { 23076@@ -454,15 +461,25 @@ 23077 23078 static bfd_boolean 23079 gld${EMULATION_NAME}_search_needed (const char *path, 23080- struct dt_needed *n, int force) 23081+ struct dt_needed *n, int force, int prepend_sysroot) 23082 { 23083 const char *s; 23084 const char *name = n->name; 23085 size_t len; 23086 struct dt_needed needed; 23087 23088- if (name[0] == '/') 23089+ if (name[0] == '/') { 23090+ if (prepend_sysroot && ld_sysroot) { 23091+ bfd_boolean rv; 23092+ needed.by = n->by; 23093+ char *filename= concat(ld_sysroot, n->name, (const char *)NULL); 23094+ needed.name = filename; 23095+ rv = gld${EMULATION_NAME}_try_needed (&needed, force); 23096+ free(filename); 23097+ return rv; 23098+ } 23099 return gld${EMULATION_NAME}_try_needed (n, force); 23100+ } 23101 23102 if (path == NULL || *path == '\0') 23103 return FALSE; 23104@@ -501,6 +518,13 @@ 23105 } 23106 strcpy (sset, name); 23107 23108+ if (prepend_sysroot && filename[0] == '=') 23109+ abort(); 23110+ if (filename[0] == '/' && prepend_sysroot && ld_sysroot) { 23111+ char *filename2 = concat(ld_sysroot, filename, (const char *)NULL); 23112+ free(filename); 23113+ filename = filename2; 23114+ } 23115 needed.name = filename; 23116 if (gld${EMULATION_NAME}_try_needed (&needed, force)) 23117 return TRUE; 23118@@ -621,6 +645,9 @@ 23119 # FreeBSD 23120 ;; 23121 23122+ *-*-netbsd*) 23123+ ;; 23124+ 23125 *-*-linux-* | *-*-k*bsd*-* | *-*-gnu*) 23126 fragment <<EOF 23127 /* For a native linker, check the file /etc/ld.so.conf for directories 23128@@ -1262,13 +1289,13 @@ 23129 fragment <<EOF 23130 23131 if (gld${EMULATION_NAME}_search_needed (command_line.rpath_link, 23132- &n, force)) 23133+ &n, force, 0)) 23134 break; 23135 EOF 23136 if [ "x${USE_LIBPATH}" = xyes ] ; then 23137 fragment <<EOF 23138 if (gld${EMULATION_NAME}_search_needed (command_line.rpath, 23139- &n, force)) 23140+ &n, force, 1)) 23141 break; 23142 EOF 23143 fi 23144@@ -1279,11 +1306,11 @@ 23145 { 23146 lib_path = (const char *) getenv ("LD_RUN_PATH"); 23147 if (gld${EMULATION_NAME}_search_needed (lib_path, &n, 23148- force)) 23149+ force, 0)) 23150 break; 23151 } 23152 lib_path = (const char *) getenv ("LD_LIBRARY_PATH"); 23153- if (gld${EMULATION_NAME}_search_needed (lib_path, &n, force)) 23154+ if (gld${EMULATION_NAME}_search_needed (lib_path, &n, force, 0)) 23155 break; 23156 EOF 23157 fi 23158@@ -1293,12 +1320,10 @@ 23159 rp = bfd_elf_get_runpath_list (link_info.output_bfd, &link_info); 23160 for (; !found && rp != NULL; rp = rp->next) 23161 { 23162- char *tmpname = gld${EMULATION_NAME}_add_sysroot (rp->name); 23163 found = (rp->by == l->by 23164- && gld${EMULATION_NAME}_search_needed (tmpname, 23165+ && gld${EMULATION_NAME}_search_needed (rp->name, 23166 &n, 23167- force)); 23168- free (tmpname); 23169+ force, 1)); 23170 } 23171 if (found) 23172 break; 23173@@ -1315,6 +1340,9 @@ 23174 # FreeBSD 23175 ;; 23176 23177+ *-*-netbsd*) 23178+ ;; 23179+ 23180 *-*-linux-* | *-*-k*bsd*-* | *-*-gnu*) 23181 # Linux 23182 fragment <<EOF 23183@@ -1515,7 +1543,8 @@ 23184 a dep audit entry. */ 23185 if (audit_libs && *audit_libs != '\0') 23186 { 23187- char *cp = xstrdup (audit_libs); 23188+ char *cp, *fcp; 23189+ fcp = cp = xstrdup (audit_libs); 23190 do 23191 { 23192 int more = 0; 23193@@ -1533,6 +1562,7 @@ 23194 cp = more ? ++cp2 : NULL; 23195 } 23196 while (cp != NULL); 23197+ free (fcp); 23198 } 23199 } 23200 23201diff -rNU3 dist.orig/ld/emultempl/riscvelf.em dist/ld/emultempl/riscvelf.em 23202--- dist.orig/ld/emultempl/riscvelf.em 1970-01-01 01:00:00.000000000 +0100 23203+++ dist/ld/emultempl/riscvelf.em 2015-10-18 13:11:17.000000000 +0200 23204@@ -0,0 +1,70 @@ 23205+# This shell script emits a C file. -*- C -*- 23206+# Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc. 23207+# 23208+# This file is part of the GNU Binutils. 23209+# 23210+# This program is free software; you can redistribute it and/or modify 23211+# it under the terms of the GNU General Public License as published by 23212+# the Free Software Foundation; either version 3 of the License, or 23213+# (at your option) any later version. 23214+# 23215+# This program is distributed in the hope that it will be useful, 23216+# but WITHOUT ANY WARRANTY; without even the implied warranty of 23217+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23218+# GNU General Public License for more details. 23219+# 23220+# You should have received a copy of the GNU General Public License 23221+# along with this program; if not, write to the Free Software 23222+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 23223+# MA 02110-1301, USA. 23224+ 23225+fragment <<EOF 23226+ 23227+#include "ldmain.h" 23228+#include "ldctor.h" 23229+#include "elf/riscv.h" 23230+#include "elfxx-riscv.h" 23231+ 23232+static void 23233+riscv_elf_before_allocation (void) 23234+{ 23235+ gld${EMULATION_NAME}_before_allocation (); 23236+ 23237+ if (link_info.discard == discard_sec_merge) 23238+ link_info.discard = discard_l; 23239+ 23240+ /* We always need at least some relaxation to handle code alignment. */ 23241+#if 0 23242+ if (RELAXATION_DISABLED_BY_USER) 23243+ TARGET_ENABLE_RELAXATION; 23244+ else 23245+#endif 23246+ ENABLE_RELAXATION; 23247+ 23248+ link_info.relax_pass = 2; 23249+} 23250+ 23251+static void 23252+gld${EMULATION_NAME}_after_allocation (void) 23253+{ 23254+ int need_layout = 0; 23255+ 23256+ /* Don't attempt to discard unused .eh_frame sections until the final link, 23257+ as we can't reliably tell if they're used until after relaxation. */ 23258+ if (!link_info.relocatable) 23259+ { 23260+ need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info); 23261+ if (need_layout < 0) 23262+ { 23263+ einfo ("%X%P: .eh_frame/.stab edit: %E\n"); 23264+ return; 23265+ } 23266+ } 23267+ 23268+ gld${EMULATION_NAME}_map_segments (need_layout); 23269+} 23270+ 23271+EOF 23272+ 23273+LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation 23274+LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation 23275diff -rNU3 dist.orig/ld/ldlex.h dist/ld/ldlex.h 23276--- dist.orig/ld/ldlex.h 2013-03-25 09:06:23.000000000 +0100 23277+++ dist/ld/ldlex.h 2015-10-18 13:11:17.000000000 +0200 23278@@ -136,6 +136,7 @@ 23279 #endif /* ENABLE_PLUGINS */ 23280 OPTION_DEFAULT_SCRIPT, 23281 OPTION_PRINT_OUTPUT_FORMAT, 23282+ OPTION_IGNORE_UNRESOLVED_SYMBOL 23283 }; 23284 23285 /* The initial parser states. */ 23286diff -rNU3 dist.orig/ld/ldlex.l dist/ld/ldlex.l 23287--- dist.orig/ld/ldlex.l 2012-09-04 16:14:15.000000000 +0200 23288+++ dist/ld/ldlex.l 2015-10-18 13:11:17.000000000 +0200 23289@@ -60,10 +60,6 @@ 23290 #undef YY_INPUT 23291 #define YY_INPUT(buf,result,max_size) result = yy_input (buf, max_size) 23292 23293-#ifndef YY_NO_UNPUT 23294-#define YY_NO_UNPUT 23295-#endif 23296- 23297 #define MAX_INCLUDE_DEPTH 10 23298 static YY_BUFFER_STATE include_stack[MAX_INCLUDE_DEPTH]; 23299 static const char *file_name_stack[MAX_INCLUDE_DEPTH]; 23300@@ -94,6 +90,8 @@ 23301 #endif 23302 %} 23303 23304+%option nounput 23305+ 23306 %a 4000 23307 %o 5000 23308 23309diff -rNU3 dist.orig/ld/ldmain.c dist/ld/ldmain.c 23310--- dist.orig/ld/ldmain.c 2013-03-25 09:06:23.000000000 +0100 23311+++ dist/ld/ldmain.c 2015-10-18 13:11:17.000000000 +0200 23312@@ -642,6 +642,23 @@ 23313 einfo (_("%P%F: bfd_hash_lookup failed: %E\n")); 23314 } 23315 23316+void 23317+add_ignoresym (const char *name) 23318+{ 23319+ if (link_info.ignore_hash == NULL) 23320+ { 23321+ link_info.ignore_hash = xmalloc (sizeof (struct bfd_hash_table)); 23322+ if (! bfd_hash_table_init_n (link_info.ignore_hash, 23323+ bfd_hash_newfunc, 23324+ sizeof (struct bfd_hash_entry), 23325+ 61)) 23326+ einfo (_("%P%F: bfd_hash_table_init failed: %E\n")); 23327+ } 23328+ 23329+ if (bfd_hash_lookup (link_info.ignore_hash, name, TRUE, TRUE) == NULL) 23330+ einfo (_("%P%F: bfd_hash_lookup failed: %E\n")); 23331+} 23332+ 23333 /* Record a symbol to be wrapped, from the --wrap option. */ 23334 23335 void 23336@@ -1239,24 +1256,25 @@ 23337 23338 #define MAX_ERRORS_IN_A_ROW 5 23339 23340+ if (info->ignore_hash != NULL 23341+ && bfd_hash_lookup (info->ignore_hash, name, FALSE, FALSE) != NULL) 23342+ return TRUE; 23343+ 23344 if (config.warn_once) 23345 { 23346- static struct bfd_hash_table *hash; 23347- 23348 /* Only warn once about a particular undefined symbol. */ 23349- if (hash == NULL) 23350+ if (info->ignore_hash == NULL) 23351 { 23352- hash = (struct bfd_hash_table *) 23353- xmalloc (sizeof (struct bfd_hash_table)); 23354- if (!bfd_hash_table_init (hash, bfd_hash_newfunc, 23355+ info->ignore_hash = xmalloc (sizeof (struct bfd_hash_table)); 23356+ if (!bfd_hash_table_init (info->ignore_hash, bfd_hash_newfunc, 23357 sizeof (struct bfd_hash_entry))) 23358 einfo (_("%F%P: bfd_hash_table_init failed: %E\n")); 23359 } 23360 23361- if (bfd_hash_lookup (hash, name, FALSE, FALSE) != NULL) 23362+ if (bfd_hash_lookup (info->ignore_hash, name, FALSE, FALSE) != NULL) 23363 return TRUE; 23364 23365- if (bfd_hash_lookup (hash, name, TRUE, TRUE) == NULL) 23366+ if (bfd_hash_lookup (info->ignore_hash, name, TRUE, TRUE) == NULL) 23367 einfo (_("%F%P: bfd_hash_lookup failed: %E\n")); 23368 } 23369 23370diff -rNU3 dist.orig/ld/ldmain.h dist/ld/ldmain.h 23371--- dist.orig/ld/ldmain.h 2012-07-13 15:20:26.000000000 +0200 23372+++ dist/ld/ldmain.h 2015-10-18 13:11:17.000000000 +0200 23373@@ -41,6 +41,7 @@ 23374 23375 extern void add_ysym (const char *); 23376 extern void add_wrap (const char *); 23377+extern void add_ignoresym (const char *); 23378 extern void add_keepsyms_file (const char *); 23379 23380 #endif 23381diff -rNU3 dist.orig/ld/lexsup.c dist/ld/lexsup.c 23382--- dist.orig/ld/lexsup.c 2013-03-25 09:06:23.000000000 +0100 23383+++ dist/ld/lexsup.c 2015-10-18 13:11:17.000000000 +0200 23384@@ -398,7 +398,7 @@ 23385 ONE_DASH }, 23386 { {"shared", no_argument, NULL, OPTION_SHARED}, 23387 '\0', NULL, N_("Create a shared library"), ONE_DASH }, 23388- { {"Bshareable", no_argument, NULL, OPTION_SHARED }, /* FreeBSD. */ 23389+ { {"Bshareable", no_argument, NULL, OPTION_SHARED }, /* FreeBSD, NetBSD. */ 23390 '\0', NULL, NULL, ONE_DASH }, 23391 { {"pie", no_argument, NULL, OPTION_PIE}, 23392 '\0', NULL, N_("Create a position independent executable"), ONE_DASH }, 23393@@ -496,8 +496,14 @@ 23394 { {"whole-archive", no_argument, NULL, OPTION_WHOLE_ARCHIVE}, 23395 '\0', NULL, N_("Include all objects from following archives"), 23396 TWO_DASHES }, 23397+ { {"Bforcearchive", no_argument, NULL, OPTION_WHOLE_ARCHIVE}, 23398+ '\0', NULL, NULL, TWO_DASHES }, /* NetBSD. */ 23399 { {"wrap", required_argument, NULL, OPTION_WRAP}, 23400 '\0', N_("SYMBOL"), N_("Use wrapper functions for SYMBOL"), TWO_DASHES }, 23401+ { {"ignore-unresolved-symbol", required_argument, NULL, 23402+ OPTION_IGNORE_UNRESOLVED_SYMBOL}, 23403+ '\0', N_("SYMBOL"), 23404+ N_("Unresolved SYMBOL will not cause an error or warning"), TWO_DASHES }, 23405 }; 23406 23407 #define OPTION_COUNT ARRAY_SIZE (ld_options) 23408@@ -1344,6 +1350,9 @@ 23409 case OPTION_WRAP: 23410 add_wrap (optarg); 23411 break; 23412+ case OPTION_IGNORE_UNRESOLVED_SYMBOL: 23413+ add_ignoresym (optarg); 23414+ break; 23415 case OPTION_DISCARD_NONE: 23416 link_info.discard = discard_none; 23417 break; 23418diff -rNU3 dist.orig/ld/scripttempl/elf.sc dist/ld/scripttempl/elf.sc 23419--- dist.orig/ld/scripttempl/elf.sc 2013-03-25 09:06:23.000000000 +0100 23420+++ dist/ld/scripttempl/elf.sc 2015-10-18 13:11:17.000000000 +0200 23421@@ -94,6 +94,8 @@ 23422 # 23423 # Each of these can also have corresponding .rel.* and .rela.* sections. 23424 23425+test -z "$TEXT_START_SYMBOLS" && TEXT_START_SYMBOLS="PROVIDE_HIDDEN (__eprol = .);" 23426+test -z "$ENTRY" && ENTRY=_start 23427 if test -n "$NOP"; then 23428 FILL="=$NOP" 23429 else 23430@@ -471,11 +473,12 @@ 23431 .text ${RELOCATING-0} : 23432 { 23433 ${RELOCATING+${TEXT_START_SYMBOLS}} 23434+ *(.text) 23435 ${RELOCATING+*(.text.unlikely .text.*_unlikely)} 23436 ${RELOCATING+*(.text.exit .text.exit.*)} 23437 ${RELOCATING+*(.text.startup .text.startup.*)} 23438 ${RELOCATING+*(.text.hot .text.hot.*)} 23439- *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*}) 23440+ *(.stub${RELOCATING+ .text.* .gnu.linkonce.t.*}) 23441 /* .gnu.warning sections are handled specially by elf32.em. */ 23442 *(.gnu.warning) 23443 ${RELOCATING+${OTHER_TEXT_SECTIONS}} 23444diff -rNU3 dist.orig/ld/scripttempl/sh.sc dist/ld/scripttempl/sh.sc 23445--- dist.orig/ld/scripttempl/sh.sc 2002-09-25 19:06:09.000000000 +0200 23446+++ dist/ld/scripttempl/sh.sc 2015-10-18 13:11:17.000000000 +0200 23447@@ -6,16 +6,13 @@ 23448 ___dtors = . ; 23449 *(.dtors) 23450 ___dtors_end = . ; 23451- } > ram" 23452+ }" 23453+ 23454 23455 cat <<EOF 23456 OUTPUT_FORMAT("${OUTPUT_FORMAT}") 23457 OUTPUT_ARCH(${ARCH}) 23458- 23459-MEMORY 23460-{ 23461- ram : o = 0x1000, l = 512k 23462-} 23463+${LIB_SEARCH_DIRS} 23464 23465 SECTIONS 23466 { 23467@@ -24,9 +21,9 @@ 23468 *(.text) 23469 *(.strings) 23470 ${RELOCATING+ _etext = . ; } 23471- } ${RELOCATING+ > ram} 23472+ } 23473 ${CONSTRUCTING+${TORS}} 23474- .data : 23475+ .data ${RELOCATING+ ALIGN(${TARGET_PAGE_SIZE})} : 23476 { 23477 *(.data) 23478 ${RELOCATING+*(.gcc_exc*)} 23479@@ -35,19 +32,19 @@ 23480 ${RELOCATING+___EH_FRAME_END__ = . ;} 23481 ${RELOCATING+LONG(0);} 23482 ${RELOCATING+ _edata = . ; } 23483- } ${RELOCATING+ > ram} 23484- .bss : 23485+ } 23486+ .bss ${RELOCATING+ ALIGN(${TARGET_PAGE_SIZE})} : 23487 { 23488 ${RELOCATING+ _bss_start = . ; } 23489 *(.bss) 23490 *(COMMON) 23491 ${RELOCATING+ _end = . ; } 23492- } ${RELOCATING+ > ram} 23493- .stack ${RELOCATING+ 0x30000 } : 23494+ } 23495+ .stack : 23496 { 23497 ${RELOCATING+ _stack = . ; } 23498 *(.stack) 23499- } ${RELOCATING+ > ram} 23500+ } 23501 .stab 0 ${RELOCATING+(NOLOAD)} : 23502 { 23503 *(.stab) 23504diff -rNU3 dist.orig/libiberty/floatformat.c dist/libiberty/floatformat.c 23505--- dist.orig/libiberty/floatformat.c 2011-01-03 22:05:58.000000000 +0100 23506+++ dist/libiberty/floatformat.c 2015-10-18 13:11:19.000000000 +0200 23507@@ -489,7 +489,11 @@ 23508 if (nan) 23509 dto = NAN; 23510 else 23511+#ifdef __vax__ 23512+ dto = HUGE_VAL; 23513+#else 23514 dto = INFINITY; 23515+#endif 23516 23517 if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) 23518 dto = -dto; 23519diff -rNU3 dist.orig/libiberty/make-temp-file.c dist/libiberty/make-temp-file.c 23520--- dist.orig/libiberty/make-temp-file.c 2011-01-03 22:05:58.000000000 +0100 23521+++ dist/libiberty/make-temp-file.c 2015-10-18 13:11:19.000000000 +0200 23522@@ -130,10 +130,10 @@ 23523 base = try_dir (P_tmpdir, base); 23524 #endif 23525 23526- /* Try /var/tmp, /usr/tmp, then /tmp. */ 23527+ /* Try /tmp, /var/tmp, then /usr/tmp. */ 23528+ base = try_dir (tmp, base); 23529 base = try_dir (vartmp, base); 23530 base = try_dir (usrtmp, base); 23531- base = try_dir (tmp, base); 23532 23533 /* If all else fails, use the current directory! */ 23534 if (base == 0) 23535diff -rNU3 dist.orig/libiberty/objalloc.c dist/libiberty/objalloc.c 23536--- dist.orig/libiberty/objalloc.c 2005-07-22 05:26:05.000000000 +0200 23537+++ dist/libiberty/objalloc.c 2015-10-18 13:11:19.000000000 +0200 23538@@ -1,5 +1,5 @@ 23539 /* objalloc.c -- routines to allocate memory for objects 23540- Copyright 1997 Free Software Foundation, Inc. 23541+ Copyright 1997-2012 Free Software Foundation, Inc. 23542 Written by Ian Lance Taylor, Cygnus Solutions. 23543 23544 This program is free software; you can redistribute it and/or modify it 23545@@ -112,8 +112,10 @@ 23546 /* Allocate space from an objalloc structure. */ 23547 23548 PTR 23549-_objalloc_alloc (struct objalloc *o, unsigned long len) 23550+_objalloc_alloc (struct objalloc *o, unsigned long original_len) 23551 { 23552+ unsigned long len = original_len; 23553+ 23554 /* We avoid confusion from zero sized objects by always allocating 23555 at least 1 byte. */ 23556 if (len == 0) 23557@@ -121,6 +123,11 @@ 23558 23559 len = (len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1); 23560 23561+ /* Check for overflow in the alignment operation above and the 23562+ malloc argument below. */ 23563+ if (len + CHUNK_HEADER_SIZE < original_len) 23564+ return NULL; 23565+ 23566 if (len <= o->current_space) 23567 { 23568 o->current_ptr += len; 23569diff -rNU3 dist.orig/libiberty/strerror.c dist/libiberty/strerror.c 23570--- dist.orig/libiberty/strerror.c 2005-03-28 04:09:01.000000000 +0200 23571+++ dist/libiberty/strerror.c 2015-10-18 13:11:19.000000000 +0200 23572@@ -347,7 +347,7 @@ 23573 ENTRY(EPROTOTYPE, "EPROTOTYPE", "Protocol wrong type for socket"), 23574 #endif 23575 #if defined (ENOPROTOOPT) 23576- ENTRY(ENOPROTOOPT, "ENOPROTOOPT", "Protocol not available"), 23577+ ENTRY(ENOPROTOOPT, "ENOPROTOOPT", "Protocol option not available"), 23578 #endif 23579 #if defined (EPROTONOSUPPORT) 23580 ENTRY(EPROTONOSUPPORT, "EPROTONOSUPPORT", "Protocol not supported"), 23581diff -rNU3 dist.orig/opcodes/Makefile.am dist/opcodes/Makefile.am 23582--- dist.orig/opcodes/Makefile.am 2012-09-04 16:21:06.000000000 +0200 23583+++ dist/opcodes/Makefile.am 2015-10-18 13:11:20.000000000 +0200 23584@@ -62,7 +62,7 @@ 23585 mep-desc.h mep-opc.h \ 23586 microblaze-opc.h \ 23587 mt-desc.h mt-opc.h \ 23588- openrisc-desc.h openrisc-opc.h \ 23589+ or1k-desc.h or1k-opc.h \ 23590 score-opc.h \ 23591 sh-opc.h \ 23592 sh64-opc.h \ 23593@@ -188,13 +188,11 @@ 23594 mt-ibld.c \ 23595 mt-opc.c \ 23596 ns32k-dis.c \ 23597- openrisc-asm.c \ 23598- openrisc-desc.c \ 23599- openrisc-dis.c \ 23600- openrisc-ibld.c \ 23601- openrisc-opc.c \ 23602- or32-dis.c \ 23603- or32-opc.c \ 23604+ or1k-asm.c \ 23605+ or1k-desc.c \ 23606+ or1k-dis.c \ 23607+ or1k-ibld.c \ 23608+ or1k-opc.c \ 23609 pdp11-dis.c \ 23610 pdp11-opc.c \ 23611 pj-dis.c \ 23612@@ -332,7 +330,7 @@ 23613 CLEANFILES = \ 23614 stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ 23615 stamp-m32c stamp-m32r stamp-mep stamp-mt \ 23616- stamp-openrisc stamp-xc16x stamp-xstormy16 \ 23617+ stamp-or1k stamp-xc16x stamp-xstormy16 \ 23618 libopcodes.a stamp-lib 23619 23620 23621@@ -348,7 +346,7 @@ 23622 $(CGENDIR)/opc-opinst.scm \ 23623 cgen-asm.in cgen-dis.in cgen-ibld.in 23624 23625-CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 23626+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16 23627 23628 if CGEN_MAINT 23629 EPIPHANY_DEPS = stamp-epiphany 23630@@ -361,7 +359,7 @@ 23631 M32R_DEPS = stamp-m32r 23632 MEP_DEPS = stamp-mep 23633 MT_DEPS = stamp-mt 23634-OPENRISC_DEPS = stamp-openrisc 23635+OR1K_DEPS = stamp-or1k 23636 XC16X_DEPS = stamp-xc16x 23637 XSTORMY16_DEPS = stamp-xstormy16 23638 else 23639@@ -375,7 +373,7 @@ 23640 M32R_DEPS = 23641 MEP_DEPS = 23642 MT_DEPS = 23643-OPENRISC_DEPS = 23644+OR1K_DEPS = 23645 XC16X_DEPS = 23646 XSTORMY16_DEPS = 23647 endif 23648@@ -469,11 +467,11 @@ 23649 archfile=$(CPUDIR)/mt.cpu \ 23650 opcfile=$(CPUDIR)/mt.opc extrafiles= 23651 23652-$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) 23653+$(srcdir)/or1k-desc.h $(srcdir)/or1k-desc.c $(srcdir)/or1k-opc.h $(srcdir)/or1k-opc.c $(srcdir)/or1k-ibld.c $(srcdir)/or1k-opinst.c $(srcdir)/or1k-asm.c $(srcdir)/or1k-dis.c: $(OR1K_DEPS) 23654 @true 23655-stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc 23656- $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \ 23657- archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles= 23658+stamp-or1k: $(CGENDEPS) $(CPUDIR)/or1k.cpu $(CPUDIR)/or1k.opc $(CPUDIR)/or1kcommon.cpu $(CPUDIR)/or1korbis.cpu $(CPUDIR)/or1korfpx.cpu 23659+ $(MAKE) run-cgen arch=or1k prefix=or1k options=opinst \ 23660+ archfile=$(CPUDIR)/or1k.cpu opcfile=$(CPUDIR)/or1k.opc extrafiles=opinst 23661 23662 $(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS) 23663 @true 23664diff -rNU3 dist.orig/opcodes/Makefile.in dist/opcodes/Makefile.in 23665--- dist.orig/opcodes/Makefile.in 2012-09-04 16:21:06.000000000 +0200 23666+++ dist/opcodes/Makefile.in 2015-10-18 13:11:20.000000000 +0200 23667@@ -459,13 +459,11 @@ 23668 mt-ibld.c \ 23669 mt-opc.c \ 23670 ns32k-dis.c \ 23671- openrisc-asm.c \ 23672- openrisc-desc.c \ 23673- openrisc-dis.c \ 23674- openrisc-ibld.c \ 23675- openrisc-opc.c \ 23676- or32-dis.c \ 23677- or32-opc.c \ 23678+ or1k-asm.c \ 23679+ or1k-desc.c \ 23680+ or1k-dis.c \ 23681+ or1k-ibld.c \ 23682+ or1k-opc.c \ 23683 pdp11-dis.c \ 23684 pdp11-opc.c \ 23685 pj-dis.c \ 23686@@ -572,7 +570,7 @@ 23687 CLEANFILES = \ 23688 stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ 23689 stamp-m32c stamp-m32r stamp-mep stamp-mt \ 23690- stamp-openrisc stamp-xc16x stamp-xstormy16 \ 23691+ stamp-or1k stamp-xc16x stamp-xstormy16 \ 23692 libopcodes.a stamp-lib 23693 23694 CGENDIR = @cgendir@ 23695@@ -586,7 +584,7 @@ 23696 $(CGENDIR)/opc-opinst.scm \ 23697 cgen-asm.in cgen-dis.in cgen-ibld.in 23698 23699-CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 23700+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16 23701 @CGEN_MAINT_FALSE@EPIPHANY_DEPS = 23702 @CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany 23703 @CGEN_MAINT_FALSE@FR30_DEPS = 23704@@ -607,8 +605,8 @@ 23705 @CGEN_MAINT_TRUE@MEP_DEPS = stamp-mep 23706 @CGEN_MAINT_FALSE@MT_DEPS = 23707 @CGEN_MAINT_TRUE@MT_DEPS = stamp-mt 23708-@CGEN_MAINT_FALSE@OPENRISC_DEPS = 23709-@CGEN_MAINT_TRUE@OPENRISC_DEPS = stamp-openrisc 23710+@CGEN_MAINT_FALSE@OR1K_DEPS = 23711+@CGEN_MAINT_TRUE@OR1K_DEPS = stamp-or1k 23712 @CGEN_MAINT_FALSE@XC16X_DEPS = 23713 @CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x 23714 @CGEN_MAINT_FALSE@XSTORMY16_DEPS = 23715@@ -855,13 +853,12 @@ 23716 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mt-ibld.Plo@am__quote@ 23717 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mt-opc.Plo@am__quote@ 23718 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ns32k-dis.Plo@am__quote@ 23719-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-asm.Plo@am__quote@ 23720-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-desc.Plo@am__quote@ 23721-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-dis.Plo@am__quote@ 23722-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-ibld.Plo@am__quote@ 23723-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-opc.Plo@am__quote@ 23724-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or32-dis.Plo@am__quote@ 23725-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or32-opc.Plo@am__quote@ 23726+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or1k-asm.Plo@am__quote@ 23727+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or1k-desc.Plo@am__quote@ 23728+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or1k-dis.Plo@am__quote@ 23729+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or1k-ibld.Plo@am__quote@ 23730+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or1k-opc.Plo@am__quote@ 23731+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or1k-opinst.Plo@am__quote@ 23732 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pdp11-dis.Plo@am__quote@ 23733 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pdp11-opc.Plo@am__quote@ 23734 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pj-dis.Plo@am__quote@ 23735@@ -1340,11 +1337,11 @@ 23736 archfile=$(CPUDIR)/mt.cpu \ 23737 opcfile=$(CPUDIR)/mt.opc extrafiles= 23738 23739-$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) 23740+$(srcdir)/or1k-desc.h $(srcdir)/or1k-desc.c $(srcdir)/or1k-opc.h $(srcdir)/or1k-opc.c $(srcdir)/or1k-ibld.c $(srcdir)/or1k-opinst.c $(srcdir)/or1k-asm.c $(srcdir)/or1k-dis.c: $(OR1K_DEPS) 23741 @true 23742-stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc 23743- $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \ 23744- archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles= 23745+stamp-or1k: $(CGENDEPS) $(CPUDIR)/or1k.cpu $(CPUDIR)/or1k.opc $(CPUDIR)/or1kcommon.cpu $(CPUDIR)/or1korbis.cpu $(CPUDIR)/or1korfpx.cpu 23746+ $(MAKE) run-cgen arch=or1k prefix=or1k options=opinst \ 23747+ archfile=$(CPUDIR)/or1k.cpu opcfile=$(CPUDIR)/or1k.opc extrafiles=opinst 23748 23749 $(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS) 23750 @true 23751diff -rNU3 dist.orig/opcodes/cgen.sh dist/opcodes/cgen.sh 23752--- dist.orig/opcodes/cgen.sh 2009-06-14 18:36:56.000000000 +0200 23753+++ dist/opcodes/cgen.sh 2015-10-18 13:11:19.000000000 +0200 23754@@ -61,6 +61,7 @@ 23755 shift ; extrafiles=$9 23756 23757 rootdir=${srcdir}/.. 23758+move_if_change="${CONFIG_SHELL:-/bin/sh} ${rootdir}/move-if-change" 23759 23760 # $arch is $6, as passed on the command line. 23761 # $ARCH is the same argument but in all uppercase. 23762diff -rNU3 dist.orig/opcodes/configure dist/opcodes/configure 23763--- dist.orig/opcodes/configure 2012-09-04 16:21:07.000000000 +0200 23764+++ dist/opcodes/configure 2015-10-18 13:11:19.000000000 +0200 23765@@ -12532,13 +12532,13 @@ 23766 bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; 23767 bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; 23768 bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; 23769- bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; 23770- bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; 23771+ bfd_or1k_arch) ta="$ta or1k-asm.lo or1k-desc.lo or1k-dis.lo or1k-ibld.lo or1k-opc.lo" using_cgen=yes ;; 23772 bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; 23773 bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; 23774 bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; 23775 bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; 23776 bfd_pyramid_arch) ;; 23777+ bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;; 23778 bfd_romp_arch) ;; 23779 bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; 23780 bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; 23781@@ -12551,6 +12551,14 @@ 23782 # specified, as in sh3-elf, sh3b-linux-gnu, etc. 23783 # Include it just for ELF targets, since the SH5 bfd:s are ELF only. 23784 for t in $target $canon_targets; do 23785+ # For NetBSD we do NOT want SH5 support unless sh5 or sh64 23786+ # is specified 23787+ case $t in 23788+ sh5*-* | sh64*-*) # let the case below handle it 23789+ ;; 23790+ sh*-*-netbsd* | sh*l*-*-netbsd*) 23791+ continue ;; 23792+ esac 23793 case $t in 23794 all | sh5*-* | sh64*-* | sh-*-*elf* | shl*-*-*elf* | \ 23795 sh-*-linux* | shl-*-linux*) 23796diff -rNU3 dist.orig/opcodes/configure.in dist/opcodes/configure.in 23797--- dist.orig/opcodes/configure.in 2012-11-05 17:29:08.000000000 +0100 23798+++ dist/opcodes/configure.in 2015-10-18 13:11:19.000000000 +0200 23799@@ -277,13 +277,13 @@ 23800 bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; 23801 bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; 23802 bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; 23803- bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; 23804- bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; 23805+ bfd_or1k_arch) ta="$ta or1k-asm.lo or1k-desc.lo or1k-dis.lo or1k-ibld.lo or1k-opc.lo" using_cgen=yes ;; 23806 bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; 23807 bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; 23808 bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; 23809 bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; 23810 bfd_pyramid_arch) ;; 23811+ bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;; 23812 bfd_romp_arch) ;; 23813 bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; 23814 bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; 23815@@ -296,6 +296,14 @@ 23816 # specified, as in sh3-elf, sh3b-linux-gnu, etc. 23817 # Include it just for ELF targets, since the SH5 bfd:s are ELF only. 23818 for t in $target $canon_targets; do 23819+ # For NetBSD we do NOT want SH5 support unless sh5 or sh64 23820+ # is specified 23821+ case $t in 23822+ sh5*-* | sh64*-*) # let the case below handle it 23823+ ;; 23824+ sh*-*-netbsd* | sh*l*-*-netbsd*) 23825+ continue ;; 23826+ esac 23827 case $t in 23828 all | sh5*-* | sh64*-* | sh-*-*elf* | shl*-*-*elf* | \ 23829 sh-*-linux* | shl-*-linux*) 23830diff -rNU3 dist.orig/opcodes/disassemble.c dist/opcodes/disassemble.c 23831--- dist.orig/opcodes/disassemble.c 2012-09-04 14:53:50.000000000 +0200 23832+++ dist/opcodes/disassemble.c 2015-10-18 13:11:19.000000000 +0200 23833@@ -67,11 +67,11 @@ 23834 #define ARCH_mt 23835 #define ARCH_msp430 23836 #define ARCH_ns32k 23837-#define ARCH_openrisc 23838-#define ARCH_or32 23839+#define ARCH_or1k 23840 #define ARCH_pdp11 23841 #define ARCH_pj 23842 #define ARCH_powerpc 23843+#define ARCH_riscv 23844 #define ARCH_rs6000 23845 #define ARCH_rl78 23846 #define ARCH_rx 23847@@ -332,17 +332,9 @@ 23848 disassemble = print_insn_mn10300; 23849 break; 23850 #endif 23851-#ifdef ARCH_openrisc 23852- case bfd_arch_openrisc: 23853- disassemble = print_insn_openrisc; 23854- break; 23855-#endif 23856-#ifdef ARCH_or32 23857- case bfd_arch_or32: 23858- if (bfd_big_endian (abfd)) 23859- disassemble = print_insn_big_or32; 23860- else 23861- disassemble = print_insn_little_or32; 23862+#ifdef ARCH_or1k 23863+ case bfd_arch_or1k: 23864+ disassemble = print_insn_or1k; 23865 break; 23866 #endif 23867 #ifdef ARCH_pdp11 23868@@ -363,6 +355,11 @@ 23869 disassemble = print_insn_little_powerpc; 23870 break; 23871 #endif 23872+#ifdef ARCH_riscv 23873+ case bfd_arch_riscv: 23874+ disassemble = print_insn_riscv; 23875+ break; 23876+#endif 23877 #ifdef ARCH_rs6000 23878 case bfd_arch_rs6000: 23879 if (bfd_get_mach (abfd) == bfd_mach_ppc_620) 23880diff -rNU3 dist.orig/opcodes/mips-opc.c dist/opcodes/mips-opc.c 23881--- dist.orig/opcodes/mips-opc.c 2012-09-04 16:21:10.000000000 +0200 23882+++ dist/opcodes/mips-opc.c 2015-10-18 13:11:20.000000000 +0200 23883@@ -791,10 +791,12 @@ 23884 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, 23885 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, 23886 {"iret", "", 0x42000038, 0xffffffff, NODS, 0, MC }, 23887+{"jr", "s", 0, (int) M_JR_S, INSN_MACRO, 0, I1 }, 23888 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, 23889 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with 23890 the same hazard barrier effect. */ 23891 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, 23892+{"j", "s", 0, (int) M_J_S, INSN_MACRO, 0, I1 }, 23893 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ 23894 /* SVR4 PIC code requires special handling for j, so it must be a 23895 macro. */ 23896@@ -803,7 +805,9 @@ 23897 assembler, but will never match user input (because the line above 23898 will match first). */ 23899 {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, 23900+{"jalr", "s", 0, (int) M_JALR_S, INSN_MACRO, 0, I1 }, 23901 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, 23902+{"jalr", "d,s", 0, (int) M_JALR_DS, INSN_MACRO, 0, I1 }, 23903 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, 23904 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr 23905 with the same hazard barrier effect. */ 23906diff -rNU3 dist.orig/opcodes/openrisc-asm.c dist/opcodes/openrisc-asm.c 23907--- dist.orig/opcodes/openrisc-asm.c 2010-06-27 06:07:55.000000000 +0200 23908+++ dist/opcodes/openrisc-asm.c 1970-01-01 01:00:00.000000000 +0100 23909@@ -1,649 +0,0 @@ 23910-/* Assembler interface for targets using CGEN. -*- C -*- 23911- CGEN: Cpu tools GENerator 23912- 23913- THIS FILE IS MACHINE GENERATED WITH CGEN. 23914- - the resultant file is machine generated, cgen-asm.in isn't 23915- 23916- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 23917- Free Software Foundation, Inc. 23918- 23919- This file is part of libopcodes. 23920- 23921- This library is free software; you can redistribute it and/or modify 23922- it under the terms of the GNU General Public License as published by 23923- the Free Software Foundation; either version 3, or (at your option) 23924- any later version. 23925- 23926- It is distributed in the hope that it will be useful, but WITHOUT 23927- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 23928- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 23929- License for more details. 23930- 23931- You should have received a copy of the GNU General Public License 23932- along with this program; if not, write to the Free Software Foundation, Inc., 23933- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23934- 23935- 23936-/* ??? Eventually more and more of this stuff can go to cpu-independent files. 23937- Keep that in mind. */ 23938- 23939-#include "sysdep.h" 23940-#include <stdio.h> 23941-#include "ansidecl.h" 23942-#include "bfd.h" 23943-#include "symcat.h" 23944-#include "openrisc-desc.h" 23945-#include "openrisc-opc.h" 23946-#include "opintl.h" 23947-#include "xregex.h" 23948-#include "libiberty.h" 23949-#include "safe-ctype.h" 23950- 23951-#undef min 23952-#define min(a,b) ((a) < (b) ? (a) : (b)) 23953-#undef max 23954-#define max(a,b) ((a) > (b) ? (a) : (b)) 23955- 23956-static const char * parse_insn_normal 23957- (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); 23958- 23959-/* -- assembler routines inserted here. */ 23960- 23961-/* -- asm.c */ 23962- 23963-static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); 23964- 23965-#define CGEN_VERBOSE_ASSEMBLER_ERRORS 23966- 23967-long 23968-openrisc_sign_extend_16bit (long value) 23969-{ 23970- return ((value & 0xffff) ^ 0x8000) - 0x8000; 23971-} 23972- 23973-/* Handle hi(). */ 23974- 23975-static const char * 23976-parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) 23977-{ 23978- const char *errmsg; 23979- enum cgen_parse_operand_result result_type; 23980- unsigned long ret; 23981- 23982- if (**strp == '#') 23983- ++*strp; 23984- 23985- if (strncasecmp (*strp, "hi(", 3) == 0) 23986- { 23987- bfd_vma value; 23988- 23989- *strp += 3; 23990- errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, 23991- & result_type, & value); 23992- if (**strp != ')') 23993- return MISSING_CLOSING_PARENTHESIS; 23994- 23995- ++*strp; 23996- if (errmsg == NULL 23997- && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 23998- value >>= 16; 23999- ret = value; 24000- } 24001- else 24002- { 24003- if (**strp == '-') 24004- { 24005- long value; 24006- 24007- errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); 24008- ret = value; 24009- } 24010- else 24011- { 24012- unsigned long value; 24013- 24014- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); 24015- ret = value; 24016- } 24017- } 24018- 24019- *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; 24020- return errmsg; 24021-} 24022- 24023-/* Handle lo(). */ 24024- 24025-static const char * 24026-parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) 24027-{ 24028- const char *errmsg; 24029- enum cgen_parse_operand_result result_type; 24030- unsigned long ret; 24031- 24032- if (**strp == '#') 24033- ++*strp; 24034- 24035- if (strncasecmp (*strp, "lo(", 3) == 0) 24036- { 24037- bfd_vma value; 24038- 24039- *strp += 3; 24040- errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, 24041- & result_type, & value); 24042- if (**strp != ')') 24043- return MISSING_CLOSING_PARENTHESIS; 24044- 24045- ++*strp; 24046- ret = value; 24047- } 24048- else 24049- { 24050- if (**strp == '-') 24051- { 24052- long value; 24053- 24054- errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); 24055- ret = value; 24056- } 24057- else 24058- { 24059- unsigned long value; 24060- 24061- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); 24062- ret = value; 24063- } 24064- } 24065- 24066- *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; 24067- return errmsg; 24068-} 24069- 24070-/* -- */ 24071- 24072-const char * openrisc_cgen_parse_operand 24073- (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); 24074- 24075-/* Main entry point for operand parsing. 24076- 24077- This function is basically just a big switch statement. Earlier versions 24078- used tables to look up the function to use, but 24079- - if the table contains both assembler and disassembler functions then 24080- the disassembler contains much of the assembler and vice-versa, 24081- - there's a lot of inlining possibilities as things grow, 24082- - using a switch statement avoids the function call overhead. 24083- 24084- This function could be moved into `parse_insn_normal', but keeping it 24085- separate makes clear the interface between `parse_insn_normal' and each of 24086- the handlers. */ 24087- 24088-const char * 24089-openrisc_cgen_parse_operand (CGEN_CPU_DESC cd, 24090- int opindex, 24091- const char ** strp, 24092- CGEN_FIELDS * fields) 24093-{ 24094- const char * errmsg = NULL; 24095- /* Used by scalar operands that still need to be parsed. */ 24096- long junk ATTRIBUTE_UNUSED; 24097- 24098- switch (opindex) 24099- { 24100- case OPENRISC_OPERAND_ABS_26 : 24101- { 24102- bfd_vma value = 0; 24103- errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_ABS_26, 0, NULL, & value); 24104- fields->f_abs26 = value; 24105- } 24106- break; 24107- case OPENRISC_OPERAND_DISP_26 : 24108- { 24109- bfd_vma value = 0; 24110- errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_DISP_26, 0, NULL, & value); 24111- fields->f_disp26 = value; 24112- } 24113- break; 24114- case OPENRISC_OPERAND_HI16 : 24115- errmsg = parse_hi16 (cd, strp, OPENRISC_OPERAND_HI16, (long *) (& fields->f_simm16)); 24116- break; 24117- case OPENRISC_OPERAND_LO16 : 24118- errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_LO16, (long *) (& fields->f_lo16)); 24119- break; 24120- case OPENRISC_OPERAND_OP_F_23 : 24121- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_23, (unsigned long *) (& fields->f_op4)); 24122- break; 24123- case OPENRISC_OPERAND_OP_F_3 : 24124- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_3, (unsigned long *) (& fields->f_op5)); 24125- break; 24126- case OPENRISC_OPERAND_RA : 24127- errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r2); 24128- break; 24129- case OPENRISC_OPERAND_RB : 24130- errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r3); 24131- break; 24132- case OPENRISC_OPERAND_RD : 24133- errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r1); 24134- break; 24135- case OPENRISC_OPERAND_SIMM_16 : 24136- errmsg = cgen_parse_signed_integer (cd, strp, OPENRISC_OPERAND_SIMM_16, (long *) (& fields->f_simm16)); 24137- break; 24138- case OPENRISC_OPERAND_UI16NC : 24139- errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_UI16NC, (long *) (& fields->f_i16nc)); 24140- break; 24141- case OPENRISC_OPERAND_UIMM_16 : 24142- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_16, (unsigned long *) (& fields->f_uimm16)); 24143- break; 24144- case OPENRISC_OPERAND_UIMM_5 : 24145- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_5, (unsigned long *) (& fields->f_uimm5)); 24146- break; 24147- 24148- default : 24149- /* xgettext:c-format */ 24150- fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); 24151- abort (); 24152- } 24153- 24154- return errmsg; 24155-} 24156- 24157-cgen_parse_fn * const openrisc_cgen_parse_handlers[] = 24158-{ 24159- parse_insn_normal, 24160-}; 24161- 24162-void 24163-openrisc_cgen_init_asm (CGEN_CPU_DESC cd) 24164-{ 24165- openrisc_cgen_init_opcode_table (cd); 24166- openrisc_cgen_init_ibld_table (cd); 24167- cd->parse_handlers = & openrisc_cgen_parse_handlers[0]; 24168- cd->parse_operand = openrisc_cgen_parse_operand; 24169-#ifdef CGEN_ASM_INIT_HOOK 24170-CGEN_ASM_INIT_HOOK 24171-#endif 24172-} 24173- 24174- 24175- 24176-/* Regex construction routine. 24177- 24178- This translates an opcode syntax string into a regex string, 24179- by replacing any non-character syntax element (such as an 24180- opcode) with the pattern '.*' 24181- 24182- It then compiles the regex and stores it in the opcode, for 24183- later use by openrisc_cgen_assemble_insn 24184- 24185- Returns NULL for success, an error message for failure. */ 24186- 24187-char * 24188-openrisc_cgen_build_insn_regex (CGEN_INSN *insn) 24189-{ 24190- CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); 24191- const char *mnem = CGEN_INSN_MNEMONIC (insn); 24192- char rxbuf[CGEN_MAX_RX_ELEMENTS]; 24193- char *rx = rxbuf; 24194- const CGEN_SYNTAX_CHAR_TYPE *syn; 24195- int reg_err; 24196- 24197- syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); 24198- 24199- /* Mnemonics come first in the syntax string. */ 24200- if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) 24201- return _("missing mnemonic in syntax string"); 24202- ++syn; 24203- 24204- /* Generate a case sensitive regular expression that emulates case 24205- insensitive matching in the "C" locale. We cannot generate a case 24206- insensitive regular expression because in Turkish locales, 'i' and 'I' 24207- are not equal modulo case conversion. */ 24208- 24209- /* Copy the literal mnemonic out of the insn. */ 24210- for (; *mnem; mnem++) 24211- { 24212- char c = *mnem; 24213- 24214- if (ISALPHA (c)) 24215- { 24216- *rx++ = '['; 24217- *rx++ = TOLOWER (c); 24218- *rx++ = TOUPPER (c); 24219- *rx++ = ']'; 24220- } 24221- else 24222- *rx++ = c; 24223- } 24224- 24225- /* Copy any remaining literals from the syntax string into the rx. */ 24226- for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) 24227- { 24228- if (CGEN_SYNTAX_CHAR_P (* syn)) 24229- { 24230- char c = CGEN_SYNTAX_CHAR (* syn); 24231- 24232- switch (c) 24233- { 24234- /* Escape any regex metacharacters in the syntax. */ 24235- case '.': case '[': case '\\': 24236- case '*': case '^': case '$': 24237- 24238-#ifdef CGEN_ESCAPE_EXTENDED_REGEX 24239- case '?': case '{': case '}': 24240- case '(': case ')': case '*': 24241- case '|': case '+': case ']': 24242-#endif 24243- *rx++ = '\\'; 24244- *rx++ = c; 24245- break; 24246- 24247- default: 24248- if (ISALPHA (c)) 24249- { 24250- *rx++ = '['; 24251- *rx++ = TOLOWER (c); 24252- *rx++ = TOUPPER (c); 24253- *rx++ = ']'; 24254- } 24255- else 24256- *rx++ = c; 24257- break; 24258- } 24259- } 24260- else 24261- { 24262- /* Replace non-syntax fields with globs. */ 24263- *rx++ = '.'; 24264- *rx++ = '*'; 24265- } 24266- } 24267- 24268- /* Trailing whitespace ok. */ 24269- * rx++ = '['; 24270- * rx++ = ' '; 24271- * rx++ = '\t'; 24272- * rx++ = ']'; 24273- * rx++ = '*'; 24274- 24275- /* But anchor it after that. */ 24276- * rx++ = '$'; 24277- * rx = '\0'; 24278- 24279- CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); 24280- reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); 24281- 24282- if (reg_err == 0) 24283- return NULL; 24284- else 24285- { 24286- static char msg[80]; 24287- 24288- regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); 24289- regfree ((regex_t *) CGEN_INSN_RX (insn)); 24290- free (CGEN_INSN_RX (insn)); 24291- (CGEN_INSN_RX (insn)) = NULL; 24292- return msg; 24293- } 24294-} 24295- 24296- 24297-/* Default insn parser. 24298- 24299- The syntax string is scanned and operands are parsed and stored in FIELDS. 24300- Relocs are queued as we go via other callbacks. 24301- 24302- ??? Note that this is currently an all-or-nothing parser. If we fail to 24303- parse the instruction, we return 0 and the caller will start over from 24304- the beginning. Backtracking will be necessary in parsing subexpressions, 24305- but that can be handled there. Not handling backtracking here may get 24306- expensive in the case of the m68k. Deal with later. 24307- 24308- Returns NULL for success, an error message for failure. */ 24309- 24310-static const char * 24311-parse_insn_normal (CGEN_CPU_DESC cd, 24312- const CGEN_INSN *insn, 24313- const char **strp, 24314- CGEN_FIELDS *fields) 24315-{ 24316- /* ??? Runtime added insns not handled yet. */ 24317- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 24318- const char *str = *strp; 24319- const char *errmsg; 24320- const char *p; 24321- const CGEN_SYNTAX_CHAR_TYPE * syn; 24322-#ifdef CGEN_MNEMONIC_OPERANDS 24323- /* FIXME: wip */ 24324- int past_opcode_p; 24325-#endif 24326- 24327- /* For now we assume the mnemonic is first (there are no leading operands). 24328- We can parse it without needing to set up operand parsing. 24329- GAS's input scrubber will ensure mnemonics are lowercase, but we may 24330- not be called from GAS. */ 24331- p = CGEN_INSN_MNEMONIC (insn); 24332- while (*p && TOLOWER (*p) == TOLOWER (*str)) 24333- ++p, ++str; 24334- 24335- if (* p) 24336- return _("unrecognized instruction"); 24337- 24338-#ifndef CGEN_MNEMONIC_OPERANDS 24339- if (* str && ! ISSPACE (* str)) 24340- return _("unrecognized instruction"); 24341-#endif 24342- 24343- CGEN_INIT_PARSE (cd); 24344- cgen_init_parse_operand (cd); 24345-#ifdef CGEN_MNEMONIC_OPERANDS 24346- past_opcode_p = 0; 24347-#endif 24348- 24349- /* We don't check for (*str != '\0') here because we want to parse 24350- any trailing fake arguments in the syntax string. */ 24351- syn = CGEN_SYNTAX_STRING (syntax); 24352- 24353- /* Mnemonics come first for now, ensure valid string. */ 24354- if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) 24355- abort (); 24356- 24357- ++syn; 24358- 24359- while (* syn != 0) 24360- { 24361- /* Non operand chars must match exactly. */ 24362- if (CGEN_SYNTAX_CHAR_P (* syn)) 24363- { 24364- /* FIXME: While we allow for non-GAS callers above, we assume the 24365- first char after the mnemonic part is a space. */ 24366- /* FIXME: We also take inappropriate advantage of the fact that 24367- GAS's input scrubber will remove extraneous blanks. */ 24368- if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) 24369- { 24370-#ifdef CGEN_MNEMONIC_OPERANDS 24371- if (CGEN_SYNTAX_CHAR(* syn) == ' ') 24372- past_opcode_p = 1; 24373-#endif 24374- ++ syn; 24375- ++ str; 24376- } 24377- else if (*str) 24378- { 24379- /* Syntax char didn't match. Can't be this insn. */ 24380- static char msg [80]; 24381- 24382- /* xgettext:c-format */ 24383- sprintf (msg, _("syntax error (expected char `%c', found `%c')"), 24384- CGEN_SYNTAX_CHAR(*syn), *str); 24385- return msg; 24386- } 24387- else 24388- { 24389- /* Ran out of input. */ 24390- static char msg [80]; 24391- 24392- /* xgettext:c-format */ 24393- sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), 24394- CGEN_SYNTAX_CHAR(*syn)); 24395- return msg; 24396- } 24397- continue; 24398- } 24399- 24400-#ifdef CGEN_MNEMONIC_OPERANDS 24401- (void) past_opcode_p; 24402-#endif 24403- /* We have an operand of some sort. */ 24404- errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); 24405- if (errmsg) 24406- return errmsg; 24407- 24408- /* Done with this operand, continue with next one. */ 24409- ++ syn; 24410- } 24411- 24412- /* If we're at the end of the syntax string, we're done. */ 24413- if (* syn == 0) 24414- { 24415- /* FIXME: For the moment we assume a valid `str' can only contain 24416- blanks now. IE: We needn't try again with a longer version of 24417- the insn and it is assumed that longer versions of insns appear 24418- before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ 24419- while (ISSPACE (* str)) 24420- ++ str; 24421- 24422- if (* str != '\0') 24423- return _("junk at end of line"); /* FIXME: would like to include `str' */ 24424- 24425- return NULL; 24426- } 24427- 24428- /* We couldn't parse it. */ 24429- return _("unrecognized instruction"); 24430-} 24431- 24432-/* Main entry point. 24433- This routine is called for each instruction to be assembled. 24434- STR points to the insn to be assembled. 24435- We assume all necessary tables have been initialized. 24436- The assembled instruction, less any fixups, is stored in BUF. 24437- Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value 24438- still needs to be converted to target byte order, otherwise BUF is an array 24439- of bytes in target byte order. 24440- The result is a pointer to the insn's entry in the opcode table, 24441- or NULL if an error occured (an error message will have already been 24442- printed). 24443- 24444- Note that when processing (non-alias) macro-insns, 24445- this function recurses. 24446- 24447- ??? It's possible to make this cpu-independent. 24448- One would have to deal with a few minor things. 24449- At this point in time doing so would be more of a curiosity than useful 24450- [for example this file isn't _that_ big], but keeping the possibility in 24451- mind helps keep the design clean. */ 24452- 24453-const CGEN_INSN * 24454-openrisc_cgen_assemble_insn (CGEN_CPU_DESC cd, 24455- const char *str, 24456- CGEN_FIELDS *fields, 24457- CGEN_INSN_BYTES_PTR buf, 24458- char **errmsg) 24459-{ 24460- const char *start; 24461- CGEN_INSN_LIST *ilist; 24462- const char *parse_errmsg = NULL; 24463- const char *insert_errmsg = NULL; 24464- int recognized_mnemonic = 0; 24465- 24466- /* Skip leading white space. */ 24467- while (ISSPACE (* str)) 24468- ++ str; 24469- 24470- /* The instructions are stored in hashed lists. 24471- Get the first in the list. */ 24472- ilist = CGEN_ASM_LOOKUP_INSN (cd, str); 24473- 24474- /* Keep looking until we find a match. */ 24475- start = str; 24476- for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) 24477- { 24478- const CGEN_INSN *insn = ilist->insn; 24479- recognized_mnemonic = 1; 24480- 24481-#ifdef CGEN_VALIDATE_INSN_SUPPORTED 24482- /* Not usually needed as unsupported opcodes 24483- shouldn't be in the hash lists. */ 24484- /* Is this insn supported by the selected cpu? */ 24485- if (! openrisc_cgen_insn_supported (cd, insn)) 24486- continue; 24487-#endif 24488- /* If the RELAXED attribute is set, this is an insn that shouldn't be 24489- chosen immediately. Instead, it is used during assembler/linker 24490- relaxation if possible. */ 24491- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) 24492- continue; 24493- 24494- str = start; 24495- 24496- /* Skip this insn if str doesn't look right lexically. */ 24497- if (CGEN_INSN_RX (insn) != NULL && 24498- regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) 24499- continue; 24500- 24501- /* Allow parse/insert handlers to obtain length of insn. */ 24502- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 24503- 24504- parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); 24505- if (parse_errmsg != NULL) 24506- continue; 24507- 24508- /* ??? 0 is passed for `pc'. */ 24509- insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, 24510- (bfd_vma) 0); 24511- if (insert_errmsg != NULL) 24512- continue; 24513- 24514- /* It is up to the caller to actually output the insn and any 24515- queued relocs. */ 24516- return insn; 24517- } 24518- 24519- { 24520- static char errbuf[150]; 24521- const char *tmp_errmsg; 24522-#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS 24523-#define be_verbose 1 24524-#else 24525-#define be_verbose 0 24526-#endif 24527- 24528- if (be_verbose) 24529- { 24530- /* If requesting verbose error messages, use insert_errmsg. 24531- Failing that, use parse_errmsg. */ 24532- tmp_errmsg = (insert_errmsg ? insert_errmsg : 24533- parse_errmsg ? parse_errmsg : 24534- recognized_mnemonic ? 24535- _("unrecognized form of instruction") : 24536- _("unrecognized instruction")); 24537- 24538- if (strlen (start) > 50) 24539- /* xgettext:c-format */ 24540- sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); 24541- else 24542- /* xgettext:c-format */ 24543- sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); 24544- } 24545- else 24546- { 24547- if (strlen (start) > 50) 24548- /* xgettext:c-format */ 24549- sprintf (errbuf, _("bad instruction `%.50s...'"), start); 24550- else 24551- /* xgettext:c-format */ 24552- sprintf (errbuf, _("bad instruction `%.50s'"), start); 24553- } 24554- 24555- *errmsg = errbuf; 24556- return NULL; 24557- } 24558-} 24559diff -rNU3 dist.orig/opcodes/openrisc-desc.c dist/opcodes/openrisc-desc.c 24560--- dist.orig/opcodes/openrisc-desc.c 2010-02-12 04:25:49.000000000 +0100 24561+++ dist/opcodes/openrisc-desc.c 1970-01-01 01:00:00.000000000 +0100 24562@@ -1,1018 +0,0 @@ 24563-/* CPU data for openrisc. 24564- 24565-THIS FILE IS MACHINE GENERATED WITH CGEN. 24566- 24567-Copyright 1996-2010 Free Software Foundation, Inc. 24568- 24569-This file is part of the GNU Binutils and/or GDB, the GNU debugger. 24570- 24571- This file is free software; you can redistribute it and/or modify 24572- it under the terms of the GNU General Public License as published by 24573- the Free Software Foundation; either version 3, or (at your option) 24574- any later version. 24575- 24576- It is distributed in the hope that it will be useful, but WITHOUT 24577- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24578- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 24579- License for more details. 24580- 24581- You should have received a copy of the GNU General Public License along 24582- with this program; if not, write to the Free Software Foundation, Inc., 24583- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 24584- 24585-*/ 24586- 24587-#include "sysdep.h" 24588-#include <stdio.h> 24589-#include <stdarg.h> 24590-#include "ansidecl.h" 24591-#include "bfd.h" 24592-#include "symcat.h" 24593-#include "openrisc-desc.h" 24594-#include "openrisc-opc.h" 24595-#include "opintl.h" 24596-#include "libiberty.h" 24597-#include "xregex.h" 24598- 24599-/* Attributes. */ 24600- 24601-static const CGEN_ATTR_ENTRY bool_attr[] = 24602-{ 24603- { "#f", 0 }, 24604- { "#t", 1 }, 24605- { 0, 0 } 24606-}; 24607- 24608-static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 24609-{ 24610- { "base", MACH_BASE }, 24611- { "openrisc", MACH_OPENRISC }, 24612- { "or1300", MACH_OR1300 }, 24613- { "max", MACH_MAX }, 24614- { 0, 0 } 24615-}; 24616- 24617-static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 24618-{ 24619- { "or32", ISA_OR32 }, 24620- { "max", ISA_MAX }, 24621- { 0, 0 } 24622-}; 24623- 24624-static const CGEN_ATTR_ENTRY HAS_CACHE_attr[] ATTRIBUTE_UNUSED = 24625-{ 24626- { "DATA_CACHE", HAS_CACHE_DATA_CACHE }, 24627- { "INSN_CACHE", HAS_CACHE_INSN_CACHE }, 24628- { 0, 0 } 24629-}; 24630- 24631-const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[] = 24632-{ 24633- { "MACH", & MACH_attr[0], & MACH_attr[0] }, 24634- { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 24635- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 24636- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 24637- { "RESERVED", &bool_attr[0], &bool_attr[0] }, 24638- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 24639- { "SIGNED", &bool_attr[0], &bool_attr[0] }, 24640- { 0, 0, 0 } 24641-}; 24642- 24643-const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[] = 24644-{ 24645- { "MACH", & MACH_attr[0], & MACH_attr[0] }, 24646- { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 24647- { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 24648- { "PC", &bool_attr[0], &bool_attr[0] }, 24649- { "PROFILE", &bool_attr[0], &bool_attr[0] }, 24650- { 0, 0, 0 } 24651-}; 24652- 24653-const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[] = 24654-{ 24655- { "MACH", & MACH_attr[0], & MACH_attr[0] }, 24656- { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 24657- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 24658- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 24659- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 24660- { "SIGNED", &bool_attr[0], &bool_attr[0] }, 24661- { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 24662- { "RELAX", &bool_attr[0], &bool_attr[0] }, 24663- { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 24664- { 0, 0, 0 } 24665-}; 24666- 24667-const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] = 24668-{ 24669- { "MACH", & MACH_attr[0], & MACH_attr[0] }, 24670- { "ALIAS", &bool_attr[0], &bool_attr[0] }, 24671- { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 24672- { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 24673- { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 24674- { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 24675- { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 24676- { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 24677- { "RELAXED", &bool_attr[0], &bool_attr[0] }, 24678- { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 24679- { "PBB", &bool_attr[0], &bool_attr[0] }, 24680- { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 24681- { 0, 0, 0 } 24682-}; 24683- 24684-/* Instruction set variants. */ 24685- 24686-static const CGEN_ISA openrisc_cgen_isa_table[] = { 24687- { "or32", 32, 32, 32, 32 }, 24688- { 0, 0, 0, 0, 0 } 24689-}; 24690- 24691-/* Machine variants. */ 24692- 24693-static const CGEN_MACH openrisc_cgen_mach_table[] = { 24694- { "openrisc", "openrisc", MACH_OPENRISC, 0 }, 24695- { "or1300", "openrisc:1300", MACH_OR1300, 0 }, 24696- { 0, 0, 0, 0 } 24697-}; 24698- 24699-static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] = 24700-{ 24701- { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 24702- { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 24703- { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 24704- { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 24705- { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 24706- { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 24707- { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 24708- { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 24709- { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 24710- { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 24711- { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 24712- { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 24713- { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 24714- { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 24715- { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 24716- { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, 24717- { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, 24718- { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, 24719- { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, 24720- { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, 24721- { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, 24722- { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, 24723- { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, 24724- { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, 24725- { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, 24726- { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, 24727- { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, 24728- { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, 24729- { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, 24730- { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, 24731- { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, 24732- { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, 24733- { "lr", 11, {0, {{{0, 0}}}}, 0, 0 }, 24734- { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, 24735- { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } 24736-}; 24737- 24738-CGEN_KEYWORD openrisc_cgen_opval_h_gr = 24739-{ 24740- & openrisc_cgen_opval_h_gr_entries[0], 24741- 35, 24742- 0, 0, 0, 0, "" 24743-}; 24744- 24745- 24746-/* The hardware table. */ 24747- 24748-#define A(a) (1 << CGEN_HW_##a) 24749- 24750-const CGEN_HW_ENTRY openrisc_cgen_hw_table[] = 24751-{ 24752- { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24753- { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24754- { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24755- { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24756- { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24757- { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, 24758- { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 24759- { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24760- { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24761- { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24762- { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24763- { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24764- { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 24765-}; 24766- 24767-#undef A 24768- 24769- 24770-/* The instruction field table. */ 24771- 24772-#define A(a) (1 << CGEN_IFLD_##a) 24773- 24774-const CGEN_IFLD openrisc_cgen_ifld_table[] = 24775-{ 24776- { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24777- { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24778- { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24779- { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24780- { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24781- { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24782- { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24783- { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24784- { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24785- { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24786- { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24787- { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24788- { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24789- { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24790- { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24791- { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24792- { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24793- { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24794- { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24795- { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24796- { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24797- { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 24798- { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 24799- { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 24800- { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, 24801- { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, 24802- { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, 24803- { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, 24804- { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, 24805- { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, 24806- { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 24807-}; 24808- 24809-#undef A 24810- 24811- 24812- 24813-/* multi ifield declarations */ 24814- 24815-const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD []; 24816- 24817- 24818-/* multi ifield definitions */ 24819- 24820-const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] = 24821-{ 24822- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_1] } }, 24823- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_2] } }, 24824- { 0, { (const PTR) 0 } } 24825-}; 24826- 24827-/* The operand table. */ 24828- 24829-#define A(a) (1 << CGEN_OPERAND_##a) 24830-#define OPERAND(op) OPENRISC_OPERAND_##op 24831- 24832-const CGEN_OPERAND openrisc_cgen_operand_table[] = 24833-{ 24834-/* pc: program counter */ 24835- { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0, 24836- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_NIL] } }, 24837- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 24838-/* sr: special register */ 24839- { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0, 24840- { 0, { (const PTR) 0 } }, 24841- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 24842-/* cbit: condition bit */ 24843- { "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0, 24844- { 0, { (const PTR) 0 } }, 24845- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 24846-/* simm-16: 16 bit signed immediate */ 24847- { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16, 24848- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 24849- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24850-/* uimm-16: 16 bit unsigned immediate */ 24851- { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16, 24852- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM16] } }, 24853- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24854-/* disp-26: pc-rel 26 bit */ 24855- { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26, 24856- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_DISP26] } }, 24857- { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 24858-/* abs-26: abs 26 bit */ 24859- { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26, 24860- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_ABS26] } }, 24861- { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 24862-/* uimm-5: imm5 */ 24863- { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5, 24864- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM5] } }, 24865- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24866-/* rD: destination register */ 24867- { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5, 24868- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R1] } }, 24869- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24870-/* rA: source register A */ 24871- { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5, 24872- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R2] } }, 24873- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24874-/* rB: source register B */ 24875- { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5, 24876- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R3] } }, 24877- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24878-/* op-f-23: f-op23 */ 24879- { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3, 24880- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP4] } }, 24881- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24882-/* op-f-3: f-op3 */ 24883- { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5, 24884- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP5] } }, 24885- { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24886-/* hi16: high 16 bit immediate, sign optional */ 24887- { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16, 24888- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 24889- { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 24890-/* lo16: low 16 bit immediate, sign optional */ 24891- { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16, 24892- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_LO16] } }, 24893- { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 24894-/* ui16nc: 16 bit immediate, sign optional */ 24895- { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16, 24896- { 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } }, 24897- { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 24898-/* sentinel */ 24899- { 0, 0, 0, 0, 0, 24900- { 0, { (const PTR) 0 } }, 24901- { 0, { { { (1<<MACH_BASE), 0 } } } } } 24902-}; 24903- 24904-#undef A 24905- 24906- 24907-/* The instruction table. */ 24908- 24909-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 24910-#define A(a) (1 << CGEN_INSN_##a) 24911- 24912-static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] = 24913-{ 24914- /* Special null first entry. 24915- A `num' value of zero is thus invalid. 24916- Also, the special `invalid' insn resides here. */ 24917- { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 24918-/* l.j ${abs-26} */ 24919- { 24920- OPENRISC_INSN_L_J, "l-j", "l.j", 32, 24921- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24922- }, 24923-/* l.jal ${abs-26} */ 24924- { 24925- OPENRISC_INSN_L_JAL, "l-jal", "l.jal", 32, 24926- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24927- }, 24928-/* l.jr $rA */ 24929- { 24930- OPENRISC_INSN_L_JR, "l-jr", "l.jr", 32, 24931- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24932- }, 24933-/* l.jalr $rA */ 24934- { 24935- OPENRISC_INSN_L_JALR, "l-jalr", "l.jalr", 32, 24936- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24937- }, 24938-/* l.bal ${disp-26} */ 24939- { 24940- OPENRISC_INSN_L_BAL, "l-bal", "l.bal", 32, 24941- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24942- }, 24943-/* l.bnf ${disp-26} */ 24944- { 24945- OPENRISC_INSN_L_BNF, "l-bnf", "l.bnf", 32, 24946- { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24947- }, 24948-/* l.bf ${disp-26} */ 24949- { 24950- OPENRISC_INSN_L_BF, "l-bf", "l.bf", 32, 24951- { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24952- }, 24953-/* l.brk ${uimm-16} */ 24954- { 24955- OPENRISC_INSN_L_BRK, "l-brk", "l.brk", 32, 24956- { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24957- }, 24958-/* l.rfe $rA */ 24959- { 24960- OPENRISC_INSN_L_RFE, "l-rfe", "l.rfe", 32, 24961- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24962- }, 24963-/* l.sys ${uimm-16} */ 24964- { 24965- OPENRISC_INSN_L_SYS, "l-sys", "l.sys", 32, 24966- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24967- }, 24968-/* l.nop */ 24969- { 24970- OPENRISC_INSN_L_NOP, "l-nop", "l.nop", 32, 24971- { 0, { { { (1<<MACH_BASE), 0 } } } } 24972- }, 24973-/* l.movhi $rD,$hi16 */ 24974- { 24975- OPENRISC_INSN_L_MOVHI, "l-movhi", "l.movhi", 32, 24976- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24977- }, 24978-/* l.mfsr $rD,$rA */ 24979- { 24980- OPENRISC_INSN_L_MFSR, "l-mfsr", "l.mfsr", 32, 24981- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24982- }, 24983-/* l.mtsr $rA,$rB */ 24984- { 24985- OPENRISC_INSN_L_MTSR, "l-mtsr", "l.mtsr", 32, 24986- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24987- }, 24988-/* l.lw $rD,${simm-16}($rA) */ 24989- { 24990- OPENRISC_INSN_L_LW, "l-lw", "l.lw", 32, 24991- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24992- }, 24993-/* l.lbz $rD,${simm-16}($rA) */ 24994- { 24995- OPENRISC_INSN_L_LBZ, "l-lbz", "l.lbz", 32, 24996- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 24997- }, 24998-/* l.lbs $rD,${simm-16}($rA) */ 24999- { 25000- OPENRISC_INSN_L_LBS, "l-lbs", "l.lbs", 32, 25001- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25002- }, 25003-/* l.lhz $rD,${simm-16}($rA) */ 25004- { 25005- OPENRISC_INSN_L_LHZ, "l-lhz", "l.lhz", 32, 25006- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25007- }, 25008-/* l.lhs $rD,${simm-16}($rA) */ 25009- { 25010- OPENRISC_INSN_L_LHS, "l-lhs", "l.lhs", 32, 25011- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25012- }, 25013-/* l.sw ${ui16nc}($rA),$rB */ 25014- { 25015- OPENRISC_INSN_L_SW, "l-sw", "l.sw", 32, 25016- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25017- }, 25018-/* l.sb ${ui16nc}($rA),$rB */ 25019- { 25020- OPENRISC_INSN_L_SB, "l-sb", "l.sb", 32, 25021- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25022- }, 25023-/* l.sh ${ui16nc}($rA),$rB */ 25024- { 25025- OPENRISC_INSN_L_SH, "l-sh", "l.sh", 32, 25026- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25027- }, 25028-/* l.sll $rD,$rA,$rB */ 25029- { 25030- OPENRISC_INSN_L_SLL, "l-sll", "l.sll", 32, 25031- { 0, { { { (1<<MACH_BASE), 0 } } } } 25032- }, 25033-/* l.slli $rD,$rA,${uimm-5} */ 25034- { 25035- OPENRISC_INSN_L_SLLI, "l-slli", "l.slli", 32, 25036- { 0, { { { (1<<MACH_BASE), 0 } } } } 25037- }, 25038-/* l.srl $rD,$rA,$rB */ 25039- { 25040- OPENRISC_INSN_L_SRL, "l-srl", "l.srl", 32, 25041- { 0, { { { (1<<MACH_BASE), 0 } } } } 25042- }, 25043-/* l.srli $rD,$rA,${uimm-5} */ 25044- { 25045- OPENRISC_INSN_L_SRLI, "l-srli", "l.srli", 32, 25046- { 0, { { { (1<<MACH_BASE), 0 } } } } 25047- }, 25048-/* l.sra $rD,$rA,$rB */ 25049- { 25050- OPENRISC_INSN_L_SRA, "l-sra", "l.sra", 32, 25051- { 0, { { { (1<<MACH_BASE), 0 } } } } 25052- }, 25053-/* l.srai $rD,$rA,${uimm-5} */ 25054- { 25055- OPENRISC_INSN_L_SRAI, "l-srai", "l.srai", 32, 25056- { 0, { { { (1<<MACH_BASE), 0 } } } } 25057- }, 25058-/* l.ror $rD,$rA,$rB */ 25059- { 25060- OPENRISC_INSN_L_ROR, "l-ror", "l.ror", 32, 25061- { 0, { { { (1<<MACH_BASE), 0 } } } } 25062- }, 25063-/* l.rori $rD,$rA,${uimm-5} */ 25064- { 25065- OPENRISC_INSN_L_RORI, "l-rori", "l.rori", 32, 25066- { 0, { { { (1<<MACH_BASE), 0 } } } } 25067- }, 25068-/* l.add $rD,$rA,$rB */ 25069- { 25070- OPENRISC_INSN_L_ADD, "l-add", "l.add", 32, 25071- { 0, { { { (1<<MACH_BASE), 0 } } } } 25072- }, 25073-/* l.addi $rD,$rA,$lo16 */ 25074- { 25075- OPENRISC_INSN_L_ADDI, "l-addi", "l.addi", 32, 25076- { 0, { { { (1<<MACH_BASE), 0 } } } } 25077- }, 25078-/* l.sub $rD,$rA,$rB */ 25079- { 25080- OPENRISC_INSN_L_SUB, "l-sub", "l.sub", 32, 25081- { 0, { { { (1<<MACH_BASE), 0 } } } } 25082- }, 25083-/* l.subi $rD,$rA,$lo16 */ 25084- { 25085- OPENRISC_INSN_L_SUBI, "l-subi", "l.subi", 32, 25086- { 0, { { { (1<<MACH_BASE), 0 } } } } 25087- }, 25088-/* l.and $rD,$rA,$rB */ 25089- { 25090- OPENRISC_INSN_L_AND, "l-and", "l.and", 32, 25091- { 0, { { { (1<<MACH_BASE), 0 } } } } 25092- }, 25093-/* l.andi $rD,$rA,$lo16 */ 25094- { 25095- OPENRISC_INSN_L_ANDI, "l-andi", "l.andi", 32, 25096- { 0, { { { (1<<MACH_BASE), 0 } } } } 25097- }, 25098-/* l.or $rD,$rA,$rB */ 25099- { 25100- OPENRISC_INSN_L_OR, "l-or", "l.or", 32, 25101- { 0, { { { (1<<MACH_BASE), 0 } } } } 25102- }, 25103-/* l.ori $rD,$rA,$lo16 */ 25104- { 25105- OPENRISC_INSN_L_ORI, "l-ori", "l.ori", 32, 25106- { 0, { { { (1<<MACH_BASE), 0 } } } } 25107- }, 25108-/* l.xor $rD,$rA,$rB */ 25109- { 25110- OPENRISC_INSN_L_XOR, "l-xor", "l.xor", 32, 25111- { 0, { { { (1<<MACH_BASE), 0 } } } } 25112- }, 25113-/* l.xori $rD,$rA,$lo16 */ 25114- { 25115- OPENRISC_INSN_L_XORI, "l-xori", "l.xori", 32, 25116- { 0, { { { (1<<MACH_BASE), 0 } } } } 25117- }, 25118-/* l.mul $rD,$rA,$rB */ 25119- { 25120- OPENRISC_INSN_L_MUL, "l-mul", "l.mul", 32, 25121- { 0, { { { (1<<MACH_BASE), 0 } } } } 25122- }, 25123-/* l.muli $rD,$rA,$lo16 */ 25124- { 25125- OPENRISC_INSN_L_MULI, "l-muli", "l.muli", 32, 25126- { 0, { { { (1<<MACH_BASE), 0 } } } } 25127- }, 25128-/* l.div $rD,$rA,$rB */ 25129- { 25130- OPENRISC_INSN_L_DIV, "l-div", "l.div", 32, 25131- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25132- }, 25133-/* l.divu $rD,$rA,$rB */ 25134- { 25135- OPENRISC_INSN_L_DIVU, "l-divu", "l.divu", 32, 25136- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25137- }, 25138-/* l.sfgts $rA,$rB */ 25139- { 25140- OPENRISC_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32, 25141- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25142- }, 25143-/* l.sfgtu $rA,$rB */ 25144- { 25145- OPENRISC_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32, 25146- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25147- }, 25148-/* l.sfges $rA,$rB */ 25149- { 25150- OPENRISC_INSN_L_SFGES, "l-sfges", "l.sfges", 32, 25151- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25152- }, 25153-/* l.sfgeu $rA,$rB */ 25154- { 25155- OPENRISC_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32, 25156- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25157- }, 25158-/* l.sflts $rA,$rB */ 25159- { 25160- OPENRISC_INSN_L_SFLTS, "l-sflts", "l.sflts", 32, 25161- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25162- }, 25163-/* l.sfltu $rA,$rB */ 25164- { 25165- OPENRISC_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32, 25166- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25167- }, 25168-/* l.sfles $rA,$rB */ 25169- { 25170- OPENRISC_INSN_L_SFLES, "l-sfles", "l.sfles", 32, 25171- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25172- }, 25173-/* l.sfleu $rA,$rB */ 25174- { 25175- OPENRISC_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32, 25176- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25177- }, 25178-/* l.sfgtsi $rA,${simm-16} */ 25179- { 25180- OPENRISC_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32, 25181- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25182- }, 25183-/* l.sfgtui $rA,${uimm-16} */ 25184- { 25185- OPENRISC_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32, 25186- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25187- }, 25188-/* l.sfgesi $rA,${simm-16} */ 25189- { 25190- OPENRISC_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32, 25191- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25192- }, 25193-/* l.sfgeui $rA,${uimm-16} */ 25194- { 25195- OPENRISC_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32, 25196- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25197- }, 25198-/* l.sfltsi $rA,${simm-16} */ 25199- { 25200- OPENRISC_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32, 25201- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25202- }, 25203-/* l.sfltui $rA,${uimm-16} */ 25204- { 25205- OPENRISC_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32, 25206- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25207- }, 25208-/* l.sflesi $rA,${simm-16} */ 25209- { 25210- OPENRISC_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32, 25211- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25212- }, 25213-/* l.sfleui $rA,${uimm-16} */ 25214- { 25215- OPENRISC_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32, 25216- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25217- }, 25218-/* l.sfeq $rA,$rB */ 25219- { 25220- OPENRISC_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32, 25221- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25222- }, 25223-/* l.sfeqi $rA,${simm-16} */ 25224- { 25225- OPENRISC_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32, 25226- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25227- }, 25228-/* l.sfne $rA,$rB */ 25229- { 25230- OPENRISC_INSN_L_SFNE, "l-sfne", "l.sfne", 32, 25231- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25232- }, 25233-/* l.sfnei $rA,${simm-16} */ 25234- { 25235- OPENRISC_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32, 25236- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 25237- }, 25238-}; 25239- 25240-#undef OP 25241-#undef A 25242- 25243-/* Initialize anything needed to be done once, before any cpu_open call. */ 25244- 25245-static void 25246-init_tables (void) 25247-{ 25248-} 25249- 25250-static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 25251-static void build_hw_table (CGEN_CPU_TABLE *); 25252-static void build_ifield_table (CGEN_CPU_TABLE *); 25253-static void build_operand_table (CGEN_CPU_TABLE *); 25254-static void build_insn_table (CGEN_CPU_TABLE *); 25255-static void openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *); 25256- 25257-/* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name. */ 25258- 25259-static const CGEN_MACH * 25260-lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 25261-{ 25262- while (table->name) 25263- { 25264- if (strcmp (name, table->bfd_name) == 0) 25265- return table; 25266- ++table; 25267- } 25268- abort (); 25269-} 25270- 25271-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ 25272- 25273-static void 25274-build_hw_table (CGEN_CPU_TABLE *cd) 25275-{ 25276- int i; 25277- int machs = cd->machs; 25278- const CGEN_HW_ENTRY *init = & openrisc_cgen_hw_table[0]; 25279- /* MAX_HW is only an upper bound on the number of selected entries. 25280- However each entry is indexed by it's enum so there can be holes in 25281- the table. */ 25282- const CGEN_HW_ENTRY **selected = 25283- (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 25284- 25285- cd->hw_table.init_entries = init; 25286- cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 25287- memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 25288- /* ??? For now we just use machs to determine which ones we want. */ 25289- for (i = 0; init[i].name != NULL; ++i) 25290- if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 25291- & machs) 25292- selected[init[i].type] = &init[i]; 25293- cd->hw_table.entries = selected; 25294- cd->hw_table.num_entries = MAX_HW; 25295-} 25296- 25297-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ 25298- 25299-static void 25300-build_ifield_table (CGEN_CPU_TABLE *cd) 25301-{ 25302- cd->ifld_table = & openrisc_cgen_ifld_table[0]; 25303-} 25304- 25305-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ 25306- 25307-static void 25308-build_operand_table (CGEN_CPU_TABLE *cd) 25309-{ 25310- int i; 25311- int machs = cd->machs; 25312- const CGEN_OPERAND *init = & openrisc_cgen_operand_table[0]; 25313- /* MAX_OPERANDS is only an upper bound on the number of selected entries. 25314- However each entry is indexed by it's enum so there can be holes in 25315- the table. */ 25316- const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 25317- 25318- cd->operand_table.init_entries = init; 25319- cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 25320- memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 25321- /* ??? For now we just use mach to determine which ones we want. */ 25322- for (i = 0; init[i].name != NULL; ++i) 25323- if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 25324- & machs) 25325- selected[init[i].type] = &init[i]; 25326- cd->operand_table.entries = selected; 25327- cd->operand_table.num_entries = MAX_OPERANDS; 25328-} 25329- 25330-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. 25331- ??? This could leave out insns not supported by the specified mach/isa, 25332- but that would cause errors like "foo only supported by bar" to become 25333- "unknown insn", so for now we include all insns and require the app to 25334- do the checking later. 25335- ??? On the other hand, parsing of such insns may require their hardware or 25336- operand elements to be in the table [which they mightn't be]. */ 25337- 25338-static void 25339-build_insn_table (CGEN_CPU_TABLE *cd) 25340-{ 25341- int i; 25342- const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0]; 25343- CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 25344- 25345- memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 25346- for (i = 0; i < MAX_INSNS; ++i) 25347- insns[i].base = &ib[i]; 25348- cd->insn_table.init_entries = insns; 25349- cd->insn_table.entry_size = sizeof (CGEN_IBASE); 25350- cd->insn_table.num_init_entries = MAX_INSNS; 25351-} 25352- 25353-/* Subroutine of openrisc_cgen_cpu_open to rebuild the tables. */ 25354- 25355-static void 25356-openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 25357-{ 25358- int i; 25359- CGEN_BITSET *isas = cd->isas; 25360- unsigned int machs = cd->machs; 25361- 25362- cd->int_insn_p = CGEN_INT_INSN_P; 25363- 25364- /* Data derived from the isa spec. */ 25365-#define UNSET (CGEN_SIZE_UNKNOWN + 1) 25366- cd->default_insn_bitsize = UNSET; 25367- cd->base_insn_bitsize = UNSET; 25368- cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 25369- cd->max_insn_bitsize = 0; 25370- for (i = 0; i < MAX_ISAS; ++i) 25371- if (cgen_bitset_contains (isas, i)) 25372- { 25373- const CGEN_ISA *isa = & openrisc_cgen_isa_table[i]; 25374- 25375- /* Default insn sizes of all selected isas must be 25376- equal or we set the result to 0, meaning "unknown". */ 25377- if (cd->default_insn_bitsize == UNSET) 25378- cd->default_insn_bitsize = isa->default_insn_bitsize; 25379- else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 25380- ; /* This is ok. */ 25381- else 25382- cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 25383- 25384- /* Base insn sizes of all selected isas must be equal 25385- or we set the result to 0, meaning "unknown". */ 25386- if (cd->base_insn_bitsize == UNSET) 25387- cd->base_insn_bitsize = isa->base_insn_bitsize; 25388- else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 25389- ; /* This is ok. */ 25390- else 25391- cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 25392- 25393- /* Set min,max insn sizes. */ 25394- if (isa->min_insn_bitsize < cd->min_insn_bitsize) 25395- cd->min_insn_bitsize = isa->min_insn_bitsize; 25396- if (isa->max_insn_bitsize > cd->max_insn_bitsize) 25397- cd->max_insn_bitsize = isa->max_insn_bitsize; 25398- } 25399- 25400- /* Data derived from the mach spec. */ 25401- for (i = 0; i < MAX_MACHS; ++i) 25402- if (((1 << i) & machs) != 0) 25403- { 25404- const CGEN_MACH *mach = & openrisc_cgen_mach_table[i]; 25405- 25406- if (mach->insn_chunk_bitsize != 0) 25407- { 25408- if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 25409- { 25410- fprintf (stderr, "openrisc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", 25411- cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 25412- abort (); 25413- } 25414- 25415- cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 25416- } 25417- } 25418- 25419- /* Determine which hw elements are used by MACH. */ 25420- build_hw_table (cd); 25421- 25422- /* Build the ifield table. */ 25423- build_ifield_table (cd); 25424- 25425- /* Determine which operands are used by MACH/ISA. */ 25426- build_operand_table (cd); 25427- 25428- /* Build the instruction table. */ 25429- build_insn_table (cd); 25430-} 25431- 25432-/* Initialize a cpu table and return a descriptor. 25433- It's much like opening a file, and must be the first function called. 25434- The arguments are a set of (type/value) pairs, terminated with 25435- CGEN_CPU_OPEN_END. 25436- 25437- Currently supported values: 25438- CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 25439- CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 25440- CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 25441- CGEN_CPU_OPEN_ENDIAN: specify endian choice 25442- CGEN_CPU_OPEN_END: terminates arguments 25443- 25444- ??? Simultaneous multiple isas might not make sense, but it's not (yet) 25445- precluded. */ 25446- 25447-CGEN_CPU_DESC 25448-openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 25449-{ 25450- CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 25451- static int init_p; 25452- CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 25453- unsigned int machs = 0; /* 0 = "unspecified" */ 25454- enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 25455- va_list ap; 25456- 25457- if (! init_p) 25458- { 25459- init_tables (); 25460- init_p = 1; 25461- } 25462- 25463- memset (cd, 0, sizeof (*cd)); 25464- 25465- va_start (ap, arg_type); 25466- while (arg_type != CGEN_CPU_OPEN_END) 25467- { 25468- switch (arg_type) 25469- { 25470- case CGEN_CPU_OPEN_ISAS : 25471- isas = va_arg (ap, CGEN_BITSET *); 25472- break; 25473- case CGEN_CPU_OPEN_MACHS : 25474- machs = va_arg (ap, unsigned int); 25475- break; 25476- case CGEN_CPU_OPEN_BFDMACH : 25477- { 25478- const char *name = va_arg (ap, const char *); 25479- const CGEN_MACH *mach = 25480- lookup_mach_via_bfd_name (openrisc_cgen_mach_table, name); 25481- 25482- machs |= 1 << mach->num; 25483- break; 25484- } 25485- case CGEN_CPU_OPEN_ENDIAN : 25486- endian = va_arg (ap, enum cgen_endian); 25487- break; 25488- default : 25489- fprintf (stderr, "openrisc_cgen_cpu_open: unsupported argument `%d'\n", 25490- arg_type); 25491- abort (); /* ??? return NULL? */ 25492- } 25493- arg_type = va_arg (ap, enum cgen_cpu_open_arg); 25494- } 25495- va_end (ap); 25496- 25497- /* Mach unspecified means "all". */ 25498- if (machs == 0) 25499- machs = (1 << MAX_MACHS) - 1; 25500- /* Base mach is always selected. */ 25501- machs |= 1; 25502- if (endian == CGEN_ENDIAN_UNKNOWN) 25503- { 25504- /* ??? If target has only one, could have a default. */ 25505- fprintf (stderr, "openrisc_cgen_cpu_open: no endianness specified\n"); 25506- abort (); 25507- } 25508- 25509- cd->isas = cgen_bitset_copy (isas); 25510- cd->machs = machs; 25511- cd->endian = endian; 25512- /* FIXME: for the sparc case we can determine insn-endianness statically. 25513- The worry here is where both data and insn endian can be independently 25514- chosen, in which case this function will need another argument. 25515- Actually, will want to allow for more arguments in the future anyway. */ 25516- cd->insn_endian = endian; 25517- 25518- /* Table (re)builder. */ 25519- cd->rebuild_tables = openrisc_cgen_rebuild_tables; 25520- openrisc_cgen_rebuild_tables (cd); 25521- 25522- /* Default to not allowing signed overflow. */ 25523- cd->signed_overflow_ok_p = 0; 25524- 25525- return (CGEN_CPU_DESC) cd; 25526-} 25527- 25528-/* Cover fn to openrisc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 25529- MACH_NAME is the bfd name of the mach. */ 25530- 25531-CGEN_CPU_DESC 25532-openrisc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 25533-{ 25534- return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 25535- CGEN_CPU_OPEN_ENDIAN, endian, 25536- CGEN_CPU_OPEN_END); 25537-} 25538- 25539-/* Close a cpu table. 25540- ??? This can live in a machine independent file, but there's currently 25541- no place to put this file (there's no libcgen). libopcodes is the wrong 25542- place as some simulator ports use this but they don't use libopcodes. */ 25543- 25544-void 25545-openrisc_cgen_cpu_close (CGEN_CPU_DESC cd) 25546-{ 25547- unsigned int i; 25548- const CGEN_INSN *insns; 25549- 25550- if (cd->macro_insn_table.init_entries) 25551- { 25552- insns = cd->macro_insn_table.init_entries; 25553- for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 25554- if (CGEN_INSN_RX ((insns))) 25555- regfree (CGEN_INSN_RX (insns)); 25556- } 25557- 25558- if (cd->insn_table.init_entries) 25559- { 25560- insns = cd->insn_table.init_entries; 25561- for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 25562- if (CGEN_INSN_RX (insns)) 25563- regfree (CGEN_INSN_RX (insns)); 25564- } 25565- 25566- if (cd->macro_insn_table.init_entries) 25567- free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 25568- 25569- if (cd->insn_table.init_entries) 25570- free ((CGEN_INSN *) cd->insn_table.init_entries); 25571- 25572- if (cd->hw_table.entries) 25573- free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 25574- 25575- if (cd->operand_table.entries) 25576- free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 25577- 25578- free (cd); 25579-} 25580- 25581diff -rNU3 dist.orig/opcodes/openrisc-desc.h dist/opcodes/openrisc-desc.h 25582--- dist.orig/opcodes/openrisc-desc.h 2010-10-09 08:50:23.000000000 +0200 25583+++ dist/opcodes/openrisc-desc.h 1970-01-01 01:00:00.000000000 +0100 25584@@ -1,288 +0,0 @@ 25585-/* CPU data header for openrisc. 25586- 25587-THIS FILE IS MACHINE GENERATED WITH CGEN. 25588- 25589-Copyright 1996-2010 Free Software Foundation, Inc. 25590- 25591-This file is part of the GNU Binutils and/or GDB, the GNU debugger. 25592- 25593- This file is free software; you can redistribute it and/or modify 25594- it under the terms of the GNU General Public License as published by 25595- the Free Software Foundation; either version 3, or (at your option) 25596- any later version. 25597- 25598- It is distributed in the hope that it will be useful, but WITHOUT 25599- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 25600- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 25601- License for more details. 25602- 25603- You should have received a copy of the GNU General Public License along 25604- with this program; if not, write to the Free Software Foundation, Inc., 25605- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 25606- 25607-*/ 25608- 25609-#ifndef OPENRISC_CPU_H 25610-#define OPENRISC_CPU_H 25611- 25612-#define CGEN_ARCH openrisc 25613- 25614-/* Given symbol S, return openrisc_cgen_<S>. */ 25615-#define CGEN_SYM(s) openrisc##_cgen_##s 25616- 25617- 25618-/* Selected cpu families. */ 25619-#define HAVE_CPU_OPENRISCBF 25620- 25621-#define CGEN_INSN_LSB0_P 1 25622- 25623-/* Minimum size of any insn (in bytes). */ 25624-#define CGEN_MIN_INSN_SIZE 4 25625- 25626-/* Maximum size of any insn (in bytes). */ 25627-#define CGEN_MAX_INSN_SIZE 4 25628- 25629-#define CGEN_INT_INSN_P 1 25630- 25631-/* Maximum number of syntax elements in an instruction. */ 25632-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14 25633- 25634-/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 25635- e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 25636- we can't hash on everything up to the space. */ 25637-#define CGEN_MNEMONIC_OPERANDS 25638- 25639-/* Maximum number of fields in an instruction. */ 25640-#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 25641- 25642-/* Enums. */ 25643- 25644-/* Enum declaration for exception vectors. */ 25645-typedef enum e_exception { 25646- E_RESET, E_BUSERR, E_DPF, E_IPF 25647- , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT 25648- , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL 25649- , E_BREAK, E_RESERVED 25650-} E_EXCEPTION; 25651- 25652-/* Enum declaration for FIXME. */ 25653-typedef enum insn_class { 25654- OP1_0, OP1_1, OP1_2, OP1_3 25655-} INSN_CLASS; 25656- 25657-/* Enum declaration for FIXME. */ 25658-typedef enum insn_sub { 25659- OP2_0, OP2_1, OP2_2, OP2_3 25660- , OP2_4, OP2_5, OP2_6, OP2_7 25661- , OP2_8, OP2_9, OP2_10, OP2_11 25662- , OP2_12, OP2_13, OP2_14, OP2_15 25663-} INSN_SUB; 25664- 25665-/* Enum declaration for FIXME. */ 25666-typedef enum insn_op3 { 25667- OP3_0, OP3_1, OP3_2, OP3_3 25668-} INSN_OP3; 25669- 25670-/* Enum declaration for FIXME. */ 25671-typedef enum insn_op4 { 25672- OP4_0, OP4_1, OP4_2, OP4_3 25673- , OP4_4, OP4_5, OP4_6, OP4_7 25674-} INSN_OP4; 25675- 25676-/* Enum declaration for FIXME. */ 25677-typedef enum insn_op5 { 25678- OP5_0, OP5_1, OP5_2, OP5_3 25679- , OP5_4, OP5_5, OP5_6, OP5_7 25680- , OP5_8, OP5_9, OP5_10, OP5_11 25681- , OP5_12, OP5_13, OP5_14, OP5_15 25682- , OP5_16, OP5_17, OP5_18, OP5_19 25683- , OP5_20, OP5_21, OP5_22, OP5_23 25684- , OP5_24, OP5_25, OP5_26, OP5_27 25685- , OP5_28, OP5_29, OP5_30, OP5_31 25686-} INSN_OP5; 25687- 25688-/* Enum declaration for FIXME. */ 25689-typedef enum insn_op6 { 25690- OP6_0, OP6_1, OP6_2, OP6_3 25691- , OP6_4, OP6_5, OP6_6, OP6_7 25692-} INSN_OP6; 25693- 25694-/* Enum declaration for FIXME. */ 25695-typedef enum insn_op7 { 25696- OP7_0, OP7_1, OP7_2, OP7_3 25697- , OP7_4, OP7_5, OP7_6, OP7_7 25698- , OP7_8, OP7_9, OP7_10, OP7_11 25699- , OP7_12, OP7_13, OP7_14, OP7_15 25700-} INSN_OP7; 25701- 25702-/* Attributes. */ 25703- 25704-/* Enum declaration for machine type selection. */ 25705-typedef enum mach_attr { 25706- MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX 25707-} MACH_ATTR; 25708- 25709-/* Enum declaration for instruction set selection. */ 25710-typedef enum isa_attr { 25711- ISA_OR32, ISA_MAX 25712-} ISA_ATTR; 25713- 25714-/* Enum declaration for if this model has caches. */ 25715-typedef enum has_cache_attr { 25716- HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE 25717-} HAS_CACHE_ATTR; 25718- 25719-/* Number of architecture variants. */ 25720-#define MAX_ISAS 1 25721-#define MAX_MACHS ((int) MACH_MAX) 25722- 25723-/* Ifield support. */ 25724- 25725-/* Ifield attribute indices. */ 25726- 25727-/* Enum declaration for cgen_ifld attrs. */ 25728-typedef enum cgen_ifld_attr { 25729- CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 25730- , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 25731- , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 25732-} CGEN_IFLD_ATTR; 25733- 25734-/* Number of non-boolean elements in cgen_ifld_attr. */ 25735-#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 25736- 25737-/* cgen_ifld attribute accessor macros. */ 25738-#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 25739-#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 25740-#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 25741-#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 25742-#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 25743-#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 25744-#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 25745- 25746-/* Enum declaration for openrisc ifield types. */ 25747-typedef enum ifield_type { 25748- OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB 25749- , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16 25750- , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16 25751- , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4 25752- , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1 25753- , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC 25754- , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3 25755- , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX 25756-} IFIELD_TYPE; 25757- 25758-#define MAX_IFLD ((int) OPENRISC_F_MAX) 25759- 25760-/* Hardware attribute indices. */ 25761- 25762-/* Enum declaration for cgen_hw attrs. */ 25763-typedef enum cgen_hw_attr { 25764- CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 25765- , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 25766-} CGEN_HW_ATTR; 25767- 25768-/* Number of non-boolean elements in cgen_hw_attr. */ 25769-#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 25770- 25771-/* cgen_hw attribute accessor macros. */ 25772-#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 25773-#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 25774-#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 25775-#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 25776-#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 25777- 25778-/* Enum declaration for openrisc hardware types. */ 25779-typedef enum cgen_hw_type { 25780- HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 25781- , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR 25782- , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN 25783- , HW_MAX 25784-} CGEN_HW_TYPE; 25785- 25786-#define MAX_HW ((int) HW_MAX) 25787- 25788-/* Operand attribute indices. */ 25789- 25790-/* Enum declaration for cgen_operand attrs. */ 25791-typedef enum cgen_operand_attr { 25792- CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 25793- , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 25794- , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS 25795-} CGEN_OPERAND_ATTR; 25796- 25797-/* Number of non-boolean elements in cgen_operand_attr. */ 25798-#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 25799- 25800-/* cgen_operand attribute accessor macros. */ 25801-#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 25802-#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 25803-#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 25804-#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 25805-#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 25806-#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 25807-#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 25808-#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 25809-#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 25810- 25811-/* Enum declaration for openrisc operand types. */ 25812-typedef enum cgen_operand_type { 25813- OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16 25814- , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5 25815- , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23 25816- , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC 25817- , OPENRISC_OPERAND_MAX 25818-} CGEN_OPERAND_TYPE; 25819- 25820-/* Number of operands types. */ 25821-#define MAX_OPERANDS 16 25822- 25823-/* Maximum number of operands referenced by any insn. */ 25824-#define MAX_OPERAND_INSTANCES 8 25825- 25826-/* Insn attribute indices. */ 25827- 25828-/* Enum declaration for cgen_insn attrs. */ 25829-typedef enum cgen_insn_attr { 25830- CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 25831- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 25832- , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS 25833- , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS 25834-} CGEN_INSN_ATTR; 25835- 25836-/* Number of non-boolean elements in cgen_insn_attr. */ 25837-#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 25838- 25839-/* cgen_insn attribute accessor macros. */ 25840-#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 25841-#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 25842-#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 25843-#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 25844-#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 25845-#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 25846-#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 25847-#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 25848-#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 25849-#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 25850-#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 25851-#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) 25852- 25853-/* cgen.h uses things we just defined. */ 25854-#include "opcode/cgen.h" 25855- 25856-extern const struct cgen_ifld openrisc_cgen_ifld_table[]; 25857- 25858-/* Attributes. */ 25859-extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[]; 25860-extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[]; 25861-extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[]; 25862-extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[]; 25863- 25864-/* Hardware decls. */ 25865- 25866-extern CGEN_KEYWORD openrisc_cgen_opval_h_gr; 25867- 25868-extern const CGEN_HW_ENTRY openrisc_cgen_hw_table[]; 25869- 25870- 25871- 25872-#endif /* OPENRISC_CPU_H */ 25873diff -rNU3 dist.orig/opcodes/openrisc-dis.c dist/opcodes/openrisc-dis.c 25874--- dist.orig/opcodes/openrisc-dis.c 2010-02-12 05:42:28.000000000 +0100 25875+++ dist/opcodes/openrisc-dis.c 1970-01-01 01:00:00.000000000 +0100 25876@@ -1,556 +0,0 @@ 25877-/* Disassembler interface for targets using CGEN. -*- C -*- 25878- CGEN: Cpu tools GENerator 25879- 25880- THIS FILE IS MACHINE GENERATED WITH CGEN. 25881- - the resultant file is machine generated, cgen-dis.in isn't 25882- 25883- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 25884- 2008, 2010 Free Software Foundation, Inc. 25885- 25886- This file is part of libopcodes. 25887- 25888- This library is free software; you can redistribute it and/or modify 25889- it under the terms of the GNU General Public License as published by 25890- the Free Software Foundation; either version 3, or (at your option) 25891- any later version. 25892- 25893- It is distributed in the hope that it will be useful, but WITHOUT 25894- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 25895- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 25896- License for more details. 25897- 25898- You should have received a copy of the GNU General Public License 25899- along with this program; if not, write to the Free Software Foundation, Inc., 25900- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 25901- 25902-/* ??? Eventually more and more of this stuff can go to cpu-independent files. 25903- Keep that in mind. */ 25904- 25905-#include "sysdep.h" 25906-#include <stdio.h> 25907-#include "ansidecl.h" 25908-#include "dis-asm.h" 25909-#include "bfd.h" 25910-#include "symcat.h" 25911-#include "libiberty.h" 25912-#include "openrisc-desc.h" 25913-#include "openrisc-opc.h" 25914-#include "opintl.h" 25915- 25916-/* Default text to print if an instruction isn't recognized. */ 25917-#define UNKNOWN_INSN_MSG _("*unknown*") 25918- 25919-static void print_normal 25920- (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 25921-static void print_address 25922- (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 25923-static void print_keyword 25924- (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 25925-static void print_insn_normal 25926- (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 25927-static int print_insn 25928- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 25929-static int default_print_insn 25930- (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 25931-static int read_insn 25932- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 25933- unsigned long *); 25934- 25935-/* -- disassembler routines inserted here. */ 25936- 25937- 25938-void openrisc_cgen_print_operand 25939- (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 25940- 25941-/* Main entry point for printing operands. 25942- XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 25943- of dis-asm.h on cgen.h. 25944- 25945- This function is basically just a big switch statement. Earlier versions 25946- used tables to look up the function to use, but 25947- - if the table contains both assembler and disassembler functions then 25948- the disassembler contains much of the assembler and vice-versa, 25949- - there's a lot of inlining possibilities as things grow, 25950- - using a switch statement avoids the function call overhead. 25951- 25952- This function could be moved into `print_insn_normal', but keeping it 25953- separate makes clear the interface between `print_insn_normal' and each of 25954- the handlers. */ 25955- 25956-void 25957-openrisc_cgen_print_operand (CGEN_CPU_DESC cd, 25958- int opindex, 25959- void * xinfo, 25960- CGEN_FIELDS *fields, 25961- void const *attrs ATTRIBUTE_UNUSED, 25962- bfd_vma pc, 25963- int length) 25964-{ 25965- disassemble_info *info = (disassemble_info *) xinfo; 25966- 25967- switch (opindex) 25968- { 25969- case OPENRISC_OPERAND_ABS_26 : 25970- print_address (cd, info, fields->f_abs26, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 25971- break; 25972- case OPENRISC_OPERAND_DISP_26 : 25973- print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 25974- break; 25975- case OPENRISC_OPERAND_HI16 : 25976- print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); 25977- break; 25978- case OPENRISC_OPERAND_LO16 : 25979- print_normal (cd, info, fields->f_lo16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); 25980- break; 25981- case OPENRISC_OPERAND_OP_F_23 : 25982- print_normal (cd, info, fields->f_op4, 0, pc, length); 25983- break; 25984- case OPENRISC_OPERAND_OP_F_3 : 25985- print_normal (cd, info, fields->f_op5, 0, pc, length); 25986- break; 25987- case OPENRISC_OPERAND_RA : 25988- print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0); 25989- break; 25990- case OPENRISC_OPERAND_RB : 25991- print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0); 25992- break; 25993- case OPENRISC_OPERAND_RD : 25994- print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0); 25995- break; 25996- case OPENRISC_OPERAND_SIMM_16 : 25997- print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 25998- break; 25999- case OPENRISC_OPERAND_UI16NC : 26000- print_normal (cd, info, fields->f_i16nc, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 26001- break; 26002- case OPENRISC_OPERAND_UIMM_16 : 26003- print_normal (cd, info, fields->f_uimm16, 0, pc, length); 26004- break; 26005- case OPENRISC_OPERAND_UIMM_5 : 26006- print_normal (cd, info, fields->f_uimm5, 0, pc, length); 26007- break; 26008- 26009- default : 26010- /* xgettext:c-format */ 26011- fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 26012- opindex); 26013- abort (); 26014- } 26015-} 26016- 26017-cgen_print_fn * const openrisc_cgen_print_handlers[] = 26018-{ 26019- print_insn_normal, 26020-}; 26021- 26022- 26023-void 26024-openrisc_cgen_init_dis (CGEN_CPU_DESC cd) 26025-{ 26026- openrisc_cgen_init_opcode_table (cd); 26027- openrisc_cgen_init_ibld_table (cd); 26028- cd->print_handlers = & openrisc_cgen_print_handlers[0]; 26029- cd->print_operand = openrisc_cgen_print_operand; 26030-} 26031- 26032- 26033-/* Default print handler. */ 26034- 26035-static void 26036-print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 26037- void *dis_info, 26038- long value, 26039- unsigned int attrs, 26040- bfd_vma pc ATTRIBUTE_UNUSED, 26041- int length ATTRIBUTE_UNUSED) 26042-{ 26043- disassemble_info *info = (disassemble_info *) dis_info; 26044- 26045- /* Print the operand as directed by the attributes. */ 26046- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 26047- ; /* nothing to do */ 26048- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 26049- (*info->fprintf_func) (info->stream, "%ld", value); 26050- else 26051- (*info->fprintf_func) (info->stream, "0x%lx", value); 26052-} 26053- 26054-/* Default address handler. */ 26055- 26056-static void 26057-print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 26058- void *dis_info, 26059- bfd_vma value, 26060- unsigned int attrs, 26061- bfd_vma pc ATTRIBUTE_UNUSED, 26062- int length ATTRIBUTE_UNUSED) 26063-{ 26064- disassemble_info *info = (disassemble_info *) dis_info; 26065- 26066- /* Print the operand as directed by the attributes. */ 26067- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 26068- ; /* Nothing to do. */ 26069- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 26070- (*info->print_address_func) (value, info); 26071- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 26072- (*info->print_address_func) (value, info); 26073- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 26074- (*info->fprintf_func) (info->stream, "%ld", (long) value); 26075- else 26076- (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 26077-} 26078- 26079-/* Keyword print handler. */ 26080- 26081-static void 26082-print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 26083- void *dis_info, 26084- CGEN_KEYWORD *keyword_table, 26085- long value, 26086- unsigned int attrs ATTRIBUTE_UNUSED) 26087-{ 26088- disassemble_info *info = (disassemble_info *) dis_info; 26089- const CGEN_KEYWORD_ENTRY *ke; 26090- 26091- ke = cgen_keyword_lookup_value (keyword_table, value); 26092- if (ke != NULL) 26093- (*info->fprintf_func) (info->stream, "%s", ke->name); 26094- else 26095- (*info->fprintf_func) (info->stream, "???"); 26096-} 26097- 26098-/* Default insn printer. 26099- 26100- DIS_INFO is defined as `void *' so the disassembler needn't know anything 26101- about disassemble_info. */ 26102- 26103-static void 26104-print_insn_normal (CGEN_CPU_DESC cd, 26105- void *dis_info, 26106- const CGEN_INSN *insn, 26107- CGEN_FIELDS *fields, 26108- bfd_vma pc, 26109- int length) 26110-{ 26111- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 26112- disassemble_info *info = (disassemble_info *) dis_info; 26113- const CGEN_SYNTAX_CHAR_TYPE *syn; 26114- 26115- CGEN_INIT_PRINT (cd); 26116- 26117- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 26118- { 26119- if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 26120- { 26121- (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 26122- continue; 26123- } 26124- if (CGEN_SYNTAX_CHAR_P (*syn)) 26125- { 26126- (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 26127- continue; 26128- } 26129- 26130- /* We have an operand. */ 26131- openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 26132- fields, CGEN_INSN_ATTRS (insn), pc, length); 26133- } 26134-} 26135- 26136-/* Subroutine of print_insn. Reads an insn into the given buffers and updates 26137- the extract info. 26138- Returns 0 if all is well, non-zero otherwise. */ 26139- 26140-static int 26141-read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 26142- bfd_vma pc, 26143- disassemble_info *info, 26144- bfd_byte *buf, 26145- int buflen, 26146- CGEN_EXTRACT_INFO *ex_info, 26147- unsigned long *insn_value) 26148-{ 26149- int status = (*info->read_memory_func) (pc, buf, buflen, info); 26150- 26151- if (status != 0) 26152- { 26153- (*info->memory_error_func) (status, pc, info); 26154- return -1; 26155- } 26156- 26157- ex_info->dis_info = info; 26158- ex_info->valid = (1 << buflen) - 1; 26159- ex_info->insn_bytes = buf; 26160- 26161- *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 26162- return 0; 26163-} 26164- 26165-/* Utility to print an insn. 26166- BUF is the base part of the insn, target byte order, BUFLEN bytes long. 26167- The result is the size of the insn in bytes or zero for an unknown insn 26168- or -1 if an error occurs fetching data (memory_error_func will have 26169- been called). */ 26170- 26171-static int 26172-print_insn (CGEN_CPU_DESC cd, 26173- bfd_vma pc, 26174- disassemble_info *info, 26175- bfd_byte *buf, 26176- unsigned int buflen) 26177-{ 26178- CGEN_INSN_INT insn_value; 26179- const CGEN_INSN_LIST *insn_list; 26180- CGEN_EXTRACT_INFO ex_info; 26181- int basesize; 26182- 26183- /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 26184- basesize = cd->base_insn_bitsize < buflen * 8 ? 26185- cd->base_insn_bitsize : buflen * 8; 26186- insn_value = cgen_get_insn_value (cd, buf, basesize); 26187- 26188- 26189- /* Fill in ex_info fields like read_insn would. Don't actually call 26190- read_insn, since the incoming buffer is already read (and possibly 26191- modified a la m32r). */ 26192- ex_info.valid = (1 << buflen) - 1; 26193- ex_info.dis_info = info; 26194- ex_info.insn_bytes = buf; 26195- 26196- /* The instructions are stored in hash lists. 26197- Pick the first one and keep trying until we find the right one. */ 26198- 26199- insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 26200- while (insn_list != NULL) 26201- { 26202- const CGEN_INSN *insn = insn_list->insn; 26203- CGEN_FIELDS fields; 26204- int length; 26205- unsigned long insn_value_cropped; 26206- 26207-#ifdef CGEN_VALIDATE_INSN_SUPPORTED 26208- /* Not needed as insn shouldn't be in hash lists if not supported. */ 26209- /* Supported by this cpu? */ 26210- if (! openrisc_cgen_insn_supported (cd, insn)) 26211- { 26212- insn_list = CGEN_DIS_NEXT_INSN (insn_list); 26213- continue; 26214- } 26215-#endif 26216- 26217- /* Basic bit mask must be correct. */ 26218- /* ??? May wish to allow target to defer this check until the extract 26219- handler. */ 26220- 26221- /* Base size may exceed this instruction's size. Extract the 26222- relevant part from the buffer. */ 26223- if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 26224- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 26225- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 26226- info->endian == BFD_ENDIAN_BIG); 26227- else 26228- insn_value_cropped = insn_value; 26229- 26230- if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 26231- == CGEN_INSN_BASE_VALUE (insn)) 26232- { 26233- /* Printing is handled in two passes. The first pass parses the 26234- machine insn and extracts the fields. The second pass prints 26235- them. */ 26236- 26237- /* Make sure the entire insn is loaded into insn_value, if it 26238- can fit. */ 26239- if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 26240- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 26241- { 26242- unsigned long full_insn_value; 26243- int rc = read_insn (cd, pc, info, buf, 26244- CGEN_INSN_BITSIZE (insn) / 8, 26245- & ex_info, & full_insn_value); 26246- if (rc != 0) 26247- return rc; 26248- length = CGEN_EXTRACT_FN (cd, insn) 26249- (cd, insn, &ex_info, full_insn_value, &fields, pc); 26250- } 26251- else 26252- length = CGEN_EXTRACT_FN (cd, insn) 26253- (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 26254- 26255- /* Length < 0 -> error. */ 26256- if (length < 0) 26257- return length; 26258- if (length > 0) 26259- { 26260- CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 26261- /* Length is in bits, result is in bytes. */ 26262- return length / 8; 26263- } 26264- } 26265- 26266- insn_list = CGEN_DIS_NEXT_INSN (insn_list); 26267- } 26268- 26269- return 0; 26270-} 26271- 26272-/* Default value for CGEN_PRINT_INSN. 26273- The result is the size of the insn in bytes or zero for an unknown insn 26274- or -1 if an error occured fetching bytes. */ 26275- 26276-#ifndef CGEN_PRINT_INSN 26277-#define CGEN_PRINT_INSN default_print_insn 26278-#endif 26279- 26280-static int 26281-default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 26282-{ 26283- bfd_byte buf[CGEN_MAX_INSN_SIZE]; 26284- int buflen; 26285- int status; 26286- 26287- /* Attempt to read the base part of the insn. */ 26288- buflen = cd->base_insn_bitsize / 8; 26289- status = (*info->read_memory_func) (pc, buf, buflen, info); 26290- 26291- /* Try again with the minimum part, if min < base. */ 26292- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 26293- { 26294- buflen = cd->min_insn_bitsize / 8; 26295- status = (*info->read_memory_func) (pc, buf, buflen, info); 26296- } 26297- 26298- if (status != 0) 26299- { 26300- (*info->memory_error_func) (status, pc, info); 26301- return -1; 26302- } 26303- 26304- return print_insn (cd, pc, info, buf, buflen); 26305-} 26306- 26307-/* Main entry point. 26308- Print one instruction from PC on INFO->STREAM. 26309- Return the size of the instruction (in bytes). */ 26310- 26311-typedef struct cpu_desc_list 26312-{ 26313- struct cpu_desc_list *next; 26314- CGEN_BITSET *isa; 26315- int mach; 26316- int endian; 26317- CGEN_CPU_DESC cd; 26318-} cpu_desc_list; 26319- 26320-int 26321-print_insn_openrisc (bfd_vma pc, disassemble_info *info) 26322-{ 26323- static cpu_desc_list *cd_list = 0; 26324- cpu_desc_list *cl = 0; 26325- static CGEN_CPU_DESC cd = 0; 26326- static CGEN_BITSET *prev_isa; 26327- static int prev_mach; 26328- static int prev_endian; 26329- int length; 26330- CGEN_BITSET *isa; 26331- int mach; 26332- int endian = (info->endian == BFD_ENDIAN_BIG 26333- ? CGEN_ENDIAN_BIG 26334- : CGEN_ENDIAN_LITTLE); 26335- enum bfd_architecture arch; 26336- 26337- /* ??? gdb will set mach but leave the architecture as "unknown" */ 26338-#ifndef CGEN_BFD_ARCH 26339-#define CGEN_BFD_ARCH bfd_arch_openrisc 26340-#endif 26341- arch = info->arch; 26342- if (arch == bfd_arch_unknown) 26343- arch = CGEN_BFD_ARCH; 26344- 26345- /* There's no standard way to compute the machine or isa number 26346- so we leave it to the target. */ 26347-#ifdef CGEN_COMPUTE_MACH 26348- mach = CGEN_COMPUTE_MACH (info); 26349-#else 26350- mach = info->mach; 26351-#endif 26352- 26353-#ifdef CGEN_COMPUTE_ISA 26354- { 26355- static CGEN_BITSET *permanent_isa; 26356- 26357- if (!permanent_isa) 26358- permanent_isa = cgen_bitset_create (MAX_ISAS); 26359- isa = permanent_isa; 26360- cgen_bitset_clear (isa); 26361- cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 26362- } 26363-#else 26364- isa = info->insn_sets; 26365-#endif 26366- 26367- /* If we've switched cpu's, try to find a handle we've used before */ 26368- if (cd 26369- && (cgen_bitset_compare (isa, prev_isa) != 0 26370- || mach != prev_mach 26371- || endian != prev_endian)) 26372- { 26373- cd = 0; 26374- for (cl = cd_list; cl; cl = cl->next) 26375- { 26376- if (cgen_bitset_compare (cl->isa, isa) == 0 && 26377- cl->mach == mach && 26378- cl->endian == endian) 26379- { 26380- cd = cl->cd; 26381- prev_isa = cd->isas; 26382- break; 26383- } 26384- } 26385- } 26386- 26387- /* If we haven't initialized yet, initialize the opcode table. */ 26388- if (! cd) 26389- { 26390- const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 26391- const char *mach_name; 26392- 26393- if (!arch_type) 26394- abort (); 26395- mach_name = arch_type->printable_name; 26396- 26397- prev_isa = cgen_bitset_copy (isa); 26398- prev_mach = mach; 26399- prev_endian = endian; 26400- cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 26401- CGEN_CPU_OPEN_BFDMACH, mach_name, 26402- CGEN_CPU_OPEN_ENDIAN, prev_endian, 26403- CGEN_CPU_OPEN_END); 26404- if (!cd) 26405- abort (); 26406- 26407- /* Save this away for future reference. */ 26408- cl = xmalloc (sizeof (struct cpu_desc_list)); 26409- cl->cd = cd; 26410- cl->isa = prev_isa; 26411- cl->mach = mach; 26412- cl->endian = endian; 26413- cl->next = cd_list; 26414- cd_list = cl; 26415- 26416- openrisc_cgen_init_dis (cd); 26417- } 26418- 26419- /* We try to have as much common code as possible. 26420- But at this point some targets need to take over. */ 26421- /* ??? Some targets may need a hook elsewhere. Try to avoid this, 26422- but if not possible try to move this hook elsewhere rather than 26423- have two hooks. */ 26424- length = CGEN_PRINT_INSN (cd, pc, info); 26425- if (length > 0) 26426- return length; 26427- if (length < 0) 26428- return -1; 26429- 26430- (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 26431- return cd->default_insn_bitsize / 8; 26432-} 26433diff -rNU3 dist.orig/opcodes/openrisc-ibld.c dist/opcodes/openrisc-ibld.c 26434--- dist.orig/opcodes/openrisc-ibld.c 2010-01-07 19:05:45.000000000 +0100 26435+++ dist/opcodes/openrisc-ibld.c 1970-01-01 01:00:00.000000000 +0100 26436@@ -1,1009 +0,0 @@ 26437-/* Instruction building/extraction support for openrisc. -*- C -*- 26438- 26439- THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 26440- - the resultant file is machine generated, cgen-ibld.in isn't 26441- 26442- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, 26443- 2008, 2010 Free Software Foundation, Inc. 26444- 26445- This file is part of libopcodes. 26446- 26447- This library is free software; you can redistribute it and/or modify 26448- it under the terms of the GNU General Public License as published by 26449- the Free Software Foundation; either version 3, or (at your option) 26450- any later version. 26451- 26452- It is distributed in the hope that it will be useful, but WITHOUT 26453- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 26454- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 26455- License for more details. 26456- 26457- You should have received a copy of the GNU General Public License 26458- along with this program; if not, write to the Free Software Foundation, Inc., 26459- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 26460- 26461-/* ??? Eventually more and more of this stuff can go to cpu-independent files. 26462- Keep that in mind. */ 26463- 26464-#include "sysdep.h" 26465-#include <stdio.h> 26466-#include "ansidecl.h" 26467-#include "dis-asm.h" 26468-#include "bfd.h" 26469-#include "symcat.h" 26470-#include "openrisc-desc.h" 26471-#include "openrisc-opc.h" 26472-#include "cgen/basic-modes.h" 26473-#include "opintl.h" 26474-#include "safe-ctype.h" 26475- 26476-#undef min 26477-#define min(a,b) ((a) < (b) ? (a) : (b)) 26478-#undef max 26479-#define max(a,b) ((a) > (b) ? (a) : (b)) 26480- 26481-/* Used by the ifield rtx function. */ 26482-#define FLD(f) (fields->f) 26483- 26484-static const char * insert_normal 26485- (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 26486- unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 26487-static const char * insert_insn_normal 26488- (CGEN_CPU_DESC, const CGEN_INSN *, 26489- CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 26490-static int extract_normal 26491- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 26492- unsigned int, unsigned int, unsigned int, unsigned int, 26493- unsigned int, unsigned int, bfd_vma, long *); 26494-static int extract_insn_normal 26495- (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 26496- CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 26497-#if CGEN_INT_INSN_P 26498-static void put_insn_int_value 26499- (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 26500-#endif 26501-#if ! CGEN_INT_INSN_P 26502-static CGEN_INLINE void insert_1 26503- (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 26504-static CGEN_INLINE int fill_cache 26505- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 26506-static CGEN_INLINE long extract_1 26507- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 26508-#endif 26509- 26510-/* Operand insertion. */ 26511- 26512-#if ! CGEN_INT_INSN_P 26513- 26514-/* Subroutine of insert_normal. */ 26515- 26516-static CGEN_INLINE void 26517-insert_1 (CGEN_CPU_DESC cd, 26518- unsigned long value, 26519- int start, 26520- int length, 26521- int word_length, 26522- unsigned char *bufp) 26523-{ 26524- unsigned long x,mask; 26525- int shift; 26526- 26527- x = cgen_get_insn_value (cd, bufp, word_length); 26528- 26529- /* Written this way to avoid undefined behaviour. */ 26530- mask = (((1L << (length - 1)) - 1) << 1) | 1; 26531- if (CGEN_INSN_LSB0_P) 26532- shift = (start + 1) - length; 26533- else 26534- shift = (word_length - (start + length)); 26535- x = (x & ~(mask << shift)) | ((value & mask) << shift); 26536- 26537- cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 26538-} 26539- 26540-#endif /* ! CGEN_INT_INSN_P */ 26541- 26542-/* Default insertion routine. 26543- 26544- ATTRS is a mask of the boolean attributes. 26545- WORD_OFFSET is the offset in bits from the start of the insn of the value. 26546- WORD_LENGTH is the length of the word in bits in which the value resides. 26547- START is the starting bit number in the word, architecture origin. 26548- LENGTH is the length of VALUE in bits. 26549- TOTAL_LENGTH is the total length of the insn in bits. 26550- 26551- The result is an error message or NULL if success. */ 26552- 26553-/* ??? This duplicates functionality with bfd's howto table and 26554- bfd_install_relocation. */ 26555-/* ??? This doesn't handle bfd_vma's. Create another function when 26556- necessary. */ 26557- 26558-static const char * 26559-insert_normal (CGEN_CPU_DESC cd, 26560- long value, 26561- unsigned int attrs, 26562- unsigned int word_offset, 26563- unsigned int start, 26564- unsigned int length, 26565- unsigned int word_length, 26566- unsigned int total_length, 26567- CGEN_INSN_BYTES_PTR buffer) 26568-{ 26569- static char errbuf[100]; 26570- /* Written this way to avoid undefined behaviour. */ 26571- unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 26572- 26573- /* If LENGTH is zero, this operand doesn't contribute to the value. */ 26574- if (length == 0) 26575- return NULL; 26576- 26577- if (word_length > 8 * sizeof (CGEN_INSN_INT)) 26578- abort (); 26579- 26580- /* For architectures with insns smaller than the base-insn-bitsize, 26581- word_length may be too big. */ 26582- if (cd->min_insn_bitsize < cd->base_insn_bitsize) 26583- { 26584- if (word_offset == 0 26585- && word_length > total_length) 26586- word_length = total_length; 26587- } 26588- 26589- /* Ensure VALUE will fit. */ 26590- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 26591- { 26592- long minval = - (1L << (length - 1)); 26593- unsigned long maxval = mask; 26594- 26595- if ((value > 0 && (unsigned long) value > maxval) 26596- || value < minval) 26597- { 26598- /* xgettext:c-format */ 26599- sprintf (errbuf, 26600- _("operand out of range (%ld not between %ld and %lu)"), 26601- value, minval, maxval); 26602- return errbuf; 26603- } 26604- } 26605- else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 26606- { 26607- unsigned long maxval = mask; 26608- unsigned long val = (unsigned long) value; 26609- 26610- /* For hosts with a word size > 32 check to see if value has been sign 26611- extended beyond 32 bits. If so then ignore these higher sign bits 26612- as the user is attempting to store a 32-bit signed value into an 26613- unsigned 32-bit field which is allowed. */ 26614- if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 26615- val &= 0xFFFFFFFF; 26616- 26617- if (val > maxval) 26618- { 26619- /* xgettext:c-format */ 26620- sprintf (errbuf, 26621- _("operand out of range (0x%lx not between 0 and 0x%lx)"), 26622- val, maxval); 26623- return errbuf; 26624- } 26625- } 26626- else 26627- { 26628- if (! cgen_signed_overflow_ok_p (cd)) 26629- { 26630- long minval = - (1L << (length - 1)); 26631- long maxval = (1L << (length - 1)) - 1; 26632- 26633- if (value < minval || value > maxval) 26634- { 26635- sprintf 26636- /* xgettext:c-format */ 26637- (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 26638- value, minval, maxval); 26639- return errbuf; 26640- } 26641- } 26642- } 26643- 26644-#if CGEN_INT_INSN_P 26645- 26646- { 26647- int shift; 26648- 26649- if (CGEN_INSN_LSB0_P) 26650- shift = (word_offset + start + 1) - length; 26651- else 26652- shift = total_length - (word_offset + start + length); 26653- *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 26654- } 26655- 26656-#else /* ! CGEN_INT_INSN_P */ 26657- 26658- { 26659- unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 26660- 26661- insert_1 (cd, value, start, length, word_length, bufp); 26662- } 26663- 26664-#endif /* ! CGEN_INT_INSN_P */ 26665- 26666- return NULL; 26667-} 26668- 26669-/* Default insn builder (insert handler). 26670- The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 26671- that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 26672- recorded in host byte order, otherwise BUFFER is an array of bytes 26673- and the value is recorded in target byte order). 26674- The result is an error message or NULL if success. */ 26675- 26676-static const char * 26677-insert_insn_normal (CGEN_CPU_DESC cd, 26678- const CGEN_INSN * insn, 26679- CGEN_FIELDS * fields, 26680- CGEN_INSN_BYTES_PTR buffer, 26681- bfd_vma pc) 26682-{ 26683- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 26684- unsigned long value; 26685- const CGEN_SYNTAX_CHAR_TYPE * syn; 26686- 26687- CGEN_INIT_INSERT (cd); 26688- value = CGEN_INSN_BASE_VALUE (insn); 26689- 26690- /* If we're recording insns as numbers (rather than a string of bytes), 26691- target byte order handling is deferred until later. */ 26692- 26693-#if CGEN_INT_INSN_P 26694- 26695- put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 26696- CGEN_FIELDS_BITSIZE (fields), value); 26697- 26698-#else 26699- 26700- cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 26701- (unsigned) CGEN_FIELDS_BITSIZE (fields)), 26702- value); 26703- 26704-#endif /* ! CGEN_INT_INSN_P */ 26705- 26706- /* ??? It would be better to scan the format's fields. 26707- Still need to be able to insert a value based on the operand though; 26708- e.g. storing a branch displacement that got resolved later. 26709- Needs more thought first. */ 26710- 26711- for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 26712- { 26713- const char *errmsg; 26714- 26715- if (CGEN_SYNTAX_CHAR_P (* syn)) 26716- continue; 26717- 26718- errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 26719- fields, buffer, pc); 26720- if (errmsg) 26721- return errmsg; 26722- } 26723- 26724- return NULL; 26725-} 26726- 26727-#if CGEN_INT_INSN_P 26728-/* Cover function to store an insn value into an integral insn. Must go here 26729- because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 26730- 26731-static void 26732-put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 26733- CGEN_INSN_BYTES_PTR buf, 26734- int length, 26735- int insn_length, 26736- CGEN_INSN_INT value) 26737-{ 26738- /* For architectures with insns smaller than the base-insn-bitsize, 26739- length may be too big. */ 26740- if (length > insn_length) 26741- *buf = value; 26742- else 26743- { 26744- int shift = insn_length - length; 26745- /* Written this way to avoid undefined behaviour. */ 26746- CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 26747- 26748- *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 26749- } 26750-} 26751-#endif 26752- 26753-/* Operand extraction. */ 26754- 26755-#if ! CGEN_INT_INSN_P 26756- 26757-/* Subroutine of extract_normal. 26758- Ensure sufficient bytes are cached in EX_INFO. 26759- OFFSET is the offset in bytes from the start of the insn of the value. 26760- BYTES is the length of the needed value. 26761- Returns 1 for success, 0 for failure. */ 26762- 26763-static CGEN_INLINE int 26764-fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 26765- CGEN_EXTRACT_INFO *ex_info, 26766- int offset, 26767- int bytes, 26768- bfd_vma pc) 26769-{ 26770- /* It's doubtful that the middle part has already been fetched so 26771- we don't optimize that case. kiss. */ 26772- unsigned int mask; 26773- disassemble_info *info = (disassemble_info *) ex_info->dis_info; 26774- 26775- /* First do a quick check. */ 26776- mask = (1 << bytes) - 1; 26777- if (((ex_info->valid >> offset) & mask) == mask) 26778- return 1; 26779- 26780- /* Search for the first byte we need to read. */ 26781- for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 26782- if (! (mask & ex_info->valid)) 26783- break; 26784- 26785- if (bytes) 26786- { 26787- int status; 26788- 26789- pc += offset; 26790- status = (*info->read_memory_func) 26791- (pc, ex_info->insn_bytes + offset, bytes, info); 26792- 26793- if (status != 0) 26794- { 26795- (*info->memory_error_func) (status, pc, info); 26796- return 0; 26797- } 26798- 26799- ex_info->valid |= ((1 << bytes) - 1) << offset; 26800- } 26801- 26802- return 1; 26803-} 26804- 26805-/* Subroutine of extract_normal. */ 26806- 26807-static CGEN_INLINE long 26808-extract_1 (CGEN_CPU_DESC cd, 26809- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 26810- int start, 26811- int length, 26812- int word_length, 26813- unsigned char *bufp, 26814- bfd_vma pc ATTRIBUTE_UNUSED) 26815-{ 26816- unsigned long x; 26817- int shift; 26818- 26819- x = cgen_get_insn_value (cd, bufp, word_length); 26820- 26821- if (CGEN_INSN_LSB0_P) 26822- shift = (start + 1) - length; 26823- else 26824- shift = (word_length - (start + length)); 26825- return x >> shift; 26826-} 26827- 26828-#endif /* ! CGEN_INT_INSN_P */ 26829- 26830-/* Default extraction routine. 26831- 26832- INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 26833- or sometimes less for cases like the m32r where the base insn size is 32 26834- but some insns are 16 bits. 26835- ATTRS is a mask of the boolean attributes. We only need `SIGNED', 26836- but for generality we take a bitmask of all of them. 26837- WORD_OFFSET is the offset in bits from the start of the insn of the value. 26838- WORD_LENGTH is the length of the word in bits in which the value resides. 26839- START is the starting bit number in the word, architecture origin. 26840- LENGTH is the length of VALUE in bits. 26841- TOTAL_LENGTH is the total length of the insn in bits. 26842- 26843- Returns 1 for success, 0 for failure. */ 26844- 26845-/* ??? The return code isn't properly used. wip. */ 26846- 26847-/* ??? This doesn't handle bfd_vma's. Create another function when 26848- necessary. */ 26849- 26850-static int 26851-extract_normal (CGEN_CPU_DESC cd, 26852-#if ! CGEN_INT_INSN_P 26853- CGEN_EXTRACT_INFO *ex_info, 26854-#else 26855- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 26856-#endif 26857- CGEN_INSN_INT insn_value, 26858- unsigned int attrs, 26859- unsigned int word_offset, 26860- unsigned int start, 26861- unsigned int length, 26862- unsigned int word_length, 26863- unsigned int total_length, 26864-#if ! CGEN_INT_INSN_P 26865- bfd_vma pc, 26866-#else 26867- bfd_vma pc ATTRIBUTE_UNUSED, 26868-#endif 26869- long *valuep) 26870-{ 26871- long value, mask; 26872- 26873- /* If LENGTH is zero, this operand doesn't contribute to the value 26874- so give it a standard value of zero. */ 26875- if (length == 0) 26876- { 26877- *valuep = 0; 26878- return 1; 26879- } 26880- 26881- if (word_length > 8 * sizeof (CGEN_INSN_INT)) 26882- abort (); 26883- 26884- /* For architectures with insns smaller than the insn-base-bitsize, 26885- word_length may be too big. */ 26886- if (cd->min_insn_bitsize < cd->base_insn_bitsize) 26887- { 26888- if (word_offset + word_length > total_length) 26889- word_length = total_length - word_offset; 26890- } 26891- 26892- /* Does the value reside in INSN_VALUE, and at the right alignment? */ 26893- 26894- if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 26895- { 26896- if (CGEN_INSN_LSB0_P) 26897- value = insn_value >> ((word_offset + start + 1) - length); 26898- else 26899- value = insn_value >> (total_length - ( word_offset + start + length)); 26900- } 26901- 26902-#if ! CGEN_INT_INSN_P 26903- 26904- else 26905- { 26906- unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 26907- 26908- if (word_length > 8 * sizeof (CGEN_INSN_INT)) 26909- abort (); 26910- 26911- if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 26912- return 0; 26913- 26914- value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 26915- } 26916- 26917-#endif /* ! CGEN_INT_INSN_P */ 26918- 26919- /* Written this way to avoid undefined behaviour. */ 26920- mask = (((1L << (length - 1)) - 1) << 1) | 1; 26921- 26922- value &= mask; 26923- /* sign extend? */ 26924- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 26925- && (value & (1L << (length - 1)))) 26926- value |= ~mask; 26927- 26928- *valuep = value; 26929- 26930- return 1; 26931-} 26932- 26933-/* Default insn extractor. 26934- 26935- INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 26936- The extracted fields are stored in FIELDS. 26937- EX_INFO is used to handle reading variable length insns. 26938- Return the length of the insn in bits, or 0 if no match, 26939- or -1 if an error occurs fetching data (memory_error_func will have 26940- been called). */ 26941- 26942-static int 26943-extract_insn_normal (CGEN_CPU_DESC cd, 26944- const CGEN_INSN *insn, 26945- CGEN_EXTRACT_INFO *ex_info, 26946- CGEN_INSN_INT insn_value, 26947- CGEN_FIELDS *fields, 26948- bfd_vma pc) 26949-{ 26950- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 26951- const CGEN_SYNTAX_CHAR_TYPE *syn; 26952- 26953- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 26954- 26955- CGEN_INIT_EXTRACT (cd); 26956- 26957- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 26958- { 26959- int length; 26960- 26961- if (CGEN_SYNTAX_CHAR_P (*syn)) 26962- continue; 26963- 26964- length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 26965- ex_info, insn_value, fields, pc); 26966- if (length <= 0) 26967- return length; 26968- } 26969- 26970- /* We recognized and successfully extracted this insn. */ 26971- return CGEN_INSN_BITSIZE (insn); 26972-} 26973- 26974-/* Machine generated code added here. */ 26975- 26976-const char * openrisc_cgen_insert_operand 26977- (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 26978- 26979-/* Main entry point for operand insertion. 26980- 26981- This function is basically just a big switch statement. Earlier versions 26982- used tables to look up the function to use, but 26983- - if the table contains both assembler and disassembler functions then 26984- the disassembler contains much of the assembler and vice-versa, 26985- - there's a lot of inlining possibilities as things grow, 26986- - using a switch statement avoids the function call overhead. 26987- 26988- This function could be moved into `parse_insn_normal', but keeping it 26989- separate makes clear the interface between `parse_insn_normal' and each of 26990- the handlers. It's also needed by GAS to insert operands that couldn't be 26991- resolved during parsing. */ 26992- 26993-const char * 26994-openrisc_cgen_insert_operand (CGEN_CPU_DESC cd, 26995- int opindex, 26996- CGEN_FIELDS * fields, 26997- CGEN_INSN_BYTES_PTR buffer, 26998- bfd_vma pc ATTRIBUTE_UNUSED) 26999-{ 27000- const char * errmsg = NULL; 27001- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 27002- 27003- switch (opindex) 27004- { 27005- case OPENRISC_OPERAND_ABS_26 : 27006- { 27007- long value = fields->f_abs26; 27008- value = ((SI) (pc) >> (2)); 27009- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, buffer); 27010- } 27011- break; 27012- case OPENRISC_OPERAND_DISP_26 : 27013- { 27014- long value = fields->f_disp26; 27015- value = ((SI) (((value) - (pc))) >> (2)); 27016- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); 27017- } 27018- break; 27019- case OPENRISC_OPERAND_HI16 : 27020- errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); 27021- break; 27022- case OPENRISC_OPERAND_LO16 : 27023- errmsg = insert_normal (cd, fields->f_lo16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); 27024- break; 27025- case OPENRISC_OPERAND_OP_F_23 : 27026- errmsg = insert_normal (cd, fields->f_op4, 0, 0, 23, 3, 32, total_length, buffer); 27027- break; 27028- case OPENRISC_OPERAND_OP_F_3 : 27029- errmsg = insert_normal (cd, fields->f_op5, 0, 0, 25, 5, 32, total_length, buffer); 27030- break; 27031- case OPENRISC_OPERAND_RA : 27032- errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 27033- break; 27034- case OPENRISC_OPERAND_RB : 27035- errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 27036- break; 27037- case OPENRISC_OPERAND_RD : 27038- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 27039- break; 27040- case OPENRISC_OPERAND_SIMM_16 : 27041- errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); 27042- break; 27043- case OPENRISC_OPERAND_UI16NC : 27044- { 27045-{ 27046- FLD (f_i16_2) = ((((HI) (FLD (f_i16nc)) >> (11))) & (31)); 27047- FLD (f_i16_1) = ((FLD (f_i16nc)) & (2047)); 27048-} 27049- errmsg = insert_normal (cd, fields->f_i16_1, 0, 0, 10, 11, 32, total_length, buffer); 27050- if (errmsg) 27051- break; 27052- errmsg = insert_normal (cd, fields->f_i16_2, 0, 0, 25, 5, 32, total_length, buffer); 27053- if (errmsg) 27054- break; 27055- } 27056- break; 27057- case OPENRISC_OPERAND_UIMM_16 : 27058- errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); 27059- break; 27060- case OPENRISC_OPERAND_UIMM_5 : 27061- errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 4, 5, 32, total_length, buffer); 27062- break; 27063- 27064- default : 27065- /* xgettext:c-format */ 27066- fprintf (stderr, _("Unrecognized field %d while building insn.\n"), 27067- opindex); 27068- abort (); 27069- } 27070- 27071- return errmsg; 27072-} 27073- 27074-int openrisc_cgen_extract_operand 27075- (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 27076- 27077-/* Main entry point for operand extraction. 27078- The result is <= 0 for error, >0 for success. 27079- ??? Actual values aren't well defined right now. 27080- 27081- This function is basically just a big switch statement. Earlier versions 27082- used tables to look up the function to use, but 27083- - if the table contains both assembler and disassembler functions then 27084- the disassembler contains much of the assembler and vice-versa, 27085- - there's a lot of inlining possibilities as things grow, 27086- - using a switch statement avoids the function call overhead. 27087- 27088- This function could be moved into `print_insn_normal', but keeping it 27089- separate makes clear the interface between `print_insn_normal' and each of 27090- the handlers. */ 27091- 27092-int 27093-openrisc_cgen_extract_operand (CGEN_CPU_DESC cd, 27094- int opindex, 27095- CGEN_EXTRACT_INFO *ex_info, 27096- CGEN_INSN_INT insn_value, 27097- CGEN_FIELDS * fields, 27098- bfd_vma pc) 27099-{ 27100- /* Assume success (for those operands that are nops). */ 27101- int length = 1; 27102- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 27103- 27104- switch (opindex) 27105- { 27106- case OPENRISC_OPERAND_ABS_26 : 27107- { 27108- long value; 27109- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, pc, & value); 27110- value = ((value) << (2)); 27111- fields->f_abs26 = value; 27112- } 27113- break; 27114- case OPENRISC_OPERAND_DISP_26 : 27115- { 27116- long value; 27117- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); 27118- value = ((((value) << (2))) + (pc)); 27119- fields->f_disp26 = value; 27120- } 27121- break; 27122- case OPENRISC_OPERAND_HI16 : 27123- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); 27124- break; 27125- case OPENRISC_OPERAND_LO16 : 27126- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_lo16); 27127- break; 27128- case OPENRISC_OPERAND_OP_F_23 : 27129- length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_op4); 27130- break; 27131- case OPENRISC_OPERAND_OP_F_3 : 27132- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_op5); 27133- break; 27134- case OPENRISC_OPERAND_RA : 27135- length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 27136- break; 27137- case OPENRISC_OPERAND_RB : 27138- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 27139- break; 27140- case OPENRISC_OPERAND_RD : 27141- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 27142- break; 27143- case OPENRISC_OPERAND_SIMM_16 : 27144- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); 27145- break; 27146- case OPENRISC_OPERAND_UI16NC : 27147- { 27148- length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_i16_1); 27149- if (length <= 0) break; 27150- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2); 27151- if (length <= 0) break; 27152-{ 27153- FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1)))); 27154-} 27155- } 27156- break; 27157- case OPENRISC_OPERAND_UIMM_16 : 27158- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); 27159- break; 27160- case OPENRISC_OPERAND_UIMM_5 : 27161- length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_uimm5); 27162- break; 27163- 27164- default : 27165- /* xgettext:c-format */ 27166- fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), 27167- opindex); 27168- abort (); 27169- } 27170- 27171- return length; 27172-} 27173- 27174-cgen_insert_fn * const openrisc_cgen_insert_handlers[] = 27175-{ 27176- insert_insn_normal, 27177-}; 27178- 27179-cgen_extract_fn * const openrisc_cgen_extract_handlers[] = 27180-{ 27181- extract_insn_normal, 27182-}; 27183- 27184-int openrisc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 27185-bfd_vma openrisc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 27186- 27187-/* Getting values from cgen_fields is handled by a collection of functions. 27188- They are distinguished by the type of the VALUE argument they return. 27189- TODO: floating point, inlining support, remove cases where result type 27190- not appropriate. */ 27191- 27192-int 27193-openrisc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 27194- int opindex, 27195- const CGEN_FIELDS * fields) 27196-{ 27197- int value; 27198- 27199- switch (opindex) 27200- { 27201- case OPENRISC_OPERAND_ABS_26 : 27202- value = fields->f_abs26; 27203- break; 27204- case OPENRISC_OPERAND_DISP_26 : 27205- value = fields->f_disp26; 27206- break; 27207- case OPENRISC_OPERAND_HI16 : 27208- value = fields->f_simm16; 27209- break; 27210- case OPENRISC_OPERAND_LO16 : 27211- value = fields->f_lo16; 27212- break; 27213- case OPENRISC_OPERAND_OP_F_23 : 27214- value = fields->f_op4; 27215- break; 27216- case OPENRISC_OPERAND_OP_F_3 : 27217- value = fields->f_op5; 27218- break; 27219- case OPENRISC_OPERAND_RA : 27220- value = fields->f_r2; 27221- break; 27222- case OPENRISC_OPERAND_RB : 27223- value = fields->f_r3; 27224- break; 27225- case OPENRISC_OPERAND_RD : 27226- value = fields->f_r1; 27227- break; 27228- case OPENRISC_OPERAND_SIMM_16 : 27229- value = fields->f_simm16; 27230- break; 27231- case OPENRISC_OPERAND_UI16NC : 27232- value = fields->f_i16nc; 27233- break; 27234- case OPENRISC_OPERAND_UIMM_16 : 27235- value = fields->f_uimm16; 27236- break; 27237- case OPENRISC_OPERAND_UIMM_5 : 27238- value = fields->f_uimm5; 27239- break; 27240- 27241- default : 27242- /* xgettext:c-format */ 27243- fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), 27244- opindex); 27245- abort (); 27246- } 27247- 27248- return value; 27249-} 27250- 27251-bfd_vma 27252-openrisc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 27253- int opindex, 27254- const CGEN_FIELDS * fields) 27255-{ 27256- bfd_vma value; 27257- 27258- switch (opindex) 27259- { 27260- case OPENRISC_OPERAND_ABS_26 : 27261- value = fields->f_abs26; 27262- break; 27263- case OPENRISC_OPERAND_DISP_26 : 27264- value = fields->f_disp26; 27265- break; 27266- case OPENRISC_OPERAND_HI16 : 27267- value = fields->f_simm16; 27268- break; 27269- case OPENRISC_OPERAND_LO16 : 27270- value = fields->f_lo16; 27271- break; 27272- case OPENRISC_OPERAND_OP_F_23 : 27273- value = fields->f_op4; 27274- break; 27275- case OPENRISC_OPERAND_OP_F_3 : 27276- value = fields->f_op5; 27277- break; 27278- case OPENRISC_OPERAND_RA : 27279- value = fields->f_r2; 27280- break; 27281- case OPENRISC_OPERAND_RB : 27282- value = fields->f_r3; 27283- break; 27284- case OPENRISC_OPERAND_RD : 27285- value = fields->f_r1; 27286- break; 27287- case OPENRISC_OPERAND_SIMM_16 : 27288- value = fields->f_simm16; 27289- break; 27290- case OPENRISC_OPERAND_UI16NC : 27291- value = fields->f_i16nc; 27292- break; 27293- case OPENRISC_OPERAND_UIMM_16 : 27294- value = fields->f_uimm16; 27295- break; 27296- case OPENRISC_OPERAND_UIMM_5 : 27297- value = fields->f_uimm5; 27298- break; 27299- 27300- default : 27301- /* xgettext:c-format */ 27302- fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), 27303- opindex); 27304- abort (); 27305- } 27306- 27307- return value; 27308-} 27309- 27310-void openrisc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 27311-void openrisc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 27312- 27313-/* Stuffing values in cgen_fields is handled by a collection of functions. 27314- They are distinguished by the type of the VALUE argument they accept. 27315- TODO: floating point, inlining support, remove cases where argument type 27316- not appropriate. */ 27317- 27318-void 27319-openrisc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 27320- int opindex, 27321- CGEN_FIELDS * fields, 27322- int value) 27323-{ 27324- switch (opindex) 27325- { 27326- case OPENRISC_OPERAND_ABS_26 : 27327- fields->f_abs26 = value; 27328- break; 27329- case OPENRISC_OPERAND_DISP_26 : 27330- fields->f_disp26 = value; 27331- break; 27332- case OPENRISC_OPERAND_HI16 : 27333- fields->f_simm16 = value; 27334- break; 27335- case OPENRISC_OPERAND_LO16 : 27336- fields->f_lo16 = value; 27337- break; 27338- case OPENRISC_OPERAND_OP_F_23 : 27339- fields->f_op4 = value; 27340- break; 27341- case OPENRISC_OPERAND_OP_F_3 : 27342- fields->f_op5 = value; 27343- break; 27344- case OPENRISC_OPERAND_RA : 27345- fields->f_r2 = value; 27346- break; 27347- case OPENRISC_OPERAND_RB : 27348- fields->f_r3 = value; 27349- break; 27350- case OPENRISC_OPERAND_RD : 27351- fields->f_r1 = value; 27352- break; 27353- case OPENRISC_OPERAND_SIMM_16 : 27354- fields->f_simm16 = value; 27355- break; 27356- case OPENRISC_OPERAND_UI16NC : 27357- fields->f_i16nc = value; 27358- break; 27359- case OPENRISC_OPERAND_UIMM_16 : 27360- fields->f_uimm16 = value; 27361- break; 27362- case OPENRISC_OPERAND_UIMM_5 : 27363- fields->f_uimm5 = value; 27364- break; 27365- 27366- default : 27367- /* xgettext:c-format */ 27368- fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), 27369- opindex); 27370- abort (); 27371- } 27372-} 27373- 27374-void 27375-openrisc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 27376- int opindex, 27377- CGEN_FIELDS * fields, 27378- bfd_vma value) 27379-{ 27380- switch (opindex) 27381- { 27382- case OPENRISC_OPERAND_ABS_26 : 27383- fields->f_abs26 = value; 27384- break; 27385- case OPENRISC_OPERAND_DISP_26 : 27386- fields->f_disp26 = value; 27387- break; 27388- case OPENRISC_OPERAND_HI16 : 27389- fields->f_simm16 = value; 27390- break; 27391- case OPENRISC_OPERAND_LO16 : 27392- fields->f_lo16 = value; 27393- break; 27394- case OPENRISC_OPERAND_OP_F_23 : 27395- fields->f_op4 = value; 27396- break; 27397- case OPENRISC_OPERAND_OP_F_3 : 27398- fields->f_op5 = value; 27399- break; 27400- case OPENRISC_OPERAND_RA : 27401- fields->f_r2 = value; 27402- break; 27403- case OPENRISC_OPERAND_RB : 27404- fields->f_r3 = value; 27405- break; 27406- case OPENRISC_OPERAND_RD : 27407- fields->f_r1 = value; 27408- break; 27409- case OPENRISC_OPERAND_SIMM_16 : 27410- fields->f_simm16 = value; 27411- break; 27412- case OPENRISC_OPERAND_UI16NC : 27413- fields->f_i16nc = value; 27414- break; 27415- case OPENRISC_OPERAND_UIMM_16 : 27416- fields->f_uimm16 = value; 27417- break; 27418- case OPENRISC_OPERAND_UIMM_5 : 27419- fields->f_uimm5 = value; 27420- break; 27421- 27422- default : 27423- /* xgettext:c-format */ 27424- fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), 27425- opindex); 27426- abort (); 27427- } 27428-} 27429- 27430-/* Function to call before using the instruction builder tables. */ 27431- 27432-void 27433-openrisc_cgen_init_ibld_table (CGEN_CPU_DESC cd) 27434-{ 27435- cd->insert_handlers = & openrisc_cgen_insert_handlers[0]; 27436- cd->extract_handlers = & openrisc_cgen_extract_handlers[0]; 27437- 27438- cd->insert_operand = openrisc_cgen_insert_operand; 27439- cd->extract_operand = openrisc_cgen_extract_operand; 27440- 27441- cd->get_int_operand = openrisc_cgen_get_int_operand; 27442- cd->set_int_operand = openrisc_cgen_set_int_operand; 27443- cd->get_vma_operand = openrisc_cgen_get_vma_operand; 27444- cd->set_vma_operand = openrisc_cgen_set_vma_operand; 27445-} 27446diff -rNU3 dist.orig/opcodes/openrisc-opc.c dist/opcodes/openrisc-opc.c 27447--- dist.orig/opcodes/openrisc-opc.c 2010-02-12 04:25:49.000000000 +0100 27448+++ dist/opcodes/openrisc-opc.c 1970-01-01 01:00:00.000000000 +0100 27449@@ -1,682 +0,0 @@ 27450-/* Instruction opcode table for openrisc. 27451- 27452-THIS FILE IS MACHINE GENERATED WITH CGEN. 27453- 27454-Copyright 1996-2010 Free Software Foundation, Inc. 27455- 27456-This file is part of the GNU Binutils and/or GDB, the GNU debugger. 27457- 27458- This file is free software; you can redistribute it and/or modify 27459- it under the terms of the GNU General Public License as published by 27460- the Free Software Foundation; either version 3, or (at your option) 27461- any later version. 27462- 27463- It is distributed in the hope that it will be useful, but WITHOUT 27464- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 27465- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 27466- License for more details. 27467- 27468- You should have received a copy of the GNU General Public License along 27469- with this program; if not, write to the Free Software Foundation, Inc., 27470- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 27471- 27472-*/ 27473- 27474-#include "sysdep.h" 27475-#include "ansidecl.h" 27476-#include "bfd.h" 27477-#include "symcat.h" 27478-#include "openrisc-desc.h" 27479-#include "openrisc-opc.h" 27480-#include "libiberty.h" 27481- 27482-/* -- opc.c */ 27483-/* -- */ 27484-/* The hash functions are recorded here to help keep assembler code out of 27485- the disassembler and vice versa. */ 27486- 27487-static int asm_hash_insn_p (const CGEN_INSN *); 27488-static unsigned int asm_hash_insn (const char *); 27489-static int dis_hash_insn_p (const CGEN_INSN *); 27490-static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); 27491- 27492-/* Instruction formats. */ 27493- 27494-#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f] 27495-static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 27496- 0, 0, 0x0, { { 0 } } 27497-}; 27498- 27499-static const CGEN_IFMT ifmt_l_j ATTRIBUTE_UNUSED = { 27500- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_ABS26) }, { 0 } } 27501-}; 27502- 27503-static const CGEN_IFMT ifmt_l_jr ATTRIBUTE_UNUSED = { 27504- 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 27505-}; 27506- 27507-static const CGEN_IFMT ifmt_l_bal ATTRIBUTE_UNUSED = { 27508- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_DISP26) }, { 0 } } 27509-}; 27510- 27511-static const CGEN_IFMT ifmt_l_movhi ATTRIBUTE_UNUSED = { 27512- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 27513-}; 27514- 27515-static const CGEN_IFMT ifmt_l_mfsr ATTRIBUTE_UNUSED = { 27516- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 27517-}; 27518- 27519-static const CGEN_IFMT ifmt_l_mtsr ATTRIBUTE_UNUSED = { 27520- 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_I16_1) }, { 0 } } 27521-}; 27522- 27523-static const CGEN_IFMT ifmt_l_lw ATTRIBUTE_UNUSED = { 27524- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 27525-}; 27526- 27527-static const CGEN_IFMT ifmt_l_sw ATTRIBUTE_UNUSED = { 27528- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R3) }, { F (F_I16NC) }, { 0 } } 27529-}; 27530- 27531-static const CGEN_IFMT ifmt_l_sll ATTRIBUTE_UNUSED = { 27532- 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_3) }, { F (F_OP6) }, { F (F_F_4_1) }, { F (F_OP7) }, { 0 } } 27533-}; 27534- 27535-static const CGEN_IFMT ifmt_l_slli ATTRIBUTE_UNUSED = { 27536- 32, 32, 0xfc00ffe0, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_F_15_8) }, { F (F_OP6) }, { F (F_UIMM5) }, { 0 } } 27537-}; 27538- 27539-static const CGEN_IFMT ifmt_l_add ATTRIBUTE_UNUSED = { 27540- 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_7) }, { F (F_OP7) }, { 0 } } 27541-}; 27542- 27543-static const CGEN_IFMT ifmt_l_addi ATTRIBUTE_UNUSED = { 27544- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_LO16) }, { 0 } } 27545-}; 27546- 27547-static const CGEN_IFMT ifmt_l_sfgts ATTRIBUTE_UNUSED = { 27548- 32, 32, 0xffe007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_11) }, { 0 } } 27549-}; 27550- 27551-static const CGEN_IFMT ifmt_l_sfgtsi ATTRIBUTE_UNUSED = { 27552- 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 27553-}; 27554- 27555-static const CGEN_IFMT ifmt_l_sfgtui ATTRIBUTE_UNUSED = { 27556- 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 27557-}; 27558- 27559-#undef F 27560- 27561-#define A(a) (1 << CGEN_INSN_##a) 27562-#define OPERAND(op) OPENRISC_OPERAND_##op 27563-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 27564-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 27565- 27566-/* The instruction table. */ 27567- 27568-static const CGEN_OPCODE openrisc_cgen_insn_opcode_table[MAX_INSNS] = 27569-{ 27570- /* Special null first entry. 27571- A `num' value of zero is thus invalid. 27572- Also, the special `invalid' insn resides here. */ 27573- { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, 27574-/* l.j ${abs-26} */ 27575- { 27576- { 0, 0, 0, 0 }, 27577- { { MNEM, ' ', OP (ABS_26), 0 } }, 27578- & ifmt_l_j, { 0x0 } 27579- }, 27580-/* l.jal ${abs-26} */ 27581- { 27582- { 0, 0, 0, 0 }, 27583- { { MNEM, ' ', OP (ABS_26), 0 } }, 27584- & ifmt_l_j, { 0x4000000 } 27585- }, 27586-/* l.jr $rA */ 27587- { 27588- { 0, 0, 0, 0 }, 27589- { { MNEM, ' ', OP (RA), 0 } }, 27590- & ifmt_l_jr, { 0x14000000 } 27591- }, 27592-/* l.jalr $rA */ 27593- { 27594- { 0, 0, 0, 0 }, 27595- { { MNEM, ' ', OP (RA), 0 } }, 27596- & ifmt_l_jr, { 0x14200000 } 27597- }, 27598-/* l.bal ${disp-26} */ 27599- { 27600- { 0, 0, 0, 0 }, 27601- { { MNEM, ' ', OP (DISP_26), 0 } }, 27602- & ifmt_l_bal, { 0x8000000 } 27603- }, 27604-/* l.bnf ${disp-26} */ 27605- { 27606- { 0, 0, 0, 0 }, 27607- { { MNEM, ' ', OP (DISP_26), 0 } }, 27608- & ifmt_l_bal, { 0xc000000 } 27609- }, 27610-/* l.bf ${disp-26} */ 27611- { 27612- { 0, 0, 0, 0 }, 27613- { { MNEM, ' ', OP (DISP_26), 0 } }, 27614- & ifmt_l_bal, { 0x10000000 } 27615- }, 27616-/* l.brk ${uimm-16} */ 27617- { 27618- { 0, 0, 0, 0 }, 27619- { { MNEM, ' ', OP (UIMM_16), 0 } }, 27620- & ifmt_l_jr, { 0x17000000 } 27621- }, 27622-/* l.rfe $rA */ 27623- { 27624- { 0, 0, 0, 0 }, 27625- { { MNEM, ' ', OP (RA), 0 } }, 27626- & ifmt_l_jr, { 0x14400000 } 27627- }, 27628-/* l.sys ${uimm-16} */ 27629- { 27630- { 0, 0, 0, 0 }, 27631- { { MNEM, ' ', OP (UIMM_16), 0 } }, 27632- & ifmt_l_jr, { 0x16000000 } 27633- }, 27634-/* l.nop */ 27635- { 27636- { 0, 0, 0, 0 }, 27637- { { MNEM, 0 } }, 27638- & ifmt_l_jr, { 0x15000000 } 27639- }, 27640-/* l.movhi $rD,$hi16 */ 27641- { 27642- { 0, 0, 0, 0 }, 27643- { { MNEM, ' ', OP (RD), ',', OP (HI16), 0 } }, 27644- & ifmt_l_movhi, { 0x18000000 } 27645- }, 27646-/* l.mfsr $rD,$rA */ 27647- { 27648- { 0, 0, 0, 0 }, 27649- { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 27650- & ifmt_l_mfsr, { 0x1c000000 } 27651- }, 27652-/* l.mtsr $rA,$rB */ 27653- { 27654- { 0, 0, 0, 0 }, 27655- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27656- & ifmt_l_mtsr, { 0x40000000 } 27657- }, 27658-/* l.lw $rD,${simm-16}($rA) */ 27659- { 27660- { 0, 0, 0, 0 }, 27661- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 27662- & ifmt_l_lw, { 0x80000000 } 27663- }, 27664-/* l.lbz $rD,${simm-16}($rA) */ 27665- { 27666- { 0, 0, 0, 0 }, 27667- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 27668- & ifmt_l_lw, { 0x84000000 } 27669- }, 27670-/* l.lbs $rD,${simm-16}($rA) */ 27671- { 27672- { 0, 0, 0, 0 }, 27673- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 27674- & ifmt_l_lw, { 0x88000000 } 27675- }, 27676-/* l.lhz $rD,${simm-16}($rA) */ 27677- { 27678- { 0, 0, 0, 0 }, 27679- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 27680- & ifmt_l_lw, { 0x8c000000 } 27681- }, 27682-/* l.lhs $rD,${simm-16}($rA) */ 27683- { 27684- { 0, 0, 0, 0 }, 27685- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 27686- & ifmt_l_lw, { 0x90000000 } 27687- }, 27688-/* l.sw ${ui16nc}($rA),$rB */ 27689- { 27690- { 0, 0, 0, 0 }, 27691- { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, 27692- & ifmt_l_sw, { 0xd4000000 } 27693- }, 27694-/* l.sb ${ui16nc}($rA),$rB */ 27695- { 27696- { 0, 0, 0, 0 }, 27697- { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, 27698- & ifmt_l_sw, { 0xd8000000 } 27699- }, 27700-/* l.sh ${ui16nc}($rA),$rB */ 27701- { 27702- { 0, 0, 0, 0 }, 27703- { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, 27704- & ifmt_l_sw, { 0xdc000000 } 27705- }, 27706-/* l.sll $rD,$rA,$rB */ 27707- { 27708- { 0, 0, 0, 0 }, 27709- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27710- & ifmt_l_sll, { 0xe0000008 } 27711- }, 27712-/* l.slli $rD,$rA,${uimm-5} */ 27713- { 27714- { 0, 0, 0, 0 }, 27715- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, 27716- & ifmt_l_slli, { 0xb4000000 } 27717- }, 27718-/* l.srl $rD,$rA,$rB */ 27719- { 27720- { 0, 0, 0, 0 }, 27721- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27722- & ifmt_l_sll, { 0xe0000028 } 27723- }, 27724-/* l.srli $rD,$rA,${uimm-5} */ 27725- { 27726- { 0, 0, 0, 0 }, 27727- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, 27728- & ifmt_l_slli, { 0xb4000020 } 27729- }, 27730-/* l.sra $rD,$rA,$rB */ 27731- { 27732- { 0, 0, 0, 0 }, 27733- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27734- & ifmt_l_sll, { 0xe0000048 } 27735- }, 27736-/* l.srai $rD,$rA,${uimm-5} */ 27737- { 27738- { 0, 0, 0, 0 }, 27739- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, 27740- & ifmt_l_slli, { 0xb4000040 } 27741- }, 27742-/* l.ror $rD,$rA,$rB */ 27743- { 27744- { 0, 0, 0, 0 }, 27745- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27746- & ifmt_l_sll, { 0xe0000088 } 27747- }, 27748-/* l.rori $rD,$rA,${uimm-5} */ 27749- { 27750- { 0, 0, 0, 0 }, 27751- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, 27752- & ifmt_l_slli, { 0xb4000080 } 27753- }, 27754-/* l.add $rD,$rA,$rB */ 27755- { 27756- { 0, 0, 0, 0 }, 27757- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27758- & ifmt_l_add, { 0xe0000000 } 27759- }, 27760-/* l.addi $rD,$rA,$lo16 */ 27761- { 27762- { 0, 0, 0, 0 }, 27763- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, 27764- & ifmt_l_addi, { 0x94000000 } 27765- }, 27766-/* l.sub $rD,$rA,$rB */ 27767- { 27768- { 0, 0, 0, 0 }, 27769- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27770- & ifmt_l_add, { 0xe0000002 } 27771- }, 27772-/* l.subi $rD,$rA,$lo16 */ 27773- { 27774- { 0, 0, 0, 0 }, 27775- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, 27776- & ifmt_l_addi, { 0x9c000000 } 27777- }, 27778-/* l.and $rD,$rA,$rB */ 27779- { 27780- { 0, 0, 0, 0 }, 27781- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27782- & ifmt_l_add, { 0xe0000003 } 27783- }, 27784-/* l.andi $rD,$rA,$lo16 */ 27785- { 27786- { 0, 0, 0, 0 }, 27787- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, 27788- & ifmt_l_addi, { 0xa0000000 } 27789- }, 27790-/* l.or $rD,$rA,$rB */ 27791- { 27792- { 0, 0, 0, 0 }, 27793- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27794- & ifmt_l_add, { 0xe0000004 } 27795- }, 27796-/* l.ori $rD,$rA,$lo16 */ 27797- { 27798- { 0, 0, 0, 0 }, 27799- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, 27800- & ifmt_l_addi, { 0xa4000000 } 27801- }, 27802-/* l.xor $rD,$rA,$rB */ 27803- { 27804- { 0, 0, 0, 0 }, 27805- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27806- & ifmt_l_add, { 0xe0000005 } 27807- }, 27808-/* l.xori $rD,$rA,$lo16 */ 27809- { 27810- { 0, 0, 0, 0 }, 27811- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, 27812- & ifmt_l_addi, { 0xa8000000 } 27813- }, 27814-/* l.mul $rD,$rA,$rB */ 27815- { 27816- { 0, 0, 0, 0 }, 27817- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27818- & ifmt_l_add, { 0xe0000006 } 27819- }, 27820-/* l.muli $rD,$rA,$lo16 */ 27821- { 27822- { 0, 0, 0, 0 }, 27823- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, 27824- & ifmt_l_addi, { 0xac000000 } 27825- }, 27826-/* l.div $rD,$rA,$rB */ 27827- { 27828- { 0, 0, 0, 0 }, 27829- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27830- & ifmt_l_add, { 0xe0000009 } 27831- }, 27832-/* l.divu $rD,$rA,$rB */ 27833- { 27834- { 0, 0, 0, 0 }, 27835- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 27836- & ifmt_l_add, { 0xe000000a } 27837- }, 27838-/* l.sfgts $rA,$rB */ 27839- { 27840- { 0, 0, 0, 0 }, 27841- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27842- & ifmt_l_sfgts, { 0xe4c00000 } 27843- }, 27844-/* l.sfgtu $rA,$rB */ 27845- { 27846- { 0, 0, 0, 0 }, 27847- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27848- & ifmt_l_sfgts, { 0xe4400000 } 27849- }, 27850-/* l.sfges $rA,$rB */ 27851- { 27852- { 0, 0, 0, 0 }, 27853- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27854- & ifmt_l_sfgts, { 0xe4e00000 } 27855- }, 27856-/* l.sfgeu $rA,$rB */ 27857- { 27858- { 0, 0, 0, 0 }, 27859- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27860- & ifmt_l_sfgts, { 0xe4600000 } 27861- }, 27862-/* l.sflts $rA,$rB */ 27863- { 27864- { 0, 0, 0, 0 }, 27865- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27866- & ifmt_l_sfgts, { 0xe5000000 } 27867- }, 27868-/* l.sfltu $rA,$rB */ 27869- { 27870- { 0, 0, 0, 0 }, 27871- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27872- & ifmt_l_sfgts, { 0xe4800000 } 27873- }, 27874-/* l.sfles $rA,$rB */ 27875- { 27876- { 0, 0, 0, 0 }, 27877- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27878- & ifmt_l_sfgts, { 0xe5200000 } 27879- }, 27880-/* l.sfleu $rA,$rB */ 27881- { 27882- { 0, 0, 0, 0 }, 27883- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27884- & ifmt_l_sfgts, { 0xe4a00000 } 27885- }, 27886-/* l.sfgtsi $rA,${simm-16} */ 27887- { 27888- { 0, 0, 0, 0 }, 27889- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, 27890- & ifmt_l_sfgtsi, { 0xb8c00000 } 27891- }, 27892-/* l.sfgtui $rA,${uimm-16} */ 27893- { 27894- { 0, 0, 0, 0 }, 27895- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, 27896- & ifmt_l_sfgtui, { 0xb8400000 } 27897- }, 27898-/* l.sfgesi $rA,${simm-16} */ 27899- { 27900- { 0, 0, 0, 0 }, 27901- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, 27902- & ifmt_l_sfgtsi, { 0xb8e00000 } 27903- }, 27904-/* l.sfgeui $rA,${uimm-16} */ 27905- { 27906- { 0, 0, 0, 0 }, 27907- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, 27908- & ifmt_l_sfgtui, { 0xb8600000 } 27909- }, 27910-/* l.sfltsi $rA,${simm-16} */ 27911- { 27912- { 0, 0, 0, 0 }, 27913- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, 27914- & ifmt_l_sfgtsi, { 0xb9000000 } 27915- }, 27916-/* l.sfltui $rA,${uimm-16} */ 27917- { 27918- { 0, 0, 0, 0 }, 27919- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, 27920- & ifmt_l_sfgtui, { 0xb8800000 } 27921- }, 27922-/* l.sflesi $rA,${simm-16} */ 27923- { 27924- { 0, 0, 0, 0 }, 27925- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, 27926- & ifmt_l_sfgtsi, { 0xb9200000 } 27927- }, 27928-/* l.sfleui $rA,${uimm-16} */ 27929- { 27930- { 0, 0, 0, 0 }, 27931- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, 27932- & ifmt_l_sfgtui, { 0xb8a00000 } 27933- }, 27934-/* l.sfeq $rA,$rB */ 27935- { 27936- { 0, 0, 0, 0 }, 27937- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27938- & ifmt_l_sfgts, { 0xe4000000 } 27939- }, 27940-/* l.sfeqi $rA,${simm-16} */ 27941- { 27942- { 0, 0, 0, 0 }, 27943- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, 27944- & ifmt_l_sfgtsi, { 0xb8000000 } 27945- }, 27946-/* l.sfne $rA,$rB */ 27947- { 27948- { 0, 0, 0, 0 }, 27949- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 27950- & ifmt_l_sfgts, { 0xe4200000 } 27951- }, 27952-/* l.sfnei $rA,${simm-16} */ 27953- { 27954- { 0, 0, 0, 0 }, 27955- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, 27956- & ifmt_l_sfgtsi, { 0xb8200000 } 27957- }, 27958-}; 27959- 27960-#undef A 27961-#undef OPERAND 27962-#undef MNEM 27963-#undef OP 27964- 27965-/* Formats for ALIAS macro-insns. */ 27966- 27967-#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f] 27968-static const CGEN_IFMT ifmt_l_ret ATTRIBUTE_UNUSED = { 27969- 32, 32, 0xffffffff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 27970-}; 27971- 27972-#undef F 27973- 27974-/* Each non-simple macro entry points to an array of expansion possibilities. */ 27975- 27976-#define A(a) (1 << CGEN_INSN_##a) 27977-#define OPERAND(op) OPENRISC_OPERAND_##op 27978-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 27979-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 27980- 27981-/* The macro instruction table. */ 27982- 27983-static const CGEN_IBASE openrisc_cgen_macro_insn_table[] = 27984-{ 27985-/* l.ret */ 27986- { 27987- -1, "l-ret", "l.ret", 32, 27988- { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 27989- }, 27990-}; 27991- 27992-/* The macro instruction opcode table. */ 27993- 27994-static const CGEN_OPCODE openrisc_cgen_macro_insn_opcode_table[] = 27995-{ 27996-/* l.ret */ 27997- { 27998- { 0, 0, 0, 0 }, 27999- { { MNEM, 0 } }, 28000- & ifmt_l_ret, { 0x140b0000 } 28001- }, 28002-}; 28003- 28004-#undef A 28005-#undef OPERAND 28006-#undef MNEM 28007-#undef OP 28008- 28009-#ifndef CGEN_ASM_HASH_P 28010-#define CGEN_ASM_HASH_P(insn) 1 28011-#endif 28012- 28013-#ifndef CGEN_DIS_HASH_P 28014-#define CGEN_DIS_HASH_P(insn) 1 28015-#endif 28016- 28017-/* Return non-zero if INSN is to be added to the hash table. 28018- Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ 28019- 28020-static int 28021-asm_hash_insn_p (insn) 28022- const CGEN_INSN *insn ATTRIBUTE_UNUSED; 28023-{ 28024- return CGEN_ASM_HASH_P (insn); 28025-} 28026- 28027-static int 28028-dis_hash_insn_p (insn) 28029- const CGEN_INSN *insn; 28030-{ 28031- /* If building the hash table and the NO-DIS attribute is present, 28032- ignore. */ 28033- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) 28034- return 0; 28035- return CGEN_DIS_HASH_P (insn); 28036-} 28037- 28038-#ifndef CGEN_ASM_HASH 28039-#define CGEN_ASM_HASH_SIZE 127 28040-#ifdef CGEN_MNEMONIC_OPERANDS 28041-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) 28042-#else 28043-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ 28044-#endif 28045-#endif 28046- 28047-/* It doesn't make much sense to provide a default here, 28048- but while this is under development we do. 28049- BUFFER is a pointer to the bytes of the insn, target order. 28050- VALUE is the first base_insn_bitsize bits as an int in host order. */ 28051- 28052-#ifndef CGEN_DIS_HASH 28053-#define CGEN_DIS_HASH_SIZE 256 28054-#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) 28055-#endif 28056- 28057-/* The result is the hash value of the insn. 28058- Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ 28059- 28060-static unsigned int 28061-asm_hash_insn (mnem) 28062- const char * mnem; 28063-{ 28064- return CGEN_ASM_HASH (mnem); 28065-} 28066- 28067-/* BUF is a pointer to the bytes of the insn, target order. 28068- VALUE is the first base_insn_bitsize bits as an int in host order. */ 28069- 28070-static unsigned int 28071-dis_hash_insn (buf, value) 28072- const char * buf ATTRIBUTE_UNUSED; 28073- CGEN_INSN_INT value ATTRIBUTE_UNUSED; 28074-{ 28075- return CGEN_DIS_HASH (buf, value); 28076-} 28077- 28078-/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ 28079- 28080-static void 28081-set_fields_bitsize (CGEN_FIELDS *fields, int size) 28082-{ 28083- CGEN_FIELDS_BITSIZE (fields) = size; 28084-} 28085- 28086-/* Function to call before using the operand instance table. 28087- This plugs the opcode entries and macro instructions into the cpu table. */ 28088- 28089-void 28090-openrisc_cgen_init_opcode_table (CGEN_CPU_DESC cd) 28091-{ 28092- int i; 28093- int num_macros = (sizeof (openrisc_cgen_macro_insn_table) / 28094- sizeof (openrisc_cgen_macro_insn_table[0])); 28095- const CGEN_IBASE *ib = & openrisc_cgen_macro_insn_table[0]; 28096- const CGEN_OPCODE *oc = & openrisc_cgen_macro_insn_opcode_table[0]; 28097- CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); 28098- 28099- /* This test has been added to avoid a warning generated 28100- if memset is called with a third argument of value zero. */ 28101- if (num_macros >= 1) 28102- memset (insns, 0, num_macros * sizeof (CGEN_INSN)); 28103- for (i = 0; i < num_macros; ++i) 28104- { 28105- insns[i].base = &ib[i]; 28106- insns[i].opcode = &oc[i]; 28107- openrisc_cgen_build_insn_regex (& insns[i]); 28108- } 28109- cd->macro_insn_table.init_entries = insns; 28110- cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); 28111- cd->macro_insn_table.num_init_entries = num_macros; 28112- 28113- oc = & openrisc_cgen_insn_opcode_table[0]; 28114- insns = (CGEN_INSN *) cd->insn_table.init_entries; 28115- for (i = 0; i < MAX_INSNS; ++i) 28116- { 28117- insns[i].opcode = &oc[i]; 28118- openrisc_cgen_build_insn_regex (& insns[i]); 28119- } 28120- 28121- cd->sizeof_fields = sizeof (CGEN_FIELDS); 28122- cd->set_fields_bitsize = set_fields_bitsize; 28123- 28124- cd->asm_hash_p = asm_hash_insn_p; 28125- cd->asm_hash = asm_hash_insn; 28126- cd->asm_hash_size = CGEN_ASM_HASH_SIZE; 28127- 28128- cd->dis_hash_p = dis_hash_insn_p; 28129- cd->dis_hash = dis_hash_insn; 28130- cd->dis_hash_size = CGEN_DIS_HASH_SIZE; 28131-} 28132diff -rNU3 dist.orig/opcodes/openrisc-opc.h dist/opcodes/openrisc-opc.h 28133--- dist.orig/opcodes/openrisc-opc.h 2010-01-02 19:50:59.000000000 +0100 28134+++ dist/opcodes/openrisc-opc.h 1970-01-01 01:00:00.000000000 +0100 28135@@ -1,113 +0,0 @@ 28136-/* Instruction opcode header for openrisc. 28137- 28138-THIS FILE IS MACHINE GENERATED WITH CGEN. 28139- 28140-Copyright 1996-2010 Free Software Foundation, Inc. 28141- 28142-This file is part of the GNU Binutils and/or GDB, the GNU debugger. 28143- 28144- This file is free software; you can redistribute it and/or modify 28145- it under the terms of the GNU General Public License as published by 28146- the Free Software Foundation; either version 3, or (at your option) 28147- any later version. 28148- 28149- It is distributed in the hope that it will be useful, but WITHOUT 28150- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 28151- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 28152- License for more details. 28153- 28154- You should have received a copy of the GNU General Public License along 28155- with this program; if not, write to the Free Software Foundation, Inc., 28156- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 28157- 28158-*/ 28159- 28160-#ifndef OPENRISC_OPC_H 28161-#define OPENRISC_OPC_H 28162- 28163-/* -- opc.h */ 28164-#undef CGEN_DIS_HASH_SIZE 28165-#define CGEN_DIS_HASH_SIZE 64 28166-#undef CGEN_DIS_HASH 28167-#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) 28168- 28169-extern long openrisc_sign_extend_16bit (long); 28170-/* -- */ 28171-/* Enum declaration for openrisc instruction types. */ 28172-typedef enum cgen_insn_type { 28173- OPENRISC_INSN_INVALID, OPENRISC_INSN_L_J, OPENRISC_INSN_L_JAL, OPENRISC_INSN_L_JR 28174- , OPENRISC_INSN_L_JALR, OPENRISC_INSN_L_BAL, OPENRISC_INSN_L_BNF, OPENRISC_INSN_L_BF 28175- , OPENRISC_INSN_L_BRK, OPENRISC_INSN_L_RFE, OPENRISC_INSN_L_SYS, OPENRISC_INSN_L_NOP 28176- , OPENRISC_INSN_L_MOVHI, OPENRISC_INSN_L_MFSR, OPENRISC_INSN_L_MTSR, OPENRISC_INSN_L_LW 28177- , OPENRISC_INSN_L_LBZ, OPENRISC_INSN_L_LBS, OPENRISC_INSN_L_LHZ, OPENRISC_INSN_L_LHS 28178- , OPENRISC_INSN_L_SW, OPENRISC_INSN_L_SB, OPENRISC_INSN_L_SH, OPENRISC_INSN_L_SLL 28179- , OPENRISC_INSN_L_SLLI, OPENRISC_INSN_L_SRL, OPENRISC_INSN_L_SRLI, OPENRISC_INSN_L_SRA 28180- , OPENRISC_INSN_L_SRAI, OPENRISC_INSN_L_ROR, OPENRISC_INSN_L_RORI, OPENRISC_INSN_L_ADD 28181- , OPENRISC_INSN_L_ADDI, OPENRISC_INSN_L_SUB, OPENRISC_INSN_L_SUBI, OPENRISC_INSN_L_AND 28182- , OPENRISC_INSN_L_ANDI, OPENRISC_INSN_L_OR, OPENRISC_INSN_L_ORI, OPENRISC_INSN_L_XOR 28183- , OPENRISC_INSN_L_XORI, OPENRISC_INSN_L_MUL, OPENRISC_INSN_L_MULI, OPENRISC_INSN_L_DIV 28184- , OPENRISC_INSN_L_DIVU, OPENRISC_INSN_L_SFGTS, OPENRISC_INSN_L_SFGTU, OPENRISC_INSN_L_SFGES 28185- , OPENRISC_INSN_L_SFGEU, OPENRISC_INSN_L_SFLTS, OPENRISC_INSN_L_SFLTU, OPENRISC_INSN_L_SFLES 28186- , OPENRISC_INSN_L_SFLEU, OPENRISC_INSN_L_SFGTSI, OPENRISC_INSN_L_SFGTUI, OPENRISC_INSN_L_SFGESI 28187- , OPENRISC_INSN_L_SFGEUI, OPENRISC_INSN_L_SFLTSI, OPENRISC_INSN_L_SFLTUI, OPENRISC_INSN_L_SFLESI 28188- , OPENRISC_INSN_L_SFLEUI, OPENRISC_INSN_L_SFEQ, OPENRISC_INSN_L_SFEQI, OPENRISC_INSN_L_SFNE 28189- , OPENRISC_INSN_L_SFNEI 28190-} CGEN_INSN_TYPE; 28191- 28192-/* Index of `invalid' insn place holder. */ 28193-#define CGEN_INSN_INVALID OPENRISC_INSN_INVALID 28194- 28195-/* Total number of insns in table. */ 28196-#define MAX_INSNS ((int) OPENRISC_INSN_L_SFNEI + 1) 28197- 28198-/* This struct records data prior to insertion or after extraction. */ 28199-struct cgen_fields 28200-{ 28201- int length; 28202- long f_nil; 28203- long f_anyof; 28204- long f_class; 28205- long f_sub; 28206- long f_r1; 28207- long f_r2; 28208- long f_r3; 28209- long f_simm16; 28210- long f_uimm16; 28211- long f_uimm5; 28212- long f_hi16; 28213- long f_lo16; 28214- long f_op1; 28215- long f_op2; 28216- long f_op3; 28217- long f_op4; 28218- long f_op5; 28219- long f_op6; 28220- long f_op7; 28221- long f_i16_1; 28222- long f_i16_2; 28223- long f_disp26; 28224- long f_abs26; 28225- long f_i16nc; 28226- long f_f_15_8; 28227- long f_f_10_3; 28228- long f_f_4_1; 28229- long f_f_7_3; 28230- long f_f_10_7; 28231- long f_f_10_11; 28232-}; 28233- 28234-#define CGEN_INIT_PARSE(od) \ 28235-{\ 28236-} 28237-#define CGEN_INIT_INSERT(od) \ 28238-{\ 28239-} 28240-#define CGEN_INIT_EXTRACT(od) \ 28241-{\ 28242-} 28243-#define CGEN_INIT_PRINT(od) \ 28244-{\ 28245-} 28246- 28247- 28248-#endif /* OPENRISC_OPC_H */ 28249diff -rNU3 dist.orig/opcodes/or1k-asm.c dist/opcodes/or1k-asm.c 28250--- dist.orig/opcodes/or1k-asm.c 1970-01-01 01:00:00.000000000 +0100 28251+++ dist/opcodes/or1k-asm.c 2015-10-18 13:11:20.000000000 +0200 28252@@ -0,0 +1,910 @@ 28253+/* Assembler interface for targets using CGEN. -*- C -*- 28254+ CGEN: Cpu tools GENerator 28255+ 28256+ THIS FILE IS MACHINE GENERATED WITH CGEN. 28257+ - the resultant file is machine generated, cgen-asm.in isn't 28258+ 28259+ Copyright (C) 1996-2014 Free Software Foundation, Inc. 28260+ 28261+ This file is part of libopcodes. 28262+ 28263+ This library is free software; you can redistribute it and/or modify 28264+ it under the terms of the GNU General Public License as published by 28265+ the Free Software Foundation; either version 3, or (at your option) 28266+ any later version. 28267+ 28268+ It is distributed in the hope that it will be useful, but WITHOUT 28269+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 28270+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 28271+ License for more details. 28272+ 28273+ You should have received a copy of the GNU General Public License 28274+ along with this program; if not, write to the Free Software Foundation, Inc., 28275+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 28276+ 28277+ 28278+/* ??? Eventually more and more of this stuff can go to cpu-independent files. 28279+ Keep that in mind. */ 28280+ 28281+#include "sysdep.h" 28282+#include <stdio.h> 28283+#include "ansidecl.h" 28284+#include "bfd.h" 28285+#include "symcat.h" 28286+#include "or1k-desc.h" 28287+#include "or1k-opc.h" 28288+#include "opintl.h" 28289+#include "xregex.h" 28290+#include "libiberty.h" 28291+#include "safe-ctype.h" 28292+ 28293+#undef min 28294+#define min(a,b) ((a) < (b) ? (a) : (b)) 28295+#undef max 28296+#define max(a,b) ((a) > (b) ? (a) : (b)) 28297+ 28298+static const char * parse_insn_normal 28299+ (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); 28300+ 28301+/* -- assembler routines inserted here. */ 28302+ 28303+/* -- asm.c */ 28304+ 28305+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); 28306+ 28307+#define CGEN_VERBOSE_ASSEMBLER_ERRORS 28308+ 28309+static const char * 28310+parse_disp26 (CGEN_CPU_DESC cd, 28311+ const char ** strp, 28312+ int opindex, 28313+ int opinfo, 28314+ enum cgen_parse_operand_result * resultp, 28315+ bfd_vma * valuep) 28316+{ 28317+ const char *errmsg = NULL; 28318+ enum cgen_parse_operand_result result_type; 28319+ 28320+ if (strncasecmp (*strp, "plt(", 4) == 0) 28321+ { 28322+ bfd_vma value; 28323+ 28324+ *strp += 4; 28325+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_PLT26, 28326+ & result_type, & value); 28327+ if (**strp != ')') 28328+ return MISSING_CLOSING_PARENTHESIS; 28329+ ++*strp; 28330+ if (errmsg == NULL 28331+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28332+ value = (value >> 2) & 0xffff; 28333+ *valuep = value; 28334+ return errmsg; 28335+ } 28336+ return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep); 28337+} 28338+ 28339+static const char * 28340+parse_simm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) 28341+{ 28342+ const char *errmsg; 28343+ enum cgen_parse_operand_result result_type; 28344+ long ret; 28345+ 28346+ if (**strp == '#') 28347+ ++*strp; 28348+ 28349+ if (strncasecmp (*strp, "hi(", 3) == 0) 28350+ { 28351+ bfd_vma value; 28352+ 28353+ *strp += 3; 28354+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, 28355+ & result_type, & value); 28356+ if (**strp != ')') 28357+ errmsg = MISSING_CLOSING_PARENTHESIS; 28358+ ++*strp; 28359+ 28360+ ret = value; 28361+ 28362+ if (errmsg == NULL 28363+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28364+ { 28365+ ret >>= 16; 28366+ ret &= 0xffff; 28367+ ret = (ret ^ 0x8000) - 0x8000; 28368+ } 28369+ } 28370+ else if (strncasecmp (*strp, "lo(", 3) == 0) 28371+ { 28372+ bfd_vma value; 28373+ 28374+ *strp += 3; 28375+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, 28376+ & result_type, & value); 28377+ if (**strp != ')') 28378+ return MISSING_CLOSING_PARENTHESIS; 28379+ ++*strp; 28380+ 28381+ ret = value; 28382+ 28383+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28384+ { 28385+ ret &= 0xffff; 28386+ ret = (ret ^ 0x8000) - 0x8000; 28387+ } 28388+ } 28389+ else if (strncasecmp (*strp, "got(", 4) == 0) 28390+ { 28391+ bfd_vma value; 28392+ 28393+ *strp += 4; 28394+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_GOT16, 28395+ & result_type, & value); 28396+ if (**strp != ')') 28397+ return MISSING_CLOSING_PARENTHESIS; 28398+ ++*strp; 28399+ if (errmsg == NULL 28400+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28401+ value &= 0xffff; 28402+ *valuep = value; 28403+ return errmsg; 28404+ } 28405+ else if (strncasecmp (*strp, "gotpchi(", 8) == 0) 28406+ { 28407+ bfd_vma value; 28408+ 28409+ *strp += 8; 28410+ errmsg = cgen_parse_address (cd, strp, opindex, 28411+ BFD_RELOC_OR1K_GOTPC_HI16, 28412+ & result_type, & value); 28413+ if (**strp != ')') 28414+ return MISSING_CLOSING_PARENTHESIS; 28415+ ++*strp; 28416+ if (errmsg == NULL 28417+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28418+ value = (value >> 16) & 0xffff; 28419+ *valuep = value; 28420+ return errmsg; 28421+ } 28422+ else if (strncasecmp (*strp, "gotpclo(", 8) == 0) 28423+ { 28424+ bfd_vma value; 28425+ 28426+ *strp += 8; 28427+ errmsg = cgen_parse_address (cd, strp, opindex, 28428+ BFD_RELOC_OR1K_GOTPC_LO16, 28429+ &result_type, &value); 28430+ if (**strp != ')') 28431+ return MISSING_CLOSING_PARENTHESIS; 28432+ ++*strp; 28433+ if (errmsg == NULL 28434+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28435+ value &= 0xffff; 28436+ *valuep = value; 28437+ return errmsg; 28438+ } 28439+ else if (strncasecmp (*strp, "gotoffhi(", 9) == 0) 28440+ { 28441+ bfd_vma value; 28442+ 28443+ *strp += 9; 28444+ errmsg = cgen_parse_address (cd, strp, opindex, 28445+ BFD_RELOC_OR1K_GOTOFF_HI16, 28446+ & result_type, & value); 28447+ 28448+ if (**strp != ')') 28449+ return MISSING_CLOSING_PARENTHESIS; 28450+ ++*strp; 28451+ if (errmsg == NULL 28452+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28453+ value = (value >> 16) & 0xffff; 28454+ *valuep = value; 28455+ return errmsg; 28456+ } 28457+ else if (strncasecmp (*strp, "gotofflo(", 9) == 0) 28458+ { 28459+ bfd_vma value; 28460+ 28461+ *strp += 9; 28462+ errmsg = cgen_parse_address (cd, strp, opindex, 28463+ BFD_RELOC_OR1K_GOTOFF_LO16, 28464+ &result_type, &value); 28465+ if (**strp != ')') 28466+ return MISSING_CLOSING_PARENTHESIS; 28467+ ++*strp; 28468+ if (errmsg == NULL 28469+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28470+ value &= 0xffff; 28471+ *valuep = value; 28472+ return errmsg; 28473+ } 28474+ else if (strncasecmp (*strp, "tlsgdhi(", 8) == 0) 28475+ { 28476+ bfd_vma value; 28477+ 28478+ *strp += 8; 28479+ errmsg = cgen_parse_address (cd, strp, opindex, 28480+ BFD_RELOC_OR1K_TLS_GD_HI16, 28481+ & result_type, & value); 28482+ 28483+ if (**strp != ')') 28484+ return MISSING_CLOSING_PARENTHESIS; 28485+ ++*strp; 28486+ if (errmsg == NULL 28487+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28488+ value = (value >> 16) & 0xffff; 28489+ *valuep = value; 28490+ return errmsg; 28491+ } 28492+ else if (strncasecmp (*strp, "tlsgdlo(", 8) == 0) 28493+ { 28494+ bfd_vma value; 28495+ 28496+ *strp += 8; 28497+ errmsg = cgen_parse_address (cd, strp, opindex, 28498+ BFD_RELOC_OR1K_TLS_GD_LO16, 28499+ &result_type, &value); 28500+ if (**strp != ')') 28501+ return MISSING_CLOSING_PARENTHESIS; 28502+ ++*strp; 28503+ if (errmsg == NULL 28504+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28505+ value &= 0xffff; 28506+ *valuep = value; 28507+ return errmsg; 28508+ } 28509+ else if (strncasecmp (*strp, "tlsldmhi(", 9) == 0) 28510+ { 28511+ bfd_vma value; 28512+ 28513+ *strp += 9; 28514+ errmsg = cgen_parse_address (cd, strp, opindex, 28515+ BFD_RELOC_OR1K_TLS_LDM_HI16, 28516+ & result_type, & value); 28517+ 28518+ if (**strp != ')') 28519+ return MISSING_CLOSING_PARENTHESIS; 28520+ ++*strp; 28521+ if (errmsg == NULL 28522+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28523+ value = (value >> 16) & 0xffff; 28524+ *valuep = value; 28525+ return errmsg; 28526+ } 28527+ else if (strncasecmp (*strp, "tlsldmlo(", 9) == 0) 28528+ { 28529+ bfd_vma value; 28530+ 28531+ *strp += 9; 28532+ errmsg = cgen_parse_address (cd, strp, opindex, 28533+ BFD_RELOC_OR1K_TLS_LDM_LO16, 28534+ &result_type, &value); 28535+ if (**strp != ')') 28536+ return MISSING_CLOSING_PARENTHESIS; 28537+ ++*strp; 28538+ if (errmsg == NULL 28539+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28540+ value &= 0xffff; 28541+ *valuep = value; 28542+ return errmsg; 28543+ } 28544+ else if (strncasecmp (*strp, "dtpoffhi(", 9) == 0) 28545+ { 28546+ bfd_vma value; 28547+ 28548+ *strp += 9; 28549+ errmsg = cgen_parse_address (cd, strp, opindex, 28550+ BFD_RELOC_OR1K_TLS_LDO_HI16, 28551+ & result_type, & value); 28552+ 28553+ if (**strp != ')') 28554+ return MISSING_CLOSING_PARENTHESIS; 28555+ ++*strp; 28556+ if (errmsg == NULL 28557+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28558+ value = (value >> 16) & 0xffff; 28559+ *valuep = value; 28560+ return errmsg; 28561+ } 28562+ else if (strncasecmp (*strp, "dtpofflo(", 9) == 0) 28563+ { 28564+ bfd_vma value; 28565+ 28566+ *strp += 9; 28567+ errmsg = cgen_parse_address (cd, strp, opindex, 28568+ BFD_RELOC_OR1K_TLS_LDO_LO16, 28569+ &result_type, &value); 28570+ if (**strp != ')') 28571+ return MISSING_CLOSING_PARENTHESIS; 28572+ ++*strp; 28573+ if (errmsg == NULL 28574+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28575+ value &= 0xffff; 28576+ *valuep = value; 28577+ return errmsg; 28578+ } 28579+ else if (strncasecmp (*strp, "gottpoffhi(", 11) == 0) 28580+ { 28581+ bfd_vma value; 28582+ 28583+ *strp += 11; 28584+ errmsg = cgen_parse_address (cd, strp, opindex, 28585+ BFD_RELOC_OR1K_TLS_IE_HI16, 28586+ & result_type, & value); 28587+ 28588+ if (**strp != ')') 28589+ return MISSING_CLOSING_PARENTHESIS; 28590+ ++*strp; 28591+ if (errmsg == NULL 28592+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28593+ value = (value >> 16) & 0xffff; 28594+ *valuep = value; 28595+ return errmsg; 28596+ } 28597+ else if (strncasecmp (*strp, "gottpofflo(", 11) == 0) 28598+ { 28599+ bfd_vma value; 28600+ 28601+ *strp += 11; 28602+ errmsg = cgen_parse_address (cd, strp, opindex, 28603+ BFD_RELOC_OR1K_TLS_IE_LO16, 28604+ &result_type, &value); 28605+ if (**strp != ')') 28606+ return MISSING_CLOSING_PARENTHESIS; 28607+ ++*strp; 28608+ if (errmsg == NULL 28609+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28610+ value &= 0xffff; 28611+ *valuep = value; 28612+ return errmsg; 28613+ } 28614+ else if (strncasecmp (*strp, "tpoffhi(", 8) == 0) 28615+ { 28616+ bfd_vma value; 28617+ 28618+ *strp += 8; 28619+ errmsg = cgen_parse_address (cd, strp, opindex, 28620+ BFD_RELOC_OR1K_TLS_LE_HI16, 28621+ & result_type, & value); 28622+ 28623+ if (**strp != ')') 28624+ return MISSING_CLOSING_PARENTHESIS; 28625+ ++*strp; 28626+ if (errmsg == NULL 28627+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28628+ value = (value >> 16) & 0xffff; 28629+ *valuep = value; 28630+ return errmsg; 28631+ } 28632+ else if (strncasecmp (*strp, "tpofflo(", 8) == 0) 28633+ { 28634+ bfd_vma value; 28635+ 28636+ *strp += 8; 28637+ errmsg = cgen_parse_address (cd, strp, opindex, 28638+ BFD_RELOC_OR1K_TLS_LE_LO16, 28639+ &result_type, &value); 28640+ if (**strp != ')') 28641+ return MISSING_CLOSING_PARENTHESIS; 28642+ ++*strp; 28643+ if (errmsg == NULL 28644+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) 28645+ value &= 0xffff; 28646+ *valuep = value; 28647+ return errmsg; 28648+ } 28649+ else 28650+ { 28651+ long value; 28652+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); 28653+ ret = value; 28654+ } 28655+ 28656+ if (errmsg == NULL) 28657+ *valuep = ret; 28658+ 28659+ return errmsg; 28660+} 28661+ 28662+static const char * 28663+parse_uimm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep) 28664+{ 28665+ const char *errmsg = parse_simm16(cd, strp, opindex, (long *) valuep); 28666+ 28667+ if (errmsg == NULL) 28668+ *valuep &= 0xffff; 28669+ return errmsg; 28670+} 28671+ 28672+/* -- */ 28673+ 28674+const char * or1k_cgen_parse_operand 28675+ (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); 28676+ 28677+/* Main entry point for operand parsing. 28678+ 28679+ This function is basically just a big switch statement. Earlier versions 28680+ used tables to look up the function to use, but 28681+ - if the table contains both assembler and disassembler functions then 28682+ the disassembler contains much of the assembler and vice-versa, 28683+ - there's a lot of inlining possibilities as things grow, 28684+ - using a switch statement avoids the function call overhead. 28685+ 28686+ This function could be moved into `parse_insn_normal', but keeping it 28687+ separate makes clear the interface between `parse_insn_normal' and each of 28688+ the handlers. */ 28689+ 28690+const char * 28691+or1k_cgen_parse_operand (CGEN_CPU_DESC cd, 28692+ int opindex, 28693+ const char ** strp, 28694+ CGEN_FIELDS * fields) 28695+{ 28696+ const char * errmsg = NULL; 28697+ /* Used by scalar operands that still need to be parsed. */ 28698+ long junk ATTRIBUTE_UNUSED; 28699+ 28700+ switch (opindex) 28701+ { 28702+ case OR1K_OPERAND_DISP26 : 28703+ { 28704+ bfd_vma value = 0; 28705+ errmsg = parse_disp26 (cd, strp, OR1K_OPERAND_DISP26, 0, NULL, & value); 28706+ fields->f_disp26 = value; 28707+ } 28708+ break; 28709+ case OR1K_OPERAND_RA : 28710+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r2); 28711+ break; 28712+ case OR1K_OPERAND_RADF : 28713+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); 28714+ break; 28715+ case OR1K_OPERAND_RASF : 28716+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r2); 28717+ break; 28718+ case OR1K_OPERAND_RB : 28719+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r3); 28720+ break; 28721+ case OR1K_OPERAND_RBDF : 28722+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); 28723+ break; 28724+ case OR1K_OPERAND_RBSF : 28725+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r3); 28726+ break; 28727+ case OR1K_OPERAND_RD : 28728+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r1); 28729+ break; 28730+ case OR1K_OPERAND_RDDF : 28731+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); 28732+ break; 28733+ case OR1K_OPERAND_RDSF : 28734+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r1); 28735+ break; 28736+ case OR1K_OPERAND_SIMM16 : 28737+ errmsg = parse_simm16 (cd, strp, OR1K_OPERAND_SIMM16, (long *) (& fields->f_simm16)); 28738+ break; 28739+ case OR1K_OPERAND_SIMM16_SPLIT : 28740+ errmsg = parse_simm16 (cd, strp, OR1K_OPERAND_SIMM16_SPLIT, (long *) (& fields->f_simm16_split)); 28741+ break; 28742+ case OR1K_OPERAND_UIMM16 : 28743+ errmsg = parse_uimm16 (cd, strp, OR1K_OPERAND_UIMM16, (unsigned long *) (& fields->f_uimm16)); 28744+ break; 28745+ case OR1K_OPERAND_UIMM16_SPLIT : 28746+ errmsg = parse_uimm16 (cd, strp, OR1K_OPERAND_UIMM16_SPLIT, (unsigned long *) (& fields->f_uimm16_split)); 28747+ break; 28748+ case OR1K_OPERAND_UIMM6 : 28749+ errmsg = cgen_parse_unsigned_integer (cd, strp, OR1K_OPERAND_UIMM6, (unsigned long *) (& fields->f_uimm6)); 28750+ break; 28751+ 28752+ default : 28753+ /* xgettext:c-format */ 28754+ fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); 28755+ abort (); 28756+ } 28757+ 28758+ return errmsg; 28759+} 28760+ 28761+cgen_parse_fn * const or1k_cgen_parse_handlers[] = 28762+{ 28763+ parse_insn_normal, 28764+}; 28765+ 28766+void 28767+or1k_cgen_init_asm (CGEN_CPU_DESC cd) 28768+{ 28769+ or1k_cgen_init_opcode_table (cd); 28770+ or1k_cgen_init_ibld_table (cd); 28771+ cd->parse_handlers = & or1k_cgen_parse_handlers[0]; 28772+ cd->parse_operand = or1k_cgen_parse_operand; 28773+#ifdef CGEN_ASM_INIT_HOOK 28774+CGEN_ASM_INIT_HOOK 28775+#endif 28776+} 28777+ 28778+ 28779+ 28780+/* Regex construction routine. 28781+ 28782+ This translates an opcode syntax string into a regex string, 28783+ by replacing any non-character syntax element (such as an 28784+ opcode) with the pattern '.*' 28785+ 28786+ It then compiles the regex and stores it in the opcode, for 28787+ later use by or1k_cgen_assemble_insn 28788+ 28789+ Returns NULL for success, an error message for failure. */ 28790+ 28791+char * 28792+or1k_cgen_build_insn_regex (CGEN_INSN *insn) 28793+{ 28794+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); 28795+ const char *mnem = CGEN_INSN_MNEMONIC (insn); 28796+ char rxbuf[CGEN_MAX_RX_ELEMENTS]; 28797+ char *rx = rxbuf; 28798+ const CGEN_SYNTAX_CHAR_TYPE *syn; 28799+ int reg_err; 28800+ 28801+ syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); 28802+ 28803+ /* Mnemonics come first in the syntax string. */ 28804+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) 28805+ return _("missing mnemonic in syntax string"); 28806+ ++syn; 28807+ 28808+ /* Generate a case sensitive regular expression that emulates case 28809+ insensitive matching in the "C" locale. We cannot generate a case 28810+ insensitive regular expression because in Turkish locales, 'i' and 'I' 28811+ are not equal modulo case conversion. */ 28812+ 28813+ /* Copy the literal mnemonic out of the insn. */ 28814+ for (; *mnem; mnem++) 28815+ { 28816+ char c = *mnem; 28817+ 28818+ if (ISALPHA (c)) 28819+ { 28820+ *rx++ = '['; 28821+ *rx++ = TOLOWER (c); 28822+ *rx++ = TOUPPER (c); 28823+ *rx++ = ']'; 28824+ } 28825+ else 28826+ *rx++ = c; 28827+ } 28828+ 28829+ /* Copy any remaining literals from the syntax string into the rx. */ 28830+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) 28831+ { 28832+ if (CGEN_SYNTAX_CHAR_P (* syn)) 28833+ { 28834+ char c = CGEN_SYNTAX_CHAR (* syn); 28835+ 28836+ switch (c) 28837+ { 28838+ /* Escape any regex metacharacters in the syntax. */ 28839+ case '.': case '[': case '\\': 28840+ case '*': case '^': case '$': 28841+ 28842+#ifdef CGEN_ESCAPE_EXTENDED_REGEX 28843+ case '?': case '{': case '}': 28844+ case '(': case ')': case '*': 28845+ case '|': case '+': case ']': 28846+#endif 28847+ *rx++ = '\\'; 28848+ *rx++ = c; 28849+ break; 28850+ 28851+ default: 28852+ if (ISALPHA (c)) 28853+ { 28854+ *rx++ = '['; 28855+ *rx++ = TOLOWER (c); 28856+ *rx++ = TOUPPER (c); 28857+ *rx++ = ']'; 28858+ } 28859+ else 28860+ *rx++ = c; 28861+ break; 28862+ } 28863+ } 28864+ else 28865+ { 28866+ /* Replace non-syntax fields with globs. */ 28867+ *rx++ = '.'; 28868+ *rx++ = '*'; 28869+ } 28870+ } 28871+ 28872+ /* Trailing whitespace ok. */ 28873+ * rx++ = '['; 28874+ * rx++ = ' '; 28875+ * rx++ = '\t'; 28876+ * rx++ = ']'; 28877+ * rx++ = '*'; 28878+ 28879+ /* But anchor it after that. */ 28880+ * rx++ = '$'; 28881+ * rx = '\0'; 28882+ 28883+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); 28884+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); 28885+ 28886+ if (reg_err == 0) 28887+ return NULL; 28888+ else 28889+ { 28890+ static char msg[80]; 28891+ 28892+ regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); 28893+ regfree ((regex_t *) CGEN_INSN_RX (insn)); 28894+ free (CGEN_INSN_RX (insn)); 28895+ (CGEN_INSN_RX (insn)) = NULL; 28896+ return msg; 28897+ } 28898+} 28899+ 28900+ 28901+/* Default insn parser. 28902+ 28903+ The syntax string is scanned and operands are parsed and stored in FIELDS. 28904+ Relocs are queued as we go via other callbacks. 28905+ 28906+ ??? Note that this is currently an all-or-nothing parser. If we fail to 28907+ parse the instruction, we return 0 and the caller will start over from 28908+ the beginning. Backtracking will be necessary in parsing subexpressions, 28909+ but that can be handled there. Not handling backtracking here may get 28910+ expensive in the case of the m68k. Deal with later. 28911+ 28912+ Returns NULL for success, an error message for failure. */ 28913+ 28914+static const char * 28915+parse_insn_normal (CGEN_CPU_DESC cd, 28916+ const CGEN_INSN *insn, 28917+ const char **strp, 28918+ CGEN_FIELDS *fields) 28919+{ 28920+ /* ??? Runtime added insns not handled yet. */ 28921+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 28922+ const char *str = *strp; 28923+ const char *errmsg; 28924+ const char *p; 28925+ const CGEN_SYNTAX_CHAR_TYPE * syn; 28926+#ifdef CGEN_MNEMONIC_OPERANDS 28927+ /* FIXME: wip */ 28928+ int past_opcode_p; 28929+#endif 28930+ 28931+ /* For now we assume the mnemonic is first (there are no leading operands). 28932+ We can parse it without needing to set up operand parsing. 28933+ GAS's input scrubber will ensure mnemonics are lowercase, but we may 28934+ not be called from GAS. */ 28935+ p = CGEN_INSN_MNEMONIC (insn); 28936+ while (*p && TOLOWER (*p) == TOLOWER (*str)) 28937+ ++p, ++str; 28938+ 28939+ if (* p) 28940+ return _("unrecognized instruction"); 28941+ 28942+#ifndef CGEN_MNEMONIC_OPERANDS 28943+ if (* str && ! ISSPACE (* str)) 28944+ return _("unrecognized instruction"); 28945+#endif 28946+ 28947+ CGEN_INIT_PARSE (cd); 28948+ cgen_init_parse_operand (cd); 28949+#ifdef CGEN_MNEMONIC_OPERANDS 28950+ past_opcode_p = 0; 28951+#endif 28952+ 28953+ /* We don't check for (*str != '\0') here because we want to parse 28954+ any trailing fake arguments in the syntax string. */ 28955+ syn = CGEN_SYNTAX_STRING (syntax); 28956+ 28957+ /* Mnemonics come first for now, ensure valid string. */ 28958+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) 28959+ abort (); 28960+ 28961+ ++syn; 28962+ 28963+ while (* syn != 0) 28964+ { 28965+ /* Non operand chars must match exactly. */ 28966+ if (CGEN_SYNTAX_CHAR_P (* syn)) 28967+ { 28968+ /* FIXME: While we allow for non-GAS callers above, we assume the 28969+ first char after the mnemonic part is a space. */ 28970+ /* FIXME: We also take inappropriate advantage of the fact that 28971+ GAS's input scrubber will remove extraneous blanks. */ 28972+ if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) 28973+ { 28974+#ifdef CGEN_MNEMONIC_OPERANDS 28975+ if (CGEN_SYNTAX_CHAR(* syn) == ' ') 28976+ past_opcode_p = 1; 28977+#endif 28978+ ++ syn; 28979+ ++ str; 28980+ } 28981+ else if (*str) 28982+ { 28983+ /* Syntax char didn't match. Can't be this insn. */ 28984+ static char msg [80]; 28985+ 28986+ /* xgettext:c-format */ 28987+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"), 28988+ CGEN_SYNTAX_CHAR(*syn), *str); 28989+ return msg; 28990+ } 28991+ else 28992+ { 28993+ /* Ran out of input. */ 28994+ static char msg [80]; 28995+ 28996+ /* xgettext:c-format */ 28997+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), 28998+ CGEN_SYNTAX_CHAR(*syn)); 28999+ return msg; 29000+ } 29001+ continue; 29002+ } 29003+ 29004+#ifdef CGEN_MNEMONIC_OPERANDS 29005+ (void) past_opcode_p; 29006+#endif 29007+ /* We have an operand of some sort. */ 29008+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); 29009+ if (errmsg) 29010+ return errmsg; 29011+ 29012+ /* Done with this operand, continue with next one. */ 29013+ ++ syn; 29014+ } 29015+ 29016+ /* If we're at the end of the syntax string, we're done. */ 29017+ if (* syn == 0) 29018+ { 29019+ /* FIXME: For the moment we assume a valid `str' can only contain 29020+ blanks now. IE: We needn't try again with a longer version of 29021+ the insn and it is assumed that longer versions of insns appear 29022+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ 29023+ while (ISSPACE (* str)) 29024+ ++ str; 29025+ 29026+ if (* str != '\0') 29027+ return _("junk at end of line"); /* FIXME: would like to include `str' */ 29028+ 29029+ return NULL; 29030+ } 29031+ 29032+ /* We couldn't parse it. */ 29033+ return _("unrecognized instruction"); 29034+} 29035+ 29036+/* Main entry point. 29037+ This routine is called for each instruction to be assembled. 29038+ STR points to the insn to be assembled. 29039+ We assume all necessary tables have been initialized. 29040+ The assembled instruction, less any fixups, is stored in BUF. 29041+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value 29042+ still needs to be converted to target byte order, otherwise BUF is an array 29043+ of bytes in target byte order. 29044+ The result is a pointer to the insn's entry in the opcode table, 29045+ or NULL if an error occured (an error message will have already been 29046+ printed). 29047+ 29048+ Note that when processing (non-alias) macro-insns, 29049+ this function recurses. 29050+ 29051+ ??? It's possible to make this cpu-independent. 29052+ One would have to deal with a few minor things. 29053+ At this point in time doing so would be more of a curiosity than useful 29054+ [for example this file isn't _that_ big], but keeping the possibility in 29055+ mind helps keep the design clean. */ 29056+ 29057+const CGEN_INSN * 29058+or1k_cgen_assemble_insn (CGEN_CPU_DESC cd, 29059+ const char *str, 29060+ CGEN_FIELDS *fields, 29061+ CGEN_INSN_BYTES_PTR buf, 29062+ char **errmsg) 29063+{ 29064+ const char *start; 29065+ CGEN_INSN_LIST *ilist; 29066+ const char *parse_errmsg = NULL; 29067+ const char *insert_errmsg = NULL; 29068+ int recognized_mnemonic = 0; 29069+ 29070+ /* Skip leading white space. */ 29071+ while (ISSPACE (* str)) 29072+ ++ str; 29073+ 29074+ /* The instructions are stored in hashed lists. 29075+ Get the first in the list. */ 29076+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str); 29077+ 29078+ /* Keep looking until we find a match. */ 29079+ start = str; 29080+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) 29081+ { 29082+ const CGEN_INSN *insn = ilist->insn; 29083+ recognized_mnemonic = 1; 29084+ 29085+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 29086+ /* Not usually needed as unsupported opcodes 29087+ shouldn't be in the hash lists. */ 29088+ /* Is this insn supported by the selected cpu? */ 29089+ if (! or1k_cgen_insn_supported (cd, insn)) 29090+ continue; 29091+#endif 29092+ /* If the RELAXED attribute is set, this is an insn that shouldn't be 29093+ chosen immediately. Instead, it is used during assembler/linker 29094+ relaxation if possible. */ 29095+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) 29096+ continue; 29097+ 29098+ str = start; 29099+ 29100+ /* Skip this insn if str doesn't look right lexically. */ 29101+ if (CGEN_INSN_RX (insn) != NULL && 29102+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) 29103+ continue; 29104+ 29105+ /* Allow parse/insert handlers to obtain length of insn. */ 29106+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 29107+ 29108+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); 29109+ if (parse_errmsg != NULL) 29110+ continue; 29111+ 29112+ /* ??? 0 is passed for `pc'. */ 29113+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, 29114+ (bfd_vma) 0); 29115+ if (insert_errmsg != NULL) 29116+ continue; 29117+ 29118+ /* It is up to the caller to actually output the insn and any 29119+ queued relocs. */ 29120+ return insn; 29121+ } 29122+ 29123+ { 29124+ static char errbuf[150]; 29125+ const char *tmp_errmsg; 29126+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS 29127+#define be_verbose 1 29128+#else 29129+#define be_verbose 0 29130+#endif 29131+ 29132+ if (be_verbose) 29133+ { 29134+ /* If requesting verbose error messages, use insert_errmsg. 29135+ Failing that, use parse_errmsg. */ 29136+ tmp_errmsg = (insert_errmsg ? insert_errmsg : 29137+ parse_errmsg ? parse_errmsg : 29138+ recognized_mnemonic ? 29139+ _("unrecognized form of instruction") : 29140+ _("unrecognized instruction")); 29141+ 29142+ if (strlen (start) > 50) 29143+ /* xgettext:c-format */ 29144+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); 29145+ else 29146+ /* xgettext:c-format */ 29147+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); 29148+ } 29149+ else 29150+ { 29151+ if (strlen (start) > 50) 29152+ /* xgettext:c-format */ 29153+ sprintf (errbuf, _("bad instruction `%.50s...'"), start); 29154+ else 29155+ /* xgettext:c-format */ 29156+ sprintf (errbuf, _("bad instruction `%.50s'"), start); 29157+ } 29158+ 29159+ *errmsg = errbuf; 29160+ return NULL; 29161+ } 29162+} 29163diff -rNU3 dist.orig/opcodes/or1k-desc.c dist/opcodes/or1k-desc.c 29164--- dist.orig/opcodes/or1k-desc.c 1970-01-01 01:00:00.000000000 +0100 29165+++ dist/opcodes/or1k-desc.c 2015-10-18 13:11:20.000000000 +0200 29166@@ -0,0 +1,2110 @@ 29167+/* CPU data for or1k. 29168+ 29169+THIS FILE IS MACHINE GENERATED WITH CGEN. 29170+ 29171+Copyright (C) 1996-2014 Free Software Foundation, Inc. 29172+ 29173+This file is part of the GNU Binutils and/or GDB, the GNU debugger. 29174+ 29175+ This file is free software; you can redistribute it and/or modify 29176+ it under the terms of the GNU General Public License as published by 29177+ the Free Software Foundation; either version 3, or (at your option) 29178+ any later version. 29179+ 29180+ It is distributed in the hope that it will be useful, but WITHOUT 29181+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 29182+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 29183+ License for more details. 29184+ 29185+ You should have received a copy of the GNU General Public License along 29186+ with this program; if not, write to the Free Software Foundation, Inc., 29187+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 29188+ 29189+*/ 29190+ 29191+#include "sysdep.h" 29192+#include <stdio.h> 29193+#include <stdarg.h> 29194+#include "ansidecl.h" 29195+#include "bfd.h" 29196+#include "symcat.h" 29197+#include "or1k-desc.h" 29198+#include "or1k-opc.h" 29199+#include "opintl.h" 29200+#include "libiberty.h" 29201+#include "xregex.h" 29202+ 29203+/* Attributes. */ 29204+ 29205+static const CGEN_ATTR_ENTRY bool_attr[] = 29206+{ 29207+ { "#f", 0 }, 29208+ { "#t", 1 }, 29209+ { 0, 0 } 29210+}; 29211+ 29212+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 29213+{ 29214+ { "base", MACH_BASE }, 29215+ { "or32", MACH_OR32 }, 29216+ { "or32nd", MACH_OR32ND }, 29217+ { "or64", MACH_OR64 }, 29218+ { "or64nd", MACH_OR64ND }, 29219+ { "max", MACH_MAX }, 29220+ { 0, 0 } 29221+}; 29222+ 29223+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 29224+{ 29225+ { "openrisc", ISA_OPENRISC }, 29226+ { "max", ISA_MAX }, 29227+ { 0, 0 } 29228+}; 29229+ 29230+const CGEN_ATTR_TABLE or1k_cgen_ifield_attr_table[] = 29231+{ 29232+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, 29233+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 29234+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 29235+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 29236+ { "RESERVED", &bool_attr[0], &bool_attr[0] }, 29237+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 29238+ { "SIGNED", &bool_attr[0], &bool_attr[0] }, 29239+ { 0, 0, 0 } 29240+}; 29241+ 29242+const CGEN_ATTR_TABLE or1k_cgen_hardware_attr_table[] = 29243+{ 29244+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, 29245+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 29246+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 29247+ { "PC", &bool_attr[0], &bool_attr[0] }, 29248+ { "PROFILE", &bool_attr[0], &bool_attr[0] }, 29249+ { 0, 0, 0 } 29250+}; 29251+ 29252+const CGEN_ATTR_TABLE or1k_cgen_operand_attr_table[] = 29253+{ 29254+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, 29255+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 29256+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 29257+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 29258+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 29259+ { "SIGNED", &bool_attr[0], &bool_attr[0] }, 29260+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 29261+ { "RELAX", &bool_attr[0], &bool_attr[0] }, 29262+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 29263+ { 0, 0, 0 } 29264+}; 29265+ 29266+const CGEN_ATTR_TABLE or1k_cgen_insn_attr_table[] = 29267+{ 29268+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, 29269+ { "ALIAS", &bool_attr[0], &bool_attr[0] }, 29270+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 29271+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 29272+ { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 29273+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 29274+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 29275+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 29276+ { "RELAXED", &bool_attr[0], &bool_attr[0] }, 29277+ { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 29278+ { "PBB", &bool_attr[0], &bool_attr[0] }, 29279+ { "DELAYED-CTI", &bool_attr[0], &bool_attr[0] }, 29280+ { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 29281+ { "FORCED-CTI", &bool_attr[0], &bool_attr[0] }, 29282+ { 0, 0, 0 } 29283+}; 29284+ 29285+/* Instruction set variants. */ 29286+ 29287+static const CGEN_ISA or1k_cgen_isa_table[] = { 29288+ { "openrisc", 32, 32, 32, 32 }, 29289+ { 0, 0, 0, 0, 0 } 29290+}; 29291+ 29292+/* Machine variants. */ 29293+ 29294+static const CGEN_MACH or1k_cgen_mach_table[] = { 29295+ { "or32", "or1k", MACH_OR32, 0 }, 29296+ { "or32nd", "or1knd", MACH_OR32ND, 0 }, 29297+ { "or64", "or1k64", MACH_OR64, 0 }, 29298+ { "or64nd", "or1k64nd", MACH_OR64ND, 0 }, 29299+ { 0, 0, 0, 0 } 29300+}; 29301+ 29302+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] = 29303+{ 29304+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 29305+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 29306+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 29307+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 29308+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 29309+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 29310+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 29311+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 29312+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 29313+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 29314+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 29315+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 29316+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 29317+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 29318+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 29319+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, 29320+ { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, 29321+ { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, 29322+ { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, 29323+ { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, 29324+ { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, 29325+ { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, 29326+ { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, 29327+ { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, 29328+ { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, 29329+ { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, 29330+ { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, 29331+ { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, 29332+ { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, 29333+ { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, 29334+ { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, 29335+ { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, 29336+ { "lr", 9, {0, {{{0, 0}}}}, 0, 0 }, 29337+ { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, 29338+ { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } 29339+}; 29340+ 29341+CGEN_KEYWORD or1k_cgen_opval_h_fsr = 29342+{ 29343+ & or1k_cgen_opval_h_fsr_entries[0], 29344+ 35, 29345+ 0, 0, 0, 0, "" 29346+}; 29347+ 29348+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] = 29349+{ 29350+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 29351+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 29352+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 29353+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 29354+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 29355+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 29356+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 29357+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 29358+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 29359+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 29360+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 29361+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 29362+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 29363+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 29364+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 29365+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, 29366+ { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, 29367+ { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, 29368+ { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, 29369+ { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, 29370+ { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, 29371+ { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, 29372+ { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, 29373+ { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, 29374+ { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, 29375+ { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, 29376+ { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, 29377+ { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, 29378+ { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, 29379+ { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, 29380+ { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, 29381+ { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, 29382+ { "lr", 9, {0, {{{0, 0}}}}, 0, 0 }, 29383+ { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, 29384+ { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } 29385+}; 29386+ 29387+CGEN_KEYWORD or1k_cgen_opval_h_fdr = 29388+{ 29389+ & or1k_cgen_opval_h_fdr_entries[0], 29390+ 35, 29391+ 0, 0, 0, 0, "" 29392+}; 29393+ 29394+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] = 29395+{ 29396+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 29397+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 29398+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 29399+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 29400+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 29401+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 29402+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 29403+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 29404+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 29405+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 29406+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 29407+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 29408+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 29409+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 29410+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 29411+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, 29412+ { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, 29413+ { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, 29414+ { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, 29415+ { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, 29416+ { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, 29417+ { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, 29418+ { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, 29419+ { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, 29420+ { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, 29421+ { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, 29422+ { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, 29423+ { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, 29424+ { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, 29425+ { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, 29426+ { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, 29427+ { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, 29428+ { "lr", 9, {0, {{{0, 0}}}}, 0, 0 }, 29429+ { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, 29430+ { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } 29431+}; 29432+ 29433+CGEN_KEYWORD or1k_cgen_opval_h_gpr = 29434+{ 29435+ & or1k_cgen_opval_h_gpr_entries[0], 29436+ 35, 29437+ 0, 0, 0, 0, "" 29438+}; 29439+ 29440+ 29441+/* The hardware table. */ 29442+ 29443+#define A(a) (1 << CGEN_HW_##a) 29444+ 29445+const CGEN_HW_ENTRY or1k_cgen_hw_table[] = 29446+{ 29447+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 29448+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 29449+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 29450+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 29451+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 29452+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29453+ { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29454+ { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29455+ { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29456+ { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29457+ { "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29458+ { "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29459+ { "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29460+ { "h-sys-dmmucfgr", HW_H_SYS_DMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29461+ { "h-sys-immucfgr", HW_H_SYS_IMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29462+ { "h-sys-dccfgr", HW_H_SYS_DCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29463+ { "h-sys-iccfgr", HW_H_SYS_ICCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29464+ { "h-sys-dcfgr", HW_H_SYS_DCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29465+ { "h-sys-pccfgr", HW_H_SYS_PCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29466+ { "h-sys-npc", HW_H_SYS_NPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29467+ { "h-sys-sr", HW_H_SYS_SR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29468+ { "h-sys-ppc", HW_H_SYS_PPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29469+ { "h-sys-fpcsr", HW_H_SYS_FPCSR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29470+ { "h-sys-epcr0", HW_H_SYS_EPCR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29471+ { "h-sys-epcr1", HW_H_SYS_EPCR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29472+ { "h-sys-epcr2", HW_H_SYS_EPCR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29473+ { "h-sys-epcr3", HW_H_SYS_EPCR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29474+ { "h-sys-epcr4", HW_H_SYS_EPCR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29475+ { "h-sys-epcr5", HW_H_SYS_EPCR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29476+ { "h-sys-epcr6", HW_H_SYS_EPCR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29477+ { "h-sys-epcr7", HW_H_SYS_EPCR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29478+ { "h-sys-epcr8", HW_H_SYS_EPCR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29479+ { "h-sys-epcr9", HW_H_SYS_EPCR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29480+ { "h-sys-epcr10", HW_H_SYS_EPCR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29481+ { "h-sys-epcr11", HW_H_SYS_EPCR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29482+ { "h-sys-epcr12", HW_H_SYS_EPCR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29483+ { "h-sys-epcr13", HW_H_SYS_EPCR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29484+ { "h-sys-epcr14", HW_H_SYS_EPCR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29485+ { "h-sys-epcr15", HW_H_SYS_EPCR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29486+ { "h-sys-eear0", HW_H_SYS_EEAR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29487+ { "h-sys-eear1", HW_H_SYS_EEAR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29488+ { "h-sys-eear2", HW_H_SYS_EEAR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29489+ { "h-sys-eear3", HW_H_SYS_EEAR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29490+ { "h-sys-eear4", HW_H_SYS_EEAR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29491+ { "h-sys-eear5", HW_H_SYS_EEAR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29492+ { "h-sys-eear6", HW_H_SYS_EEAR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29493+ { "h-sys-eear7", HW_H_SYS_EEAR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29494+ { "h-sys-eear8", HW_H_SYS_EEAR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29495+ { "h-sys-eear9", HW_H_SYS_EEAR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29496+ { "h-sys-eear10", HW_H_SYS_EEAR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29497+ { "h-sys-eear11", HW_H_SYS_EEAR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29498+ { "h-sys-eear12", HW_H_SYS_EEAR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29499+ { "h-sys-eear13", HW_H_SYS_EEAR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29500+ { "h-sys-eear14", HW_H_SYS_EEAR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29501+ { "h-sys-eear15", HW_H_SYS_EEAR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29502+ { "h-sys-esr0", HW_H_SYS_ESR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29503+ { "h-sys-esr1", HW_H_SYS_ESR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29504+ { "h-sys-esr2", HW_H_SYS_ESR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29505+ { "h-sys-esr3", HW_H_SYS_ESR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29506+ { "h-sys-esr4", HW_H_SYS_ESR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29507+ { "h-sys-esr5", HW_H_SYS_ESR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29508+ { "h-sys-esr6", HW_H_SYS_ESR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29509+ { "h-sys-esr7", HW_H_SYS_ESR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29510+ { "h-sys-esr8", HW_H_SYS_ESR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29511+ { "h-sys-esr9", HW_H_SYS_ESR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29512+ { "h-sys-esr10", HW_H_SYS_ESR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29513+ { "h-sys-esr11", HW_H_SYS_ESR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29514+ { "h-sys-esr12", HW_H_SYS_ESR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29515+ { "h-sys-esr13", HW_H_SYS_ESR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29516+ { "h-sys-esr14", HW_H_SYS_ESR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29517+ { "h-sys-esr15", HW_H_SYS_ESR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29518+ { "h-sys-gpr0", HW_H_SYS_GPR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29519+ { "h-sys-gpr1", HW_H_SYS_GPR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29520+ { "h-sys-gpr2", HW_H_SYS_GPR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29521+ { "h-sys-gpr3", HW_H_SYS_GPR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29522+ { "h-sys-gpr4", HW_H_SYS_GPR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29523+ { "h-sys-gpr5", HW_H_SYS_GPR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29524+ { "h-sys-gpr6", HW_H_SYS_GPR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29525+ { "h-sys-gpr7", HW_H_SYS_GPR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29526+ { "h-sys-gpr8", HW_H_SYS_GPR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29527+ { "h-sys-gpr9", HW_H_SYS_GPR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29528+ { "h-sys-gpr10", HW_H_SYS_GPR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29529+ { "h-sys-gpr11", HW_H_SYS_GPR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29530+ { "h-sys-gpr12", HW_H_SYS_GPR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29531+ { "h-sys-gpr13", HW_H_SYS_GPR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29532+ { "h-sys-gpr14", HW_H_SYS_GPR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29533+ { "h-sys-gpr15", HW_H_SYS_GPR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29534+ { "h-sys-gpr16", HW_H_SYS_GPR16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29535+ { "h-sys-gpr17", HW_H_SYS_GPR17, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29536+ { "h-sys-gpr18", HW_H_SYS_GPR18, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29537+ { "h-sys-gpr19", HW_H_SYS_GPR19, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29538+ { "h-sys-gpr20", HW_H_SYS_GPR20, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29539+ { "h-sys-gpr21", HW_H_SYS_GPR21, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29540+ { "h-sys-gpr22", HW_H_SYS_GPR22, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29541+ { "h-sys-gpr23", HW_H_SYS_GPR23, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29542+ { "h-sys-gpr24", HW_H_SYS_GPR24, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29543+ { "h-sys-gpr25", HW_H_SYS_GPR25, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29544+ { "h-sys-gpr26", HW_H_SYS_GPR26, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29545+ { "h-sys-gpr27", HW_H_SYS_GPR27, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29546+ { "h-sys-gpr28", HW_H_SYS_GPR28, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29547+ { "h-sys-gpr29", HW_H_SYS_GPR29, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29548+ { "h-sys-gpr30", HW_H_SYS_GPR30, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29549+ { "h-sys-gpr31", HW_H_SYS_GPR31, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29550+ { "h-sys-gpr32", HW_H_SYS_GPR32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29551+ { "h-sys-gpr33", HW_H_SYS_GPR33, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29552+ { "h-sys-gpr34", HW_H_SYS_GPR34, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29553+ { "h-sys-gpr35", HW_H_SYS_GPR35, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29554+ { "h-sys-gpr36", HW_H_SYS_GPR36, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29555+ { "h-sys-gpr37", HW_H_SYS_GPR37, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29556+ { "h-sys-gpr38", HW_H_SYS_GPR38, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29557+ { "h-sys-gpr39", HW_H_SYS_GPR39, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29558+ { "h-sys-gpr40", HW_H_SYS_GPR40, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29559+ { "h-sys-gpr41", HW_H_SYS_GPR41, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29560+ { "h-sys-gpr42", HW_H_SYS_GPR42, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29561+ { "h-sys-gpr43", HW_H_SYS_GPR43, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29562+ { "h-sys-gpr44", HW_H_SYS_GPR44, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29563+ { "h-sys-gpr45", HW_H_SYS_GPR45, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29564+ { "h-sys-gpr46", HW_H_SYS_GPR46, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29565+ { "h-sys-gpr47", HW_H_SYS_GPR47, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29566+ { "h-sys-gpr48", HW_H_SYS_GPR48, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29567+ { "h-sys-gpr49", HW_H_SYS_GPR49, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29568+ { "h-sys-gpr50", HW_H_SYS_GPR50, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29569+ { "h-sys-gpr51", HW_H_SYS_GPR51, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29570+ { "h-sys-gpr52", HW_H_SYS_GPR52, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29571+ { "h-sys-gpr53", HW_H_SYS_GPR53, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29572+ { "h-sys-gpr54", HW_H_SYS_GPR54, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29573+ { "h-sys-gpr55", HW_H_SYS_GPR55, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29574+ { "h-sys-gpr56", HW_H_SYS_GPR56, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29575+ { "h-sys-gpr57", HW_H_SYS_GPR57, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29576+ { "h-sys-gpr58", HW_H_SYS_GPR58, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29577+ { "h-sys-gpr59", HW_H_SYS_GPR59, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29578+ { "h-sys-gpr60", HW_H_SYS_GPR60, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29579+ { "h-sys-gpr61", HW_H_SYS_GPR61, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29580+ { "h-sys-gpr62", HW_H_SYS_GPR62, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29581+ { "h-sys-gpr63", HW_H_SYS_GPR63, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29582+ { "h-sys-gpr64", HW_H_SYS_GPR64, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29583+ { "h-sys-gpr65", HW_H_SYS_GPR65, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29584+ { "h-sys-gpr66", HW_H_SYS_GPR66, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29585+ { "h-sys-gpr67", HW_H_SYS_GPR67, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29586+ { "h-sys-gpr68", HW_H_SYS_GPR68, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29587+ { "h-sys-gpr69", HW_H_SYS_GPR69, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29588+ { "h-sys-gpr70", HW_H_SYS_GPR70, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29589+ { "h-sys-gpr71", HW_H_SYS_GPR71, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29590+ { "h-sys-gpr72", HW_H_SYS_GPR72, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29591+ { "h-sys-gpr73", HW_H_SYS_GPR73, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29592+ { "h-sys-gpr74", HW_H_SYS_GPR74, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29593+ { "h-sys-gpr75", HW_H_SYS_GPR75, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29594+ { "h-sys-gpr76", HW_H_SYS_GPR76, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29595+ { "h-sys-gpr77", HW_H_SYS_GPR77, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29596+ { "h-sys-gpr78", HW_H_SYS_GPR78, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29597+ { "h-sys-gpr79", HW_H_SYS_GPR79, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29598+ { "h-sys-gpr80", HW_H_SYS_GPR80, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29599+ { "h-sys-gpr81", HW_H_SYS_GPR81, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29600+ { "h-sys-gpr82", HW_H_SYS_GPR82, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29601+ { "h-sys-gpr83", HW_H_SYS_GPR83, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29602+ { "h-sys-gpr84", HW_H_SYS_GPR84, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29603+ { "h-sys-gpr85", HW_H_SYS_GPR85, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29604+ { "h-sys-gpr86", HW_H_SYS_GPR86, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29605+ { "h-sys-gpr87", HW_H_SYS_GPR87, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29606+ { "h-sys-gpr88", HW_H_SYS_GPR88, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29607+ { "h-sys-gpr89", HW_H_SYS_GPR89, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29608+ { "h-sys-gpr90", HW_H_SYS_GPR90, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29609+ { "h-sys-gpr91", HW_H_SYS_GPR91, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29610+ { "h-sys-gpr92", HW_H_SYS_GPR92, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29611+ { "h-sys-gpr93", HW_H_SYS_GPR93, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29612+ { "h-sys-gpr94", HW_H_SYS_GPR94, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29613+ { "h-sys-gpr95", HW_H_SYS_GPR95, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29614+ { "h-sys-gpr96", HW_H_SYS_GPR96, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29615+ { "h-sys-gpr97", HW_H_SYS_GPR97, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29616+ { "h-sys-gpr98", HW_H_SYS_GPR98, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29617+ { "h-sys-gpr99", HW_H_SYS_GPR99, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29618+ { "h-sys-gpr100", HW_H_SYS_GPR100, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29619+ { "h-sys-gpr101", HW_H_SYS_GPR101, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29620+ { "h-sys-gpr102", HW_H_SYS_GPR102, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29621+ { "h-sys-gpr103", HW_H_SYS_GPR103, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29622+ { "h-sys-gpr104", HW_H_SYS_GPR104, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29623+ { "h-sys-gpr105", HW_H_SYS_GPR105, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29624+ { "h-sys-gpr106", HW_H_SYS_GPR106, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29625+ { "h-sys-gpr107", HW_H_SYS_GPR107, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29626+ { "h-sys-gpr108", HW_H_SYS_GPR108, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29627+ { "h-sys-gpr109", HW_H_SYS_GPR109, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29628+ { "h-sys-gpr110", HW_H_SYS_GPR110, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29629+ { "h-sys-gpr111", HW_H_SYS_GPR111, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29630+ { "h-sys-gpr112", HW_H_SYS_GPR112, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29631+ { "h-sys-gpr113", HW_H_SYS_GPR113, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29632+ { "h-sys-gpr114", HW_H_SYS_GPR114, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29633+ { "h-sys-gpr115", HW_H_SYS_GPR115, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29634+ { "h-sys-gpr116", HW_H_SYS_GPR116, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29635+ { "h-sys-gpr117", HW_H_SYS_GPR117, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29636+ { "h-sys-gpr118", HW_H_SYS_GPR118, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29637+ { "h-sys-gpr119", HW_H_SYS_GPR119, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29638+ { "h-sys-gpr120", HW_H_SYS_GPR120, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29639+ { "h-sys-gpr121", HW_H_SYS_GPR121, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29640+ { "h-sys-gpr122", HW_H_SYS_GPR122, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29641+ { "h-sys-gpr123", HW_H_SYS_GPR123, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29642+ { "h-sys-gpr124", HW_H_SYS_GPR124, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29643+ { "h-sys-gpr125", HW_H_SYS_GPR125, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29644+ { "h-sys-gpr126", HW_H_SYS_GPR126, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29645+ { "h-sys-gpr127", HW_H_SYS_GPR127, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29646+ { "h-sys-gpr128", HW_H_SYS_GPR128, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29647+ { "h-sys-gpr129", HW_H_SYS_GPR129, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29648+ { "h-sys-gpr130", HW_H_SYS_GPR130, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29649+ { "h-sys-gpr131", HW_H_SYS_GPR131, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29650+ { "h-sys-gpr132", HW_H_SYS_GPR132, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29651+ { "h-sys-gpr133", HW_H_SYS_GPR133, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29652+ { "h-sys-gpr134", HW_H_SYS_GPR134, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29653+ { "h-sys-gpr135", HW_H_SYS_GPR135, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29654+ { "h-sys-gpr136", HW_H_SYS_GPR136, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29655+ { "h-sys-gpr137", HW_H_SYS_GPR137, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29656+ { "h-sys-gpr138", HW_H_SYS_GPR138, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29657+ { "h-sys-gpr139", HW_H_SYS_GPR139, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29658+ { "h-sys-gpr140", HW_H_SYS_GPR140, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29659+ { "h-sys-gpr141", HW_H_SYS_GPR141, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29660+ { "h-sys-gpr142", HW_H_SYS_GPR142, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29661+ { "h-sys-gpr143", HW_H_SYS_GPR143, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29662+ { "h-sys-gpr144", HW_H_SYS_GPR144, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29663+ { "h-sys-gpr145", HW_H_SYS_GPR145, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29664+ { "h-sys-gpr146", HW_H_SYS_GPR146, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29665+ { "h-sys-gpr147", HW_H_SYS_GPR147, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29666+ { "h-sys-gpr148", HW_H_SYS_GPR148, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29667+ { "h-sys-gpr149", HW_H_SYS_GPR149, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29668+ { "h-sys-gpr150", HW_H_SYS_GPR150, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29669+ { "h-sys-gpr151", HW_H_SYS_GPR151, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29670+ { "h-sys-gpr152", HW_H_SYS_GPR152, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29671+ { "h-sys-gpr153", HW_H_SYS_GPR153, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29672+ { "h-sys-gpr154", HW_H_SYS_GPR154, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29673+ { "h-sys-gpr155", HW_H_SYS_GPR155, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29674+ { "h-sys-gpr156", HW_H_SYS_GPR156, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29675+ { "h-sys-gpr157", HW_H_SYS_GPR157, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29676+ { "h-sys-gpr158", HW_H_SYS_GPR158, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29677+ { "h-sys-gpr159", HW_H_SYS_GPR159, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29678+ { "h-sys-gpr160", HW_H_SYS_GPR160, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29679+ { "h-sys-gpr161", HW_H_SYS_GPR161, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29680+ { "h-sys-gpr162", HW_H_SYS_GPR162, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29681+ { "h-sys-gpr163", HW_H_SYS_GPR163, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29682+ { "h-sys-gpr164", HW_H_SYS_GPR164, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29683+ { "h-sys-gpr165", HW_H_SYS_GPR165, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29684+ { "h-sys-gpr166", HW_H_SYS_GPR166, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29685+ { "h-sys-gpr167", HW_H_SYS_GPR167, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29686+ { "h-sys-gpr168", HW_H_SYS_GPR168, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29687+ { "h-sys-gpr169", HW_H_SYS_GPR169, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29688+ { "h-sys-gpr170", HW_H_SYS_GPR170, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29689+ { "h-sys-gpr171", HW_H_SYS_GPR171, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29690+ { "h-sys-gpr172", HW_H_SYS_GPR172, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29691+ { "h-sys-gpr173", HW_H_SYS_GPR173, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29692+ { "h-sys-gpr174", HW_H_SYS_GPR174, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29693+ { "h-sys-gpr175", HW_H_SYS_GPR175, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29694+ { "h-sys-gpr176", HW_H_SYS_GPR176, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29695+ { "h-sys-gpr177", HW_H_SYS_GPR177, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29696+ { "h-sys-gpr178", HW_H_SYS_GPR178, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29697+ { "h-sys-gpr179", HW_H_SYS_GPR179, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29698+ { "h-sys-gpr180", HW_H_SYS_GPR180, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29699+ { "h-sys-gpr181", HW_H_SYS_GPR181, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29700+ { "h-sys-gpr182", HW_H_SYS_GPR182, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29701+ { "h-sys-gpr183", HW_H_SYS_GPR183, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29702+ { "h-sys-gpr184", HW_H_SYS_GPR184, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29703+ { "h-sys-gpr185", HW_H_SYS_GPR185, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29704+ { "h-sys-gpr186", HW_H_SYS_GPR186, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29705+ { "h-sys-gpr187", HW_H_SYS_GPR187, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29706+ { "h-sys-gpr188", HW_H_SYS_GPR188, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29707+ { "h-sys-gpr189", HW_H_SYS_GPR189, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29708+ { "h-sys-gpr190", HW_H_SYS_GPR190, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29709+ { "h-sys-gpr191", HW_H_SYS_GPR191, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29710+ { "h-sys-gpr192", HW_H_SYS_GPR192, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29711+ { "h-sys-gpr193", HW_H_SYS_GPR193, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29712+ { "h-sys-gpr194", HW_H_SYS_GPR194, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29713+ { "h-sys-gpr195", HW_H_SYS_GPR195, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29714+ { "h-sys-gpr196", HW_H_SYS_GPR196, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29715+ { "h-sys-gpr197", HW_H_SYS_GPR197, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29716+ { "h-sys-gpr198", HW_H_SYS_GPR198, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29717+ { "h-sys-gpr199", HW_H_SYS_GPR199, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29718+ { "h-sys-gpr200", HW_H_SYS_GPR200, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29719+ { "h-sys-gpr201", HW_H_SYS_GPR201, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29720+ { "h-sys-gpr202", HW_H_SYS_GPR202, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29721+ { "h-sys-gpr203", HW_H_SYS_GPR203, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29722+ { "h-sys-gpr204", HW_H_SYS_GPR204, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29723+ { "h-sys-gpr205", HW_H_SYS_GPR205, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29724+ { "h-sys-gpr206", HW_H_SYS_GPR206, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29725+ { "h-sys-gpr207", HW_H_SYS_GPR207, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29726+ { "h-sys-gpr208", HW_H_SYS_GPR208, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29727+ { "h-sys-gpr209", HW_H_SYS_GPR209, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29728+ { "h-sys-gpr210", HW_H_SYS_GPR210, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29729+ { "h-sys-gpr211", HW_H_SYS_GPR211, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29730+ { "h-sys-gpr212", HW_H_SYS_GPR212, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29731+ { "h-sys-gpr213", HW_H_SYS_GPR213, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29732+ { "h-sys-gpr214", HW_H_SYS_GPR214, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29733+ { "h-sys-gpr215", HW_H_SYS_GPR215, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29734+ { "h-sys-gpr216", HW_H_SYS_GPR216, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29735+ { "h-sys-gpr217", HW_H_SYS_GPR217, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29736+ { "h-sys-gpr218", HW_H_SYS_GPR218, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29737+ { "h-sys-gpr219", HW_H_SYS_GPR219, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29738+ { "h-sys-gpr220", HW_H_SYS_GPR220, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29739+ { "h-sys-gpr221", HW_H_SYS_GPR221, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29740+ { "h-sys-gpr222", HW_H_SYS_GPR222, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29741+ { "h-sys-gpr223", HW_H_SYS_GPR223, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29742+ { "h-sys-gpr224", HW_H_SYS_GPR224, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29743+ { "h-sys-gpr225", HW_H_SYS_GPR225, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29744+ { "h-sys-gpr226", HW_H_SYS_GPR226, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29745+ { "h-sys-gpr227", HW_H_SYS_GPR227, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29746+ { "h-sys-gpr228", HW_H_SYS_GPR228, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29747+ { "h-sys-gpr229", HW_H_SYS_GPR229, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29748+ { "h-sys-gpr230", HW_H_SYS_GPR230, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29749+ { "h-sys-gpr231", HW_H_SYS_GPR231, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29750+ { "h-sys-gpr232", HW_H_SYS_GPR232, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29751+ { "h-sys-gpr233", HW_H_SYS_GPR233, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29752+ { "h-sys-gpr234", HW_H_SYS_GPR234, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29753+ { "h-sys-gpr235", HW_H_SYS_GPR235, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29754+ { "h-sys-gpr236", HW_H_SYS_GPR236, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29755+ { "h-sys-gpr237", HW_H_SYS_GPR237, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29756+ { "h-sys-gpr238", HW_H_SYS_GPR238, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29757+ { "h-sys-gpr239", HW_H_SYS_GPR239, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29758+ { "h-sys-gpr240", HW_H_SYS_GPR240, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29759+ { "h-sys-gpr241", HW_H_SYS_GPR241, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29760+ { "h-sys-gpr242", HW_H_SYS_GPR242, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29761+ { "h-sys-gpr243", HW_H_SYS_GPR243, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29762+ { "h-sys-gpr244", HW_H_SYS_GPR244, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29763+ { "h-sys-gpr245", HW_H_SYS_GPR245, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29764+ { "h-sys-gpr246", HW_H_SYS_GPR246, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29765+ { "h-sys-gpr247", HW_H_SYS_GPR247, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29766+ { "h-sys-gpr248", HW_H_SYS_GPR248, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29767+ { "h-sys-gpr249", HW_H_SYS_GPR249, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29768+ { "h-sys-gpr250", HW_H_SYS_GPR250, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29769+ { "h-sys-gpr251", HW_H_SYS_GPR251, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29770+ { "h-sys-gpr252", HW_H_SYS_GPR252, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29771+ { "h-sys-gpr253", HW_H_SYS_GPR253, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29772+ { "h-sys-gpr254", HW_H_SYS_GPR254, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29773+ { "h-sys-gpr255", HW_H_SYS_GPR255, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29774+ { "h-sys-gpr256", HW_H_SYS_GPR256, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29775+ { "h-sys-gpr257", HW_H_SYS_GPR257, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29776+ { "h-sys-gpr258", HW_H_SYS_GPR258, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29777+ { "h-sys-gpr259", HW_H_SYS_GPR259, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29778+ { "h-sys-gpr260", HW_H_SYS_GPR260, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29779+ { "h-sys-gpr261", HW_H_SYS_GPR261, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29780+ { "h-sys-gpr262", HW_H_SYS_GPR262, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29781+ { "h-sys-gpr263", HW_H_SYS_GPR263, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29782+ { "h-sys-gpr264", HW_H_SYS_GPR264, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29783+ { "h-sys-gpr265", HW_H_SYS_GPR265, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29784+ { "h-sys-gpr266", HW_H_SYS_GPR266, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29785+ { "h-sys-gpr267", HW_H_SYS_GPR267, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29786+ { "h-sys-gpr268", HW_H_SYS_GPR268, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29787+ { "h-sys-gpr269", HW_H_SYS_GPR269, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29788+ { "h-sys-gpr270", HW_H_SYS_GPR270, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29789+ { "h-sys-gpr271", HW_H_SYS_GPR271, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29790+ { "h-sys-gpr272", HW_H_SYS_GPR272, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29791+ { "h-sys-gpr273", HW_H_SYS_GPR273, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29792+ { "h-sys-gpr274", HW_H_SYS_GPR274, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29793+ { "h-sys-gpr275", HW_H_SYS_GPR275, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29794+ { "h-sys-gpr276", HW_H_SYS_GPR276, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29795+ { "h-sys-gpr277", HW_H_SYS_GPR277, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29796+ { "h-sys-gpr278", HW_H_SYS_GPR278, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29797+ { "h-sys-gpr279", HW_H_SYS_GPR279, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29798+ { "h-sys-gpr280", HW_H_SYS_GPR280, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29799+ { "h-sys-gpr281", HW_H_SYS_GPR281, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29800+ { "h-sys-gpr282", HW_H_SYS_GPR282, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29801+ { "h-sys-gpr283", HW_H_SYS_GPR283, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29802+ { "h-sys-gpr284", HW_H_SYS_GPR284, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29803+ { "h-sys-gpr285", HW_H_SYS_GPR285, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29804+ { "h-sys-gpr286", HW_H_SYS_GPR286, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29805+ { "h-sys-gpr287", HW_H_SYS_GPR287, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29806+ { "h-sys-gpr288", HW_H_SYS_GPR288, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29807+ { "h-sys-gpr289", HW_H_SYS_GPR289, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29808+ { "h-sys-gpr290", HW_H_SYS_GPR290, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29809+ { "h-sys-gpr291", HW_H_SYS_GPR291, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29810+ { "h-sys-gpr292", HW_H_SYS_GPR292, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29811+ { "h-sys-gpr293", HW_H_SYS_GPR293, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29812+ { "h-sys-gpr294", HW_H_SYS_GPR294, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29813+ { "h-sys-gpr295", HW_H_SYS_GPR295, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29814+ { "h-sys-gpr296", HW_H_SYS_GPR296, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29815+ { "h-sys-gpr297", HW_H_SYS_GPR297, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29816+ { "h-sys-gpr298", HW_H_SYS_GPR298, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29817+ { "h-sys-gpr299", HW_H_SYS_GPR299, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29818+ { "h-sys-gpr300", HW_H_SYS_GPR300, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29819+ { "h-sys-gpr301", HW_H_SYS_GPR301, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29820+ { "h-sys-gpr302", HW_H_SYS_GPR302, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29821+ { "h-sys-gpr303", HW_H_SYS_GPR303, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29822+ { "h-sys-gpr304", HW_H_SYS_GPR304, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29823+ { "h-sys-gpr305", HW_H_SYS_GPR305, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29824+ { "h-sys-gpr306", HW_H_SYS_GPR306, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29825+ { "h-sys-gpr307", HW_H_SYS_GPR307, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29826+ { "h-sys-gpr308", HW_H_SYS_GPR308, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29827+ { "h-sys-gpr309", HW_H_SYS_GPR309, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29828+ { "h-sys-gpr310", HW_H_SYS_GPR310, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29829+ { "h-sys-gpr311", HW_H_SYS_GPR311, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29830+ { "h-sys-gpr312", HW_H_SYS_GPR312, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29831+ { "h-sys-gpr313", HW_H_SYS_GPR313, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29832+ { "h-sys-gpr314", HW_H_SYS_GPR314, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29833+ { "h-sys-gpr315", HW_H_SYS_GPR315, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29834+ { "h-sys-gpr316", HW_H_SYS_GPR316, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29835+ { "h-sys-gpr317", HW_H_SYS_GPR317, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29836+ { "h-sys-gpr318", HW_H_SYS_GPR318, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29837+ { "h-sys-gpr319", HW_H_SYS_GPR319, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29838+ { "h-sys-gpr320", HW_H_SYS_GPR320, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29839+ { "h-sys-gpr321", HW_H_SYS_GPR321, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29840+ { "h-sys-gpr322", HW_H_SYS_GPR322, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29841+ { "h-sys-gpr323", HW_H_SYS_GPR323, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29842+ { "h-sys-gpr324", HW_H_SYS_GPR324, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29843+ { "h-sys-gpr325", HW_H_SYS_GPR325, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29844+ { "h-sys-gpr326", HW_H_SYS_GPR326, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29845+ { "h-sys-gpr327", HW_H_SYS_GPR327, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29846+ { "h-sys-gpr328", HW_H_SYS_GPR328, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29847+ { "h-sys-gpr329", HW_H_SYS_GPR329, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29848+ { "h-sys-gpr330", HW_H_SYS_GPR330, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29849+ { "h-sys-gpr331", HW_H_SYS_GPR331, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29850+ { "h-sys-gpr332", HW_H_SYS_GPR332, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29851+ { "h-sys-gpr333", HW_H_SYS_GPR333, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29852+ { "h-sys-gpr334", HW_H_SYS_GPR334, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29853+ { "h-sys-gpr335", HW_H_SYS_GPR335, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29854+ { "h-sys-gpr336", HW_H_SYS_GPR336, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29855+ { "h-sys-gpr337", HW_H_SYS_GPR337, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29856+ { "h-sys-gpr338", HW_H_SYS_GPR338, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29857+ { "h-sys-gpr339", HW_H_SYS_GPR339, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29858+ { "h-sys-gpr340", HW_H_SYS_GPR340, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29859+ { "h-sys-gpr341", HW_H_SYS_GPR341, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29860+ { "h-sys-gpr342", HW_H_SYS_GPR342, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29861+ { "h-sys-gpr343", HW_H_SYS_GPR343, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29862+ { "h-sys-gpr344", HW_H_SYS_GPR344, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29863+ { "h-sys-gpr345", HW_H_SYS_GPR345, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29864+ { "h-sys-gpr346", HW_H_SYS_GPR346, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29865+ { "h-sys-gpr347", HW_H_SYS_GPR347, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29866+ { "h-sys-gpr348", HW_H_SYS_GPR348, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29867+ { "h-sys-gpr349", HW_H_SYS_GPR349, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29868+ { "h-sys-gpr350", HW_H_SYS_GPR350, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29869+ { "h-sys-gpr351", HW_H_SYS_GPR351, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29870+ { "h-sys-gpr352", HW_H_SYS_GPR352, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29871+ { "h-sys-gpr353", HW_H_SYS_GPR353, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29872+ { "h-sys-gpr354", HW_H_SYS_GPR354, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29873+ { "h-sys-gpr355", HW_H_SYS_GPR355, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29874+ { "h-sys-gpr356", HW_H_SYS_GPR356, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29875+ { "h-sys-gpr357", HW_H_SYS_GPR357, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29876+ { "h-sys-gpr358", HW_H_SYS_GPR358, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29877+ { "h-sys-gpr359", HW_H_SYS_GPR359, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29878+ { "h-sys-gpr360", HW_H_SYS_GPR360, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29879+ { "h-sys-gpr361", HW_H_SYS_GPR361, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29880+ { "h-sys-gpr362", HW_H_SYS_GPR362, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29881+ { "h-sys-gpr363", HW_H_SYS_GPR363, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29882+ { "h-sys-gpr364", HW_H_SYS_GPR364, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29883+ { "h-sys-gpr365", HW_H_SYS_GPR365, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29884+ { "h-sys-gpr366", HW_H_SYS_GPR366, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29885+ { "h-sys-gpr367", HW_H_SYS_GPR367, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29886+ { "h-sys-gpr368", HW_H_SYS_GPR368, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29887+ { "h-sys-gpr369", HW_H_SYS_GPR369, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29888+ { "h-sys-gpr370", HW_H_SYS_GPR370, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29889+ { "h-sys-gpr371", HW_H_SYS_GPR371, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29890+ { "h-sys-gpr372", HW_H_SYS_GPR372, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29891+ { "h-sys-gpr373", HW_H_SYS_GPR373, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29892+ { "h-sys-gpr374", HW_H_SYS_GPR374, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29893+ { "h-sys-gpr375", HW_H_SYS_GPR375, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29894+ { "h-sys-gpr376", HW_H_SYS_GPR376, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29895+ { "h-sys-gpr377", HW_H_SYS_GPR377, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29896+ { "h-sys-gpr378", HW_H_SYS_GPR378, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29897+ { "h-sys-gpr379", HW_H_SYS_GPR379, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29898+ { "h-sys-gpr380", HW_H_SYS_GPR380, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29899+ { "h-sys-gpr381", HW_H_SYS_GPR381, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29900+ { "h-sys-gpr382", HW_H_SYS_GPR382, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29901+ { "h-sys-gpr383", HW_H_SYS_GPR383, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29902+ { "h-sys-gpr384", HW_H_SYS_GPR384, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29903+ { "h-sys-gpr385", HW_H_SYS_GPR385, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29904+ { "h-sys-gpr386", HW_H_SYS_GPR386, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29905+ { "h-sys-gpr387", HW_H_SYS_GPR387, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29906+ { "h-sys-gpr388", HW_H_SYS_GPR388, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29907+ { "h-sys-gpr389", HW_H_SYS_GPR389, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29908+ { "h-sys-gpr390", HW_H_SYS_GPR390, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29909+ { "h-sys-gpr391", HW_H_SYS_GPR391, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29910+ { "h-sys-gpr392", HW_H_SYS_GPR392, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29911+ { "h-sys-gpr393", HW_H_SYS_GPR393, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29912+ { "h-sys-gpr394", HW_H_SYS_GPR394, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29913+ { "h-sys-gpr395", HW_H_SYS_GPR395, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29914+ { "h-sys-gpr396", HW_H_SYS_GPR396, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29915+ { "h-sys-gpr397", HW_H_SYS_GPR397, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29916+ { "h-sys-gpr398", HW_H_SYS_GPR398, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29917+ { "h-sys-gpr399", HW_H_SYS_GPR399, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29918+ { "h-sys-gpr400", HW_H_SYS_GPR400, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29919+ { "h-sys-gpr401", HW_H_SYS_GPR401, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29920+ { "h-sys-gpr402", HW_H_SYS_GPR402, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29921+ { "h-sys-gpr403", HW_H_SYS_GPR403, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29922+ { "h-sys-gpr404", HW_H_SYS_GPR404, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29923+ { "h-sys-gpr405", HW_H_SYS_GPR405, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29924+ { "h-sys-gpr406", HW_H_SYS_GPR406, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29925+ { "h-sys-gpr407", HW_H_SYS_GPR407, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29926+ { "h-sys-gpr408", HW_H_SYS_GPR408, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29927+ { "h-sys-gpr409", HW_H_SYS_GPR409, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29928+ { "h-sys-gpr410", HW_H_SYS_GPR410, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29929+ { "h-sys-gpr411", HW_H_SYS_GPR411, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29930+ { "h-sys-gpr412", HW_H_SYS_GPR412, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29931+ { "h-sys-gpr413", HW_H_SYS_GPR413, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29932+ { "h-sys-gpr414", HW_H_SYS_GPR414, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29933+ { "h-sys-gpr415", HW_H_SYS_GPR415, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29934+ { "h-sys-gpr416", HW_H_SYS_GPR416, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29935+ { "h-sys-gpr417", HW_H_SYS_GPR417, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29936+ { "h-sys-gpr418", HW_H_SYS_GPR418, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29937+ { "h-sys-gpr419", HW_H_SYS_GPR419, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29938+ { "h-sys-gpr420", HW_H_SYS_GPR420, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29939+ { "h-sys-gpr421", HW_H_SYS_GPR421, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29940+ { "h-sys-gpr422", HW_H_SYS_GPR422, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29941+ { "h-sys-gpr423", HW_H_SYS_GPR423, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29942+ { "h-sys-gpr424", HW_H_SYS_GPR424, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29943+ { "h-sys-gpr425", HW_H_SYS_GPR425, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29944+ { "h-sys-gpr426", HW_H_SYS_GPR426, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29945+ { "h-sys-gpr427", HW_H_SYS_GPR427, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29946+ { "h-sys-gpr428", HW_H_SYS_GPR428, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29947+ { "h-sys-gpr429", HW_H_SYS_GPR429, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29948+ { "h-sys-gpr430", HW_H_SYS_GPR430, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29949+ { "h-sys-gpr431", HW_H_SYS_GPR431, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29950+ { "h-sys-gpr432", HW_H_SYS_GPR432, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29951+ { "h-sys-gpr433", HW_H_SYS_GPR433, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29952+ { "h-sys-gpr434", HW_H_SYS_GPR434, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29953+ { "h-sys-gpr435", HW_H_SYS_GPR435, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29954+ { "h-sys-gpr436", HW_H_SYS_GPR436, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29955+ { "h-sys-gpr437", HW_H_SYS_GPR437, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29956+ { "h-sys-gpr438", HW_H_SYS_GPR438, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29957+ { "h-sys-gpr439", HW_H_SYS_GPR439, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29958+ { "h-sys-gpr440", HW_H_SYS_GPR440, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29959+ { "h-sys-gpr441", HW_H_SYS_GPR441, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29960+ { "h-sys-gpr442", HW_H_SYS_GPR442, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29961+ { "h-sys-gpr443", HW_H_SYS_GPR443, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29962+ { "h-sys-gpr444", HW_H_SYS_GPR444, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29963+ { "h-sys-gpr445", HW_H_SYS_GPR445, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29964+ { "h-sys-gpr446", HW_H_SYS_GPR446, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29965+ { "h-sys-gpr447", HW_H_SYS_GPR447, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29966+ { "h-sys-gpr448", HW_H_SYS_GPR448, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29967+ { "h-sys-gpr449", HW_H_SYS_GPR449, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29968+ { "h-sys-gpr450", HW_H_SYS_GPR450, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29969+ { "h-sys-gpr451", HW_H_SYS_GPR451, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29970+ { "h-sys-gpr452", HW_H_SYS_GPR452, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29971+ { "h-sys-gpr453", HW_H_SYS_GPR453, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29972+ { "h-sys-gpr454", HW_H_SYS_GPR454, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29973+ { "h-sys-gpr455", HW_H_SYS_GPR455, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29974+ { "h-sys-gpr456", HW_H_SYS_GPR456, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29975+ { "h-sys-gpr457", HW_H_SYS_GPR457, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29976+ { "h-sys-gpr458", HW_H_SYS_GPR458, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29977+ { "h-sys-gpr459", HW_H_SYS_GPR459, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29978+ { "h-sys-gpr460", HW_H_SYS_GPR460, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29979+ { "h-sys-gpr461", HW_H_SYS_GPR461, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29980+ { "h-sys-gpr462", HW_H_SYS_GPR462, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29981+ { "h-sys-gpr463", HW_H_SYS_GPR463, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29982+ { "h-sys-gpr464", HW_H_SYS_GPR464, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29983+ { "h-sys-gpr465", HW_H_SYS_GPR465, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29984+ { "h-sys-gpr466", HW_H_SYS_GPR466, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29985+ { "h-sys-gpr467", HW_H_SYS_GPR467, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29986+ { "h-sys-gpr468", HW_H_SYS_GPR468, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29987+ { "h-sys-gpr469", HW_H_SYS_GPR469, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29988+ { "h-sys-gpr470", HW_H_SYS_GPR470, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29989+ { "h-sys-gpr471", HW_H_SYS_GPR471, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29990+ { "h-sys-gpr472", HW_H_SYS_GPR472, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29991+ { "h-sys-gpr473", HW_H_SYS_GPR473, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29992+ { "h-sys-gpr474", HW_H_SYS_GPR474, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29993+ { "h-sys-gpr475", HW_H_SYS_GPR475, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29994+ { "h-sys-gpr476", HW_H_SYS_GPR476, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29995+ { "h-sys-gpr477", HW_H_SYS_GPR477, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29996+ { "h-sys-gpr478", HW_H_SYS_GPR478, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29997+ { "h-sys-gpr479", HW_H_SYS_GPR479, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29998+ { "h-sys-gpr480", HW_H_SYS_GPR480, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 29999+ { "h-sys-gpr481", HW_H_SYS_GPR481, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30000+ { "h-sys-gpr482", HW_H_SYS_GPR482, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30001+ { "h-sys-gpr483", HW_H_SYS_GPR483, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30002+ { "h-sys-gpr484", HW_H_SYS_GPR484, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30003+ { "h-sys-gpr485", HW_H_SYS_GPR485, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30004+ { "h-sys-gpr486", HW_H_SYS_GPR486, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30005+ { "h-sys-gpr487", HW_H_SYS_GPR487, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30006+ { "h-sys-gpr488", HW_H_SYS_GPR488, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30007+ { "h-sys-gpr489", HW_H_SYS_GPR489, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30008+ { "h-sys-gpr490", HW_H_SYS_GPR490, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30009+ { "h-sys-gpr491", HW_H_SYS_GPR491, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30010+ { "h-sys-gpr492", HW_H_SYS_GPR492, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30011+ { "h-sys-gpr493", HW_H_SYS_GPR493, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30012+ { "h-sys-gpr494", HW_H_SYS_GPR494, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30013+ { "h-sys-gpr495", HW_H_SYS_GPR495, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30014+ { "h-sys-gpr496", HW_H_SYS_GPR496, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30015+ { "h-sys-gpr497", HW_H_SYS_GPR497, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30016+ { "h-sys-gpr498", HW_H_SYS_GPR498, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30017+ { "h-sys-gpr499", HW_H_SYS_GPR499, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30018+ { "h-sys-gpr500", HW_H_SYS_GPR500, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30019+ { "h-sys-gpr501", HW_H_SYS_GPR501, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30020+ { "h-sys-gpr502", HW_H_SYS_GPR502, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30021+ { "h-sys-gpr503", HW_H_SYS_GPR503, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30022+ { "h-sys-gpr504", HW_H_SYS_GPR504, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30023+ { "h-sys-gpr505", HW_H_SYS_GPR505, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30024+ { "h-sys-gpr506", HW_H_SYS_GPR506, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30025+ { "h-sys-gpr507", HW_H_SYS_GPR507, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30026+ { "h-sys-gpr508", HW_H_SYS_GPR508, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30027+ { "h-sys-gpr509", HW_H_SYS_GPR509, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30028+ { "h-sys-gpr510", HW_H_SYS_GPR510, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30029+ { "h-sys-gpr511", HW_H_SYS_GPR511, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30030+ { "h-mac-maclo", HW_H_MAC_MACLO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30031+ { "h-mac-machi", HW_H_MAC_MACHI, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30032+ { "h-tick-ttmr", HW_H_TICK_TTMR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30033+ { "h-sys-vr-rev", HW_H_SYS_VR_REV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30034+ { "h-sys-vr-cfg", HW_H_SYS_VR_CFG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30035+ { "h-sys-vr-ver", HW_H_SYS_VR_VER, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30036+ { "h-sys-upr-up", HW_H_SYS_UPR_UP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30037+ { "h-sys-upr-dcp", HW_H_SYS_UPR_DCP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30038+ { "h-sys-upr-icp", HW_H_SYS_UPR_ICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30039+ { "h-sys-upr-dmp", HW_H_SYS_UPR_DMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30040+ { "h-sys-upr-mp", HW_H_SYS_UPR_MP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30041+ { "h-sys-upr-imp", HW_H_SYS_UPR_IMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30042+ { "h-sys-upr-dup", HW_H_SYS_UPR_DUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30043+ { "h-sys-upr-pcup", HW_H_SYS_UPR_PCUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30044+ { "h-sys-upr-picp", HW_H_SYS_UPR_PICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30045+ { "h-sys-upr-pmp", HW_H_SYS_UPR_PMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30046+ { "h-sys-upr-ttp", HW_H_SYS_UPR_TTP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30047+ { "h-sys-upr-cup", HW_H_SYS_UPR_CUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30048+ { "h-sys-cpucfgr-nsgr", HW_H_SYS_CPUCFGR_NSGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30049+ { "h-sys-cpucfgr-cgf", HW_H_SYS_CPUCFGR_CGF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30050+ { "h-sys-cpucfgr-ob32s", HW_H_SYS_CPUCFGR_OB32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30051+ { "h-sys-cpucfgr-ob64s", HW_H_SYS_CPUCFGR_OB64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30052+ { "h-sys-cpucfgr-of32s", HW_H_SYS_CPUCFGR_OF32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30053+ { "h-sys-cpucfgr-of64s", HW_H_SYS_CPUCFGR_OF64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30054+ { "h-sys-cpucfgr-ov64s", HW_H_SYS_CPUCFGR_OV64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30055+ { "h-sys-cpucfgr-nd", HW_H_SYS_CPUCFGR_ND, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30056+ { "h-sys-sr-sm", HW_H_SYS_SR_SM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30057+ { "h-sys-sr-tee", HW_H_SYS_SR_TEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30058+ { "h-sys-sr-iee", HW_H_SYS_SR_IEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30059+ { "h-sys-sr-dce", HW_H_SYS_SR_DCE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30060+ { "h-sys-sr-ice", HW_H_SYS_SR_ICE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30061+ { "h-sys-sr-dme", HW_H_SYS_SR_DME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30062+ { "h-sys-sr-ime", HW_H_SYS_SR_IME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30063+ { "h-sys-sr-lee", HW_H_SYS_SR_LEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30064+ { "h-sys-sr-ce", HW_H_SYS_SR_CE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30065+ { "h-sys-sr-f", HW_H_SYS_SR_F, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30066+ { "h-sys-sr-cy", HW_H_SYS_SR_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30067+ { "h-sys-sr-ov", HW_H_SYS_SR_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30068+ { "h-sys-sr-ove", HW_H_SYS_SR_OVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30069+ { "h-sys-sr-dsx", HW_H_SYS_SR_DSX, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30070+ { "h-sys-sr-eph", HW_H_SYS_SR_EPH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30071+ { "h-sys-sr-fo", HW_H_SYS_SR_FO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30072+ { "h-sys-sr-sumra", HW_H_SYS_SR_SUMRA, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30073+ { "h-sys-sr-cid", HW_H_SYS_SR_CID, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30074+ { "h-sys-fpcsr-fpee", HW_H_SYS_FPCSR_FPEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30075+ { "h-sys-fpcsr-rm", HW_H_SYS_FPCSR_RM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30076+ { "h-sys-fpcsr-ovf", HW_H_SYS_FPCSR_OVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30077+ { "h-sys-fpcsr-unf", HW_H_SYS_FPCSR_UNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30078+ { "h-sys-fpcsr-snf", HW_H_SYS_FPCSR_SNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30079+ { "h-sys-fpcsr-qnf", HW_H_SYS_FPCSR_QNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30080+ { "h-sys-fpcsr-zf", HW_H_SYS_FPCSR_ZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30081+ { "h-sys-fpcsr-ixf", HW_H_SYS_FPCSR_IXF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30082+ { "h-sys-fpcsr-ivf", HW_H_SYS_FPCSR_IVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30083+ { "h-sys-fpcsr-inf", HW_H_SYS_FPCSR_INF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30084+ { "h-sys-fpcsr-dzf", HW_H_SYS_FPCSR_DZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30085+ { "h-simm16", HW_H_SIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30086+ { "h-uimm16", HW_H_UIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 30087+ { "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 30088+ { "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 30089+ { "h-atomic-address", HW_H_ATOMIC_ADDRESS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 30090+ { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 30091+}; 30092+ 30093+#undef A 30094+ 30095+ 30096+/* The instruction field table. */ 30097+ 30098+#define A(a) (1 << CGEN_IFLD_##a) 30099+ 30100+const CGEN_IFLD or1k_cgen_ifld_table[] = 30101+{ 30102+ { OR1K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 30103+ { OR1K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 30104+ { OR1K_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30105+ { OR1K_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30106+ { OR1K_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30107+ { OR1K_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30108+ { OR1K_F_OP_25_2, "f-op-25-2", 0, 32, 25, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30109+ { OR1K_F_OP_25_5, "f-op-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30110+ { OR1K_F_OP_16_1, "f-op-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30111+ { OR1K_F_OP_7_4, "f-op-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30112+ { OR1K_F_OP_3_4, "f-op-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30113+ { OR1K_F_OP_9_2, "f-op-9-2", 0, 32, 9, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30114+ { OR1K_F_OP_9_4, "f-op-9-4", 0, 32, 9, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30115+ { OR1K_F_OP_7_8, "f-op-7-8", 0, 32, 7, 8, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30116+ { OR1K_F_OP_7_2, "f-op-7-2", 0, 32, 7, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30117+ { OR1K_F_RESV_25_26, "f-resv-25-26", 0, 32, 25, 26, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30118+ { OR1K_F_RESV_25_10, "f-resv-25-10", 0, 32, 25, 10, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30119+ { OR1K_F_RESV_25_5, "f-resv-25-5", 0, 32, 25, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30120+ { OR1K_F_RESV_23_8, "f-resv-23-8", 0, 32, 23, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30121+ { OR1K_F_RESV_20_21, "f-resv-20-21", 0, 32, 20, 21, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30122+ { OR1K_F_RESV_20_5, "f-resv-20-5", 0, 32, 20, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30123+ { OR1K_F_RESV_20_4, "f-resv-20-4", 0, 32, 20, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30124+ { OR1K_F_RESV_15_8, "f-resv-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30125+ { OR1K_F_RESV_15_6, "f-resv-15-6", 0, 32, 15, 6, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30126+ { OR1K_F_RESV_10_11, "f-resv-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30127+ { OR1K_F_RESV_10_7, "f-resv-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30128+ { OR1K_F_RESV_10_3, "f-resv-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30129+ { OR1K_F_RESV_10_1, "f-resv-10-1", 0, 32, 10, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30130+ { OR1K_F_RESV_7_4, "f-resv-7-4", 0, 32, 7, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30131+ { OR1K_F_RESV_5_2, "f-resv-5-2", 0, 32, 5, 2, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30132+ { OR1K_F_IMM16_25_5, "f-imm16-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30133+ { OR1K_F_IMM16_10_11, "f-imm16-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30134+ { OR1K_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30135+ { OR1K_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30136+ { OR1K_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30137+ { OR1K_F_UIMM6, "f-uimm6", 0, 32, 5, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30138+ { OR1K_F_UIMM16_SPLIT, "f-uimm16-split", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30139+ { OR1K_F_SIMM16_SPLIT, "f-simm16-split", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30140+ { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 30141+}; 30142+ 30143+#undef A 30144+ 30145+ 30146+ 30147+/* multi ifield declarations */ 30148+ 30149+const CGEN_MAYBE_MULTI_IFLD OR1K_F_UIMM16_SPLIT_MULTI_IFIELD []; 30150+const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD []; 30151+ 30152+ 30153+/* multi ifield definitions */ 30154+ 30155+const CGEN_MAYBE_MULTI_IFLD OR1K_F_UIMM16_SPLIT_MULTI_IFIELD [] = 30156+{ 30157+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } }, 30158+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } }, 30159+ { 0, { (const PTR) 0 } } 30160+}; 30161+const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [] = 30162+{ 30163+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } }, 30164+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } }, 30165+ { 0, { (const PTR) 0 } } 30166+}; 30167+ 30168+/* The operand table. */ 30169+ 30170+#define A(a) (1 << CGEN_OPERAND_##a) 30171+#define OPERAND(op) OR1K_OPERAND_##op 30172+ 30173+const CGEN_OPERAND or1k_cgen_operand_table[] = 30174+{ 30175+/* pc: program counter */ 30176+ { "pc", OR1K_OPERAND_PC, HW_H_PC, 0, 0, 30177+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } }, 30178+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 30179+/* sys-sr: supervision register */ 30180+ { "sys-sr", OR1K_OPERAND_SYS_SR, HW_H_SYS_SR, 0, 0, 30181+ { 0, { (const PTR) 0 } }, 30182+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30183+/* sys-esr0: exception supervision register 0 */ 30184+ { "sys-esr0", OR1K_OPERAND_SYS_ESR0, HW_H_SYS_ESR0, 0, 0, 30185+ { 0, { (const PTR) 0 } }, 30186+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30187+/* sys-epcr0: exception PC register 0 */ 30188+ { "sys-epcr0", OR1K_OPERAND_SYS_EPCR0, HW_H_SYS_EPCR0, 0, 0, 30189+ { 0, { (const PTR) 0 } }, 30190+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30191+/* sys-sr-lee: SR little endian enable bit */ 30192+ { "sys-sr-lee", OR1K_OPERAND_SYS_SR_LEE, HW_H_SYS_SR_LEE, 0, 0, 30193+ { 0, { (const PTR) 0 } }, 30194+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30195+/* sys-sr-f: SR flag bit */ 30196+ { "sys-sr-f", OR1K_OPERAND_SYS_SR_F, HW_H_SYS_SR_F, 0, 0, 30197+ { 0, { (const PTR) 0 } }, 30198+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30199+/* sys-sr-cy: SR carry bit */ 30200+ { "sys-sr-cy", OR1K_OPERAND_SYS_SR_CY, HW_H_SYS_SR_CY, 0, 0, 30201+ { 0, { (const PTR) 0 } }, 30202+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30203+/* sys-sr-ov: SR overflow bit */ 30204+ { "sys-sr-ov", OR1K_OPERAND_SYS_SR_OV, HW_H_SYS_SR_OV, 0, 0, 30205+ { 0, { (const PTR) 0 } }, 30206+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30207+/* sys-sr-ove: SR overflow exception enable bit */ 30208+ { "sys-sr-ove", OR1K_OPERAND_SYS_SR_OVE, HW_H_SYS_SR_OVE, 0, 0, 30209+ { 0, { (const PTR) 0 } }, 30210+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30211+/* sys-cpucfgr-ob64s: CPUCFGR ORBIS64 supported bit */ 30212+ { "sys-cpucfgr-ob64s", OR1K_OPERAND_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OB64S, 0, 0, 30213+ { 0, { (const PTR) 0 } }, 30214+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30215+/* sys-cpucfgr-nd: CPUCFGR no delay bit */ 30216+ { "sys-cpucfgr-nd", OR1K_OPERAND_SYS_CPUCFGR_ND, HW_H_SYS_CPUCFGR_ND, 0, 0, 30217+ { 0, { (const PTR) 0 } }, 30218+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30219+/* sys-fpcsr-rm: floating point round mode */ 30220+ { "sys-fpcsr-rm", OR1K_OPERAND_SYS_FPCSR_RM, HW_H_SYS_FPCSR_RM, 0, 0, 30221+ { 0, { (const PTR) 0 } }, 30222+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30223+/* mac-machi: MAC HI result register */ 30224+ { "mac-machi", OR1K_OPERAND_MAC_MACHI, HW_H_MAC_MACHI, 0, 0, 30225+ { 0, { (const PTR) 0 } }, 30226+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30227+/* mac-maclo: MAC LO result register */ 30228+ { "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0, 30229+ { 0, { (const PTR) 0 } }, 30230+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30231+/* atomic-reserve: atomic reserve flag */ 30232+ { "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0, 30233+ { 0, { (const PTR) 0 } }, 30234+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30235+/* atomic-address: atomic address */ 30236+ { "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0, 30237+ { 0, { (const PTR) 0 } }, 30238+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30239+/* uimm6: uimm6 */ 30240+ { "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6, 30241+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } }, 30242+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30243+/* rD: destination register */ 30244+ { "rD", OR1K_OPERAND_RD, HW_H_GPR, 25, 5, 30245+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } }, 30246+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30247+/* rA: source register A */ 30248+ { "rA", OR1K_OPERAND_RA, HW_H_GPR, 20, 5, 30249+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } }, 30250+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30251+/* rB: source register B */ 30252+ { "rB", OR1K_OPERAND_RB, HW_H_GPR, 15, 5, 30253+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } }, 30254+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30255+/* disp26: pc-rel 26 bit */ 30256+ { "disp26", OR1K_OPERAND_DISP26, HW_H_IADDR, 25, 26, 30257+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } }, 30258+ { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30259+/* simm16: 16-bit signed immediate */ 30260+ { "simm16", OR1K_OPERAND_SIMM16, HW_H_SIMM16, 15, 16, 30261+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } }, 30262+ { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30263+/* uimm16: 16-bit unsigned immediate */ 30264+ { "uimm16", OR1K_OPERAND_UIMM16, HW_H_UIMM16, 15, 16, 30265+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } }, 30266+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30267+/* simm16-split: split 16-bit signed immediate */ 30268+ { "simm16-split", OR1K_OPERAND_SIMM16_SPLIT, HW_H_SIMM16, 10, 16, 30269+ { 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } }, 30270+ { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30271+/* uimm16-split: split 16-bit unsigned immediate */ 30272+ { "uimm16-split", OR1K_OPERAND_UIMM16_SPLIT, HW_H_UIMM16, 10, 16, 30273+ { 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } }, 30274+ { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30275+/* rDSF: destination register (single floating point mode) */ 30276+ { "rDSF", OR1K_OPERAND_RDSF, HW_H_FSR, 25, 5, 30277+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } }, 30278+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30279+/* rASF: source register A (single floating point mode) */ 30280+ { "rASF", OR1K_OPERAND_RASF, HW_H_FSR, 20, 5, 30281+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } }, 30282+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30283+/* rBSF: source register B (single floating point mode) */ 30284+ { "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5, 30285+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } }, 30286+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30287+/* rDDF: destination register (double floating point mode) */ 30288+ { "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5, 30289+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } }, 30290+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30291+/* rADF: source register A (double floating point mode) */ 30292+ { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 25, 5, 30293+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } }, 30294+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30295+/* rBDF: source register B (double floating point mode) */ 30296+ { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 25, 5, 30297+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } }, 30298+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, 30299+/* sentinel */ 30300+ { 0, 0, 0, 0, 0, 30301+ { 0, { (const PTR) 0 } }, 30302+ { 0, { { { (1<<MACH_BASE), 0 } } } } } 30303+}; 30304+ 30305+#undef A 30306+ 30307+ 30308+/* The instruction table. */ 30309+ 30310+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 30311+#define A(a) (1 << CGEN_INSN_##a) 30312+ 30313+static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] = 30314+{ 30315+ /* Special null first entry. 30316+ A `num' value of zero is thus invalid. 30317+ Also, the special `invalid' insn resides here. */ 30318+ { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 30319+/* l.j ${disp26} */ 30320+ { 30321+ OR1K_INSN_L_J, "l-j", "l.j", 32, 30322+ { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30323+ }, 30324+/* l.jal ${disp26} */ 30325+ { 30326+ OR1K_INSN_L_JAL, "l-jal", "l.jal", 32, 30327+ { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30328+ }, 30329+/* l.jr $rB */ 30330+ { 30331+ OR1K_INSN_L_JR, "l-jr", "l.jr", 32, 30332+ { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30333+ }, 30334+/* l.jalr $rB */ 30335+ { 30336+ OR1K_INSN_L_JALR, "l-jalr", "l.jalr", 32, 30337+ { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30338+ }, 30339+/* l.bnf ${disp26} */ 30340+ { 30341+ OR1K_INSN_L_BNF, "l-bnf", "l.bnf", 32, 30342+ { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30343+ }, 30344+/* l.bf ${disp26} */ 30345+ { 30346+ OR1K_INSN_L_BF, "l-bf", "l.bf", 32, 30347+ { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30348+ }, 30349+/* l.trap ${uimm16} */ 30350+ { 30351+ OR1K_INSN_L_TRAP, "l-trap", "l.trap", 32, 30352+ { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30353+ }, 30354+/* l.sys ${uimm16} */ 30355+ { 30356+ OR1K_INSN_L_SYS, "l-sys", "l.sys", 32, 30357+ { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30358+ }, 30359+/* l.msync */ 30360+ { 30361+ OR1K_INSN_L_MSYNC, "l-msync", "l.msync", 32, 30362+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30363+ }, 30364+/* l.psync */ 30365+ { 30366+ OR1K_INSN_L_PSYNC, "l-psync", "l.psync", 32, 30367+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30368+ }, 30369+/* l.csync */ 30370+ { 30371+ OR1K_INSN_L_CSYNC, "l-csync", "l.csync", 32, 30372+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30373+ }, 30374+/* l.rfe */ 30375+ { 30376+ OR1K_INSN_L_RFE, "l-rfe", "l.rfe", 32, 30377+ { 0|A(FORCED_CTI)|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30378+ }, 30379+/* l.nop ${uimm16} */ 30380+ { 30381+ OR1K_INSN_L_NOP_IMM, "l-nop-imm", "l.nop", 32, 30382+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30383+ }, 30384+/* l.nop */ 30385+ { 30386+ OR1K_INSN_L_NOP, "l-nop", "l.nop", 32, 30387+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30388+ }, 30389+/* l.movhi $rD,$uimm16 */ 30390+ { 30391+ OR1K_INSN_L_MOVHI, "l-movhi", "l.movhi", 32, 30392+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30393+ }, 30394+/* l.macrc $rD */ 30395+ { 30396+ OR1K_INSN_L_MACRC, "l-macrc", "l.macrc", 32, 30397+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30398+ }, 30399+/* l.mfspr $rD,$rA,${uimm16} */ 30400+ { 30401+ OR1K_INSN_L_MFSPR, "l-mfspr", "l.mfspr", 32, 30402+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30403+ }, 30404+/* l.mtspr $rA,$rB,${uimm16-split} */ 30405+ { 30406+ OR1K_INSN_L_MTSPR, "l-mtspr", "l.mtspr", 32, 30407+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30408+ }, 30409+/* l.lwz $rD,${simm16}($rA) */ 30410+ { 30411+ OR1K_INSN_L_LWZ, "l-lwz", "l.lwz", 32, 30412+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30413+ }, 30414+/* l.lws $rD,${simm16}($rA) */ 30415+ { 30416+ OR1K_INSN_L_LWS, "l-lws", "l.lws", 32, 30417+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30418+ }, 30419+/* l.lwa $rD,${simm16}($rA) */ 30420+ { 30421+ OR1K_INSN_L_LWA, "l-lwa", "l.lwa", 32, 30422+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30423+ }, 30424+/* l.lbz $rD,${simm16}($rA) */ 30425+ { 30426+ OR1K_INSN_L_LBZ, "l-lbz", "l.lbz", 32, 30427+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30428+ }, 30429+/* l.lbs $rD,${simm16}($rA) */ 30430+ { 30431+ OR1K_INSN_L_LBS, "l-lbs", "l.lbs", 32, 30432+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30433+ }, 30434+/* l.lhz $rD,${simm16}($rA) */ 30435+ { 30436+ OR1K_INSN_L_LHZ, "l-lhz", "l.lhz", 32, 30437+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30438+ }, 30439+/* l.lhs $rD,${simm16}($rA) */ 30440+ { 30441+ OR1K_INSN_L_LHS, "l-lhs", "l.lhs", 32, 30442+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30443+ }, 30444+/* l.sw ${simm16-split}($rA),$rB */ 30445+ { 30446+ OR1K_INSN_L_SW, "l-sw", "l.sw", 32, 30447+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30448+ }, 30449+/* l.sb ${simm16-split}($rA),$rB */ 30450+ { 30451+ OR1K_INSN_L_SB, "l-sb", "l.sb", 32, 30452+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30453+ }, 30454+/* l.sh ${simm16-split}($rA),$rB */ 30455+ { 30456+ OR1K_INSN_L_SH, "l-sh", "l.sh", 32, 30457+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30458+ }, 30459+/* l.swa ${simm16-split}($rA),$rB */ 30460+ { 30461+ OR1K_INSN_L_SWA, "l-swa", "l.swa", 32, 30462+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30463+ }, 30464+/* l.sll $rD,$rA,$rB */ 30465+ { 30466+ OR1K_INSN_L_SLL, "l-sll", "l.sll", 32, 30467+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30468+ }, 30469+/* l.slli $rD,$rA,${uimm6} */ 30470+ { 30471+ OR1K_INSN_L_SLLI, "l-slli", "l.slli", 32, 30472+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30473+ }, 30474+/* l.srl $rD,$rA,$rB */ 30475+ { 30476+ OR1K_INSN_L_SRL, "l-srl", "l.srl", 32, 30477+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30478+ }, 30479+/* l.srli $rD,$rA,${uimm6} */ 30480+ { 30481+ OR1K_INSN_L_SRLI, "l-srli", "l.srli", 32, 30482+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30483+ }, 30484+/* l.sra $rD,$rA,$rB */ 30485+ { 30486+ OR1K_INSN_L_SRA, "l-sra", "l.sra", 32, 30487+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30488+ }, 30489+/* l.srai $rD,$rA,${uimm6} */ 30490+ { 30491+ OR1K_INSN_L_SRAI, "l-srai", "l.srai", 32, 30492+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30493+ }, 30494+/* l.ror $rD,$rA,$rB */ 30495+ { 30496+ OR1K_INSN_L_ROR, "l-ror", "l.ror", 32, 30497+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30498+ }, 30499+/* l.rori $rD,$rA,${uimm6} */ 30500+ { 30501+ OR1K_INSN_L_RORI, "l-rori", "l.rori", 32, 30502+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30503+ }, 30504+/* l.and $rD,$rA,$rB */ 30505+ { 30506+ OR1K_INSN_L_AND, "l-and", "l.and", 32, 30507+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30508+ }, 30509+/* l.or $rD,$rA,$rB */ 30510+ { 30511+ OR1K_INSN_L_OR, "l-or", "l.or", 32, 30512+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30513+ }, 30514+/* l.xor $rD,$rA,$rB */ 30515+ { 30516+ OR1K_INSN_L_XOR, "l-xor", "l.xor", 32, 30517+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30518+ }, 30519+/* l.add $rD,$rA,$rB */ 30520+ { 30521+ OR1K_INSN_L_ADD, "l-add", "l.add", 32, 30522+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30523+ }, 30524+/* l.sub $rD,$rA,$rB */ 30525+ { 30526+ OR1K_INSN_L_SUB, "l-sub", "l.sub", 32, 30527+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30528+ }, 30529+/* l.addc $rD,$rA,$rB */ 30530+ { 30531+ OR1K_INSN_L_ADDC, "l-addc", "l.addc", 32, 30532+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30533+ }, 30534+/* l.mul $rD,$rA,$rB */ 30535+ { 30536+ OR1K_INSN_L_MUL, "l-mul", "l.mul", 32, 30537+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30538+ }, 30539+/* l.mulu $rD,$rA,$rB */ 30540+ { 30541+ OR1K_INSN_L_MULU, "l-mulu", "l.mulu", 32, 30542+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30543+ }, 30544+/* l.div $rD,$rA,$rB */ 30545+ { 30546+ OR1K_INSN_L_DIV, "l-div", "l.div", 32, 30547+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30548+ }, 30549+/* l.divu $rD,$rA,$rB */ 30550+ { 30551+ OR1K_INSN_L_DIVU, "l-divu", "l.divu", 32, 30552+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30553+ }, 30554+/* l.ff1 $rD,$rA */ 30555+ { 30556+ OR1K_INSN_L_FF1, "l-ff1", "l.ff1", 32, 30557+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30558+ }, 30559+/* l.fl1 $rD,$rA */ 30560+ { 30561+ OR1K_INSN_L_FL1, "l-fl1", "l.fl1", 32, 30562+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30563+ }, 30564+/* l.andi $rD,$rA,$uimm16 */ 30565+ { 30566+ OR1K_INSN_L_ANDI, "l-andi", "l.andi", 32, 30567+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30568+ }, 30569+/* l.ori $rD,$rA,$uimm16 */ 30570+ { 30571+ OR1K_INSN_L_ORI, "l-ori", "l.ori", 32, 30572+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30573+ }, 30574+/* l.xori $rD,$rA,$simm16 */ 30575+ { 30576+ OR1K_INSN_L_XORI, "l-xori", "l.xori", 32, 30577+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30578+ }, 30579+/* l.addi $rD,$rA,$simm16 */ 30580+ { 30581+ OR1K_INSN_L_ADDI, "l-addi", "l.addi", 32, 30582+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30583+ }, 30584+/* l.addic $rD,$rA,$simm16 */ 30585+ { 30586+ OR1K_INSN_L_ADDIC, "l-addic", "l.addic", 32, 30587+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30588+ }, 30589+/* l.muli $rD,$rA,$simm16 */ 30590+ { 30591+ OR1K_INSN_L_MULI, "l-muli", "l.muli", 32, 30592+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30593+ }, 30594+/* l.exths $rD,$rA */ 30595+ { 30596+ OR1K_INSN_L_EXTHS, "l-exths", "l.exths", 32, 30597+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30598+ }, 30599+/* l.extbs $rD,$rA */ 30600+ { 30601+ OR1K_INSN_L_EXTBS, "l-extbs", "l.extbs", 32, 30602+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30603+ }, 30604+/* l.exthz $rD,$rA */ 30605+ { 30606+ OR1K_INSN_L_EXTHZ, "l-exthz", "l.exthz", 32, 30607+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30608+ }, 30609+/* l.extbz $rD,$rA */ 30610+ { 30611+ OR1K_INSN_L_EXTBZ, "l-extbz", "l.extbz", 32, 30612+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30613+ }, 30614+/* l.extws $rD,$rA */ 30615+ { 30616+ OR1K_INSN_L_EXTWS, "l-extws", "l.extws", 32, 30617+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30618+ }, 30619+/* l.extwz $rD,$rA */ 30620+ { 30621+ OR1K_INSN_L_EXTWZ, "l-extwz", "l.extwz", 32, 30622+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30623+ }, 30624+/* l.cmov $rD,$rA,$rB */ 30625+ { 30626+ OR1K_INSN_L_CMOV, "l-cmov", "l.cmov", 32, 30627+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30628+ }, 30629+/* l.sfgts $rA,$rB */ 30630+ { 30631+ OR1K_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32, 30632+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30633+ }, 30634+/* l.sfgtsi $rA,$simm16 */ 30635+ { 30636+ OR1K_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32, 30637+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30638+ }, 30639+/* l.sfgtu $rA,$rB */ 30640+ { 30641+ OR1K_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32, 30642+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30643+ }, 30644+/* l.sfgtui $rA,$simm16 */ 30645+ { 30646+ OR1K_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32, 30647+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30648+ }, 30649+/* l.sfges $rA,$rB */ 30650+ { 30651+ OR1K_INSN_L_SFGES, "l-sfges", "l.sfges", 32, 30652+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30653+ }, 30654+/* l.sfgesi $rA,$simm16 */ 30655+ { 30656+ OR1K_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32, 30657+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30658+ }, 30659+/* l.sfgeu $rA,$rB */ 30660+ { 30661+ OR1K_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32, 30662+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30663+ }, 30664+/* l.sfgeui $rA,$simm16 */ 30665+ { 30666+ OR1K_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32, 30667+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30668+ }, 30669+/* l.sflts $rA,$rB */ 30670+ { 30671+ OR1K_INSN_L_SFLTS, "l-sflts", "l.sflts", 32, 30672+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30673+ }, 30674+/* l.sfltsi $rA,$simm16 */ 30675+ { 30676+ OR1K_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32, 30677+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30678+ }, 30679+/* l.sfltu $rA,$rB */ 30680+ { 30681+ OR1K_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32, 30682+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30683+ }, 30684+/* l.sfltui $rA,$simm16 */ 30685+ { 30686+ OR1K_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32, 30687+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30688+ }, 30689+/* l.sfles $rA,$rB */ 30690+ { 30691+ OR1K_INSN_L_SFLES, "l-sfles", "l.sfles", 32, 30692+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30693+ }, 30694+/* l.sflesi $rA,$simm16 */ 30695+ { 30696+ OR1K_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32, 30697+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30698+ }, 30699+/* l.sfleu $rA,$rB */ 30700+ { 30701+ OR1K_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32, 30702+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30703+ }, 30704+/* l.sfleui $rA,$simm16 */ 30705+ { 30706+ OR1K_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32, 30707+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30708+ }, 30709+/* l.sfeq $rA,$rB */ 30710+ { 30711+ OR1K_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32, 30712+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30713+ }, 30714+/* l.sfeqi $rA,$simm16 */ 30715+ { 30716+ OR1K_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32, 30717+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30718+ }, 30719+/* l.sfne $rA,$rB */ 30720+ { 30721+ OR1K_INSN_L_SFNE, "l-sfne", "l.sfne", 32, 30722+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30723+ }, 30724+/* l.sfnei $rA,$simm16 */ 30725+ { 30726+ OR1K_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32, 30727+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30728+ }, 30729+/* l.mac $rA,$rB */ 30730+ { 30731+ OR1K_INSN_L_MAC, "l-mac", "l.mac", 32, 30732+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30733+ }, 30734+/* l.msb $rA,$rB */ 30735+ { 30736+ OR1K_INSN_L_MSB, "l-msb", "l.msb", 32, 30737+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30738+ }, 30739+/* l.maci $rA,${simm16} */ 30740+ { 30741+ OR1K_INSN_L_MACI, "l-maci", "l.maci", 32, 30742+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30743+ }, 30744+/* l.cust1 */ 30745+ { 30746+ OR1K_INSN_L_CUST1, "l-cust1", "l.cust1", 32, 30747+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30748+ }, 30749+/* l.cust2 */ 30750+ { 30751+ OR1K_INSN_L_CUST2, "l-cust2", "l.cust2", 32, 30752+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30753+ }, 30754+/* l.cust3 */ 30755+ { 30756+ OR1K_INSN_L_CUST3, "l-cust3", "l.cust3", 32, 30757+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30758+ }, 30759+/* l.cust4 */ 30760+ { 30761+ OR1K_INSN_L_CUST4, "l-cust4", "l.cust4", 32, 30762+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30763+ }, 30764+/* l.cust5 */ 30765+ { 30766+ OR1K_INSN_L_CUST5, "l-cust5", "l.cust5", 32, 30767+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30768+ }, 30769+/* l.cust6 */ 30770+ { 30771+ OR1K_INSN_L_CUST6, "l-cust6", "l.cust6", 32, 30772+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30773+ }, 30774+/* l.cust7 */ 30775+ { 30776+ OR1K_INSN_L_CUST7, "l-cust7", "l.cust7", 32, 30777+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30778+ }, 30779+/* l.cust8 */ 30780+ { 30781+ OR1K_INSN_L_CUST8, "l-cust8", "l.cust8", 32, 30782+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30783+ }, 30784+/* lf.add.s $rDSF,$rASF,$rBSF */ 30785+ { 30786+ OR1K_INSN_LF_ADD_S, "lf-add-s", "lf.add.s", 32, 30787+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30788+ }, 30789+/* lf.add.d $rDDF,$rADF,$rBDF */ 30790+ { 30791+ OR1K_INSN_LF_ADD_D, "lf-add-d", "lf.add.d", 32, 30792+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30793+ }, 30794+/* lf.sub.s $rDSF,$rASF,$rBSF */ 30795+ { 30796+ OR1K_INSN_LF_SUB_S, "lf-sub-s", "lf.sub.s", 32, 30797+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30798+ }, 30799+/* lf.sub.d $rDDF,$rADF,$rBDF */ 30800+ { 30801+ OR1K_INSN_LF_SUB_D, "lf-sub-d", "lf.sub.d", 32, 30802+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30803+ }, 30804+/* lf.mul.s $rDSF,$rASF,$rBSF */ 30805+ { 30806+ OR1K_INSN_LF_MUL_S, "lf-mul-s", "lf.mul.s", 32, 30807+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30808+ }, 30809+/* lf.mul.d $rDDF,$rADF,$rBDF */ 30810+ { 30811+ OR1K_INSN_LF_MUL_D, "lf-mul-d", "lf.mul.d", 32, 30812+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30813+ }, 30814+/* lf.div.s $rDSF,$rASF,$rBSF */ 30815+ { 30816+ OR1K_INSN_LF_DIV_S, "lf-div-s", "lf.div.s", 32, 30817+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30818+ }, 30819+/* lf.div.d $rDDF,$rADF,$rBDF */ 30820+ { 30821+ OR1K_INSN_LF_DIV_D, "lf-div-d", "lf.div.d", 32, 30822+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30823+ }, 30824+/* lf.rem.s $rDSF,$rASF,$rBSF */ 30825+ { 30826+ OR1K_INSN_LF_REM_S, "lf-rem-s", "lf.rem.s", 32, 30827+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30828+ }, 30829+/* lf.rem.d $rDDF,$rADF,$rBDF */ 30830+ { 30831+ OR1K_INSN_LF_REM_D, "lf-rem-d", "lf.rem.d", 32, 30832+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30833+ }, 30834+/* lf.itof.s $rDSF,$rA */ 30835+ { 30836+ OR1K_INSN_LF_ITOF_S, "lf-itof-s", "lf.itof.s", 32, 30837+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30838+ }, 30839+/* lf.itof.d $rDSF,$rA */ 30840+ { 30841+ OR1K_INSN_LF_ITOF_D, "lf-itof-d", "lf.itof.d", 32, 30842+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30843+ }, 30844+/* lf.ftoi.s $rD,$rASF */ 30845+ { 30846+ OR1K_INSN_LF_FTOI_S, "lf-ftoi-s", "lf.ftoi.s", 32, 30847+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30848+ }, 30849+/* lf.ftoi.d $rD,$rADF */ 30850+ { 30851+ OR1K_INSN_LF_FTOI_D, "lf-ftoi-d", "lf.ftoi.d", 32, 30852+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30853+ }, 30854+/* lf.sfeq.s $rASF,$rBSF */ 30855+ { 30856+ OR1K_INSN_LF_EQ_S, "lf-eq-s", "lf.sfeq.s", 32, 30857+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30858+ }, 30859+/* lf.sfeq.d $rASF,$rBSF */ 30860+ { 30861+ OR1K_INSN_LF_EQ_D, "lf-eq-d", "lf.sfeq.d", 32, 30862+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30863+ }, 30864+/* lf.sfne.s $rASF,$rBSF */ 30865+ { 30866+ OR1K_INSN_LF_NE_S, "lf-ne-s", "lf.sfne.s", 32, 30867+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30868+ }, 30869+/* lf.sfne.d $rASF,$rBSF */ 30870+ { 30871+ OR1K_INSN_LF_NE_D, "lf-ne-d", "lf.sfne.d", 32, 30872+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30873+ }, 30874+/* lf.sfge.s $rASF,$rBSF */ 30875+ { 30876+ OR1K_INSN_LF_GE_S, "lf-ge-s", "lf.sfge.s", 32, 30877+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30878+ }, 30879+/* lf.sfge.d $rASF,$rBSF */ 30880+ { 30881+ OR1K_INSN_LF_GE_D, "lf-ge-d", "lf.sfge.d", 32, 30882+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30883+ }, 30884+/* lf.sfgt.s $rASF,$rBSF */ 30885+ { 30886+ OR1K_INSN_LF_GT_S, "lf-gt-s", "lf.sfgt.s", 32, 30887+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30888+ }, 30889+/* lf.sfgt.d $rASF,$rBSF */ 30890+ { 30891+ OR1K_INSN_LF_GT_D, "lf-gt-d", "lf.sfgt.d", 32, 30892+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30893+ }, 30894+/* lf.sflt.s $rASF,$rBSF */ 30895+ { 30896+ OR1K_INSN_LF_LT_S, "lf-lt-s", "lf.sflt.s", 32, 30897+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30898+ }, 30899+/* lf.sflt.d $rASF,$rBSF */ 30900+ { 30901+ OR1K_INSN_LF_LT_D, "lf-lt-d", "lf.sflt.d", 32, 30902+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30903+ }, 30904+/* lf.sfle.s $rASF,$rBSF */ 30905+ { 30906+ OR1K_INSN_LF_LE_S, "lf-le-s", "lf.sfle.s", 32, 30907+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30908+ }, 30909+/* lf.sfle.d $rASF,$rBSF */ 30910+ { 30911+ OR1K_INSN_LF_LE_D, "lf-le-d", "lf.sfle.d", 32, 30912+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30913+ }, 30914+/* lf.madd.s $rDSF,$rASF,$rBSF */ 30915+ { 30916+ OR1K_INSN_LF_MADD_S, "lf-madd-s", "lf.madd.s", 32, 30917+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30918+ }, 30919+/* lf.madd.d $rDDF,$rADF,$rBDF */ 30920+ { 30921+ OR1K_INSN_LF_MADD_D, "lf-madd-d", "lf.madd.d", 32, 30922+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30923+ }, 30924+/* lf.cust1.s $rASF,$rBSF */ 30925+ { 30926+ OR1K_INSN_LF_CUST1_S, "lf-cust1-s", "lf.cust1.s", 32, 30927+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30928+ }, 30929+/* lf.cust1.d */ 30930+ { 30931+ OR1K_INSN_LF_CUST1_D, "lf-cust1-d", "lf.cust1.d", 32, 30932+ { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } 30933+ }, 30934+}; 30935+ 30936+#undef OP 30937+#undef A 30938+ 30939+/* Initialize anything needed to be done once, before any cpu_open call. */ 30940+ 30941+static void 30942+init_tables (void) 30943+{ 30944+} 30945+ 30946+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 30947+static void build_hw_table (CGEN_CPU_TABLE *); 30948+static void build_ifield_table (CGEN_CPU_TABLE *); 30949+static void build_operand_table (CGEN_CPU_TABLE *); 30950+static void build_insn_table (CGEN_CPU_TABLE *); 30951+static void or1k_cgen_rebuild_tables (CGEN_CPU_TABLE *); 30952+ 30953+/* Subroutine of or1k_cgen_cpu_open to look up a mach via its bfd name. */ 30954+ 30955+static const CGEN_MACH * 30956+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 30957+{ 30958+ while (table->name) 30959+ { 30960+ if (strcmp (name, table->bfd_name) == 0) 30961+ return table; 30962+ ++table; 30963+ } 30964+ abort (); 30965+} 30966+ 30967+/* Subroutine of or1k_cgen_cpu_open to build the hardware table. */ 30968+ 30969+static void 30970+build_hw_table (CGEN_CPU_TABLE *cd) 30971+{ 30972+ int i; 30973+ int machs = cd->machs; 30974+ const CGEN_HW_ENTRY *init = & or1k_cgen_hw_table[0]; 30975+ /* MAX_HW is only an upper bound on the number of selected entries. 30976+ However each entry is indexed by it's enum so there can be holes in 30977+ the table. */ 30978+ const CGEN_HW_ENTRY **selected = 30979+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 30980+ 30981+ cd->hw_table.init_entries = init; 30982+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 30983+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 30984+ /* ??? For now we just use machs to determine which ones we want. */ 30985+ for (i = 0; init[i].name != NULL; ++i) 30986+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 30987+ & machs) 30988+ selected[init[i].type] = &init[i]; 30989+ cd->hw_table.entries = selected; 30990+ cd->hw_table.num_entries = MAX_HW; 30991+} 30992+ 30993+/* Subroutine of or1k_cgen_cpu_open to build the hardware table. */ 30994+ 30995+static void 30996+build_ifield_table (CGEN_CPU_TABLE *cd) 30997+{ 30998+ cd->ifld_table = & or1k_cgen_ifld_table[0]; 30999+} 31000+ 31001+/* Subroutine of or1k_cgen_cpu_open to build the hardware table. */ 31002+ 31003+static void 31004+build_operand_table (CGEN_CPU_TABLE *cd) 31005+{ 31006+ int i; 31007+ int machs = cd->machs; 31008+ const CGEN_OPERAND *init = & or1k_cgen_operand_table[0]; 31009+ /* MAX_OPERANDS is only an upper bound on the number of selected entries. 31010+ However each entry is indexed by it's enum so there can be holes in 31011+ the table. */ 31012+ const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 31013+ 31014+ cd->operand_table.init_entries = init; 31015+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 31016+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 31017+ /* ??? For now we just use mach to determine which ones we want. */ 31018+ for (i = 0; init[i].name != NULL; ++i) 31019+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 31020+ & machs) 31021+ selected[init[i].type] = &init[i]; 31022+ cd->operand_table.entries = selected; 31023+ cd->operand_table.num_entries = MAX_OPERANDS; 31024+} 31025+ 31026+/* Subroutine of or1k_cgen_cpu_open to build the hardware table. 31027+ ??? This could leave out insns not supported by the specified mach/isa, 31028+ but that would cause errors like "foo only supported by bar" to become 31029+ "unknown insn", so for now we include all insns and require the app to 31030+ do the checking later. 31031+ ??? On the other hand, parsing of such insns may require their hardware or 31032+ operand elements to be in the table [which they mightn't be]. */ 31033+ 31034+static void 31035+build_insn_table (CGEN_CPU_TABLE *cd) 31036+{ 31037+ int i; 31038+ const CGEN_IBASE *ib = & or1k_cgen_insn_table[0]; 31039+ CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 31040+ 31041+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 31042+ for (i = 0; i < MAX_INSNS; ++i) 31043+ insns[i].base = &ib[i]; 31044+ cd->insn_table.init_entries = insns; 31045+ cd->insn_table.entry_size = sizeof (CGEN_IBASE); 31046+ cd->insn_table.num_init_entries = MAX_INSNS; 31047+} 31048+ 31049+/* Subroutine of or1k_cgen_cpu_open to rebuild the tables. */ 31050+ 31051+static void 31052+or1k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 31053+{ 31054+ int i; 31055+ CGEN_BITSET *isas = cd->isas; 31056+ unsigned int machs = cd->machs; 31057+ 31058+ cd->int_insn_p = CGEN_INT_INSN_P; 31059+ 31060+ /* Data derived from the isa spec. */ 31061+#define UNSET (CGEN_SIZE_UNKNOWN + 1) 31062+ cd->default_insn_bitsize = UNSET; 31063+ cd->base_insn_bitsize = UNSET; 31064+ cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 31065+ cd->max_insn_bitsize = 0; 31066+ for (i = 0; i < MAX_ISAS; ++i) 31067+ if (cgen_bitset_contains (isas, i)) 31068+ { 31069+ const CGEN_ISA *isa = & or1k_cgen_isa_table[i]; 31070+ 31071+ /* Default insn sizes of all selected isas must be 31072+ equal or we set the result to 0, meaning "unknown". */ 31073+ if (cd->default_insn_bitsize == UNSET) 31074+ cd->default_insn_bitsize = isa->default_insn_bitsize; 31075+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 31076+ ; /* This is ok. */ 31077+ else 31078+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 31079+ 31080+ /* Base insn sizes of all selected isas must be equal 31081+ or we set the result to 0, meaning "unknown". */ 31082+ if (cd->base_insn_bitsize == UNSET) 31083+ cd->base_insn_bitsize = isa->base_insn_bitsize; 31084+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 31085+ ; /* This is ok. */ 31086+ else 31087+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 31088+ 31089+ /* Set min,max insn sizes. */ 31090+ if (isa->min_insn_bitsize < cd->min_insn_bitsize) 31091+ cd->min_insn_bitsize = isa->min_insn_bitsize; 31092+ if (isa->max_insn_bitsize > cd->max_insn_bitsize) 31093+ cd->max_insn_bitsize = isa->max_insn_bitsize; 31094+ } 31095+ 31096+ /* Data derived from the mach spec. */ 31097+ for (i = 0; i < MAX_MACHS; ++i) 31098+ if (((1 << i) & machs) != 0) 31099+ { 31100+ const CGEN_MACH *mach = & or1k_cgen_mach_table[i]; 31101+ 31102+ if (mach->insn_chunk_bitsize != 0) 31103+ { 31104+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 31105+ { 31106+ fprintf (stderr, "or1k_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", 31107+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 31108+ abort (); 31109+ } 31110+ 31111+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 31112+ } 31113+ } 31114+ 31115+ /* Determine which hw elements are used by MACH. */ 31116+ build_hw_table (cd); 31117+ 31118+ /* Build the ifield table. */ 31119+ build_ifield_table (cd); 31120+ 31121+ /* Determine which operands are used by MACH/ISA. */ 31122+ build_operand_table (cd); 31123+ 31124+ /* Build the instruction table. */ 31125+ build_insn_table (cd); 31126+} 31127+ 31128+/* Initialize a cpu table and return a descriptor. 31129+ It's much like opening a file, and must be the first function called. 31130+ The arguments are a set of (type/value) pairs, terminated with 31131+ CGEN_CPU_OPEN_END. 31132+ 31133+ Currently supported values: 31134+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 31135+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 31136+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 31137+ CGEN_CPU_OPEN_ENDIAN: specify endian choice 31138+ CGEN_CPU_OPEN_END: terminates arguments 31139+ 31140+ ??? Simultaneous multiple isas might not make sense, but it's not (yet) 31141+ precluded. */ 31142+ 31143+CGEN_CPU_DESC 31144+or1k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 31145+{ 31146+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 31147+ static int init_p; 31148+ CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 31149+ unsigned int machs = 0; /* 0 = "unspecified" */ 31150+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 31151+ va_list ap; 31152+ 31153+ if (! init_p) 31154+ { 31155+ init_tables (); 31156+ init_p = 1; 31157+ } 31158+ 31159+ memset (cd, 0, sizeof (*cd)); 31160+ 31161+ va_start (ap, arg_type); 31162+ while (arg_type != CGEN_CPU_OPEN_END) 31163+ { 31164+ switch (arg_type) 31165+ { 31166+ case CGEN_CPU_OPEN_ISAS : 31167+ isas = va_arg (ap, CGEN_BITSET *); 31168+ break; 31169+ case CGEN_CPU_OPEN_MACHS : 31170+ machs = va_arg (ap, unsigned int); 31171+ break; 31172+ case CGEN_CPU_OPEN_BFDMACH : 31173+ { 31174+ const char *name = va_arg (ap, const char *); 31175+ const CGEN_MACH *mach = 31176+ lookup_mach_via_bfd_name (or1k_cgen_mach_table, name); 31177+ 31178+ machs |= 1 << mach->num; 31179+ break; 31180+ } 31181+ case CGEN_CPU_OPEN_ENDIAN : 31182+ endian = va_arg (ap, enum cgen_endian); 31183+ break; 31184+ default : 31185+ fprintf (stderr, "or1k_cgen_cpu_open: unsupported argument `%d'\n", 31186+ arg_type); 31187+ abort (); /* ??? return NULL? */ 31188+ } 31189+ arg_type = va_arg (ap, enum cgen_cpu_open_arg); 31190+ } 31191+ va_end (ap); 31192+ 31193+ /* Mach unspecified means "all". */ 31194+ if (machs == 0) 31195+ machs = (1 << MAX_MACHS) - 1; 31196+ /* Base mach is always selected. */ 31197+ machs |= 1; 31198+ if (endian == CGEN_ENDIAN_UNKNOWN) 31199+ { 31200+ /* ??? If target has only one, could have a default. */ 31201+ fprintf (stderr, "or1k_cgen_cpu_open: no endianness specified\n"); 31202+ abort (); 31203+ } 31204+ 31205+ cd->isas = cgen_bitset_copy (isas); 31206+ cd->machs = machs; 31207+ cd->endian = endian; 31208+ /* FIXME: for the sparc case we can determine insn-endianness statically. 31209+ The worry here is where both data and insn endian can be independently 31210+ chosen, in which case this function will need another argument. 31211+ Actually, will want to allow for more arguments in the future anyway. */ 31212+ cd->insn_endian = endian; 31213+ 31214+ /* Table (re)builder. */ 31215+ cd->rebuild_tables = or1k_cgen_rebuild_tables; 31216+ or1k_cgen_rebuild_tables (cd); 31217+ 31218+ /* Default to not allowing signed overflow. */ 31219+ cd->signed_overflow_ok_p = 0; 31220+ 31221+ return (CGEN_CPU_DESC) cd; 31222+} 31223+ 31224+/* Cover fn to or1k_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 31225+ MACH_NAME is the bfd name of the mach. */ 31226+ 31227+CGEN_CPU_DESC 31228+or1k_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 31229+{ 31230+ return or1k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 31231+ CGEN_CPU_OPEN_ENDIAN, endian, 31232+ CGEN_CPU_OPEN_END); 31233+} 31234+ 31235+/* Close a cpu table. 31236+ ??? This can live in a machine independent file, but there's currently 31237+ no place to put this file (there's no libcgen). libopcodes is the wrong 31238+ place as some simulator ports use this but they don't use libopcodes. */ 31239+ 31240+void 31241+or1k_cgen_cpu_close (CGEN_CPU_DESC cd) 31242+{ 31243+ unsigned int i; 31244+ const CGEN_INSN *insns; 31245+ 31246+ if (cd->macro_insn_table.init_entries) 31247+ { 31248+ insns = cd->macro_insn_table.init_entries; 31249+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 31250+ if (CGEN_INSN_RX ((insns))) 31251+ regfree (CGEN_INSN_RX (insns)); 31252+ } 31253+ 31254+ if (cd->insn_table.init_entries) 31255+ { 31256+ insns = cd->insn_table.init_entries; 31257+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 31258+ if (CGEN_INSN_RX (insns)) 31259+ regfree (CGEN_INSN_RX (insns)); 31260+ } 31261+ 31262+ if (cd->macro_insn_table.init_entries) 31263+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 31264+ 31265+ if (cd->insn_table.init_entries) 31266+ free ((CGEN_INSN *) cd->insn_table.init_entries); 31267+ 31268+ if (cd->hw_table.entries) 31269+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 31270+ 31271+ if (cd->operand_table.entries) 31272+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 31273+ 31274+ free (cd); 31275+} 31276+ 31277diff -rNU3 dist.orig/opcodes/or1k-desc.h dist/opcodes/or1k-desc.h 31278--- dist.orig/opcodes/or1k-desc.h 1970-01-01 01:00:00.000000000 +0100 31279+++ dist/opcodes/or1k-desc.h 2015-10-18 13:11:20.000000000 +0200 31280@@ -0,0 +1,682 @@ 31281+/* CPU data header for or1k. 31282+ 31283+THIS FILE IS MACHINE GENERATED WITH CGEN. 31284+ 31285+Copyright (C) 1996-2014 Free Software Foundation, Inc. 31286+ 31287+This file is part of the GNU Binutils and/or GDB, the GNU debugger. 31288+ 31289+ This file is free software; you can redistribute it and/or modify 31290+ it under the terms of the GNU General Public License as published by 31291+ the Free Software Foundation; either version 3, or (at your option) 31292+ any later version. 31293+ 31294+ It is distributed in the hope that it will be useful, but WITHOUT 31295+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 31296+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 31297+ License for more details. 31298+ 31299+ You should have received a copy of the GNU General Public License along 31300+ with this program; if not, write to the Free Software Foundation, Inc., 31301+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 31302+ 31303+*/ 31304+ 31305+#ifndef OR1K_CPU_H 31306+#define OR1K_CPU_H 31307+ 31308+#define CGEN_ARCH or1k 31309+ 31310+/* Given symbol S, return or1k_cgen_<S>. */ 31311+#define CGEN_SYM(s) or1k##_cgen_##s 31312+ 31313+ 31314+/* Selected cpu families. */ 31315+#define HAVE_CPU_OR1K32BF 31316+#define HAVE_CPU_OR1K64BF 31317+ 31318+#define CGEN_INSN_LSB0_P 1 31319+ 31320+/* Minimum size of any insn (in bytes). */ 31321+#define CGEN_MIN_INSN_SIZE 4 31322+ 31323+/* Maximum size of any insn (in bytes). */ 31324+#define CGEN_MAX_INSN_SIZE 4 31325+ 31326+#define CGEN_INT_INSN_P 1 31327+ 31328+/* Maximum number of syntax elements in an instruction. */ 31329+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17 31330+ 31331+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 31332+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 31333+ we can't hash on everything up to the space. */ 31334+#define CGEN_MNEMONIC_OPERANDS 31335+ 31336+/* Maximum number of fields in an instruction. */ 31337+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 31338+ 31339+/* Enums. */ 31340+ 31341+/* Enum declaration for Exception numbers. */ 31342+typedef enum except_number { 31343+ EXCEPT_NONE, EXCEPT_RESET, EXCEPT_BUSERR, EXCEPT_DPF 31344+ , EXCEPT_IPF, EXCEPT_TICK, EXCEPT_ALIGN, EXCEPT_ILLEGAL 31345+ , EXCEPT_INT, EXCEPT_DTLBMISS, EXCEPT_ITLBMISS, EXCEPT_RANGE 31346+ , EXCEPT_SYSCALL, EXCEPT_FPE, EXCEPT_TRAP 31347+} EXCEPT_NUMBER; 31348+ 31349+/* Enum declaration for special purpose register groups. */ 31350+typedef enum spr_groups { 31351+ SPR_GROUP_SYS, SPR_GROUP_DMMU, SPR_GROUP_IMMU, SPR_GROUP_DCACHE 31352+ , SPR_GROUP_ICACHE, SPR_GROUP_MAC, SPR_GROUP_DEBUG, SPR_GROUP_PERF 31353+ , SPR_GROUP_POWER, SPR_GROUP_PIC, SPR_GROUP_TICK, SPR_GROUP_FPU 31354+} SPR_GROUPS; 31355+ 31356+/* Enum declaration for special purpose register indicies. */ 31357+typedef enum spr_reg_indices { 31358+ SPR_INDEX_SYS_VR = 0, SPR_INDEX_SYS_UPR = 1, SPR_INDEX_SYS_CPUCFGR = 2, SPR_INDEX_SYS_DMMUCFGR = 3 31359+ , SPR_INDEX_SYS_IMMUCFGR = 4, SPR_INDEX_SYS_DCCFGR = 5, SPR_INDEX_SYS_ICCFGR = 6, SPR_INDEX_SYS_DCFGR = 7 31360+ , SPR_INDEX_SYS_PCCFGR = 8, SPR_INDEX_SYS_NPC = 16, SPR_INDEX_SYS_SR = 17, SPR_INDEX_SYS_PPC = 18 31361+ , SPR_INDEX_SYS_FPCSR = 20, SPR_INDEX_SYS_EPCR0 = 32, SPR_INDEX_SYS_EPCR1 = 33, SPR_INDEX_SYS_EPCR2 = 34 31362+ , SPR_INDEX_SYS_EPCR3 = 35, SPR_INDEX_SYS_EPCR4 = 36, SPR_INDEX_SYS_EPCR5 = 37, SPR_INDEX_SYS_EPCR6 = 38 31363+ , SPR_INDEX_SYS_EPCR7 = 39, SPR_INDEX_SYS_EPCR8 = 40, SPR_INDEX_SYS_EPCR9 = 41, SPR_INDEX_SYS_EPCR10 = 42 31364+ , SPR_INDEX_SYS_EPCR11 = 43, SPR_INDEX_SYS_EPCR12 = 44, SPR_INDEX_SYS_EPCR13 = 45, SPR_INDEX_SYS_EPCR14 = 46 31365+ , SPR_INDEX_SYS_EPCR15 = 47, SPR_INDEX_SYS_EEAR0 = 48, SPR_INDEX_SYS_EEAR1 = 49, SPR_INDEX_SYS_EEAR2 = 50 31366+ , SPR_INDEX_SYS_EEAR3 = 51, SPR_INDEX_SYS_EEAR4 = 52, SPR_INDEX_SYS_EEAR5 = 53, SPR_INDEX_SYS_EEAR6 = 54 31367+ , SPR_INDEX_SYS_EEAR7 = 55, SPR_INDEX_SYS_EEAR8 = 56, SPR_INDEX_SYS_EEAR9 = 57, SPR_INDEX_SYS_EEAR10 = 58 31368+ , SPR_INDEX_SYS_EEAR11 = 59, SPR_INDEX_SYS_EEAR12 = 60, SPR_INDEX_SYS_EEAR13 = 61, SPR_INDEX_SYS_EEAR14 = 62 31369+ , SPR_INDEX_SYS_EEAR15 = 63, SPR_INDEX_SYS_ESR0 = 64, SPR_INDEX_SYS_ESR1 = 65, SPR_INDEX_SYS_ESR2 = 66 31370+ , SPR_INDEX_SYS_ESR3 = 67, SPR_INDEX_SYS_ESR4 = 68, SPR_INDEX_SYS_ESR5 = 69, SPR_INDEX_SYS_ESR6 = 70 31371+ , SPR_INDEX_SYS_ESR7 = 71, SPR_INDEX_SYS_ESR8 = 72, SPR_INDEX_SYS_ESR9 = 73, SPR_INDEX_SYS_ESR10 = 74 31372+ , SPR_INDEX_SYS_ESR11 = 75, SPR_INDEX_SYS_ESR12 = 76, SPR_INDEX_SYS_ESR13 = 77, SPR_INDEX_SYS_ESR14 = 78 31373+ , SPR_INDEX_SYS_ESR15 = 79, SPR_INDEX_SYS_GPR0 = 1024, SPR_INDEX_SYS_GPR1 = 1025, SPR_INDEX_SYS_GPR2 = 1026 31374+ , SPR_INDEX_SYS_GPR3 = 1027, SPR_INDEX_SYS_GPR4 = 1028, SPR_INDEX_SYS_GPR5 = 1029, SPR_INDEX_SYS_GPR6 = 1030 31375+ , SPR_INDEX_SYS_GPR7 = 1031, SPR_INDEX_SYS_GPR8 = 1032, SPR_INDEX_SYS_GPR9 = 1033, SPR_INDEX_SYS_GPR10 = 1034 31376+ , SPR_INDEX_SYS_GPR11 = 1035, SPR_INDEX_SYS_GPR12 = 1036, SPR_INDEX_SYS_GPR13 = 1037, SPR_INDEX_SYS_GPR14 = 1038 31377+ , SPR_INDEX_SYS_GPR15 = 1039, SPR_INDEX_SYS_GPR16 = 1040, SPR_INDEX_SYS_GPR17 = 1041, SPR_INDEX_SYS_GPR18 = 1042 31378+ , SPR_INDEX_SYS_GPR19 = 1043, SPR_INDEX_SYS_GPR20 = 1044, SPR_INDEX_SYS_GPR21 = 1045, SPR_INDEX_SYS_GPR22 = 1046 31379+ , SPR_INDEX_SYS_GPR23 = 1047, SPR_INDEX_SYS_GPR24 = 1048, SPR_INDEX_SYS_GPR25 = 1049, SPR_INDEX_SYS_GPR26 = 1050 31380+ , SPR_INDEX_SYS_GPR27 = 1051, SPR_INDEX_SYS_GPR28 = 1052, SPR_INDEX_SYS_GPR29 = 1053, SPR_INDEX_SYS_GPR30 = 1054 31381+ , SPR_INDEX_SYS_GPR31 = 1055, SPR_INDEX_SYS_GPR32 = 1056, SPR_INDEX_SYS_GPR33 = 1057, SPR_INDEX_SYS_GPR34 = 1058 31382+ , SPR_INDEX_SYS_GPR35 = 1059, SPR_INDEX_SYS_GPR36 = 1060, SPR_INDEX_SYS_GPR37 = 1061, SPR_INDEX_SYS_GPR38 = 1062 31383+ , SPR_INDEX_SYS_GPR39 = 1063, SPR_INDEX_SYS_GPR40 = 1064, SPR_INDEX_SYS_GPR41 = 1065, SPR_INDEX_SYS_GPR42 = 1066 31384+ , SPR_INDEX_SYS_GPR43 = 1067, SPR_INDEX_SYS_GPR44 = 1068, SPR_INDEX_SYS_GPR45 = 1069, SPR_INDEX_SYS_GPR46 = 1070 31385+ , SPR_INDEX_SYS_GPR47 = 1071, SPR_INDEX_SYS_GPR48 = 1072, SPR_INDEX_SYS_GPR49 = 1073, SPR_INDEX_SYS_GPR50 = 1074 31386+ , SPR_INDEX_SYS_GPR51 = 1075, SPR_INDEX_SYS_GPR52 = 1076, SPR_INDEX_SYS_GPR53 = 1077, SPR_INDEX_SYS_GPR54 = 1078 31387+ , SPR_INDEX_SYS_GPR55 = 1079, SPR_INDEX_SYS_GPR56 = 1080, SPR_INDEX_SYS_GPR57 = 1081, SPR_INDEX_SYS_GPR58 = 1082 31388+ , SPR_INDEX_SYS_GPR59 = 1083, SPR_INDEX_SYS_GPR60 = 1084, SPR_INDEX_SYS_GPR61 = 1085, SPR_INDEX_SYS_GPR62 = 1086 31389+ , SPR_INDEX_SYS_GPR63 = 1087, SPR_INDEX_SYS_GPR64 = 1088, SPR_INDEX_SYS_GPR65 = 1089, SPR_INDEX_SYS_GPR66 = 1090 31390+ , SPR_INDEX_SYS_GPR67 = 1091, SPR_INDEX_SYS_GPR68 = 1092, SPR_INDEX_SYS_GPR69 = 1093, SPR_INDEX_SYS_GPR70 = 1094 31391+ , SPR_INDEX_SYS_GPR71 = 1095, SPR_INDEX_SYS_GPR72 = 1096, SPR_INDEX_SYS_GPR73 = 1097, SPR_INDEX_SYS_GPR74 = 1098 31392+ , SPR_INDEX_SYS_GPR75 = 1099, SPR_INDEX_SYS_GPR76 = 1100, SPR_INDEX_SYS_GPR77 = 1101, SPR_INDEX_SYS_GPR78 = 1102 31393+ , SPR_INDEX_SYS_GPR79 = 1103, SPR_INDEX_SYS_GPR80 = 1104, SPR_INDEX_SYS_GPR81 = 1105, SPR_INDEX_SYS_GPR82 = 1106 31394+ , SPR_INDEX_SYS_GPR83 = 1107, SPR_INDEX_SYS_GPR84 = 1108, SPR_INDEX_SYS_GPR85 = 1109, SPR_INDEX_SYS_GPR86 = 1110 31395+ , SPR_INDEX_SYS_GPR87 = 1111, SPR_INDEX_SYS_GPR88 = 1112, SPR_INDEX_SYS_GPR89 = 1113, SPR_INDEX_SYS_GPR90 = 1114 31396+ , SPR_INDEX_SYS_GPR91 = 1115, SPR_INDEX_SYS_GPR92 = 1116, SPR_INDEX_SYS_GPR93 = 1117, SPR_INDEX_SYS_GPR94 = 1118 31397+ , SPR_INDEX_SYS_GPR95 = 1119, SPR_INDEX_SYS_GPR96 = 1120, SPR_INDEX_SYS_GPR97 = 1121, SPR_INDEX_SYS_GPR98 = 1122 31398+ , SPR_INDEX_SYS_GPR99 = 1123, SPR_INDEX_SYS_GPR100 = 1124, SPR_INDEX_SYS_GPR101 = 1125, SPR_INDEX_SYS_GPR102 = 1126 31399+ , SPR_INDEX_SYS_GPR103 = 1127, SPR_INDEX_SYS_GPR104 = 1128, SPR_INDEX_SYS_GPR105 = 1129, SPR_INDEX_SYS_GPR106 = 1130 31400+ , SPR_INDEX_SYS_GPR107 = 1131, SPR_INDEX_SYS_GPR108 = 1132, SPR_INDEX_SYS_GPR109 = 1133, SPR_INDEX_SYS_GPR110 = 1134 31401+ , SPR_INDEX_SYS_GPR111 = 1135, SPR_INDEX_SYS_GPR112 = 1136, SPR_INDEX_SYS_GPR113 = 1137, SPR_INDEX_SYS_GPR114 = 1138 31402+ , SPR_INDEX_SYS_GPR115 = 1139, SPR_INDEX_SYS_GPR116 = 1140, SPR_INDEX_SYS_GPR117 = 1141, SPR_INDEX_SYS_GPR118 = 1142 31403+ , SPR_INDEX_SYS_GPR119 = 1143, SPR_INDEX_SYS_GPR120 = 1144, SPR_INDEX_SYS_GPR121 = 1145, SPR_INDEX_SYS_GPR122 = 1146 31404+ , SPR_INDEX_SYS_GPR123 = 1147, SPR_INDEX_SYS_GPR124 = 1148, SPR_INDEX_SYS_GPR125 = 1149, SPR_INDEX_SYS_GPR126 = 1150 31405+ , SPR_INDEX_SYS_GPR127 = 1151, SPR_INDEX_SYS_GPR128 = 1152, SPR_INDEX_SYS_GPR129 = 1153, SPR_INDEX_SYS_GPR130 = 1154 31406+ , SPR_INDEX_SYS_GPR131 = 1155, SPR_INDEX_SYS_GPR132 = 1156, SPR_INDEX_SYS_GPR133 = 1157, SPR_INDEX_SYS_GPR134 = 1158 31407+ , SPR_INDEX_SYS_GPR135 = 1159, SPR_INDEX_SYS_GPR136 = 1160, SPR_INDEX_SYS_GPR137 = 1161, SPR_INDEX_SYS_GPR138 = 1162 31408+ , SPR_INDEX_SYS_GPR139 = 1163, SPR_INDEX_SYS_GPR140 = 1164, SPR_INDEX_SYS_GPR141 = 1165, SPR_INDEX_SYS_GPR142 = 1166 31409+ , SPR_INDEX_SYS_GPR143 = 1167, SPR_INDEX_SYS_GPR144 = 1168, SPR_INDEX_SYS_GPR145 = 1169, SPR_INDEX_SYS_GPR146 = 1170 31410+ , SPR_INDEX_SYS_GPR147 = 1171, SPR_INDEX_SYS_GPR148 = 1172, SPR_INDEX_SYS_GPR149 = 1173, SPR_INDEX_SYS_GPR150 = 1174 31411+ , SPR_INDEX_SYS_GPR151 = 1175, SPR_INDEX_SYS_GPR152 = 1176, SPR_INDEX_SYS_GPR153 = 1177, SPR_INDEX_SYS_GPR154 = 1178 31412+ , SPR_INDEX_SYS_GPR155 = 1179, SPR_INDEX_SYS_GPR156 = 1180, SPR_INDEX_SYS_GPR157 = 1181, SPR_INDEX_SYS_GPR158 = 1182 31413+ , SPR_INDEX_SYS_GPR159 = 1183, SPR_INDEX_SYS_GPR160 = 1184, SPR_INDEX_SYS_GPR161 = 1185, SPR_INDEX_SYS_GPR162 = 1186 31414+ , SPR_INDEX_SYS_GPR163 = 1187, SPR_INDEX_SYS_GPR164 = 1188, SPR_INDEX_SYS_GPR165 = 1189, SPR_INDEX_SYS_GPR166 = 1190 31415+ , SPR_INDEX_SYS_GPR167 = 1191, SPR_INDEX_SYS_GPR168 = 1192, SPR_INDEX_SYS_GPR169 = 1193, SPR_INDEX_SYS_GPR170 = 1194 31416+ , SPR_INDEX_SYS_GPR171 = 1195, SPR_INDEX_SYS_GPR172 = 1196, SPR_INDEX_SYS_GPR173 = 1197, SPR_INDEX_SYS_GPR174 = 1198 31417+ , SPR_INDEX_SYS_GPR175 = 1199, SPR_INDEX_SYS_GPR176 = 1200, SPR_INDEX_SYS_GPR177 = 1201, SPR_INDEX_SYS_GPR178 = 1202 31418+ , SPR_INDEX_SYS_GPR179 = 1203, SPR_INDEX_SYS_GPR180 = 1204, SPR_INDEX_SYS_GPR181 = 1205, SPR_INDEX_SYS_GPR182 = 1206 31419+ , SPR_INDEX_SYS_GPR183 = 1207, SPR_INDEX_SYS_GPR184 = 1208, SPR_INDEX_SYS_GPR185 = 1209, SPR_INDEX_SYS_GPR186 = 1210 31420+ , SPR_INDEX_SYS_GPR187 = 1211, SPR_INDEX_SYS_GPR188 = 1212, SPR_INDEX_SYS_GPR189 = 1213, SPR_INDEX_SYS_GPR190 = 1214 31421+ , SPR_INDEX_SYS_GPR191 = 1215, SPR_INDEX_SYS_GPR192 = 1216, SPR_INDEX_SYS_GPR193 = 1217, SPR_INDEX_SYS_GPR194 = 1218 31422+ , SPR_INDEX_SYS_GPR195 = 1219, SPR_INDEX_SYS_GPR196 = 1220, SPR_INDEX_SYS_GPR197 = 1221, SPR_INDEX_SYS_GPR198 = 1222 31423+ , SPR_INDEX_SYS_GPR199 = 1223, SPR_INDEX_SYS_GPR200 = 1224, SPR_INDEX_SYS_GPR201 = 1225, SPR_INDEX_SYS_GPR202 = 1226 31424+ , SPR_INDEX_SYS_GPR203 = 1227, SPR_INDEX_SYS_GPR204 = 1228, SPR_INDEX_SYS_GPR205 = 1229, SPR_INDEX_SYS_GPR206 = 1230 31425+ , SPR_INDEX_SYS_GPR207 = 1231, SPR_INDEX_SYS_GPR208 = 1232, SPR_INDEX_SYS_GPR209 = 1233, SPR_INDEX_SYS_GPR210 = 1234 31426+ , SPR_INDEX_SYS_GPR211 = 1235, SPR_INDEX_SYS_GPR212 = 1236, SPR_INDEX_SYS_GPR213 = 1237, SPR_INDEX_SYS_GPR214 = 1238 31427+ , SPR_INDEX_SYS_GPR215 = 1239, SPR_INDEX_SYS_GPR216 = 1240, SPR_INDEX_SYS_GPR217 = 1241, SPR_INDEX_SYS_GPR218 = 1242 31428+ , SPR_INDEX_SYS_GPR219 = 1243, SPR_INDEX_SYS_GPR220 = 1244, SPR_INDEX_SYS_GPR221 = 1245, SPR_INDEX_SYS_GPR222 = 1246 31429+ , SPR_INDEX_SYS_GPR223 = 1247, SPR_INDEX_SYS_GPR224 = 1248, SPR_INDEX_SYS_GPR225 = 1249, SPR_INDEX_SYS_GPR226 = 1250 31430+ , SPR_INDEX_SYS_GPR227 = 1251, SPR_INDEX_SYS_GPR228 = 1252, SPR_INDEX_SYS_GPR229 = 1253, SPR_INDEX_SYS_GPR230 = 1254 31431+ , SPR_INDEX_SYS_GPR231 = 1255, SPR_INDEX_SYS_GPR232 = 1256, SPR_INDEX_SYS_GPR233 = 1257, SPR_INDEX_SYS_GPR234 = 1258 31432+ , SPR_INDEX_SYS_GPR235 = 1259, SPR_INDEX_SYS_GPR236 = 1260, SPR_INDEX_SYS_GPR237 = 1261, SPR_INDEX_SYS_GPR238 = 1262 31433+ , SPR_INDEX_SYS_GPR239 = 1263, SPR_INDEX_SYS_GPR240 = 1264, SPR_INDEX_SYS_GPR241 = 1265, SPR_INDEX_SYS_GPR242 = 1266 31434+ , SPR_INDEX_SYS_GPR243 = 1267, SPR_INDEX_SYS_GPR244 = 1268, SPR_INDEX_SYS_GPR245 = 1269, SPR_INDEX_SYS_GPR246 = 1270 31435+ , SPR_INDEX_SYS_GPR247 = 1271, SPR_INDEX_SYS_GPR248 = 1272, SPR_INDEX_SYS_GPR249 = 1273, SPR_INDEX_SYS_GPR250 = 1274 31436+ , SPR_INDEX_SYS_GPR251 = 1275, SPR_INDEX_SYS_GPR252 = 1276, SPR_INDEX_SYS_GPR253 = 1277, SPR_INDEX_SYS_GPR254 = 1278 31437+ , SPR_INDEX_SYS_GPR255 = 1279, SPR_INDEX_SYS_GPR256 = 1280, SPR_INDEX_SYS_GPR257 = 1281, SPR_INDEX_SYS_GPR258 = 1282 31438+ , SPR_INDEX_SYS_GPR259 = 1283, SPR_INDEX_SYS_GPR260 = 1284, SPR_INDEX_SYS_GPR261 = 1285, SPR_INDEX_SYS_GPR262 = 1286 31439+ , SPR_INDEX_SYS_GPR263 = 1287, SPR_INDEX_SYS_GPR264 = 1288, SPR_INDEX_SYS_GPR265 = 1289, SPR_INDEX_SYS_GPR266 = 1290 31440+ , SPR_INDEX_SYS_GPR267 = 1291, SPR_INDEX_SYS_GPR268 = 1292, SPR_INDEX_SYS_GPR269 = 1293, SPR_INDEX_SYS_GPR270 = 1294 31441+ , SPR_INDEX_SYS_GPR271 = 1295, SPR_INDEX_SYS_GPR272 = 1296, SPR_INDEX_SYS_GPR273 = 1297, SPR_INDEX_SYS_GPR274 = 1298 31442+ , SPR_INDEX_SYS_GPR275 = 1299, SPR_INDEX_SYS_GPR276 = 1300, SPR_INDEX_SYS_GPR277 = 1301, SPR_INDEX_SYS_GPR278 = 1302 31443+ , SPR_INDEX_SYS_GPR279 = 1303, SPR_INDEX_SYS_GPR280 = 1304, SPR_INDEX_SYS_GPR281 = 1305, SPR_INDEX_SYS_GPR282 = 1306 31444+ , SPR_INDEX_SYS_GPR283 = 1307, SPR_INDEX_SYS_GPR284 = 1308, SPR_INDEX_SYS_GPR285 = 1309, SPR_INDEX_SYS_GPR286 = 1310 31445+ , SPR_INDEX_SYS_GPR287 = 1311, SPR_INDEX_SYS_GPR288 = 1312, SPR_INDEX_SYS_GPR289 = 1313, SPR_INDEX_SYS_GPR290 = 1314 31446+ , SPR_INDEX_SYS_GPR291 = 1315, SPR_INDEX_SYS_GPR292 = 1316, SPR_INDEX_SYS_GPR293 = 1317, SPR_INDEX_SYS_GPR294 = 1318 31447+ , SPR_INDEX_SYS_GPR295 = 1319, SPR_INDEX_SYS_GPR296 = 1320, SPR_INDEX_SYS_GPR297 = 1321, SPR_INDEX_SYS_GPR298 = 1322 31448+ , SPR_INDEX_SYS_GPR299 = 1323, SPR_INDEX_SYS_GPR300 = 1324, SPR_INDEX_SYS_GPR301 = 1325, SPR_INDEX_SYS_GPR302 = 1326 31449+ , SPR_INDEX_SYS_GPR303 = 1327, SPR_INDEX_SYS_GPR304 = 1328, SPR_INDEX_SYS_GPR305 = 1329, SPR_INDEX_SYS_GPR306 = 1330 31450+ , SPR_INDEX_SYS_GPR307 = 1331, SPR_INDEX_SYS_GPR308 = 1332, SPR_INDEX_SYS_GPR309 = 1333, SPR_INDEX_SYS_GPR310 = 1334 31451+ , SPR_INDEX_SYS_GPR311 = 1335, SPR_INDEX_SYS_GPR312 = 1336, SPR_INDEX_SYS_GPR313 = 1337, SPR_INDEX_SYS_GPR314 = 1338 31452+ , SPR_INDEX_SYS_GPR315 = 1339, SPR_INDEX_SYS_GPR316 = 1340, SPR_INDEX_SYS_GPR317 = 1341, SPR_INDEX_SYS_GPR318 = 1342 31453+ , SPR_INDEX_SYS_GPR319 = 1343, SPR_INDEX_SYS_GPR320 = 1344, SPR_INDEX_SYS_GPR321 = 1345, SPR_INDEX_SYS_GPR322 = 1346 31454+ , SPR_INDEX_SYS_GPR323 = 1347, SPR_INDEX_SYS_GPR324 = 1348, SPR_INDEX_SYS_GPR325 = 1349, SPR_INDEX_SYS_GPR326 = 1350 31455+ , SPR_INDEX_SYS_GPR327 = 1351, SPR_INDEX_SYS_GPR328 = 1352, SPR_INDEX_SYS_GPR329 = 1353, SPR_INDEX_SYS_GPR330 = 1354 31456+ , SPR_INDEX_SYS_GPR331 = 1355, SPR_INDEX_SYS_GPR332 = 1356, SPR_INDEX_SYS_GPR333 = 1357, SPR_INDEX_SYS_GPR334 = 1358 31457+ , SPR_INDEX_SYS_GPR335 = 1359, SPR_INDEX_SYS_GPR336 = 1360, SPR_INDEX_SYS_GPR337 = 1361, SPR_INDEX_SYS_GPR338 = 1362 31458+ , SPR_INDEX_SYS_GPR339 = 1363, SPR_INDEX_SYS_GPR340 = 1364, SPR_INDEX_SYS_GPR341 = 1365, SPR_INDEX_SYS_GPR342 = 1366 31459+ , SPR_INDEX_SYS_GPR343 = 1367, SPR_INDEX_SYS_GPR344 = 1368, SPR_INDEX_SYS_GPR345 = 1369, SPR_INDEX_SYS_GPR346 = 1370 31460+ , SPR_INDEX_SYS_GPR347 = 1371, SPR_INDEX_SYS_GPR348 = 1372, SPR_INDEX_SYS_GPR349 = 1373, SPR_INDEX_SYS_GPR350 = 1374 31461+ , SPR_INDEX_SYS_GPR351 = 1375, SPR_INDEX_SYS_GPR352 = 1376, SPR_INDEX_SYS_GPR353 = 1377, SPR_INDEX_SYS_GPR354 = 1378 31462+ , SPR_INDEX_SYS_GPR355 = 1379, SPR_INDEX_SYS_GPR356 = 1380, SPR_INDEX_SYS_GPR357 = 1381, SPR_INDEX_SYS_GPR358 = 1382 31463+ , SPR_INDEX_SYS_GPR359 = 1383, SPR_INDEX_SYS_GPR360 = 1384, SPR_INDEX_SYS_GPR361 = 1385, SPR_INDEX_SYS_GPR362 = 1386 31464+ , SPR_INDEX_SYS_GPR363 = 1387, SPR_INDEX_SYS_GPR364 = 1388, SPR_INDEX_SYS_GPR365 = 1389, SPR_INDEX_SYS_GPR366 = 1390 31465+ , SPR_INDEX_SYS_GPR367 = 1391, SPR_INDEX_SYS_GPR368 = 1392, SPR_INDEX_SYS_GPR369 = 1393, SPR_INDEX_SYS_GPR370 = 1394 31466+ , SPR_INDEX_SYS_GPR371 = 1395, SPR_INDEX_SYS_GPR372 = 1396, SPR_INDEX_SYS_GPR373 = 1397, SPR_INDEX_SYS_GPR374 = 1398 31467+ , SPR_INDEX_SYS_GPR375 = 1399, SPR_INDEX_SYS_GPR376 = 1400, SPR_INDEX_SYS_GPR377 = 1401, SPR_INDEX_SYS_GPR378 = 1402 31468+ , SPR_INDEX_SYS_GPR379 = 1403, SPR_INDEX_SYS_GPR380 = 1404, SPR_INDEX_SYS_GPR381 = 1405, SPR_INDEX_SYS_GPR382 = 1406 31469+ , SPR_INDEX_SYS_GPR383 = 1407, SPR_INDEX_SYS_GPR384 = 1408, SPR_INDEX_SYS_GPR385 = 1409, SPR_INDEX_SYS_GPR386 = 1410 31470+ , SPR_INDEX_SYS_GPR387 = 1411, SPR_INDEX_SYS_GPR388 = 1412, SPR_INDEX_SYS_GPR389 = 1413, SPR_INDEX_SYS_GPR390 = 1414 31471+ , SPR_INDEX_SYS_GPR391 = 1415, SPR_INDEX_SYS_GPR392 = 1416, SPR_INDEX_SYS_GPR393 = 1417, SPR_INDEX_SYS_GPR394 = 1418 31472+ , SPR_INDEX_SYS_GPR395 = 1419, SPR_INDEX_SYS_GPR396 = 1420, SPR_INDEX_SYS_GPR397 = 1421, SPR_INDEX_SYS_GPR398 = 1422 31473+ , SPR_INDEX_SYS_GPR399 = 1423, SPR_INDEX_SYS_GPR400 = 1424, SPR_INDEX_SYS_GPR401 = 1425, SPR_INDEX_SYS_GPR402 = 1426 31474+ , SPR_INDEX_SYS_GPR403 = 1427, SPR_INDEX_SYS_GPR404 = 1428, SPR_INDEX_SYS_GPR405 = 1429, SPR_INDEX_SYS_GPR406 = 1430 31475+ , SPR_INDEX_SYS_GPR407 = 1431, SPR_INDEX_SYS_GPR408 = 1432, SPR_INDEX_SYS_GPR409 = 1433, SPR_INDEX_SYS_GPR410 = 1434 31476+ , SPR_INDEX_SYS_GPR411 = 1435, SPR_INDEX_SYS_GPR412 = 1436, SPR_INDEX_SYS_GPR413 = 1437, SPR_INDEX_SYS_GPR414 = 1438 31477+ , SPR_INDEX_SYS_GPR415 = 1439, SPR_INDEX_SYS_GPR416 = 1440, SPR_INDEX_SYS_GPR417 = 1441, SPR_INDEX_SYS_GPR418 = 1442 31478+ , SPR_INDEX_SYS_GPR419 = 1443, SPR_INDEX_SYS_GPR420 = 1444, SPR_INDEX_SYS_GPR421 = 1445, SPR_INDEX_SYS_GPR422 = 1446 31479+ , SPR_INDEX_SYS_GPR423 = 1447, SPR_INDEX_SYS_GPR424 = 1448, SPR_INDEX_SYS_GPR425 = 1449, SPR_INDEX_SYS_GPR426 = 1450 31480+ , SPR_INDEX_SYS_GPR427 = 1451, SPR_INDEX_SYS_GPR428 = 1452, SPR_INDEX_SYS_GPR429 = 1453, SPR_INDEX_SYS_GPR430 = 1454 31481+ , SPR_INDEX_SYS_GPR431 = 1455, SPR_INDEX_SYS_GPR432 = 1456, SPR_INDEX_SYS_GPR433 = 1457, SPR_INDEX_SYS_GPR434 = 1458 31482+ , SPR_INDEX_SYS_GPR435 = 1459, SPR_INDEX_SYS_GPR436 = 1460, SPR_INDEX_SYS_GPR437 = 1461, SPR_INDEX_SYS_GPR438 = 1462 31483+ , SPR_INDEX_SYS_GPR439 = 1463, SPR_INDEX_SYS_GPR440 = 1464, SPR_INDEX_SYS_GPR441 = 1465, SPR_INDEX_SYS_GPR442 = 1466 31484+ , SPR_INDEX_SYS_GPR443 = 1467, SPR_INDEX_SYS_GPR444 = 1468, SPR_INDEX_SYS_GPR445 = 1469, SPR_INDEX_SYS_GPR446 = 1470 31485+ , SPR_INDEX_SYS_GPR447 = 1471, SPR_INDEX_SYS_GPR448 = 1472, SPR_INDEX_SYS_GPR449 = 1473, SPR_INDEX_SYS_GPR450 = 1474 31486+ , SPR_INDEX_SYS_GPR451 = 1475, SPR_INDEX_SYS_GPR452 = 1476, SPR_INDEX_SYS_GPR453 = 1477, SPR_INDEX_SYS_GPR454 = 1478 31487+ , SPR_INDEX_SYS_GPR455 = 1479, SPR_INDEX_SYS_GPR456 = 1480, SPR_INDEX_SYS_GPR457 = 1481, SPR_INDEX_SYS_GPR458 = 1482 31488+ , SPR_INDEX_SYS_GPR459 = 1483, SPR_INDEX_SYS_GPR460 = 1484, SPR_INDEX_SYS_GPR461 = 1485, SPR_INDEX_SYS_GPR462 = 1486 31489+ , SPR_INDEX_SYS_GPR463 = 1487, SPR_INDEX_SYS_GPR464 = 1488, SPR_INDEX_SYS_GPR465 = 1489, SPR_INDEX_SYS_GPR466 = 1490 31490+ , SPR_INDEX_SYS_GPR467 = 1491, SPR_INDEX_SYS_GPR468 = 1492, SPR_INDEX_SYS_GPR469 = 1493, SPR_INDEX_SYS_GPR470 = 1494 31491+ , SPR_INDEX_SYS_GPR471 = 1495, SPR_INDEX_SYS_GPR472 = 1496, SPR_INDEX_SYS_GPR473 = 1497, SPR_INDEX_SYS_GPR474 = 1498 31492+ , SPR_INDEX_SYS_GPR475 = 1499, SPR_INDEX_SYS_GPR476 = 1500, SPR_INDEX_SYS_GPR477 = 1501, SPR_INDEX_SYS_GPR478 = 1502 31493+ , SPR_INDEX_SYS_GPR479 = 1503, SPR_INDEX_SYS_GPR480 = 1504, SPR_INDEX_SYS_GPR481 = 1505, SPR_INDEX_SYS_GPR482 = 1506 31494+ , SPR_INDEX_SYS_GPR483 = 1507, SPR_INDEX_SYS_GPR484 = 1508, SPR_INDEX_SYS_GPR485 = 1509, SPR_INDEX_SYS_GPR486 = 1510 31495+ , SPR_INDEX_SYS_GPR487 = 1511, SPR_INDEX_SYS_GPR488 = 1512, SPR_INDEX_SYS_GPR489 = 1513, SPR_INDEX_SYS_GPR490 = 1514 31496+ , SPR_INDEX_SYS_GPR491 = 1515, SPR_INDEX_SYS_GPR492 = 1516, SPR_INDEX_SYS_GPR493 = 1517, SPR_INDEX_SYS_GPR494 = 1518 31497+ , SPR_INDEX_SYS_GPR495 = 1519, SPR_INDEX_SYS_GPR496 = 1520, SPR_INDEX_SYS_GPR497 = 1521, SPR_INDEX_SYS_GPR498 = 1522 31498+ , SPR_INDEX_SYS_GPR499 = 1523, SPR_INDEX_SYS_GPR500 = 1524, SPR_INDEX_SYS_GPR501 = 1525, SPR_INDEX_SYS_GPR502 = 1526 31499+ , SPR_INDEX_SYS_GPR503 = 1527, SPR_INDEX_SYS_GPR504 = 1528, SPR_INDEX_SYS_GPR505 = 1529, SPR_INDEX_SYS_GPR506 = 1530 31500+ , SPR_INDEX_SYS_GPR507 = 1531, SPR_INDEX_SYS_GPR508 = 1532, SPR_INDEX_SYS_GPR509 = 1533, SPR_INDEX_SYS_GPR510 = 1534 31501+ , SPR_INDEX_SYS_GPR511 = 1535, SPR_INDEX_MAC_MACLO = 1, SPR_INDEX_MAC_MACHI = 2, SPR_INDEX_TICK_TTMR = 0 31502+} SPR_REG_INDICES; 31503+ 31504+/* Enum declaration for SPR field msb positions. */ 31505+typedef enum spr_field_msbs { 31506+ SPR_FIELD_MSB_SYS_VR_REV = 5, SPR_FIELD_MSB_SYS_VR_CFG = 23, SPR_FIELD_MSB_SYS_VR_VER = 31, SPR_FIELD_MSB_SYS_UPR_UP = 0 31507+ , SPR_FIELD_MSB_SYS_UPR_DCP = 1, SPR_FIELD_MSB_SYS_UPR_ICP = 2, SPR_FIELD_MSB_SYS_UPR_DMP = 3, SPR_FIELD_MSB_SYS_UPR_MP = 4 31508+ , SPR_FIELD_MSB_SYS_UPR_IMP = 5, SPR_FIELD_MSB_SYS_UPR_DUP = 6, SPR_FIELD_MSB_SYS_UPR_PCUP = 7, SPR_FIELD_MSB_SYS_UPR_PICP = 8 31509+ , SPR_FIELD_MSB_SYS_UPR_PMP = 9, SPR_FIELD_MSB_SYS_UPR_TTP = 10, SPR_FIELD_MSB_SYS_UPR_CUP = 31, SPR_FIELD_MSB_SYS_CPUCFGR_NSGR = 3 31510+ , SPR_FIELD_MSB_SYS_CPUCFGR_CGF = 4, SPR_FIELD_MSB_SYS_CPUCFGR_OB32S = 5, SPR_FIELD_MSB_SYS_CPUCFGR_OB64S = 6, SPR_FIELD_MSB_SYS_CPUCFGR_OF32S = 7 31511+ , SPR_FIELD_MSB_SYS_CPUCFGR_OF64S = 8, SPR_FIELD_MSB_SYS_CPUCFGR_OV64S = 9, SPR_FIELD_MSB_SYS_CPUCFGR_ND = 10, SPR_FIELD_MSB_SYS_SR_SM = 0 31512+ , SPR_FIELD_MSB_SYS_SR_TEE = 1, SPR_FIELD_MSB_SYS_SR_IEE = 2, SPR_FIELD_MSB_SYS_SR_DCE = 3, SPR_FIELD_MSB_SYS_SR_ICE = 4 31513+ , SPR_FIELD_MSB_SYS_SR_DME = 5, SPR_FIELD_MSB_SYS_SR_IME = 6, SPR_FIELD_MSB_SYS_SR_LEE = 7, SPR_FIELD_MSB_SYS_SR_CE = 8 31514+ , SPR_FIELD_MSB_SYS_SR_F = 9, SPR_FIELD_MSB_SYS_SR_CY = 10, SPR_FIELD_MSB_SYS_SR_OV = 11, SPR_FIELD_MSB_SYS_SR_OVE = 12 31515+ , SPR_FIELD_MSB_SYS_SR_DSX = 13, SPR_FIELD_MSB_SYS_SR_EPH = 14, SPR_FIELD_MSB_SYS_SR_FO = 15, SPR_FIELD_MSB_SYS_SR_SUMRA = 16 31516+ , SPR_FIELD_MSB_SYS_SR_CID = 31, SPR_FIELD_MSB_SYS_FPCSR_FPEE = 0, SPR_FIELD_MSB_SYS_FPCSR_RM = 2, SPR_FIELD_MSB_SYS_FPCSR_OVF = 3 31517+ , SPR_FIELD_MSB_SYS_FPCSR_UNF = 4, SPR_FIELD_MSB_SYS_FPCSR_SNF = 5, SPR_FIELD_MSB_SYS_FPCSR_QNF = 6, SPR_FIELD_MSB_SYS_FPCSR_ZF = 7 31518+ , SPR_FIELD_MSB_SYS_FPCSR_IXF = 8, SPR_FIELD_MSB_SYS_FPCSR_IVF = 9, SPR_FIELD_MSB_SYS_FPCSR_INF = 10, SPR_FIELD_MSB_SYS_FPCSR_DZF = 11 31519+} SPR_FIELD_MSBS; 31520+ 31521+/* Enum declaration for SPR field lsb positions. */ 31522+typedef enum spr_field_lsbs { 31523+ SPR_FIELD_SIZE_SYS_VR_REV = 0, SPR_FIELD_SIZE_SYS_VR_CFG = 16, SPR_FIELD_SIZE_SYS_VR_VER = 24, SPR_FIELD_SIZE_SYS_UPR_UP = 0 31524+ , SPR_FIELD_SIZE_SYS_UPR_DCP = 1, SPR_FIELD_SIZE_SYS_UPR_ICP = 2, SPR_FIELD_SIZE_SYS_UPR_DMP = 3, SPR_FIELD_SIZE_SYS_UPR_MP = 4 31525+ , SPR_FIELD_SIZE_SYS_UPR_IMP = 5, SPR_FIELD_SIZE_SYS_UPR_DUP = 6, SPR_FIELD_SIZE_SYS_UPR_PCUP = 7, SPR_FIELD_SIZE_SYS_UPR_PICP = 8 31526+ , SPR_FIELD_SIZE_SYS_UPR_PMP = 9, SPR_FIELD_SIZE_SYS_UPR_TTP = 10, SPR_FIELD_SIZE_SYS_UPR_CUP = 24, SPR_FIELD_SIZE_SYS_CPUCFGR_NSGR = 0 31527+ , SPR_FIELD_SIZE_SYS_CPUCFGR_CGF = 4, SPR_FIELD_SIZE_SYS_CPUCFGR_OB32S = 5, SPR_FIELD_SIZE_SYS_CPUCFGR_OB64S = 6, SPR_FIELD_SIZE_SYS_CPUCFGR_OF32S = 7 31528+ , SPR_FIELD_SIZE_SYS_CPUCFGR_OF64S = 8, SPR_FIELD_SIZE_SYS_CPUCFGR_OV64S = 9, SPR_FIELD_SIZE_SYS_CPUCFGR_ND = 10, SPR_FIELD_SIZE_SYS_SR_SM = 0 31529+ , SPR_FIELD_SIZE_SYS_SR_TEE = 1, SPR_FIELD_SIZE_SYS_SR_IEE = 2, SPR_FIELD_SIZE_SYS_SR_DCE = 3, SPR_FIELD_SIZE_SYS_SR_ICE = 4 31530+ , SPR_FIELD_SIZE_SYS_SR_DME = 5, SPR_FIELD_SIZE_SYS_SR_IME = 6, SPR_FIELD_SIZE_SYS_SR_LEE = 7, SPR_FIELD_SIZE_SYS_SR_CE = 8 31531+ , SPR_FIELD_SIZE_SYS_SR_F = 9, SPR_FIELD_SIZE_SYS_SR_CY = 10, SPR_FIELD_SIZE_SYS_SR_OV = 11, SPR_FIELD_SIZE_SYS_SR_OVE = 12 31532+ , SPR_FIELD_SIZE_SYS_SR_DSX = 13, SPR_FIELD_SIZE_SYS_SR_EPH = 14, SPR_FIELD_SIZE_SYS_SR_FO = 15, SPR_FIELD_SIZE_SYS_SR_SUMRA = 16 31533+ , SPR_FIELD_SIZE_SYS_SR_CID = 28, SPR_FIELD_SIZE_SYS_FPCSR_FPEE = 0, SPR_FIELD_SIZE_SYS_FPCSR_RM = 1, SPR_FIELD_SIZE_SYS_FPCSR_OVF = 3 31534+ , SPR_FIELD_SIZE_SYS_FPCSR_UNF = 4, SPR_FIELD_SIZE_SYS_FPCSR_SNF = 5, SPR_FIELD_SIZE_SYS_FPCSR_QNF = 6, SPR_FIELD_SIZE_SYS_FPCSR_ZF = 7 31535+ , SPR_FIELD_SIZE_SYS_FPCSR_IXF = 8, SPR_FIELD_SIZE_SYS_FPCSR_IVF = 9, SPR_FIELD_SIZE_SYS_FPCSR_INF = 10, SPR_FIELD_SIZE_SYS_FPCSR_DZF = 11 31536+} SPR_FIELD_LSBS; 31537+ 31538+/* Enum declaration for SPR field masks. */ 31539+typedef enum spr_field_masks { 31540+ SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIELD_MASK_SYS_VR_VER = 4278190080u, SPR_FIELD_MASK_SYS_UPR_UP = 1 31541+ , SPR_FIELD_MASK_SYS_UPR_DCP = 2, SPR_FIELD_MASK_SYS_UPR_ICP = 4, SPR_FIELD_MASK_SYS_UPR_DMP = 8, SPR_FIELD_MASK_SYS_UPR_MP = 16 31542+ , SPR_FIELD_MASK_SYS_UPR_IMP = 32, SPR_FIELD_MASK_SYS_UPR_DUP = 64, SPR_FIELD_MASK_SYS_UPR_PCUP = 128, SPR_FIELD_MASK_SYS_UPR_PICP = 256 31543+ , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIELD_MASK_SYS_UPR_CUP = 4278190080u, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15 31544+ , SPR_FIELD_MASK_SYS_CPUCFGR_CGF = 16, SPR_FIELD_MASK_SYS_CPUCFGR_OB32S = 32, SPR_FIELD_MASK_SYS_CPUCFGR_OB64S = 64, SPR_FIELD_MASK_SYS_CPUCFGR_OF32S = 128 31545+ , SPR_FIELD_MASK_SYS_CPUCFGR_OF64S = 256, SPR_FIELD_MASK_SYS_CPUCFGR_OV64S = 512, SPR_FIELD_MASK_SYS_CPUCFGR_ND = 1024, SPR_FIELD_MASK_SYS_SR_SM = 1 31546+ , SPR_FIELD_MASK_SYS_SR_TEE = 2, SPR_FIELD_MASK_SYS_SR_IEE = 4, SPR_FIELD_MASK_SYS_SR_DCE = 8, SPR_FIELD_MASK_SYS_SR_ICE = 16 31547+ , SPR_FIELD_MASK_SYS_SR_DME = 32, SPR_FIELD_MASK_SYS_SR_IME = 64, SPR_FIELD_MASK_SYS_SR_LEE = 128, SPR_FIELD_MASK_SYS_SR_CE = 256 31548+ , SPR_FIELD_MASK_SYS_SR_F = 512, SPR_FIELD_MASK_SYS_SR_CY = 1024, SPR_FIELD_MASK_SYS_SR_OV = 2048, SPR_FIELD_MASK_SYS_SR_OVE = 4096 31549+ , SPR_FIELD_MASK_SYS_SR_DSX = 8192, SPR_FIELD_MASK_SYS_SR_EPH = 16384, SPR_FIELD_MASK_SYS_SR_FO = 32768, SPR_FIELD_MASK_SYS_SR_SUMRA = 65536 31550+ , SPR_FIELD_MASK_SYS_SR_CID = 4026531840u, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, SPR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8 31551+ , SPR_FIELD_MASK_SYS_FPCSR_UNF = 16, SPR_FIELD_MASK_SYS_FPCSR_SNF = 32, SPR_FIELD_MASK_SYS_FPCSR_QNF = 64, SPR_FIELD_MASK_SYS_FPCSR_ZF = 128 31552+ , SPR_FIELD_MASK_SYS_FPCSR_IXF = 256, SPR_FIELD_MASK_SYS_FPCSR_IVF = 512, SPR_FIELD_MASK_SYS_FPCSR_INF = 1024, SPR_FIELD_MASK_SYS_FPCSR_DZF = 2048 31553+} SPR_FIELD_MASKS; 31554+ 31555+/* Enum declaration for insn main opcode enums. */ 31556+typedef enum insn_opcode { 31557+ OPC_J = 0, OPC_JAL = 1, OPC_BNF = 3, OPC_BF = 4 31558+ , OPC_NOP = 5, OPC_MOVHIMACRC = 6, OPC_SYSTRAPSYNCS = 8, OPC_RFE = 9 31559+ , OPC_VECTOR = 10, OPC_JR = 17, OPC_JALR = 18, OPC_MACI = 19 31560+ , OPC_LWA = 27, OPC_CUST1 = 28, OPC_CUST2 = 29, OPC_CUST3 = 30 31561+ , OPC_CUST4 = 31, OPC_LD = 32, OPC_LWZ = 33, OPC_LWS = 34 31562+ , OPC_LBZ = 35, OPC_LBS = 36, OPC_LHZ = 37, OPC_LHS = 38 31563+ , OPC_ADDI = 39, OPC_ADDIC = 40, OPC_ANDI = 41, OPC_ORI = 42 31564+ , OPC_XORI = 43, OPC_MULI = 44, OPC_MFSPR = 45, OPC_SHROTI = 46 31565+ , OPC_SFI = 47, OPC_MTSPR = 48, OPC_MAC = 49, OPC_FLOAT = 50 31566+ , OPC_SWA = 51, OPC_SD = 52, OPC_SW = 53, OPC_SB = 54 31567+ , OPC_SH = 55, OPC_ALU = 56, OPC_SF = 57, OPC_CUST5 = 60 31568+ , OPC_CUST6 = 61, OPC_CUST7 = 62, OPC_CUST8 = 63 31569+} INSN_OPCODE; 31570+ 31571+/* Enum declaration for systrapsync insn opcode enums. */ 31572+typedef enum insn_opcode_systrapsyncs { 31573+ OPC_SYSTRAPSYNCS_SYSCALL = 0, OPC_SYSTRAPSYNCS_TRAP = 8, OPC_SYSTRAPSYNCS_MSYNC = 16, OPC_SYSTRAPSYNCS_PSYNC = 20 31574+ , OPC_SYSTRAPSYNCS_CSYNC = 24 31575+} INSN_OPCODE_SYSTRAPSYNCS; 31576+ 31577+/* Enum declaration for movhi/macrc insn opcode enums. */ 31578+typedef enum insn_opcode_movehimacrc { 31579+ OPC_MOVHIMACRC_MOVHI, OPC_MOVHIMACRC_MACRC 31580+} INSN_OPCODE_MOVEHIMACRC; 31581+ 31582+/* Enum declaration for multiply/accumulate insn opcode enums. */ 31583+typedef enum insn_opcode_mac { 31584+ OPC_MAC_MAC = 1, OPC_MAC_MSB = 2 31585+} INSN_OPCODE_MAC; 31586+ 31587+/* Enum declaration for shift/rotate insn opcode enums. */ 31588+typedef enum insn_opcode_shorts { 31589+ OPC_SHROTS_SLL, OPC_SHROTS_SRL, OPC_SHROTS_SRA, OPC_SHROTS_ROR 31590+} INSN_OPCODE_SHORTS; 31591+ 31592+/* Enum declaration for extend byte/half opcode enums. */ 31593+typedef enum insn_opcode_extbhs { 31594+ OPC_EXTBHS_EXTHS, OPC_EXTBHS_EXTBS, OPC_EXTBHS_EXTHZ, OPC_EXTBHS_EXTBZ 31595+} INSN_OPCODE_EXTBHS; 31596+ 31597+/* Enum declaration for extend word opcode enums. */ 31598+typedef enum insn_opcode_extws { 31599+ OPC_EXTWS_EXTWS, OPC_EXTWS_EXTWZ 31600+} INSN_OPCODE_EXTWS; 31601+ 31602+/* Enum declaration for alu reg/reg insn opcode enums. */ 31603+typedef enum insn_opcode_alu_regreg { 31604+ OPC_ALU_REGREG_ADD = 0, OPC_ALU_REGREG_ADDC = 1, OPC_ALU_REGREG_SUB = 2, OPC_ALU_REGREG_AND = 3 31605+ , OPC_ALU_REGREG_OR = 4, OPC_ALU_REGREG_XOR = 5, OPC_ALU_REGREG_MUL = 6, OPC_ALU_REGREG_SHROT = 8 31606+ , OPC_ALU_REGREG_DIV = 9, OPC_ALU_REGREG_DIVU = 10, OPC_ALU_REGREG_MULU = 11, OPC_ALU_REGREG_EXTBH = 12 31607+ , OPC_ALU_REGREG_EXTW = 13, OPC_ALU_REGREG_CMOV = 14, OPC_ALU_REGREG_FFL1 = 15 31608+} INSN_OPCODE_ALU_REGREG; 31609+ 31610+/* Enum declaration for setflag insn opcode enums. */ 31611+typedef enum insn_opcode_setflag { 31612+ OPC_SF_EQ = 0, OPC_SF_NE = 1, OPC_SF_GTU = 2, OPC_SF_GEU = 3 31613+ , OPC_SF_LTU = 4, OPC_SF_LEU = 5, OPC_SF_GTS = 10, OPC_SF_GES = 11 31614+ , OPC_SF_LTS = 12, OPC_SF_LES = 13 31615+} INSN_OPCODE_SETFLAG; 31616+ 31617+/* Enum declaration for floating point reg/reg insn opcode enums. */ 31618+typedef enum insn_opcode_float_regreg { 31619+ OPC_FLOAT_REGREG_ADD_S = 0, OPC_FLOAT_REGREG_SUB_S = 1, OPC_FLOAT_REGREG_MUL_S = 2, OPC_FLOAT_REGREG_DIV_S = 3 31620+ , OPC_FLOAT_REGREG_ITOF_S = 4, OPC_FLOAT_REGREG_FTOI_S = 5, OPC_FLOAT_REGREG_REM_S = 6, OPC_FLOAT_REGREG_MADD_S = 7 31621+ , OPC_FLOAT_REGREG_SFEQ_S = 8, OPC_FLOAT_REGREG_SFNE_S = 9, OPC_FLOAT_REGREG_SFGT_S = 10, OPC_FLOAT_REGREG_SFGE_S = 11 31622+ , OPC_FLOAT_REGREG_SFLT_S = 12, OPC_FLOAT_REGREG_SFLE_S = 13, OPC_FLOAT_REGREG_ADD_D = 16, OPC_FLOAT_REGREG_SUB_D = 17 31623+ , OPC_FLOAT_REGREG_MUL_D = 18, OPC_FLOAT_REGREG_DIV_D = 19, OPC_FLOAT_REGREG_ITOF_D = 20, OPC_FLOAT_REGREG_FTOI_D = 21 31624+ , OPC_FLOAT_REGREG_REM_D = 22, OPC_FLOAT_REGREG_MADD_D = 23, OPC_FLOAT_REGREG_SFEQ_D = 24, OPC_FLOAT_REGREG_SFNE_D = 25 31625+ , OPC_FLOAT_REGREG_SFGT_D = 26, OPC_FLOAT_REGREG_SFGE_D = 27, OPC_FLOAT_REGREG_SFLT_D = 28, OPC_FLOAT_REGREG_SFLE_D = 29 31626+ , OPC_FLOAT_REGREG_CUST1_S = 208, OPC_FLOAT_REGREG_CUST1_D = 224 31627+} INSN_OPCODE_FLOAT_REGREG; 31628+ 31629+/* Attributes. */ 31630+ 31631+/* Enum declaration for machine type selection. */ 31632+typedef enum mach_attr { 31633+ MACH_BASE, MACH_OR32, MACH_OR32ND, MACH_OR64 31634+ , MACH_OR64ND, MACH_MAX 31635+} MACH_ATTR; 31636+ 31637+/* Enum declaration for instruction set selection. */ 31638+typedef enum isa_attr { 31639+ ISA_OPENRISC, ISA_MAX 31640+} ISA_ATTR; 31641+ 31642+/* Number of architecture variants. */ 31643+#define MAX_ISAS 1 31644+#define MAX_MACHS ((int) MACH_MAX) 31645+ 31646+/* Ifield support. */ 31647+ 31648+/* Ifield attribute indices. */ 31649+ 31650+/* Enum declaration for cgen_ifld attrs. */ 31651+typedef enum cgen_ifld_attr { 31652+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 31653+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 31654+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 31655+} CGEN_IFLD_ATTR; 31656+ 31657+/* Number of non-boolean elements in cgen_ifld_attr. */ 31658+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 31659+ 31660+/* cgen_ifld attribute accessor macros. */ 31661+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 31662+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 31663+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 31664+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 31665+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 31666+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 31667+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 31668+ 31669+/* Enum declaration for or1k ifield types. */ 31670+typedef enum ifield_type { 31671+ OR1K_F_NIL, OR1K_F_ANYOF, OR1K_F_OPCODE, OR1K_F_R1 31672+ , OR1K_F_R2, OR1K_F_R3, OR1K_F_OP_25_2, OR1K_F_OP_25_5 31673+ , OR1K_F_OP_16_1, OR1K_F_OP_7_4, OR1K_F_OP_3_4, OR1K_F_OP_9_2 31674+ , OR1K_F_OP_9_4, OR1K_F_OP_7_8, OR1K_F_OP_7_2, OR1K_F_RESV_25_26 31675+ , OR1K_F_RESV_25_10, OR1K_F_RESV_25_5, OR1K_F_RESV_23_8, OR1K_F_RESV_20_21 31676+ , OR1K_F_RESV_20_5, OR1K_F_RESV_20_4, OR1K_F_RESV_15_8, OR1K_F_RESV_15_6 31677+ , OR1K_F_RESV_10_11, OR1K_F_RESV_10_7, OR1K_F_RESV_10_3, OR1K_F_RESV_10_1 31678+ , OR1K_F_RESV_7_4, OR1K_F_RESV_5_2, OR1K_F_IMM16_25_5, OR1K_F_IMM16_10_11 31679+ , OR1K_F_DISP26, OR1K_F_UIMM16, OR1K_F_SIMM16, OR1K_F_UIMM6 31680+ , OR1K_F_UIMM16_SPLIT, OR1K_F_SIMM16_SPLIT, OR1K_F_MAX 31681+} IFIELD_TYPE; 31682+ 31683+#define MAX_IFLD ((int) OR1K_F_MAX) 31684+ 31685+/* Hardware attribute indices. */ 31686+ 31687+/* Enum declaration for cgen_hw attrs. */ 31688+typedef enum cgen_hw_attr { 31689+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 31690+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 31691+} CGEN_HW_ATTR; 31692+ 31693+/* Number of non-boolean elements in cgen_hw_attr. */ 31694+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 31695+ 31696+/* cgen_hw attribute accessor macros. */ 31697+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 31698+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 31699+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 31700+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 31701+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 31702+ 31703+/* Enum declaration for or1k hardware types. */ 31704+typedef enum cgen_hw_type { 31705+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 31706+ , HW_H_IADDR, HW_H_PC, HW_H_FSR, HW_H_FDR 31707+ , HW_H_SPR, HW_H_GPR, HW_H_SYS_VR, HW_H_SYS_UPR 31708+ , HW_H_SYS_CPUCFGR, HW_H_SYS_DMMUCFGR, HW_H_SYS_IMMUCFGR, HW_H_SYS_DCCFGR 31709+ , HW_H_SYS_ICCFGR, HW_H_SYS_DCFGR, HW_H_SYS_PCCFGR, HW_H_SYS_NPC 31710+ , HW_H_SYS_SR, HW_H_SYS_PPC, HW_H_SYS_FPCSR, HW_H_SYS_EPCR0 31711+ , HW_H_SYS_EPCR1, HW_H_SYS_EPCR2, HW_H_SYS_EPCR3, HW_H_SYS_EPCR4 31712+ , HW_H_SYS_EPCR5, HW_H_SYS_EPCR6, HW_H_SYS_EPCR7, HW_H_SYS_EPCR8 31713+ , HW_H_SYS_EPCR9, HW_H_SYS_EPCR10, HW_H_SYS_EPCR11, HW_H_SYS_EPCR12 31714+ , HW_H_SYS_EPCR13, HW_H_SYS_EPCR14, HW_H_SYS_EPCR15, HW_H_SYS_EEAR0 31715+ , HW_H_SYS_EEAR1, HW_H_SYS_EEAR2, HW_H_SYS_EEAR3, HW_H_SYS_EEAR4 31716+ , HW_H_SYS_EEAR5, HW_H_SYS_EEAR6, HW_H_SYS_EEAR7, HW_H_SYS_EEAR8 31717+ , HW_H_SYS_EEAR9, HW_H_SYS_EEAR10, HW_H_SYS_EEAR11, HW_H_SYS_EEAR12 31718+ , HW_H_SYS_EEAR13, HW_H_SYS_EEAR14, HW_H_SYS_EEAR15, HW_H_SYS_ESR0 31719+ , HW_H_SYS_ESR1, HW_H_SYS_ESR2, HW_H_SYS_ESR3, HW_H_SYS_ESR4 31720+ , HW_H_SYS_ESR5, HW_H_SYS_ESR6, HW_H_SYS_ESR7, HW_H_SYS_ESR8 31721+ , HW_H_SYS_ESR9, HW_H_SYS_ESR10, HW_H_SYS_ESR11, HW_H_SYS_ESR12 31722+ , HW_H_SYS_ESR13, HW_H_SYS_ESR14, HW_H_SYS_ESR15, HW_H_SYS_GPR0 31723+ , HW_H_SYS_GPR1, HW_H_SYS_GPR2, HW_H_SYS_GPR3, HW_H_SYS_GPR4 31724+ , HW_H_SYS_GPR5, HW_H_SYS_GPR6, HW_H_SYS_GPR7, HW_H_SYS_GPR8 31725+ , HW_H_SYS_GPR9, HW_H_SYS_GPR10, HW_H_SYS_GPR11, HW_H_SYS_GPR12 31726+ , HW_H_SYS_GPR13, HW_H_SYS_GPR14, HW_H_SYS_GPR15, HW_H_SYS_GPR16 31727+ , HW_H_SYS_GPR17, HW_H_SYS_GPR18, HW_H_SYS_GPR19, HW_H_SYS_GPR20 31728+ , HW_H_SYS_GPR21, HW_H_SYS_GPR22, HW_H_SYS_GPR23, HW_H_SYS_GPR24 31729+ , HW_H_SYS_GPR25, HW_H_SYS_GPR26, HW_H_SYS_GPR27, HW_H_SYS_GPR28 31730+ , HW_H_SYS_GPR29, HW_H_SYS_GPR30, HW_H_SYS_GPR31, HW_H_SYS_GPR32 31731+ , HW_H_SYS_GPR33, HW_H_SYS_GPR34, HW_H_SYS_GPR35, HW_H_SYS_GPR36 31732+ , HW_H_SYS_GPR37, HW_H_SYS_GPR38, HW_H_SYS_GPR39, HW_H_SYS_GPR40 31733+ , HW_H_SYS_GPR41, HW_H_SYS_GPR42, HW_H_SYS_GPR43, HW_H_SYS_GPR44 31734+ , HW_H_SYS_GPR45, HW_H_SYS_GPR46, HW_H_SYS_GPR47, HW_H_SYS_GPR48 31735+ , HW_H_SYS_GPR49, HW_H_SYS_GPR50, HW_H_SYS_GPR51, HW_H_SYS_GPR52 31736+ , HW_H_SYS_GPR53, HW_H_SYS_GPR54, HW_H_SYS_GPR55, HW_H_SYS_GPR56 31737+ , HW_H_SYS_GPR57, HW_H_SYS_GPR58, HW_H_SYS_GPR59, HW_H_SYS_GPR60 31738+ , HW_H_SYS_GPR61, HW_H_SYS_GPR62, HW_H_SYS_GPR63, HW_H_SYS_GPR64 31739+ , HW_H_SYS_GPR65, HW_H_SYS_GPR66, HW_H_SYS_GPR67, HW_H_SYS_GPR68 31740+ , HW_H_SYS_GPR69, HW_H_SYS_GPR70, HW_H_SYS_GPR71, HW_H_SYS_GPR72 31741+ , HW_H_SYS_GPR73, HW_H_SYS_GPR74, HW_H_SYS_GPR75, HW_H_SYS_GPR76 31742+ , HW_H_SYS_GPR77, HW_H_SYS_GPR78, HW_H_SYS_GPR79, HW_H_SYS_GPR80 31743+ , HW_H_SYS_GPR81, HW_H_SYS_GPR82, HW_H_SYS_GPR83, HW_H_SYS_GPR84 31744+ , HW_H_SYS_GPR85, HW_H_SYS_GPR86, HW_H_SYS_GPR87, HW_H_SYS_GPR88 31745+ , HW_H_SYS_GPR89, HW_H_SYS_GPR90, HW_H_SYS_GPR91, HW_H_SYS_GPR92 31746+ , HW_H_SYS_GPR93, HW_H_SYS_GPR94, HW_H_SYS_GPR95, HW_H_SYS_GPR96 31747+ , HW_H_SYS_GPR97, HW_H_SYS_GPR98, HW_H_SYS_GPR99, HW_H_SYS_GPR100 31748+ , HW_H_SYS_GPR101, HW_H_SYS_GPR102, HW_H_SYS_GPR103, HW_H_SYS_GPR104 31749+ , HW_H_SYS_GPR105, HW_H_SYS_GPR106, HW_H_SYS_GPR107, HW_H_SYS_GPR108 31750+ , HW_H_SYS_GPR109, HW_H_SYS_GPR110, HW_H_SYS_GPR111, HW_H_SYS_GPR112 31751+ , HW_H_SYS_GPR113, HW_H_SYS_GPR114, HW_H_SYS_GPR115, HW_H_SYS_GPR116 31752+ , HW_H_SYS_GPR117, HW_H_SYS_GPR118, HW_H_SYS_GPR119, HW_H_SYS_GPR120 31753+ , HW_H_SYS_GPR121, HW_H_SYS_GPR122, HW_H_SYS_GPR123, HW_H_SYS_GPR124 31754+ , HW_H_SYS_GPR125, HW_H_SYS_GPR126, HW_H_SYS_GPR127, HW_H_SYS_GPR128 31755+ , HW_H_SYS_GPR129, HW_H_SYS_GPR130, HW_H_SYS_GPR131, HW_H_SYS_GPR132 31756+ , HW_H_SYS_GPR133, HW_H_SYS_GPR134, HW_H_SYS_GPR135, HW_H_SYS_GPR136 31757+ , HW_H_SYS_GPR137, HW_H_SYS_GPR138, HW_H_SYS_GPR139, HW_H_SYS_GPR140 31758+ , HW_H_SYS_GPR141, HW_H_SYS_GPR142, HW_H_SYS_GPR143, HW_H_SYS_GPR144 31759+ , HW_H_SYS_GPR145, HW_H_SYS_GPR146, HW_H_SYS_GPR147, HW_H_SYS_GPR148 31760+ , HW_H_SYS_GPR149, HW_H_SYS_GPR150, HW_H_SYS_GPR151, HW_H_SYS_GPR152 31761+ , HW_H_SYS_GPR153, HW_H_SYS_GPR154, HW_H_SYS_GPR155, HW_H_SYS_GPR156 31762+ , HW_H_SYS_GPR157, HW_H_SYS_GPR158, HW_H_SYS_GPR159, HW_H_SYS_GPR160 31763+ , HW_H_SYS_GPR161, HW_H_SYS_GPR162, HW_H_SYS_GPR163, HW_H_SYS_GPR164 31764+ , HW_H_SYS_GPR165, HW_H_SYS_GPR166, HW_H_SYS_GPR167, HW_H_SYS_GPR168 31765+ , HW_H_SYS_GPR169, HW_H_SYS_GPR170, HW_H_SYS_GPR171, HW_H_SYS_GPR172 31766+ , HW_H_SYS_GPR173, HW_H_SYS_GPR174, HW_H_SYS_GPR175, HW_H_SYS_GPR176 31767+ , HW_H_SYS_GPR177, HW_H_SYS_GPR178, HW_H_SYS_GPR179, HW_H_SYS_GPR180 31768+ , HW_H_SYS_GPR181, HW_H_SYS_GPR182, HW_H_SYS_GPR183, HW_H_SYS_GPR184 31769+ , HW_H_SYS_GPR185, HW_H_SYS_GPR186, HW_H_SYS_GPR187, HW_H_SYS_GPR188 31770+ , HW_H_SYS_GPR189, HW_H_SYS_GPR190, HW_H_SYS_GPR191, HW_H_SYS_GPR192 31771+ , HW_H_SYS_GPR193, HW_H_SYS_GPR194, HW_H_SYS_GPR195, HW_H_SYS_GPR196 31772+ , HW_H_SYS_GPR197, HW_H_SYS_GPR198, HW_H_SYS_GPR199, HW_H_SYS_GPR200 31773+ , HW_H_SYS_GPR201, HW_H_SYS_GPR202, HW_H_SYS_GPR203, HW_H_SYS_GPR204 31774+ , HW_H_SYS_GPR205, HW_H_SYS_GPR206, HW_H_SYS_GPR207, HW_H_SYS_GPR208 31775+ , HW_H_SYS_GPR209, HW_H_SYS_GPR210, HW_H_SYS_GPR211, HW_H_SYS_GPR212 31776+ , HW_H_SYS_GPR213, HW_H_SYS_GPR214, HW_H_SYS_GPR215, HW_H_SYS_GPR216 31777+ , HW_H_SYS_GPR217, HW_H_SYS_GPR218, HW_H_SYS_GPR219, HW_H_SYS_GPR220 31778+ , HW_H_SYS_GPR221, HW_H_SYS_GPR222, HW_H_SYS_GPR223, HW_H_SYS_GPR224 31779+ , HW_H_SYS_GPR225, HW_H_SYS_GPR226, HW_H_SYS_GPR227, HW_H_SYS_GPR228 31780+ , HW_H_SYS_GPR229, HW_H_SYS_GPR230, HW_H_SYS_GPR231, HW_H_SYS_GPR232 31781+ , HW_H_SYS_GPR233, HW_H_SYS_GPR234, HW_H_SYS_GPR235, HW_H_SYS_GPR236 31782+ , HW_H_SYS_GPR237, HW_H_SYS_GPR238, HW_H_SYS_GPR239, HW_H_SYS_GPR240 31783+ , HW_H_SYS_GPR241, HW_H_SYS_GPR242, HW_H_SYS_GPR243, HW_H_SYS_GPR244 31784+ , HW_H_SYS_GPR245, HW_H_SYS_GPR246, HW_H_SYS_GPR247, HW_H_SYS_GPR248 31785+ , HW_H_SYS_GPR249, HW_H_SYS_GPR250, HW_H_SYS_GPR251, HW_H_SYS_GPR252 31786+ , HW_H_SYS_GPR253, HW_H_SYS_GPR254, HW_H_SYS_GPR255, HW_H_SYS_GPR256 31787+ , HW_H_SYS_GPR257, HW_H_SYS_GPR258, HW_H_SYS_GPR259, HW_H_SYS_GPR260 31788+ , HW_H_SYS_GPR261, HW_H_SYS_GPR262, HW_H_SYS_GPR263, HW_H_SYS_GPR264 31789+ , HW_H_SYS_GPR265, HW_H_SYS_GPR266, HW_H_SYS_GPR267, HW_H_SYS_GPR268 31790+ , HW_H_SYS_GPR269, HW_H_SYS_GPR270, HW_H_SYS_GPR271, HW_H_SYS_GPR272 31791+ , HW_H_SYS_GPR273, HW_H_SYS_GPR274, HW_H_SYS_GPR275, HW_H_SYS_GPR276 31792+ , HW_H_SYS_GPR277, HW_H_SYS_GPR278, HW_H_SYS_GPR279, HW_H_SYS_GPR280 31793+ , HW_H_SYS_GPR281, HW_H_SYS_GPR282, HW_H_SYS_GPR283, HW_H_SYS_GPR284 31794+ , HW_H_SYS_GPR285, HW_H_SYS_GPR286, HW_H_SYS_GPR287, HW_H_SYS_GPR288 31795+ , HW_H_SYS_GPR289, HW_H_SYS_GPR290, HW_H_SYS_GPR291, HW_H_SYS_GPR292 31796+ , HW_H_SYS_GPR293, HW_H_SYS_GPR294, HW_H_SYS_GPR295, HW_H_SYS_GPR296 31797+ , HW_H_SYS_GPR297, HW_H_SYS_GPR298, HW_H_SYS_GPR299, HW_H_SYS_GPR300 31798+ , HW_H_SYS_GPR301, HW_H_SYS_GPR302, HW_H_SYS_GPR303, HW_H_SYS_GPR304 31799+ , HW_H_SYS_GPR305, HW_H_SYS_GPR306, HW_H_SYS_GPR307, HW_H_SYS_GPR308 31800+ , HW_H_SYS_GPR309, HW_H_SYS_GPR310, HW_H_SYS_GPR311, HW_H_SYS_GPR312 31801+ , HW_H_SYS_GPR313, HW_H_SYS_GPR314, HW_H_SYS_GPR315, HW_H_SYS_GPR316 31802+ , HW_H_SYS_GPR317, HW_H_SYS_GPR318, HW_H_SYS_GPR319, HW_H_SYS_GPR320 31803+ , HW_H_SYS_GPR321, HW_H_SYS_GPR322, HW_H_SYS_GPR323, HW_H_SYS_GPR324 31804+ , HW_H_SYS_GPR325, HW_H_SYS_GPR326, HW_H_SYS_GPR327, HW_H_SYS_GPR328 31805+ , HW_H_SYS_GPR329, HW_H_SYS_GPR330, HW_H_SYS_GPR331, HW_H_SYS_GPR332 31806+ , HW_H_SYS_GPR333, HW_H_SYS_GPR334, HW_H_SYS_GPR335, HW_H_SYS_GPR336 31807+ , HW_H_SYS_GPR337, HW_H_SYS_GPR338, HW_H_SYS_GPR339, HW_H_SYS_GPR340 31808+ , HW_H_SYS_GPR341, HW_H_SYS_GPR342, HW_H_SYS_GPR343, HW_H_SYS_GPR344 31809+ , HW_H_SYS_GPR345, HW_H_SYS_GPR346, HW_H_SYS_GPR347, HW_H_SYS_GPR348 31810+ , HW_H_SYS_GPR349, HW_H_SYS_GPR350, HW_H_SYS_GPR351, HW_H_SYS_GPR352 31811+ , HW_H_SYS_GPR353, HW_H_SYS_GPR354, HW_H_SYS_GPR355, HW_H_SYS_GPR356 31812+ , HW_H_SYS_GPR357, HW_H_SYS_GPR358, HW_H_SYS_GPR359, HW_H_SYS_GPR360 31813+ , HW_H_SYS_GPR361, HW_H_SYS_GPR362, HW_H_SYS_GPR363, HW_H_SYS_GPR364 31814+ , HW_H_SYS_GPR365, HW_H_SYS_GPR366, HW_H_SYS_GPR367, HW_H_SYS_GPR368 31815+ , HW_H_SYS_GPR369, HW_H_SYS_GPR370, HW_H_SYS_GPR371, HW_H_SYS_GPR372 31816+ , HW_H_SYS_GPR373, HW_H_SYS_GPR374, HW_H_SYS_GPR375, HW_H_SYS_GPR376 31817+ , HW_H_SYS_GPR377, HW_H_SYS_GPR378, HW_H_SYS_GPR379, HW_H_SYS_GPR380 31818+ , HW_H_SYS_GPR381, HW_H_SYS_GPR382, HW_H_SYS_GPR383, HW_H_SYS_GPR384 31819+ , HW_H_SYS_GPR385, HW_H_SYS_GPR386, HW_H_SYS_GPR387, HW_H_SYS_GPR388 31820+ , HW_H_SYS_GPR389, HW_H_SYS_GPR390, HW_H_SYS_GPR391, HW_H_SYS_GPR392 31821+ , HW_H_SYS_GPR393, HW_H_SYS_GPR394, HW_H_SYS_GPR395, HW_H_SYS_GPR396 31822+ , HW_H_SYS_GPR397, HW_H_SYS_GPR398, HW_H_SYS_GPR399, HW_H_SYS_GPR400 31823+ , HW_H_SYS_GPR401, HW_H_SYS_GPR402, HW_H_SYS_GPR403, HW_H_SYS_GPR404 31824+ , HW_H_SYS_GPR405, HW_H_SYS_GPR406, HW_H_SYS_GPR407, HW_H_SYS_GPR408 31825+ , HW_H_SYS_GPR409, HW_H_SYS_GPR410, HW_H_SYS_GPR411, HW_H_SYS_GPR412 31826+ , HW_H_SYS_GPR413, HW_H_SYS_GPR414, HW_H_SYS_GPR415, HW_H_SYS_GPR416 31827+ , HW_H_SYS_GPR417, HW_H_SYS_GPR418, HW_H_SYS_GPR419, HW_H_SYS_GPR420 31828+ , HW_H_SYS_GPR421, HW_H_SYS_GPR422, HW_H_SYS_GPR423, HW_H_SYS_GPR424 31829+ , HW_H_SYS_GPR425, HW_H_SYS_GPR426, HW_H_SYS_GPR427, HW_H_SYS_GPR428 31830+ , HW_H_SYS_GPR429, HW_H_SYS_GPR430, HW_H_SYS_GPR431, HW_H_SYS_GPR432 31831+ , HW_H_SYS_GPR433, HW_H_SYS_GPR434, HW_H_SYS_GPR435, HW_H_SYS_GPR436 31832+ , HW_H_SYS_GPR437, HW_H_SYS_GPR438, HW_H_SYS_GPR439, HW_H_SYS_GPR440 31833+ , HW_H_SYS_GPR441, HW_H_SYS_GPR442, HW_H_SYS_GPR443, HW_H_SYS_GPR444 31834+ , HW_H_SYS_GPR445, HW_H_SYS_GPR446, HW_H_SYS_GPR447, HW_H_SYS_GPR448 31835+ , HW_H_SYS_GPR449, HW_H_SYS_GPR450, HW_H_SYS_GPR451, HW_H_SYS_GPR452 31836+ , HW_H_SYS_GPR453, HW_H_SYS_GPR454, HW_H_SYS_GPR455, HW_H_SYS_GPR456 31837+ , HW_H_SYS_GPR457, HW_H_SYS_GPR458, HW_H_SYS_GPR459, HW_H_SYS_GPR460 31838+ , HW_H_SYS_GPR461, HW_H_SYS_GPR462, HW_H_SYS_GPR463, HW_H_SYS_GPR464 31839+ , HW_H_SYS_GPR465, HW_H_SYS_GPR466, HW_H_SYS_GPR467, HW_H_SYS_GPR468 31840+ , HW_H_SYS_GPR469, HW_H_SYS_GPR470, HW_H_SYS_GPR471, HW_H_SYS_GPR472 31841+ , HW_H_SYS_GPR473, HW_H_SYS_GPR474, HW_H_SYS_GPR475, HW_H_SYS_GPR476 31842+ , HW_H_SYS_GPR477, HW_H_SYS_GPR478, HW_H_SYS_GPR479, HW_H_SYS_GPR480 31843+ , HW_H_SYS_GPR481, HW_H_SYS_GPR482, HW_H_SYS_GPR483, HW_H_SYS_GPR484 31844+ , HW_H_SYS_GPR485, HW_H_SYS_GPR486, HW_H_SYS_GPR487, HW_H_SYS_GPR488 31845+ , HW_H_SYS_GPR489, HW_H_SYS_GPR490, HW_H_SYS_GPR491, HW_H_SYS_GPR492 31846+ , HW_H_SYS_GPR493, HW_H_SYS_GPR494, HW_H_SYS_GPR495, HW_H_SYS_GPR496 31847+ , HW_H_SYS_GPR497, HW_H_SYS_GPR498, HW_H_SYS_GPR499, HW_H_SYS_GPR500 31848+ , HW_H_SYS_GPR501, HW_H_SYS_GPR502, HW_H_SYS_GPR503, HW_H_SYS_GPR504 31849+ , HW_H_SYS_GPR505, HW_H_SYS_GPR506, HW_H_SYS_GPR507, HW_H_SYS_GPR508 31850+ , HW_H_SYS_GPR509, HW_H_SYS_GPR510, HW_H_SYS_GPR511, HW_H_MAC_MACLO 31851+ , HW_H_MAC_MACHI, HW_H_TICK_TTMR, HW_H_SYS_VR_REV, HW_H_SYS_VR_CFG 31852+ , HW_H_SYS_VR_VER, HW_H_SYS_UPR_UP, HW_H_SYS_UPR_DCP, HW_H_SYS_UPR_ICP 31853+ , HW_H_SYS_UPR_DMP, HW_H_SYS_UPR_MP, HW_H_SYS_UPR_IMP, HW_H_SYS_UPR_DUP 31854+ , HW_H_SYS_UPR_PCUP, HW_H_SYS_UPR_PICP, HW_H_SYS_UPR_PMP, HW_H_SYS_UPR_TTP 31855+ , HW_H_SYS_UPR_CUP, HW_H_SYS_CPUCFGR_NSGR, HW_H_SYS_CPUCFGR_CGF, HW_H_SYS_CPUCFGR_OB32S 31856+ , HW_H_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OF32S, HW_H_SYS_CPUCFGR_OF64S, HW_H_SYS_CPUCFGR_OV64S 31857+ , HW_H_SYS_CPUCFGR_ND, HW_H_SYS_SR_SM, HW_H_SYS_SR_TEE, HW_H_SYS_SR_IEE 31858+ , HW_H_SYS_SR_DCE, HW_H_SYS_SR_ICE, HW_H_SYS_SR_DME, HW_H_SYS_SR_IME 31859+ , HW_H_SYS_SR_LEE, HW_H_SYS_SR_CE, HW_H_SYS_SR_F, HW_H_SYS_SR_CY 31860+ , HW_H_SYS_SR_OV, HW_H_SYS_SR_OVE, HW_H_SYS_SR_DSX, HW_H_SYS_SR_EPH 31861+ , HW_H_SYS_SR_FO, HW_H_SYS_SR_SUMRA, HW_H_SYS_SR_CID, HW_H_SYS_FPCSR_FPEE 31862+ , HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF, HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF 31863+ , HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF, HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF 31864+ , HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF, HW_H_SIMM16, HW_H_UIMM16 31865+ , HW_H_UIMM6, HW_H_ATOMIC_RESERVE, HW_H_ATOMIC_ADDRESS, HW_MAX 31866+} CGEN_HW_TYPE; 31867+ 31868+#define MAX_HW ((int) HW_MAX) 31869+ 31870+/* Operand attribute indices. */ 31871+ 31872+/* Enum declaration for cgen_operand attrs. */ 31873+typedef enum cgen_operand_attr { 31874+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 31875+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 31876+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS 31877+} CGEN_OPERAND_ATTR; 31878+ 31879+/* Number of non-boolean elements in cgen_operand_attr. */ 31880+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 31881+ 31882+/* cgen_operand attribute accessor macros. */ 31883+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 31884+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 31885+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 31886+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 31887+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 31888+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 31889+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 31890+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 31891+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 31892+ 31893+/* Enum declaration for or1k operand types. */ 31894+typedef enum cgen_operand_type { 31895+ OR1K_OPERAND_PC, OR1K_OPERAND_SYS_SR, OR1K_OPERAND_SYS_ESR0, OR1K_OPERAND_SYS_EPCR0 31896+ , OR1K_OPERAND_SYS_SR_LEE, OR1K_OPERAND_SYS_SR_F, OR1K_OPERAND_SYS_SR_CY, OR1K_OPERAND_SYS_SR_OV 31897+ , OR1K_OPERAND_SYS_SR_OVE, OR1K_OPERAND_SYS_CPUCFGR_OB64S, OR1K_OPERAND_SYS_CPUCFGR_ND, OR1K_OPERAND_SYS_FPCSR_RM 31898+ , OR1K_OPERAND_MAC_MACHI, OR1K_OPERAND_MAC_MACLO, OR1K_OPERAND_ATOMIC_RESERVE, OR1K_OPERAND_ATOMIC_ADDRESS 31899+ , OR1K_OPERAND_UIMM6, OR1K_OPERAND_RD, OR1K_OPERAND_RA, OR1K_OPERAND_RB 31900+ , OR1K_OPERAND_DISP26, OR1K_OPERAND_SIMM16, OR1K_OPERAND_UIMM16, OR1K_OPERAND_SIMM16_SPLIT 31901+ , OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF, OR1K_OPERAND_RASF, OR1K_OPERAND_RBSF 31902+ , OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF, OR1K_OPERAND_RBDF, OR1K_OPERAND_MAX 31903+} CGEN_OPERAND_TYPE; 31904+ 31905+/* Number of operands types. */ 31906+#define MAX_OPERANDS 31 31907+ 31908+/* Maximum number of operands referenced by any insn. */ 31909+#define MAX_OPERAND_INSTANCES 9 31910+ 31911+/* Insn attribute indices. */ 31912+ 31913+/* Enum declaration for cgen_insn attrs. */ 31914+typedef enum cgen_insn_attr { 31915+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 31916+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 31917+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_DELAYED_CTI, CGEN_INSN_NOT_IN_DELAY_SLOT 31918+ , CGEN_INSN_FORCED_CTI, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH 31919+ , CGEN_INSN_END_NBOOLS 31920+} CGEN_INSN_ATTR; 31921+ 31922+/* Number of non-boolean elements in cgen_insn_attr. */ 31923+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 31924+ 31925+/* cgen_insn attribute accessor macros. */ 31926+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 31927+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 31928+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 31929+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 31930+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 31931+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 31932+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 31933+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 31934+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 31935+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 31936+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 31937+#define CGEN_ATTR_CGEN_INSN_DELAYED_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAYED_CTI)) != 0) 31938+#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) 31939+#define CGEN_ATTR_CGEN_INSN_FORCED_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FORCED_CTI)) != 0) 31940+ 31941+/* cgen.h uses things we just defined. */ 31942+#include "opcode/cgen.h" 31943+ 31944+extern const struct cgen_ifld or1k_cgen_ifld_table[]; 31945+ 31946+/* Attributes. */ 31947+extern const CGEN_ATTR_TABLE or1k_cgen_hardware_attr_table[]; 31948+extern const CGEN_ATTR_TABLE or1k_cgen_ifield_attr_table[]; 31949+extern const CGEN_ATTR_TABLE or1k_cgen_operand_attr_table[]; 31950+extern const CGEN_ATTR_TABLE or1k_cgen_insn_attr_table[]; 31951+ 31952+/* Hardware decls. */ 31953+ 31954+extern CGEN_KEYWORD or1k_cgen_opval_h_fsr; 31955+extern CGEN_KEYWORD or1k_cgen_opval_h_fdr; 31956+extern CGEN_KEYWORD or1k_cgen_opval_h_gpr; 31957+ 31958+extern const CGEN_HW_ENTRY or1k_cgen_hw_table[]; 31959+ 31960+ 31961+ 31962+#endif /* OR1K_CPU_H */ 31963diff -rNU3 dist.orig/opcodes/or1k-dis.c dist/opcodes/or1k-dis.c 31964--- dist.orig/opcodes/or1k-dis.c 1970-01-01 01:00:00.000000000 +0100 31965+++ dist/opcodes/or1k-dis.c 2015-10-18 13:11:20.000000000 +0200 31966@@ -0,0 +1,561 @@ 31967+/* Disassembler interface for targets using CGEN. -*- C -*- 31968+ CGEN: Cpu tools GENerator 31969+ 31970+ THIS FILE IS MACHINE GENERATED WITH CGEN. 31971+ - the resultant file is machine generated, cgen-dis.in isn't 31972+ 31973+ Copyright (C) 1996-2014 Free Software Foundation, Inc. 31974+ 31975+ This file is part of libopcodes. 31976+ 31977+ This library is free software; you can redistribute it and/or modify 31978+ it under the terms of the GNU General Public License as published by 31979+ the Free Software Foundation; either version 3, or (at your option) 31980+ any later version. 31981+ 31982+ It is distributed in the hope that it will be useful, but WITHOUT 31983+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 31984+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 31985+ License for more details. 31986+ 31987+ You should have received a copy of the GNU General Public License 31988+ along with this program; if not, write to the Free Software Foundation, Inc., 31989+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 31990+ 31991+/* ??? Eventually more and more of this stuff can go to cpu-independent files. 31992+ Keep that in mind. */ 31993+ 31994+#include "sysdep.h" 31995+#include <stdio.h> 31996+#include "ansidecl.h" 31997+#include "dis-asm.h" 31998+#include "bfd.h" 31999+#include "symcat.h" 32000+#include "libiberty.h" 32001+#include "or1k-desc.h" 32002+#include "or1k-opc.h" 32003+#include "opintl.h" 32004+ 32005+/* Default text to print if an instruction isn't recognized. */ 32006+#define UNKNOWN_INSN_MSG _("*unknown*") 32007+ 32008+static void print_normal 32009+ (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 32010+static void print_address 32011+ (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 32012+static void print_keyword 32013+ (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 32014+static void print_insn_normal 32015+ (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 32016+static int print_insn 32017+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 32018+static int default_print_insn 32019+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 32020+static int read_insn 32021+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 32022+ unsigned long *); 32023+ 32024+/* -- disassembler routines inserted here. */ 32025+ 32026+ 32027+void or1k_cgen_print_operand 32028+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 32029+ 32030+/* Main entry point for printing operands. 32031+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 32032+ of dis-asm.h on cgen.h. 32033+ 32034+ This function is basically just a big switch statement. Earlier versions 32035+ used tables to look up the function to use, but 32036+ - if the table contains both assembler and disassembler functions then 32037+ the disassembler contains much of the assembler and vice-versa, 32038+ - there's a lot of inlining possibilities as things grow, 32039+ - using a switch statement avoids the function call overhead. 32040+ 32041+ This function could be moved into `print_insn_normal', but keeping it 32042+ separate makes clear the interface between `print_insn_normal' and each of 32043+ the handlers. */ 32044+ 32045+void 32046+or1k_cgen_print_operand (CGEN_CPU_DESC cd, 32047+ int opindex, 32048+ void * xinfo, 32049+ CGEN_FIELDS *fields, 32050+ void const *attrs ATTRIBUTE_UNUSED, 32051+ bfd_vma pc, 32052+ int length) 32053+{ 32054+ disassemble_info *info = (disassemble_info *) xinfo; 32055+ 32056+ switch (opindex) 32057+ { 32058+ case OR1K_OPERAND_DISP26 : 32059+ print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 32060+ break; 32061+ case OR1K_OPERAND_RA : 32062+ print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r2, 0); 32063+ break; 32064+ case OR1K_OPERAND_RADF : 32065+ print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0); 32066+ break; 32067+ case OR1K_OPERAND_RASF : 32068+ print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r2, 0); 32069+ break; 32070+ case OR1K_OPERAND_RB : 32071+ print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r3, 0); 32072+ break; 32073+ case OR1K_OPERAND_RBDF : 32074+ print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0); 32075+ break; 32076+ case OR1K_OPERAND_RBSF : 32077+ print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r3, 0); 32078+ break; 32079+ case OR1K_OPERAND_RD : 32080+ print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r1, 0); 32081+ break; 32082+ case OR1K_OPERAND_RDDF : 32083+ print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0); 32084+ break; 32085+ case OR1K_OPERAND_RDSF : 32086+ print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r1, 0); 32087+ break; 32088+ case OR1K_OPERAND_SIMM16 : 32089+ print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); 32090+ break; 32091+ case OR1K_OPERAND_SIMM16_SPLIT : 32092+ print_normal (cd, info, fields->f_simm16_split, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 32093+ break; 32094+ case OR1K_OPERAND_UIMM16 : 32095+ print_normal (cd, info, fields->f_uimm16, 0, pc, length); 32096+ break; 32097+ case OR1K_OPERAND_UIMM16_SPLIT : 32098+ print_normal (cd, info, fields->f_uimm16_split, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 32099+ break; 32100+ case OR1K_OPERAND_UIMM6 : 32101+ print_normal (cd, info, fields->f_uimm6, 0, pc, length); 32102+ break; 32103+ 32104+ default : 32105+ /* xgettext:c-format */ 32106+ fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 32107+ opindex); 32108+ abort (); 32109+ } 32110+} 32111+ 32112+cgen_print_fn * const or1k_cgen_print_handlers[] = 32113+{ 32114+ print_insn_normal, 32115+}; 32116+ 32117+ 32118+void 32119+or1k_cgen_init_dis (CGEN_CPU_DESC cd) 32120+{ 32121+ or1k_cgen_init_opcode_table (cd); 32122+ or1k_cgen_init_ibld_table (cd); 32123+ cd->print_handlers = & or1k_cgen_print_handlers[0]; 32124+ cd->print_operand = or1k_cgen_print_operand; 32125+} 32126+ 32127+ 32128+/* Default print handler. */ 32129+ 32130+static void 32131+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 32132+ void *dis_info, 32133+ long value, 32134+ unsigned int attrs, 32135+ bfd_vma pc ATTRIBUTE_UNUSED, 32136+ int length ATTRIBUTE_UNUSED) 32137+{ 32138+ disassemble_info *info = (disassemble_info *) dis_info; 32139+ 32140+ /* Print the operand as directed by the attributes. */ 32141+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 32142+ ; /* nothing to do */ 32143+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 32144+ (*info->fprintf_func) (info->stream, "%ld", value); 32145+ else 32146+ (*info->fprintf_func) (info->stream, "0x%lx", value); 32147+} 32148+ 32149+/* Default address handler. */ 32150+ 32151+static void 32152+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 32153+ void *dis_info, 32154+ bfd_vma value, 32155+ unsigned int attrs, 32156+ bfd_vma pc ATTRIBUTE_UNUSED, 32157+ int length ATTRIBUTE_UNUSED) 32158+{ 32159+ disassemble_info *info = (disassemble_info *) dis_info; 32160+ 32161+ /* Print the operand as directed by the attributes. */ 32162+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 32163+ ; /* Nothing to do. */ 32164+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 32165+ (*info->print_address_func) (value, info); 32166+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 32167+ (*info->print_address_func) (value, info); 32168+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 32169+ (*info->fprintf_func) (info->stream, "%ld", (long) value); 32170+ else 32171+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 32172+} 32173+ 32174+/* Keyword print handler. */ 32175+ 32176+static void 32177+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 32178+ void *dis_info, 32179+ CGEN_KEYWORD *keyword_table, 32180+ long value, 32181+ unsigned int attrs ATTRIBUTE_UNUSED) 32182+{ 32183+ disassemble_info *info = (disassemble_info *) dis_info; 32184+ const CGEN_KEYWORD_ENTRY *ke; 32185+ 32186+ ke = cgen_keyword_lookup_value (keyword_table, value); 32187+ if (ke != NULL) 32188+ (*info->fprintf_func) (info->stream, "%s", ke->name); 32189+ else 32190+ (*info->fprintf_func) (info->stream, "???"); 32191+} 32192+ 32193+/* Default insn printer. 32194+ 32195+ DIS_INFO is defined as `void *' so the disassembler needn't know anything 32196+ about disassemble_info. */ 32197+ 32198+static void 32199+print_insn_normal (CGEN_CPU_DESC cd, 32200+ void *dis_info, 32201+ const CGEN_INSN *insn, 32202+ CGEN_FIELDS *fields, 32203+ bfd_vma pc, 32204+ int length) 32205+{ 32206+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 32207+ disassemble_info *info = (disassemble_info *) dis_info; 32208+ const CGEN_SYNTAX_CHAR_TYPE *syn; 32209+ 32210+ CGEN_INIT_PRINT (cd); 32211+ 32212+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 32213+ { 32214+ if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 32215+ { 32216+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 32217+ continue; 32218+ } 32219+ if (CGEN_SYNTAX_CHAR_P (*syn)) 32220+ { 32221+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 32222+ continue; 32223+ } 32224+ 32225+ /* We have an operand. */ 32226+ or1k_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 32227+ fields, CGEN_INSN_ATTRS (insn), pc, length); 32228+ } 32229+} 32230+ 32231+/* Subroutine of print_insn. Reads an insn into the given buffers and updates 32232+ the extract info. 32233+ Returns 0 if all is well, non-zero otherwise. */ 32234+ 32235+static int 32236+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 32237+ bfd_vma pc, 32238+ disassemble_info *info, 32239+ bfd_byte *buf, 32240+ int buflen, 32241+ CGEN_EXTRACT_INFO *ex_info, 32242+ unsigned long *insn_value) 32243+{ 32244+ int status = (*info->read_memory_func) (pc, buf, buflen, info); 32245+ 32246+ if (status != 0) 32247+ { 32248+ (*info->memory_error_func) (status, pc, info); 32249+ return -1; 32250+ } 32251+ 32252+ ex_info->dis_info = info; 32253+ ex_info->valid = (1 << buflen) - 1; 32254+ ex_info->insn_bytes = buf; 32255+ 32256+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 32257+ return 0; 32258+} 32259+ 32260+/* Utility to print an insn. 32261+ BUF is the base part of the insn, target byte order, BUFLEN bytes long. 32262+ The result is the size of the insn in bytes or zero for an unknown insn 32263+ or -1 if an error occurs fetching data (memory_error_func will have 32264+ been called). */ 32265+ 32266+static int 32267+print_insn (CGEN_CPU_DESC cd, 32268+ bfd_vma pc, 32269+ disassemble_info *info, 32270+ bfd_byte *buf, 32271+ unsigned int buflen) 32272+{ 32273+ CGEN_INSN_INT insn_value; 32274+ const CGEN_INSN_LIST *insn_list; 32275+ CGEN_EXTRACT_INFO ex_info; 32276+ int basesize; 32277+ 32278+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 32279+ basesize = cd->base_insn_bitsize < buflen * 8 ? 32280+ cd->base_insn_bitsize : buflen * 8; 32281+ insn_value = cgen_get_insn_value (cd, buf, basesize); 32282+ 32283+ 32284+ /* Fill in ex_info fields like read_insn would. Don't actually call 32285+ read_insn, since the incoming buffer is already read (and possibly 32286+ modified a la m32r). */ 32287+ ex_info.valid = (1 << buflen) - 1; 32288+ ex_info.dis_info = info; 32289+ ex_info.insn_bytes = buf; 32290+ 32291+ /* The instructions are stored in hash lists. 32292+ Pick the first one and keep trying until we find the right one. */ 32293+ 32294+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 32295+ while (insn_list != NULL) 32296+ { 32297+ const CGEN_INSN *insn = insn_list->insn; 32298+ CGEN_FIELDS fields; 32299+ int length; 32300+ unsigned long insn_value_cropped; 32301+ 32302+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 32303+ /* Not needed as insn shouldn't be in hash lists if not supported. */ 32304+ /* Supported by this cpu? */ 32305+ if (! or1k_cgen_insn_supported (cd, insn)) 32306+ { 32307+ insn_list = CGEN_DIS_NEXT_INSN (insn_list); 32308+ continue; 32309+ } 32310+#endif 32311+ 32312+ /* Basic bit mask must be correct. */ 32313+ /* ??? May wish to allow target to defer this check until the extract 32314+ handler. */ 32315+ 32316+ /* Base size may exceed this instruction's size. Extract the 32317+ relevant part from the buffer. */ 32318+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 32319+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 32320+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 32321+ info->endian == BFD_ENDIAN_BIG); 32322+ else 32323+ insn_value_cropped = insn_value; 32324+ 32325+ if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 32326+ == CGEN_INSN_BASE_VALUE (insn)) 32327+ { 32328+ /* Printing is handled in two passes. The first pass parses the 32329+ machine insn and extracts the fields. The second pass prints 32330+ them. */ 32331+ 32332+ /* Make sure the entire insn is loaded into insn_value, if it 32333+ can fit. */ 32334+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 32335+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 32336+ { 32337+ unsigned long full_insn_value; 32338+ int rc = read_insn (cd, pc, info, buf, 32339+ CGEN_INSN_BITSIZE (insn) / 8, 32340+ & ex_info, & full_insn_value); 32341+ if (rc != 0) 32342+ return rc; 32343+ length = CGEN_EXTRACT_FN (cd, insn) 32344+ (cd, insn, &ex_info, full_insn_value, &fields, pc); 32345+ } 32346+ else 32347+ length = CGEN_EXTRACT_FN (cd, insn) 32348+ (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 32349+ 32350+ /* Length < 0 -> error. */ 32351+ if (length < 0) 32352+ return length; 32353+ if (length > 0) 32354+ { 32355+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 32356+ /* Length is in bits, result is in bytes. */ 32357+ return length / 8; 32358+ } 32359+ } 32360+ 32361+ insn_list = CGEN_DIS_NEXT_INSN (insn_list); 32362+ } 32363+ 32364+ return 0; 32365+} 32366+ 32367+/* Default value for CGEN_PRINT_INSN. 32368+ The result is the size of the insn in bytes or zero for an unknown insn 32369+ or -1 if an error occured fetching bytes. */ 32370+ 32371+#ifndef CGEN_PRINT_INSN 32372+#define CGEN_PRINT_INSN default_print_insn 32373+#endif 32374+ 32375+static int 32376+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 32377+{ 32378+ bfd_byte buf[CGEN_MAX_INSN_SIZE]; 32379+ int buflen; 32380+ int status; 32381+ 32382+ /* Attempt to read the base part of the insn. */ 32383+ buflen = cd->base_insn_bitsize / 8; 32384+ status = (*info->read_memory_func) (pc, buf, buflen, info); 32385+ 32386+ /* Try again with the minimum part, if min < base. */ 32387+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 32388+ { 32389+ buflen = cd->min_insn_bitsize / 8; 32390+ status = (*info->read_memory_func) (pc, buf, buflen, info); 32391+ } 32392+ 32393+ if (status != 0) 32394+ { 32395+ (*info->memory_error_func) (status, pc, info); 32396+ return -1; 32397+ } 32398+ 32399+ return print_insn (cd, pc, info, buf, buflen); 32400+} 32401+ 32402+/* Main entry point. 32403+ Print one instruction from PC on INFO->STREAM. 32404+ Return the size of the instruction (in bytes). */ 32405+ 32406+typedef struct cpu_desc_list 32407+{ 32408+ struct cpu_desc_list *next; 32409+ CGEN_BITSET *isa; 32410+ int mach; 32411+ int endian; 32412+ CGEN_CPU_DESC cd; 32413+} cpu_desc_list; 32414+ 32415+int 32416+print_insn_or1k (bfd_vma pc, disassemble_info *info) 32417+{ 32418+ static cpu_desc_list *cd_list = 0; 32419+ cpu_desc_list *cl = 0; 32420+ static CGEN_CPU_DESC cd = 0; 32421+ static CGEN_BITSET *prev_isa; 32422+ static int prev_mach; 32423+ static int prev_endian; 32424+ int length; 32425+ CGEN_BITSET *isa; 32426+ int mach; 32427+ int endian = (info->endian == BFD_ENDIAN_BIG 32428+ ? CGEN_ENDIAN_BIG 32429+ : CGEN_ENDIAN_LITTLE); 32430+ enum bfd_architecture arch; 32431+ 32432+ /* ??? gdb will set mach but leave the architecture as "unknown" */ 32433+#ifndef CGEN_BFD_ARCH 32434+#define CGEN_BFD_ARCH bfd_arch_or1k 32435+#endif 32436+ arch = info->arch; 32437+ if (arch == bfd_arch_unknown) 32438+ arch = CGEN_BFD_ARCH; 32439+ 32440+ /* There's no standard way to compute the machine or isa number 32441+ so we leave it to the target. */ 32442+#ifdef CGEN_COMPUTE_MACH 32443+ mach = CGEN_COMPUTE_MACH (info); 32444+#else 32445+ mach = info->mach; 32446+#endif 32447+ 32448+#ifdef CGEN_COMPUTE_ISA 32449+ { 32450+ static CGEN_BITSET *permanent_isa; 32451+ 32452+ if (!permanent_isa) 32453+ permanent_isa = cgen_bitset_create (MAX_ISAS); 32454+ isa = permanent_isa; 32455+ cgen_bitset_clear (isa); 32456+ cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 32457+ } 32458+#else 32459+ isa = info->insn_sets; 32460+#endif 32461+ 32462+ /* If we've switched cpu's, try to find a handle we've used before */ 32463+ if (cd 32464+ && (cgen_bitset_compare (isa, prev_isa) != 0 32465+ || mach != prev_mach 32466+ || endian != prev_endian)) 32467+ { 32468+ cd = 0; 32469+ for (cl = cd_list; cl; cl = cl->next) 32470+ { 32471+ if (cgen_bitset_compare (cl->isa, isa) == 0 && 32472+ cl->mach == mach && 32473+ cl->endian == endian) 32474+ { 32475+ cd = cl->cd; 32476+ prev_isa = cd->isas; 32477+ break; 32478+ } 32479+ } 32480+ } 32481+ 32482+ /* If we haven't initialized yet, initialize the opcode table. */ 32483+ if (! cd) 32484+ { 32485+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 32486+ const char *mach_name; 32487+ 32488+ if (!arch_type) 32489+ abort (); 32490+ mach_name = arch_type->printable_name; 32491+ 32492+ prev_isa = cgen_bitset_copy (isa); 32493+ prev_mach = mach; 32494+ prev_endian = endian; 32495+ cd = or1k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 32496+ CGEN_CPU_OPEN_BFDMACH, mach_name, 32497+ CGEN_CPU_OPEN_ENDIAN, prev_endian, 32498+ CGEN_CPU_OPEN_END); 32499+ if (!cd) 32500+ abort (); 32501+ 32502+ /* Save this away for future reference. */ 32503+ cl = xmalloc (sizeof (struct cpu_desc_list)); 32504+ cl->cd = cd; 32505+ cl->isa = prev_isa; 32506+ cl->mach = mach; 32507+ cl->endian = endian; 32508+ cl->next = cd_list; 32509+ cd_list = cl; 32510+ 32511+ or1k_cgen_init_dis (cd); 32512+ } 32513+ 32514+ /* We try to have as much common code as possible. 32515+ But at this point some targets need to take over. */ 32516+ /* ??? Some targets may need a hook elsewhere. Try to avoid this, 32517+ but if not possible try to move this hook elsewhere rather than 32518+ have two hooks. */ 32519+ length = CGEN_PRINT_INSN (cd, pc, info); 32520+ if (length > 0) 32521+ return length; 32522+ if (length < 0) 32523+ return -1; 32524+ 32525+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 32526+ return cd->default_insn_bitsize / 8; 32527+} 32528diff -rNU3 dist.orig/opcodes/or1k-ibld.c dist/opcodes/or1k-ibld.c 32529--- dist.orig/opcodes/or1k-ibld.c 1970-01-01 01:00:00.000000000 +0100 32530+++ dist/opcodes/or1k-ibld.c 2015-10-18 13:11:20.000000000 +0200 32531@@ -0,0 +1,1050 @@ 32532+/* Instruction building/extraction support for or1k. -*- C -*- 32533+ 32534+ THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 32535+ - the resultant file is machine generated, cgen-ibld.in isn't 32536+ 32537+ Copyright (C) 1996-2014 Free Software Foundation, Inc. 32538+ 32539+ This file is part of libopcodes. 32540+ 32541+ This library is free software; you can redistribute it and/or modify 32542+ it under the terms of the GNU General Public License as published by 32543+ the Free Software Foundation; either version 3, or (at your option) 32544+ any later version. 32545+ 32546+ It is distributed in the hope that it will be useful, but WITHOUT 32547+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 32548+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 32549+ License for more details. 32550+ 32551+ You should have received a copy of the GNU General Public License 32552+ along with this program; if not, write to the Free Software Foundation, Inc., 32553+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 32554+ 32555+/* ??? Eventually more and more of this stuff can go to cpu-independent files. 32556+ Keep that in mind. */ 32557+ 32558+#include "sysdep.h" 32559+#include <stdio.h> 32560+#include "ansidecl.h" 32561+#include "dis-asm.h" 32562+#include "bfd.h" 32563+#include "symcat.h" 32564+#include "or1k-desc.h" 32565+#include "or1k-opc.h" 32566+#include "cgen/basic-modes.h" 32567+#include "opintl.h" 32568+#include "safe-ctype.h" 32569+ 32570+#undef min 32571+#define min(a,b) ((a) < (b) ? (a) : (b)) 32572+#undef max 32573+#define max(a,b) ((a) > (b) ? (a) : (b)) 32574+ 32575+/* Used by the ifield rtx function. */ 32576+#define FLD(f) (fields->f) 32577+ 32578+static const char * insert_normal 32579+ (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 32580+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 32581+static const char * insert_insn_normal 32582+ (CGEN_CPU_DESC, const CGEN_INSN *, 32583+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 32584+static int extract_normal 32585+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 32586+ unsigned int, unsigned int, unsigned int, unsigned int, 32587+ unsigned int, unsigned int, bfd_vma, long *); 32588+static int extract_insn_normal 32589+ (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 32590+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 32591+#if CGEN_INT_INSN_P 32592+static void put_insn_int_value 32593+ (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 32594+#endif 32595+#if ! CGEN_INT_INSN_P 32596+static CGEN_INLINE void insert_1 32597+ (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 32598+static CGEN_INLINE int fill_cache 32599+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 32600+static CGEN_INLINE long extract_1 32601+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 32602+#endif 32603+ 32604+/* Operand insertion. */ 32605+ 32606+#if ! CGEN_INT_INSN_P 32607+ 32608+/* Subroutine of insert_normal. */ 32609+ 32610+static CGEN_INLINE void 32611+insert_1 (CGEN_CPU_DESC cd, 32612+ unsigned long value, 32613+ int start, 32614+ int length, 32615+ int word_length, 32616+ unsigned char *bufp) 32617+{ 32618+ unsigned long x,mask; 32619+ int shift; 32620+ 32621+ x = cgen_get_insn_value (cd, bufp, word_length); 32622+ 32623+ /* Written this way to avoid undefined behaviour. */ 32624+ mask = (((1L << (length - 1)) - 1) << 1) | 1; 32625+ if (CGEN_INSN_LSB0_P) 32626+ shift = (start + 1) - length; 32627+ else 32628+ shift = (word_length - (start + length)); 32629+ x = (x & ~(mask << shift)) | ((value & mask) << shift); 32630+ 32631+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 32632+} 32633+ 32634+#endif /* ! CGEN_INT_INSN_P */ 32635+ 32636+/* Default insertion routine. 32637+ 32638+ ATTRS is a mask of the boolean attributes. 32639+ WORD_OFFSET is the offset in bits from the start of the insn of the value. 32640+ WORD_LENGTH is the length of the word in bits in which the value resides. 32641+ START is the starting bit number in the word, architecture origin. 32642+ LENGTH is the length of VALUE in bits. 32643+ TOTAL_LENGTH is the total length of the insn in bits. 32644+ 32645+ The result is an error message or NULL if success. */ 32646+ 32647+/* ??? This duplicates functionality with bfd's howto table and 32648+ bfd_install_relocation. */ 32649+/* ??? This doesn't handle bfd_vma's. Create another function when 32650+ necessary. */ 32651+ 32652+static const char * 32653+insert_normal (CGEN_CPU_DESC cd, 32654+ long value, 32655+ unsigned int attrs, 32656+ unsigned int word_offset, 32657+ unsigned int start, 32658+ unsigned int length, 32659+ unsigned int word_length, 32660+ unsigned int total_length, 32661+ CGEN_INSN_BYTES_PTR buffer) 32662+{ 32663+ static char errbuf[100]; 32664+ /* Written this way to avoid undefined behaviour. */ 32665+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 32666+ 32667+ /* If LENGTH is zero, this operand doesn't contribute to the value. */ 32668+ if (length == 0) 32669+ return NULL; 32670+ 32671+ if (word_length > 8 * sizeof (CGEN_INSN_INT)) 32672+ abort (); 32673+ 32674+ /* For architectures with insns smaller than the base-insn-bitsize, 32675+ word_length may be too big. */ 32676+ if (cd->min_insn_bitsize < cd->base_insn_bitsize) 32677+ { 32678+ if (word_offset == 0 32679+ && word_length > total_length) 32680+ word_length = total_length; 32681+ } 32682+ 32683+ /* Ensure VALUE will fit. */ 32684+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 32685+ { 32686+ long minval = - (1L << (length - 1)); 32687+ unsigned long maxval = mask; 32688+ 32689+ if ((value > 0 && (unsigned long) value > maxval) 32690+ || value < minval) 32691+ { 32692+ /* xgettext:c-format */ 32693+ sprintf (errbuf, 32694+ _("operand out of range (%ld not between %ld and %lu)"), 32695+ value, minval, maxval); 32696+ return errbuf; 32697+ } 32698+ } 32699+ else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 32700+ { 32701+ unsigned long maxval = mask; 32702+ unsigned long val = (unsigned long) value; 32703+ 32704+ /* For hosts with a word size > 32 check to see if value has been sign 32705+ extended beyond 32 bits. If so then ignore these higher sign bits 32706+ as the user is attempting to store a 32-bit signed value into an 32707+ unsigned 32-bit field which is allowed. */ 32708+ if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 32709+ val &= 0xFFFFFFFF; 32710+ 32711+ if (val > maxval) 32712+ { 32713+ /* xgettext:c-format */ 32714+ sprintf (errbuf, 32715+ _("operand out of range (0x%lx not between 0 and 0x%lx)"), 32716+ val, maxval); 32717+ return errbuf; 32718+ } 32719+ } 32720+ else 32721+ { 32722+ if (! cgen_signed_overflow_ok_p (cd)) 32723+ { 32724+ long minval = - (1L << (length - 1)); 32725+ long maxval = (1L << (length - 1)) - 1; 32726+ 32727+ if (value < minval || value > maxval) 32728+ { 32729+ sprintf 32730+ /* xgettext:c-format */ 32731+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 32732+ value, minval, maxval); 32733+ return errbuf; 32734+ } 32735+ } 32736+ } 32737+ 32738+#if CGEN_INT_INSN_P 32739+ 32740+ { 32741+ int shift; 32742+ 32743+ if (CGEN_INSN_LSB0_P) 32744+ shift = (word_offset + start + 1) - length; 32745+ else 32746+ shift = total_length - (word_offset + start + length); 32747+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 32748+ } 32749+ 32750+#else /* ! CGEN_INT_INSN_P */ 32751+ 32752+ { 32753+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 32754+ 32755+ insert_1 (cd, value, start, length, word_length, bufp); 32756+ } 32757+ 32758+#endif /* ! CGEN_INT_INSN_P */ 32759+ 32760+ return NULL; 32761+} 32762+ 32763+/* Default insn builder (insert handler). 32764+ The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 32765+ that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 32766+ recorded in host byte order, otherwise BUFFER is an array of bytes 32767+ and the value is recorded in target byte order). 32768+ The result is an error message or NULL if success. */ 32769+ 32770+static const char * 32771+insert_insn_normal (CGEN_CPU_DESC cd, 32772+ const CGEN_INSN * insn, 32773+ CGEN_FIELDS * fields, 32774+ CGEN_INSN_BYTES_PTR buffer, 32775+ bfd_vma pc) 32776+{ 32777+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 32778+ unsigned long value; 32779+ const CGEN_SYNTAX_CHAR_TYPE * syn; 32780+ 32781+ CGEN_INIT_INSERT (cd); 32782+ value = CGEN_INSN_BASE_VALUE (insn); 32783+ 32784+ /* If we're recording insns as numbers (rather than a string of bytes), 32785+ target byte order handling is deferred until later. */ 32786+ 32787+#if CGEN_INT_INSN_P 32788+ 32789+ put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 32790+ CGEN_FIELDS_BITSIZE (fields), value); 32791+ 32792+#else 32793+ 32794+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 32795+ (unsigned) CGEN_FIELDS_BITSIZE (fields)), 32796+ value); 32797+ 32798+#endif /* ! CGEN_INT_INSN_P */ 32799+ 32800+ /* ??? It would be better to scan the format's fields. 32801+ Still need to be able to insert a value based on the operand though; 32802+ e.g. storing a branch displacement that got resolved later. 32803+ Needs more thought first. */ 32804+ 32805+ for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 32806+ { 32807+ const char *errmsg; 32808+ 32809+ if (CGEN_SYNTAX_CHAR_P (* syn)) 32810+ continue; 32811+ 32812+ errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 32813+ fields, buffer, pc); 32814+ if (errmsg) 32815+ return errmsg; 32816+ } 32817+ 32818+ return NULL; 32819+} 32820+ 32821+#if CGEN_INT_INSN_P 32822+/* Cover function to store an insn value into an integral insn. Must go here 32823+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 32824+ 32825+static void 32826+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 32827+ CGEN_INSN_BYTES_PTR buf, 32828+ int length, 32829+ int insn_length, 32830+ CGEN_INSN_INT value) 32831+{ 32832+ /* For architectures with insns smaller than the base-insn-bitsize, 32833+ length may be too big. */ 32834+ if (length > insn_length) 32835+ *buf = value; 32836+ else 32837+ { 32838+ int shift = insn_length - length; 32839+ /* Written this way to avoid undefined behaviour. */ 32840+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 32841+ 32842+ *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 32843+ } 32844+} 32845+#endif 32846+ 32847+/* Operand extraction. */ 32848+ 32849+#if ! CGEN_INT_INSN_P 32850+ 32851+/* Subroutine of extract_normal. 32852+ Ensure sufficient bytes are cached in EX_INFO. 32853+ OFFSET is the offset in bytes from the start of the insn of the value. 32854+ BYTES is the length of the needed value. 32855+ Returns 1 for success, 0 for failure. */ 32856+ 32857+static CGEN_INLINE int 32858+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 32859+ CGEN_EXTRACT_INFO *ex_info, 32860+ int offset, 32861+ int bytes, 32862+ bfd_vma pc) 32863+{ 32864+ /* It's doubtful that the middle part has already been fetched so 32865+ we don't optimize that case. kiss. */ 32866+ unsigned int mask; 32867+ disassemble_info *info = (disassemble_info *) ex_info->dis_info; 32868+ 32869+ /* First do a quick check. */ 32870+ mask = (1 << bytes) - 1; 32871+ if (((ex_info->valid >> offset) & mask) == mask) 32872+ return 1; 32873+ 32874+ /* Search for the first byte we need to read. */ 32875+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 32876+ if (! (mask & ex_info->valid)) 32877+ break; 32878+ 32879+ if (bytes) 32880+ { 32881+ int status; 32882+ 32883+ pc += offset; 32884+ status = (*info->read_memory_func) 32885+ (pc, ex_info->insn_bytes + offset, bytes, info); 32886+ 32887+ if (status != 0) 32888+ { 32889+ (*info->memory_error_func) (status, pc, info); 32890+ return 0; 32891+ } 32892+ 32893+ ex_info->valid |= ((1 << bytes) - 1) << offset; 32894+ } 32895+ 32896+ return 1; 32897+} 32898+ 32899+/* Subroutine of extract_normal. */ 32900+ 32901+static CGEN_INLINE long 32902+extract_1 (CGEN_CPU_DESC cd, 32903+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 32904+ int start, 32905+ int length, 32906+ int word_length, 32907+ unsigned char *bufp, 32908+ bfd_vma pc ATTRIBUTE_UNUSED) 32909+{ 32910+ unsigned long x; 32911+ int shift; 32912+ 32913+ x = cgen_get_insn_value (cd, bufp, word_length); 32914+ 32915+ if (CGEN_INSN_LSB0_P) 32916+ shift = (start + 1) - length; 32917+ else 32918+ shift = (word_length - (start + length)); 32919+ return x >> shift; 32920+} 32921+ 32922+#endif /* ! CGEN_INT_INSN_P */ 32923+ 32924+/* Default extraction routine. 32925+ 32926+ INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 32927+ or sometimes less for cases like the m32r where the base insn size is 32 32928+ but some insns are 16 bits. 32929+ ATTRS is a mask of the boolean attributes. We only need `SIGNED', 32930+ but for generality we take a bitmask of all of them. 32931+ WORD_OFFSET is the offset in bits from the start of the insn of the value. 32932+ WORD_LENGTH is the length of the word in bits in which the value resides. 32933+ START is the starting bit number in the word, architecture origin. 32934+ LENGTH is the length of VALUE in bits. 32935+ TOTAL_LENGTH is the total length of the insn in bits. 32936+ 32937+ Returns 1 for success, 0 for failure. */ 32938+ 32939+/* ??? The return code isn't properly used. wip. */ 32940+ 32941+/* ??? This doesn't handle bfd_vma's. Create another function when 32942+ necessary. */ 32943+ 32944+static int 32945+extract_normal (CGEN_CPU_DESC cd, 32946+#if ! CGEN_INT_INSN_P 32947+ CGEN_EXTRACT_INFO *ex_info, 32948+#else 32949+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 32950+#endif 32951+ CGEN_INSN_INT insn_value, 32952+ unsigned int attrs, 32953+ unsigned int word_offset, 32954+ unsigned int start, 32955+ unsigned int length, 32956+ unsigned int word_length, 32957+ unsigned int total_length, 32958+#if ! CGEN_INT_INSN_P 32959+ bfd_vma pc, 32960+#else 32961+ bfd_vma pc ATTRIBUTE_UNUSED, 32962+#endif 32963+ long *valuep) 32964+{ 32965+ long value, mask; 32966+ 32967+ /* If LENGTH is zero, this operand doesn't contribute to the value 32968+ so give it a standard value of zero. */ 32969+ if (length == 0) 32970+ { 32971+ *valuep = 0; 32972+ return 1; 32973+ } 32974+ 32975+ if (word_length > 8 * sizeof (CGEN_INSN_INT)) 32976+ abort (); 32977+ 32978+ /* For architectures with insns smaller than the insn-base-bitsize, 32979+ word_length may be too big. */ 32980+ if (cd->min_insn_bitsize < cd->base_insn_bitsize) 32981+ { 32982+ if (word_offset + word_length > total_length) 32983+ word_length = total_length - word_offset; 32984+ } 32985+ 32986+ /* Does the value reside in INSN_VALUE, and at the right alignment? */ 32987+ 32988+ if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 32989+ { 32990+ if (CGEN_INSN_LSB0_P) 32991+ value = insn_value >> ((word_offset + start + 1) - length); 32992+ else 32993+ value = insn_value >> (total_length - ( word_offset + start + length)); 32994+ } 32995+ 32996+#if ! CGEN_INT_INSN_P 32997+ 32998+ else 32999+ { 33000+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 33001+ 33002+ if (word_length > 8 * sizeof (CGEN_INSN_INT)) 33003+ abort (); 33004+ 33005+ if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 33006+ return 0; 33007+ 33008+ value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 33009+ } 33010+ 33011+#endif /* ! CGEN_INT_INSN_P */ 33012+ 33013+ /* Written this way to avoid undefined behaviour. */ 33014+ mask = (((1L << (length - 1)) - 1) << 1) | 1; 33015+ 33016+ value &= mask; 33017+ /* sign extend? */ 33018+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 33019+ && (value & (1L << (length - 1)))) 33020+ value |= ~mask; 33021+ 33022+ *valuep = value; 33023+ 33024+ return 1; 33025+} 33026+ 33027+/* Default insn extractor. 33028+ 33029+ INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 33030+ The extracted fields are stored in FIELDS. 33031+ EX_INFO is used to handle reading variable length insns. 33032+ Return the length of the insn in bits, or 0 if no match, 33033+ or -1 if an error occurs fetching data (memory_error_func will have 33034+ been called). */ 33035+ 33036+static int 33037+extract_insn_normal (CGEN_CPU_DESC cd, 33038+ const CGEN_INSN *insn, 33039+ CGEN_EXTRACT_INFO *ex_info, 33040+ CGEN_INSN_INT insn_value, 33041+ CGEN_FIELDS *fields, 33042+ bfd_vma pc) 33043+{ 33044+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 33045+ const CGEN_SYNTAX_CHAR_TYPE *syn; 33046+ 33047+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 33048+ 33049+ CGEN_INIT_EXTRACT (cd); 33050+ 33051+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 33052+ { 33053+ int length; 33054+ 33055+ if (CGEN_SYNTAX_CHAR_P (*syn)) 33056+ continue; 33057+ 33058+ length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 33059+ ex_info, insn_value, fields, pc); 33060+ if (length <= 0) 33061+ return length; 33062+ } 33063+ 33064+ /* We recognized and successfully extracted this insn. */ 33065+ return CGEN_INSN_BITSIZE (insn); 33066+} 33067+ 33068+/* Machine generated code added here. */ 33069+ 33070+const char * or1k_cgen_insert_operand 33071+ (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 33072+ 33073+/* Main entry point for operand insertion. 33074+ 33075+ This function is basically just a big switch statement. Earlier versions 33076+ used tables to look up the function to use, but 33077+ - if the table contains both assembler and disassembler functions then 33078+ the disassembler contains much of the assembler and vice-versa, 33079+ - there's a lot of inlining possibilities as things grow, 33080+ - using a switch statement avoids the function call overhead. 33081+ 33082+ This function could be moved into `parse_insn_normal', but keeping it 33083+ separate makes clear the interface between `parse_insn_normal' and each of 33084+ the handlers. It's also needed by GAS to insert operands that couldn't be 33085+ resolved during parsing. */ 33086+ 33087+const char * 33088+or1k_cgen_insert_operand (CGEN_CPU_DESC cd, 33089+ int opindex, 33090+ CGEN_FIELDS * fields, 33091+ CGEN_INSN_BYTES_PTR buffer, 33092+ bfd_vma pc ATTRIBUTE_UNUSED) 33093+{ 33094+ const char * errmsg = NULL; 33095+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 33096+ 33097+ switch (opindex) 33098+ { 33099+ case OR1K_OPERAND_DISP26 : 33100+ { 33101+ long value = fields->f_disp26; 33102+ value = ((SI) (((value) - (pc))) >> (2)); 33103+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); 33104+ } 33105+ break; 33106+ case OR1K_OPERAND_RA : 33107+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 33108+ break; 33109+ case OR1K_OPERAND_RADF : 33110+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 33111+ break; 33112+ case OR1K_OPERAND_RASF : 33113+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 33114+ break; 33115+ case OR1K_OPERAND_RB : 33116+ errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 33117+ break; 33118+ case OR1K_OPERAND_RBDF : 33119+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 33120+ break; 33121+ case OR1K_OPERAND_RBSF : 33122+ errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 33123+ break; 33124+ case OR1K_OPERAND_RD : 33125+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 33126+ break; 33127+ case OR1K_OPERAND_RDDF : 33128+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 33129+ break; 33130+ case OR1K_OPERAND_RDSF : 33131+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 33132+ break; 33133+ case OR1K_OPERAND_SIMM16 : 33134+ errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer); 33135+ break; 33136+ case OR1K_OPERAND_SIMM16_SPLIT : 33137+ { 33138+{ 33139+ FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31)); 33140+ FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047)); 33141+} 33142+ errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 33143+ if (errmsg) 33144+ break; 33145+ errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 33146+ if (errmsg) 33147+ break; 33148+ } 33149+ break; 33150+ case OR1K_OPERAND_UIMM16 : 33151+ errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); 33152+ break; 33153+ case OR1K_OPERAND_UIMM16_SPLIT : 33154+ { 33155+{ 33156+ FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31)); 33157+ FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047)); 33158+} 33159+ errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 33160+ if (errmsg) 33161+ break; 33162+ errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 33163+ if (errmsg) 33164+ break; 33165+ } 33166+ break; 33167+ case OR1K_OPERAND_UIMM6 : 33168+ errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer); 33169+ break; 33170+ 33171+ default : 33172+ /* xgettext:c-format */ 33173+ fprintf (stderr, _("Unrecognized field %d while building insn.\n"), 33174+ opindex); 33175+ abort (); 33176+ } 33177+ 33178+ return errmsg; 33179+} 33180+ 33181+int or1k_cgen_extract_operand 33182+ (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 33183+ 33184+/* Main entry point for operand extraction. 33185+ The result is <= 0 for error, >0 for success. 33186+ ??? Actual values aren't well defined right now. 33187+ 33188+ This function is basically just a big switch statement. Earlier versions 33189+ used tables to look up the function to use, but 33190+ - if the table contains both assembler and disassembler functions then 33191+ the disassembler contains much of the assembler and vice-versa, 33192+ - there's a lot of inlining possibilities as things grow, 33193+ - using a switch statement avoids the function call overhead. 33194+ 33195+ This function could be moved into `print_insn_normal', but keeping it 33196+ separate makes clear the interface between `print_insn_normal' and each of 33197+ the handlers. */ 33198+ 33199+int 33200+or1k_cgen_extract_operand (CGEN_CPU_DESC cd, 33201+ int opindex, 33202+ CGEN_EXTRACT_INFO *ex_info, 33203+ CGEN_INSN_INT insn_value, 33204+ CGEN_FIELDS * fields, 33205+ bfd_vma pc) 33206+{ 33207+ /* Assume success (for those operands that are nops). */ 33208+ int length = 1; 33209+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 33210+ 33211+ switch (opindex) 33212+ { 33213+ case OR1K_OPERAND_DISP26 : 33214+ { 33215+ long value; 33216+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); 33217+ value = ((((value) << (2))) + (pc)); 33218+ fields->f_disp26 = value; 33219+ } 33220+ break; 33221+ case OR1K_OPERAND_RA : 33222+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 33223+ break; 33224+ case OR1K_OPERAND_RADF : 33225+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 33226+ break; 33227+ case OR1K_OPERAND_RASF : 33228+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 33229+ break; 33230+ case OR1K_OPERAND_RB : 33231+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 33232+ break; 33233+ case OR1K_OPERAND_RBDF : 33234+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 33235+ break; 33236+ case OR1K_OPERAND_RBSF : 33237+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 33238+ break; 33239+ case OR1K_OPERAND_RD : 33240+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 33241+ break; 33242+ case OR1K_OPERAND_RDDF : 33243+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 33244+ break; 33245+ case OR1K_OPERAND_RDSF : 33246+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 33247+ break; 33248+ case OR1K_OPERAND_SIMM16 : 33249+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); 33250+ break; 33251+ case OR1K_OPERAND_SIMM16_SPLIT : 33252+ { 33253+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 33254+ if (length <= 0) break; 33255+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 33256+ if (length <= 0) break; 33257+ FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 33258+ } 33259+ break; 33260+ case OR1K_OPERAND_UIMM16 : 33261+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); 33262+ break; 33263+ case OR1K_OPERAND_UIMM16_SPLIT : 33264+ { 33265+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 33266+ if (length <= 0) break; 33267+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 33268+ if (length <= 0) break; 33269+ FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 33270+ } 33271+ break; 33272+ case OR1K_OPERAND_UIMM6 : 33273+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6); 33274+ break; 33275+ 33276+ default : 33277+ /* xgettext:c-format */ 33278+ fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), 33279+ opindex); 33280+ abort (); 33281+ } 33282+ 33283+ return length; 33284+} 33285+ 33286+cgen_insert_fn * const or1k_cgen_insert_handlers[] = 33287+{ 33288+ insert_insn_normal, 33289+}; 33290+ 33291+cgen_extract_fn * const or1k_cgen_extract_handlers[] = 33292+{ 33293+ extract_insn_normal, 33294+}; 33295+ 33296+int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 33297+bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 33298+ 33299+/* Getting values from cgen_fields is handled by a collection of functions. 33300+ They are distinguished by the type of the VALUE argument they return. 33301+ TODO: floating point, inlining support, remove cases where result type 33302+ not appropriate. */ 33303+ 33304+int 33305+or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 33306+ int opindex, 33307+ const CGEN_FIELDS * fields) 33308+{ 33309+ int value; 33310+ 33311+ switch (opindex) 33312+ { 33313+ case OR1K_OPERAND_DISP26 : 33314+ value = fields->f_disp26; 33315+ break; 33316+ case OR1K_OPERAND_RA : 33317+ value = fields->f_r2; 33318+ break; 33319+ case OR1K_OPERAND_RADF : 33320+ value = fields->f_r1; 33321+ break; 33322+ case OR1K_OPERAND_RASF : 33323+ value = fields->f_r2; 33324+ break; 33325+ case OR1K_OPERAND_RB : 33326+ value = fields->f_r3; 33327+ break; 33328+ case OR1K_OPERAND_RBDF : 33329+ value = fields->f_r1; 33330+ break; 33331+ case OR1K_OPERAND_RBSF : 33332+ value = fields->f_r3; 33333+ break; 33334+ case OR1K_OPERAND_RD : 33335+ value = fields->f_r1; 33336+ break; 33337+ case OR1K_OPERAND_RDDF : 33338+ value = fields->f_r1; 33339+ break; 33340+ case OR1K_OPERAND_RDSF : 33341+ value = fields->f_r1; 33342+ break; 33343+ case OR1K_OPERAND_SIMM16 : 33344+ value = fields->f_simm16; 33345+ break; 33346+ case OR1K_OPERAND_SIMM16_SPLIT : 33347+ value = fields->f_simm16_split; 33348+ break; 33349+ case OR1K_OPERAND_UIMM16 : 33350+ value = fields->f_uimm16; 33351+ break; 33352+ case OR1K_OPERAND_UIMM16_SPLIT : 33353+ value = fields->f_uimm16_split; 33354+ break; 33355+ case OR1K_OPERAND_UIMM6 : 33356+ value = fields->f_uimm6; 33357+ break; 33358+ 33359+ default : 33360+ /* xgettext:c-format */ 33361+ fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), 33362+ opindex); 33363+ abort (); 33364+ } 33365+ 33366+ return value; 33367+} 33368+ 33369+bfd_vma 33370+or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 33371+ int opindex, 33372+ const CGEN_FIELDS * fields) 33373+{ 33374+ bfd_vma value; 33375+ 33376+ switch (opindex) 33377+ { 33378+ case OR1K_OPERAND_DISP26 : 33379+ value = fields->f_disp26; 33380+ break; 33381+ case OR1K_OPERAND_RA : 33382+ value = fields->f_r2; 33383+ break; 33384+ case OR1K_OPERAND_RADF : 33385+ value = fields->f_r1; 33386+ break; 33387+ case OR1K_OPERAND_RASF : 33388+ value = fields->f_r2; 33389+ break; 33390+ case OR1K_OPERAND_RB : 33391+ value = fields->f_r3; 33392+ break; 33393+ case OR1K_OPERAND_RBDF : 33394+ value = fields->f_r1; 33395+ break; 33396+ case OR1K_OPERAND_RBSF : 33397+ value = fields->f_r3; 33398+ break; 33399+ case OR1K_OPERAND_RD : 33400+ value = fields->f_r1; 33401+ break; 33402+ case OR1K_OPERAND_RDDF : 33403+ value = fields->f_r1; 33404+ break; 33405+ case OR1K_OPERAND_RDSF : 33406+ value = fields->f_r1; 33407+ break; 33408+ case OR1K_OPERAND_SIMM16 : 33409+ value = fields->f_simm16; 33410+ break; 33411+ case OR1K_OPERAND_SIMM16_SPLIT : 33412+ value = fields->f_simm16_split; 33413+ break; 33414+ case OR1K_OPERAND_UIMM16 : 33415+ value = fields->f_uimm16; 33416+ break; 33417+ case OR1K_OPERAND_UIMM16_SPLIT : 33418+ value = fields->f_uimm16_split; 33419+ break; 33420+ case OR1K_OPERAND_UIMM6 : 33421+ value = fields->f_uimm6; 33422+ break; 33423+ 33424+ default : 33425+ /* xgettext:c-format */ 33426+ fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), 33427+ opindex); 33428+ abort (); 33429+ } 33430+ 33431+ return value; 33432+} 33433+ 33434+void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 33435+void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 33436+ 33437+/* Stuffing values in cgen_fields is handled by a collection of functions. 33438+ They are distinguished by the type of the VALUE argument they accept. 33439+ TODO: floating point, inlining support, remove cases where argument type 33440+ not appropriate. */ 33441+ 33442+void 33443+or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 33444+ int opindex, 33445+ CGEN_FIELDS * fields, 33446+ int value) 33447+{ 33448+ switch (opindex) 33449+ { 33450+ case OR1K_OPERAND_DISP26 : 33451+ fields->f_disp26 = value; 33452+ break; 33453+ case OR1K_OPERAND_RA : 33454+ fields->f_r2 = value; 33455+ break; 33456+ case OR1K_OPERAND_RADF : 33457+ fields->f_r1 = value; 33458+ break; 33459+ case OR1K_OPERAND_RASF : 33460+ fields->f_r2 = value; 33461+ break; 33462+ case OR1K_OPERAND_RB : 33463+ fields->f_r3 = value; 33464+ break; 33465+ case OR1K_OPERAND_RBDF : 33466+ fields->f_r1 = value; 33467+ break; 33468+ case OR1K_OPERAND_RBSF : 33469+ fields->f_r3 = value; 33470+ break; 33471+ case OR1K_OPERAND_RD : 33472+ fields->f_r1 = value; 33473+ break; 33474+ case OR1K_OPERAND_RDDF : 33475+ fields->f_r1 = value; 33476+ break; 33477+ case OR1K_OPERAND_RDSF : 33478+ fields->f_r1 = value; 33479+ break; 33480+ case OR1K_OPERAND_SIMM16 : 33481+ fields->f_simm16 = value; 33482+ break; 33483+ case OR1K_OPERAND_SIMM16_SPLIT : 33484+ fields->f_simm16_split = value; 33485+ break; 33486+ case OR1K_OPERAND_UIMM16 : 33487+ fields->f_uimm16 = value; 33488+ break; 33489+ case OR1K_OPERAND_UIMM16_SPLIT : 33490+ fields->f_uimm16_split = value; 33491+ break; 33492+ case OR1K_OPERAND_UIMM6 : 33493+ fields->f_uimm6 = value; 33494+ break; 33495+ 33496+ default : 33497+ /* xgettext:c-format */ 33498+ fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), 33499+ opindex); 33500+ abort (); 33501+ } 33502+} 33503+ 33504+void 33505+or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 33506+ int opindex, 33507+ CGEN_FIELDS * fields, 33508+ bfd_vma value) 33509+{ 33510+ switch (opindex) 33511+ { 33512+ case OR1K_OPERAND_DISP26 : 33513+ fields->f_disp26 = value; 33514+ break; 33515+ case OR1K_OPERAND_RA : 33516+ fields->f_r2 = value; 33517+ break; 33518+ case OR1K_OPERAND_RADF : 33519+ fields->f_r1 = value; 33520+ break; 33521+ case OR1K_OPERAND_RASF : 33522+ fields->f_r2 = value; 33523+ break; 33524+ case OR1K_OPERAND_RB : 33525+ fields->f_r3 = value; 33526+ break; 33527+ case OR1K_OPERAND_RBDF : 33528+ fields->f_r1 = value; 33529+ break; 33530+ case OR1K_OPERAND_RBSF : 33531+ fields->f_r3 = value; 33532+ break; 33533+ case OR1K_OPERAND_RD : 33534+ fields->f_r1 = value; 33535+ break; 33536+ case OR1K_OPERAND_RDDF : 33537+ fields->f_r1 = value; 33538+ break; 33539+ case OR1K_OPERAND_RDSF : 33540+ fields->f_r1 = value; 33541+ break; 33542+ case OR1K_OPERAND_SIMM16 : 33543+ fields->f_simm16 = value; 33544+ break; 33545+ case OR1K_OPERAND_SIMM16_SPLIT : 33546+ fields->f_simm16_split = value; 33547+ break; 33548+ case OR1K_OPERAND_UIMM16 : 33549+ fields->f_uimm16 = value; 33550+ break; 33551+ case OR1K_OPERAND_UIMM16_SPLIT : 33552+ fields->f_uimm16_split = value; 33553+ break; 33554+ case OR1K_OPERAND_UIMM6 : 33555+ fields->f_uimm6 = value; 33556+ break; 33557+ 33558+ default : 33559+ /* xgettext:c-format */ 33560+ fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), 33561+ opindex); 33562+ abort (); 33563+ } 33564+} 33565+ 33566+/* Function to call before using the instruction builder tables. */ 33567+ 33568+void 33569+or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd) 33570+{ 33571+ cd->insert_handlers = & or1k_cgen_insert_handlers[0]; 33572+ cd->extract_handlers = & or1k_cgen_extract_handlers[0]; 33573+ 33574+ cd->insert_operand = or1k_cgen_insert_operand; 33575+ cd->extract_operand = or1k_cgen_extract_operand; 33576+ 33577+ cd->get_int_operand = or1k_cgen_get_int_operand; 33578+ cd->set_int_operand = or1k_cgen_set_int_operand; 33579+ cd->get_vma_operand = or1k_cgen_get_vma_operand; 33580+ cd->set_vma_operand = or1k_cgen_set_vma_operand; 33581+} 33582diff -rNU3 dist.orig/opcodes/or1k-opc.c dist/opcodes/or1k-opc.c 33583--- dist.orig/opcodes/or1k-opc.c 1970-01-01 01:00:00.000000000 +0100 33584+++ dist/opcodes/or1k-opc.c 2015-10-18 13:11:20.000000000 +0200 33585@@ -0,0 +1,1081 @@ 33586+/* Instruction opcode table for or1k. 33587+ 33588+THIS FILE IS MACHINE GENERATED WITH CGEN. 33589+ 33590+Copyright (C) 1996-2014 Free Software Foundation, Inc. 33591+ 33592+This file is part of the GNU Binutils and/or GDB, the GNU debugger. 33593+ 33594+ This file is free software; you can redistribute it and/or modify 33595+ it under the terms of the GNU General Public License as published by 33596+ the Free Software Foundation; either version 3, or (at your option) 33597+ any later version. 33598+ 33599+ It is distributed in the hope that it will be useful, but WITHOUT 33600+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 33601+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 33602+ License for more details. 33603+ 33604+ You should have received a copy of the GNU General Public License along 33605+ with this program; if not, write to the Free Software Foundation, Inc., 33606+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 33607+ 33608+*/ 33609+ 33610+#include "sysdep.h" 33611+#include "ansidecl.h" 33612+#include "bfd.h" 33613+#include "symcat.h" 33614+#include "or1k-desc.h" 33615+#include "or1k-opc.h" 33616+#include "libiberty.h" 33617+ 33618+/* -- opc.c */ 33619+/* -- */ 33620+/* The hash functions are recorded here to help keep assembler code out of 33621+ the disassembler and vice versa. */ 33622+ 33623+static int asm_hash_insn_p (const CGEN_INSN *); 33624+static unsigned int asm_hash_insn (const char *); 33625+static int dis_hash_insn_p (const CGEN_INSN *); 33626+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); 33627+ 33628+/* Instruction formats. */ 33629+ 33630+#define F(f) & or1k_cgen_ifld_table[OR1K_##f] 33631+static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 33632+ 0, 0, 0x0, { { 0 } } 33633+}; 33634+ 33635+static const CGEN_IFMT ifmt_l_j ATTRIBUTE_UNUSED = { 33636+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_DISP26) }, { 0 } } 33637+}; 33638+ 33639+static const CGEN_IFMT ifmt_l_jr ATTRIBUTE_UNUSED = { 33640+ 32, 32, 0xffff07ff, { { F (F_OPCODE) }, { F (F_RESV_25_10) }, { F (F_R3) }, { F (F_RESV_10_11) }, { 0 } } 33641+}; 33642+ 33643+static const CGEN_IFMT ifmt_l_trap ATTRIBUTE_UNUSED = { 33644+ 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_OP_25_5) }, { F (F_RESV_20_5) }, { F (F_UIMM16) }, { 0 } } 33645+}; 33646+ 33647+static const CGEN_IFMT ifmt_l_msync ATTRIBUTE_UNUSED = { 33648+ 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_OP_25_5) }, { F (F_RESV_20_21) }, { 0 } } 33649+}; 33650+ 33651+static const CGEN_IFMT ifmt_l_rfe ATTRIBUTE_UNUSED = { 33652+ 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RESV_25_26) }, { 0 } } 33653+}; 33654+ 33655+static const CGEN_IFMT ifmt_l_nop_imm ATTRIBUTE_UNUSED = { 33656+ 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_OP_25_2) }, { F (F_RESV_23_8) }, { F (F_UIMM16) }, { 0 } } 33657+}; 33658+ 33659+static const CGEN_IFMT ifmt_l_movhi ATTRIBUTE_UNUSED = { 33660+ 32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_20_4) }, { F (F_OP_16_1) }, { F (F_UIMM16) }, { 0 } } 33661+}; 33662+ 33663+static const CGEN_IFMT ifmt_l_macrc ATTRIBUTE_UNUSED = { 33664+ 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_20_4) }, { F (F_OP_16_1) }, { F (F_UIMM16) }, { 0 } } 33665+}; 33666+ 33667+static const CGEN_IFMT ifmt_l_mfspr ATTRIBUTE_UNUSED = { 33668+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } 33669+}; 33670+ 33671+static const CGEN_IFMT ifmt_l_mtspr ATTRIBUTE_UNUSED = { 33672+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R2) }, { F (F_R3) }, { F (F_UIMM16_SPLIT) }, { 0 } } 33673+}; 33674+ 33675+static const CGEN_IFMT ifmt_l_lwz ATTRIBUTE_UNUSED = { 33676+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 33677+}; 33678+ 33679+static const CGEN_IFMT ifmt_l_sw ATTRIBUTE_UNUSED = { 33680+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R2) }, { F (F_R3) }, { F (F_SIMM16_SPLIT) }, { 0 } } 33681+}; 33682+ 33683+static const CGEN_IFMT ifmt_l_swa ATTRIBUTE_UNUSED = { 33684+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R2) }, { F (F_R3) }, { F (F_SIMM16) }, { 0 } } 33685+}; 33686+ 33687+static const CGEN_IFMT ifmt_l_sll ATTRIBUTE_UNUSED = { 33688+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_2) }, { F (F_RESV_5_2) }, { F (F_OP_3_4) }, { 0 } } 33689+}; 33690+ 33691+static const CGEN_IFMT ifmt_l_slli ATTRIBUTE_UNUSED = { 33692+ 32, 32, 0xfc00ffc0, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV_15_8) }, { F (F_OP_7_2) }, { F (F_UIMM6) }, { 0 } } 33693+}; 33694+ 33695+static const CGEN_IFMT ifmt_l_and ATTRIBUTE_UNUSED = { 33696+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_7) }, { F (F_OP_3_4) }, { 0 } } 33697+}; 33698+ 33699+static const CGEN_IFMT ifmt_l_exths ATTRIBUTE_UNUSED = { 33700+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV_15_6) }, { F (F_OP_9_4) }, { F (F_RESV_5_2) }, { F (F_OP_3_4) }, { 0 } } 33701+}; 33702+ 33703+static const CGEN_IFMT ifmt_l_cmov ATTRIBUTE_UNUSED = { 33704+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_1) }, { F (F_OP_9_2) }, { F (F_RESV_7_4) }, { F (F_OP_3_4) }, { 0 } } 33705+}; 33706+ 33707+static const CGEN_IFMT ifmt_l_sfgts ATTRIBUTE_UNUSED = { 33708+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_OP_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_11) }, { 0 } } 33709+}; 33710+ 33711+static const CGEN_IFMT ifmt_l_sfgtsi ATTRIBUTE_UNUSED = { 33712+ 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_OP_25_5) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 33713+}; 33714+ 33715+static const CGEN_IFMT ifmt_l_mac ATTRIBUTE_UNUSED = { 33716+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_OP_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_7) }, { F (F_OP_3_4) }, { 0 } } 33717+}; 33718+ 33719+static const CGEN_IFMT ifmt_l_maci ATTRIBUTE_UNUSED = { 33720+ 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } 33721+}; 33722+ 33723+static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED = { 33724+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33725+}; 33726+ 33727+static const CGEN_IFMT ifmt_lf_add_d ATTRIBUTE_UNUSED = { 33728+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33729+}; 33730+ 33731+static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED = { 33732+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33733+}; 33734+ 33735+static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED = { 33736+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33737+}; 33738+ 33739+static const CGEN_IFMT ifmt_lf_ftoi_d ATTRIBUTE_UNUSED = { 33740+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33741+}; 33742+ 33743+static const CGEN_IFMT ifmt_lf_eq_s ATTRIBUTE_UNUSED = { 33744+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33745+}; 33746+ 33747+static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED = { 33748+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33749+}; 33750+ 33751+static const CGEN_IFMT ifmt_lf_cust1_d ATTRIBUTE_UNUSED = { 33752+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } 33753+}; 33754+ 33755+#undef F 33756+ 33757+#define A(a) (1 << CGEN_INSN_##a) 33758+#define OPERAND(op) OR1K_OPERAND_##op 33759+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 33760+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 33761+ 33762+/* The instruction table. */ 33763+ 33764+static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = 33765+{ 33766+ /* Special null first entry. 33767+ A `num' value of zero is thus invalid. 33768+ Also, the special `invalid' insn resides here. */ 33769+ { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, 33770+/* l.j ${disp26} */ 33771+ { 33772+ { 0, 0, 0, 0 }, 33773+ { { MNEM, ' ', OP (DISP26), 0 } }, 33774+ & ifmt_l_j, { 0x0 } 33775+ }, 33776+/* l.jal ${disp26} */ 33777+ { 33778+ { 0, 0, 0, 0 }, 33779+ { { MNEM, ' ', OP (DISP26), 0 } }, 33780+ & ifmt_l_j, { 0x4000000 } 33781+ }, 33782+/* l.jr $rB */ 33783+ { 33784+ { 0, 0, 0, 0 }, 33785+ { { MNEM, ' ', OP (RB), 0 } }, 33786+ & ifmt_l_jr, { 0x44000000 } 33787+ }, 33788+/* l.jalr $rB */ 33789+ { 33790+ { 0, 0, 0, 0 }, 33791+ { { MNEM, ' ', OP (RB), 0 } }, 33792+ & ifmt_l_jr, { 0x48000000 } 33793+ }, 33794+/* l.bnf ${disp26} */ 33795+ { 33796+ { 0, 0, 0, 0 }, 33797+ { { MNEM, ' ', OP (DISP26), 0 } }, 33798+ & ifmt_l_j, { 0xc000000 } 33799+ }, 33800+/* l.bf ${disp26} */ 33801+ { 33802+ { 0, 0, 0, 0 }, 33803+ { { MNEM, ' ', OP (DISP26), 0 } }, 33804+ & ifmt_l_j, { 0x10000000 } 33805+ }, 33806+/* l.trap ${uimm16} */ 33807+ { 33808+ { 0, 0, 0, 0 }, 33809+ { { MNEM, ' ', OP (UIMM16), 0 } }, 33810+ & ifmt_l_trap, { 0x21000000 } 33811+ }, 33812+/* l.sys ${uimm16} */ 33813+ { 33814+ { 0, 0, 0, 0 }, 33815+ { { MNEM, ' ', OP (UIMM16), 0 } }, 33816+ & ifmt_l_trap, { 0x20000000 } 33817+ }, 33818+/* l.msync */ 33819+ { 33820+ { 0, 0, 0, 0 }, 33821+ { { MNEM, 0 } }, 33822+ & ifmt_l_msync, { 0x22000000 } 33823+ }, 33824+/* l.psync */ 33825+ { 33826+ { 0, 0, 0, 0 }, 33827+ { { MNEM, 0 } }, 33828+ & ifmt_l_msync, { 0x22800000 } 33829+ }, 33830+/* l.csync */ 33831+ { 33832+ { 0, 0, 0, 0 }, 33833+ { { MNEM, 0 } }, 33834+ & ifmt_l_msync, { 0x23000000 } 33835+ }, 33836+/* l.rfe */ 33837+ { 33838+ { 0, 0, 0, 0 }, 33839+ { { MNEM, 0 } }, 33840+ & ifmt_l_rfe, { 0x24000000 } 33841+ }, 33842+/* l.nop ${uimm16} */ 33843+ { 33844+ { 0, 0, 0, 0 }, 33845+ { { MNEM, ' ', OP (UIMM16), 0 } }, 33846+ & ifmt_l_nop_imm, { 0x15000000 } 33847+ }, 33848+/* l.nop */ 33849+ { 33850+ { 0, 0, 0, 0 }, 33851+ { { MNEM, 0 } }, 33852+ & ifmt_l_nop_imm, { 0x15000000 } 33853+ }, 33854+/* l.movhi $rD,$uimm16 */ 33855+ { 33856+ { 0, 0, 0, 0 }, 33857+ { { MNEM, ' ', OP (RD), ',', OP (UIMM16), 0 } }, 33858+ & ifmt_l_movhi, { 0x18000000 } 33859+ }, 33860+/* l.macrc $rD */ 33861+ { 33862+ { 0, 0, 0, 0 }, 33863+ { { MNEM, ' ', OP (RD), 0 } }, 33864+ & ifmt_l_macrc, { 0x18010000 } 33865+ }, 33866+/* l.mfspr $rD,$rA,${uimm16} */ 33867+ { 33868+ { 0, 0, 0, 0 }, 33869+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } }, 33870+ & ifmt_l_mfspr, { 0xb4000000 } 33871+ }, 33872+/* l.mtspr $rA,$rB,${uimm16-split} */ 33873+ { 33874+ { 0, 0, 0, 0 }, 33875+ { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } }, 33876+ & ifmt_l_mtspr, { 0xc0000000 } 33877+ }, 33878+/* l.lwz $rD,${simm16}($rA) */ 33879+ { 33880+ { 0, 0, 0, 0 }, 33881+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }, 33882+ & ifmt_l_lwz, { 0x84000000 } 33883+ }, 33884+/* l.lws $rD,${simm16}($rA) */ 33885+ { 33886+ { 0, 0, 0, 0 }, 33887+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }, 33888+ & ifmt_l_lwz, { 0x88000000 } 33889+ }, 33890+/* l.lwa $rD,${simm16}($rA) */ 33891+ { 33892+ { 0, 0, 0, 0 }, 33893+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }, 33894+ & ifmt_l_lwz, { 0x6c000000 } 33895+ }, 33896+/* l.lbz $rD,${simm16}($rA) */ 33897+ { 33898+ { 0, 0, 0, 0 }, 33899+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }, 33900+ & ifmt_l_lwz, { 0x8c000000 } 33901+ }, 33902+/* l.lbs $rD,${simm16}($rA) */ 33903+ { 33904+ { 0, 0, 0, 0 }, 33905+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }, 33906+ & ifmt_l_lwz, { 0x90000000 } 33907+ }, 33908+/* l.lhz $rD,${simm16}($rA) */ 33909+ { 33910+ { 0, 0, 0, 0 }, 33911+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }, 33912+ & ifmt_l_lwz, { 0x94000000 } 33913+ }, 33914+/* l.lhs $rD,${simm16}($rA) */ 33915+ { 33916+ { 0, 0, 0, 0 }, 33917+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }, 33918+ & ifmt_l_lwz, { 0x98000000 } 33919+ }, 33920+/* l.sw ${simm16-split}($rA),$rB */ 33921+ { 33922+ { 0, 0, 0, 0 }, 33923+ { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 33924+ & ifmt_l_sw, { 0xd4000000 } 33925+ }, 33926+/* l.sb ${simm16-split}($rA),$rB */ 33927+ { 33928+ { 0, 0, 0, 0 }, 33929+ { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 33930+ & ifmt_l_sw, { 0xd8000000 } 33931+ }, 33932+/* l.sh ${simm16-split}($rA),$rB */ 33933+ { 33934+ { 0, 0, 0, 0 }, 33935+ { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 33936+ & ifmt_l_sw, { 0xdc000000 } 33937+ }, 33938+/* l.swa ${simm16-split}($rA),$rB */ 33939+ { 33940+ { 0, 0, 0, 0 }, 33941+ { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 33942+ & ifmt_l_swa, { 0xcc000000 } 33943+ }, 33944+/* l.sll $rD,$rA,$rB */ 33945+ { 33946+ { 0, 0, 0, 0 }, 33947+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 33948+ & ifmt_l_sll, { 0xe0000008 } 33949+ }, 33950+/* l.slli $rD,$rA,${uimm6} */ 33951+ { 33952+ { 0, 0, 0, 0 }, 33953+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM6), 0 } }, 33954+ & ifmt_l_slli, { 0xb8000000 } 33955+ }, 33956+/* l.srl $rD,$rA,$rB */ 33957+ { 33958+ { 0, 0, 0, 0 }, 33959+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 33960+ & ifmt_l_sll, { 0xe0000048 } 33961+ }, 33962+/* l.srli $rD,$rA,${uimm6} */ 33963+ { 33964+ { 0, 0, 0, 0 }, 33965+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM6), 0 } }, 33966+ & ifmt_l_slli, { 0xb8000040 } 33967+ }, 33968+/* l.sra $rD,$rA,$rB */ 33969+ { 33970+ { 0, 0, 0, 0 }, 33971+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 33972+ & ifmt_l_sll, { 0xe0000088 } 33973+ }, 33974+/* l.srai $rD,$rA,${uimm6} */ 33975+ { 33976+ { 0, 0, 0, 0 }, 33977+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM6), 0 } }, 33978+ & ifmt_l_slli, { 0xb8000080 } 33979+ }, 33980+/* l.ror $rD,$rA,$rB */ 33981+ { 33982+ { 0, 0, 0, 0 }, 33983+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 33984+ & ifmt_l_sll, { 0xe00000c8 } 33985+ }, 33986+/* l.rori $rD,$rA,${uimm6} */ 33987+ { 33988+ { 0, 0, 0, 0 }, 33989+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM6), 0 } }, 33990+ & ifmt_l_slli, { 0xb80000c0 } 33991+ }, 33992+/* l.and $rD,$rA,$rB */ 33993+ { 33994+ { 0, 0, 0, 0 }, 33995+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 33996+ & ifmt_l_and, { 0xe0000003 } 33997+ }, 33998+/* l.or $rD,$rA,$rB */ 33999+ { 34000+ { 0, 0, 0, 0 }, 34001+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34002+ & ifmt_l_and, { 0xe0000004 } 34003+ }, 34004+/* l.xor $rD,$rA,$rB */ 34005+ { 34006+ { 0, 0, 0, 0 }, 34007+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34008+ & ifmt_l_and, { 0xe0000005 } 34009+ }, 34010+/* l.add $rD,$rA,$rB */ 34011+ { 34012+ { 0, 0, 0, 0 }, 34013+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34014+ & ifmt_l_and, { 0xe0000000 } 34015+ }, 34016+/* l.sub $rD,$rA,$rB */ 34017+ { 34018+ { 0, 0, 0, 0 }, 34019+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34020+ & ifmt_l_and, { 0xe0000002 } 34021+ }, 34022+/* l.addc $rD,$rA,$rB */ 34023+ { 34024+ { 0, 0, 0, 0 }, 34025+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34026+ & ifmt_l_and, { 0xe0000001 } 34027+ }, 34028+/* l.mul $rD,$rA,$rB */ 34029+ { 34030+ { 0, 0, 0, 0 }, 34031+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34032+ & ifmt_l_and, { 0xe0000306 } 34033+ }, 34034+/* l.mulu $rD,$rA,$rB */ 34035+ { 34036+ { 0, 0, 0, 0 }, 34037+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34038+ & ifmt_l_and, { 0xe000030b } 34039+ }, 34040+/* l.div $rD,$rA,$rB */ 34041+ { 34042+ { 0, 0, 0, 0 }, 34043+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34044+ & ifmt_l_and, { 0xe0000309 } 34045+ }, 34046+/* l.divu $rD,$rA,$rB */ 34047+ { 34048+ { 0, 0, 0, 0 }, 34049+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34050+ & ifmt_l_and, { 0xe000030a } 34051+ }, 34052+/* l.ff1 $rD,$rA */ 34053+ { 34054+ { 0, 0, 0, 0 }, 34055+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34056+ & ifmt_l_and, { 0xe000000f } 34057+ }, 34058+/* l.fl1 $rD,$rA */ 34059+ { 34060+ { 0, 0, 0, 0 }, 34061+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34062+ & ifmt_l_and, { 0xe000010f } 34063+ }, 34064+/* l.andi $rD,$rA,$uimm16 */ 34065+ { 34066+ { 0, 0, 0, 0 }, 34067+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } }, 34068+ & ifmt_l_mfspr, { 0xa4000000 } 34069+ }, 34070+/* l.ori $rD,$rA,$uimm16 */ 34071+ { 34072+ { 0, 0, 0, 0 }, 34073+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } }, 34074+ & ifmt_l_mfspr, { 0xa8000000 } 34075+ }, 34076+/* l.xori $rD,$rA,$simm16 */ 34077+ { 34078+ { 0, 0, 0, 0 }, 34079+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (SIMM16), 0 } }, 34080+ & ifmt_l_lwz, { 0xac000000 } 34081+ }, 34082+/* l.addi $rD,$rA,$simm16 */ 34083+ { 34084+ { 0, 0, 0, 0 }, 34085+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (SIMM16), 0 } }, 34086+ & ifmt_l_lwz, { 0x9c000000 } 34087+ }, 34088+/* l.addic $rD,$rA,$simm16 */ 34089+ { 34090+ { 0, 0, 0, 0 }, 34091+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (SIMM16), 0 } }, 34092+ & ifmt_l_lwz, { 0xa0000000 } 34093+ }, 34094+/* l.muli $rD,$rA,$simm16 */ 34095+ { 34096+ { 0, 0, 0, 0 }, 34097+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (SIMM16), 0 } }, 34098+ & ifmt_l_lwz, { 0xb0000000 } 34099+ }, 34100+/* l.exths $rD,$rA */ 34101+ { 34102+ { 0, 0, 0, 0 }, 34103+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34104+ & ifmt_l_exths, { 0xe000000c } 34105+ }, 34106+/* l.extbs $rD,$rA */ 34107+ { 34108+ { 0, 0, 0, 0 }, 34109+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34110+ & ifmt_l_exths, { 0xe000004c } 34111+ }, 34112+/* l.exthz $rD,$rA */ 34113+ { 34114+ { 0, 0, 0, 0 }, 34115+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34116+ & ifmt_l_exths, { 0xe000008c } 34117+ }, 34118+/* l.extbz $rD,$rA */ 34119+ { 34120+ { 0, 0, 0, 0 }, 34121+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34122+ & ifmt_l_exths, { 0xe00000cc } 34123+ }, 34124+/* l.extws $rD,$rA */ 34125+ { 34126+ { 0, 0, 0, 0 }, 34127+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34128+ & ifmt_l_exths, { 0xe000000d } 34129+ }, 34130+/* l.extwz $rD,$rA */ 34131+ { 34132+ { 0, 0, 0, 0 }, 34133+ { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 34134+ & ifmt_l_exths, { 0xe000004d } 34135+ }, 34136+/* l.cmov $rD,$rA,$rB */ 34137+ { 34138+ { 0, 0, 0, 0 }, 34139+ { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 34140+ & ifmt_l_cmov, { 0xe000000e } 34141+ }, 34142+/* l.sfgts $rA,$rB */ 34143+ { 34144+ { 0, 0, 0, 0 }, 34145+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34146+ & ifmt_l_sfgts, { 0xe5400000 } 34147+ }, 34148+/* l.sfgtsi $rA,$simm16 */ 34149+ { 34150+ { 0, 0, 0, 0 }, 34151+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34152+ & ifmt_l_sfgtsi, { 0xbd400000 } 34153+ }, 34154+/* l.sfgtu $rA,$rB */ 34155+ { 34156+ { 0, 0, 0, 0 }, 34157+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34158+ & ifmt_l_sfgts, { 0xe4400000 } 34159+ }, 34160+/* l.sfgtui $rA,$simm16 */ 34161+ { 34162+ { 0, 0, 0, 0 }, 34163+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34164+ & ifmt_l_sfgtsi, { 0xbc400000 } 34165+ }, 34166+/* l.sfges $rA,$rB */ 34167+ { 34168+ { 0, 0, 0, 0 }, 34169+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34170+ & ifmt_l_sfgts, { 0xe5600000 } 34171+ }, 34172+/* l.sfgesi $rA,$simm16 */ 34173+ { 34174+ { 0, 0, 0, 0 }, 34175+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34176+ & ifmt_l_sfgtsi, { 0xbd600000 } 34177+ }, 34178+/* l.sfgeu $rA,$rB */ 34179+ { 34180+ { 0, 0, 0, 0 }, 34181+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34182+ & ifmt_l_sfgts, { 0xe4600000 } 34183+ }, 34184+/* l.sfgeui $rA,$simm16 */ 34185+ { 34186+ { 0, 0, 0, 0 }, 34187+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34188+ & ifmt_l_sfgtsi, { 0xbc600000 } 34189+ }, 34190+/* l.sflts $rA,$rB */ 34191+ { 34192+ { 0, 0, 0, 0 }, 34193+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34194+ & ifmt_l_sfgts, { 0xe5800000 } 34195+ }, 34196+/* l.sfltsi $rA,$simm16 */ 34197+ { 34198+ { 0, 0, 0, 0 }, 34199+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34200+ & ifmt_l_sfgtsi, { 0xbd800000 } 34201+ }, 34202+/* l.sfltu $rA,$rB */ 34203+ { 34204+ { 0, 0, 0, 0 }, 34205+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34206+ & ifmt_l_sfgts, { 0xe4800000 } 34207+ }, 34208+/* l.sfltui $rA,$simm16 */ 34209+ { 34210+ { 0, 0, 0, 0 }, 34211+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34212+ & ifmt_l_sfgtsi, { 0xbc800000 } 34213+ }, 34214+/* l.sfles $rA,$rB */ 34215+ { 34216+ { 0, 0, 0, 0 }, 34217+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34218+ & ifmt_l_sfgts, { 0xe5a00000 } 34219+ }, 34220+/* l.sflesi $rA,$simm16 */ 34221+ { 34222+ { 0, 0, 0, 0 }, 34223+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34224+ & ifmt_l_sfgtsi, { 0xbda00000 } 34225+ }, 34226+/* l.sfleu $rA,$rB */ 34227+ { 34228+ { 0, 0, 0, 0 }, 34229+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34230+ & ifmt_l_sfgts, { 0xe4a00000 } 34231+ }, 34232+/* l.sfleui $rA,$simm16 */ 34233+ { 34234+ { 0, 0, 0, 0 }, 34235+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34236+ & ifmt_l_sfgtsi, { 0xbca00000 } 34237+ }, 34238+/* l.sfeq $rA,$rB */ 34239+ { 34240+ { 0, 0, 0, 0 }, 34241+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34242+ & ifmt_l_sfgts, { 0xe4000000 } 34243+ }, 34244+/* l.sfeqi $rA,$simm16 */ 34245+ { 34246+ { 0, 0, 0, 0 }, 34247+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34248+ & ifmt_l_sfgtsi, { 0xbc000000 } 34249+ }, 34250+/* l.sfne $rA,$rB */ 34251+ { 34252+ { 0, 0, 0, 0 }, 34253+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34254+ & ifmt_l_sfgts, { 0xe4200000 } 34255+ }, 34256+/* l.sfnei $rA,$simm16 */ 34257+ { 34258+ { 0, 0, 0, 0 }, 34259+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34260+ & ifmt_l_sfgtsi, { 0xbc200000 } 34261+ }, 34262+/* l.mac $rA,$rB */ 34263+ { 34264+ { 0, 0, 0, 0 }, 34265+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34266+ & ifmt_l_mac, { 0xc4000001 } 34267+ }, 34268+/* l.msb $rA,$rB */ 34269+ { 34270+ { 0, 0, 0, 0 }, 34271+ { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 34272+ & ifmt_l_mac, { 0xc4000002 } 34273+ }, 34274+/* l.maci $rA,${simm16} */ 34275+ { 34276+ { 0, 0, 0, 0 }, 34277+ { { MNEM, ' ', OP (RA), ',', OP (SIMM16), 0 } }, 34278+ & ifmt_l_maci, { 0x4c000000 } 34279+ }, 34280+/* l.cust1 */ 34281+ { 34282+ { 0, 0, 0, 0 }, 34283+ { { MNEM, 0 } }, 34284+ & ifmt_l_rfe, { 0x70000000 } 34285+ }, 34286+/* l.cust2 */ 34287+ { 34288+ { 0, 0, 0, 0 }, 34289+ { { MNEM, 0 } }, 34290+ & ifmt_l_rfe, { 0x74000000 } 34291+ }, 34292+/* l.cust3 */ 34293+ { 34294+ { 0, 0, 0, 0 }, 34295+ { { MNEM, 0 } }, 34296+ & ifmt_l_rfe, { 0x78000000 } 34297+ }, 34298+/* l.cust4 */ 34299+ { 34300+ { 0, 0, 0, 0 }, 34301+ { { MNEM, 0 } }, 34302+ & ifmt_l_rfe, { 0x7c000000 } 34303+ }, 34304+/* l.cust5 */ 34305+ { 34306+ { 0, 0, 0, 0 }, 34307+ { { MNEM, 0 } }, 34308+ & ifmt_l_rfe, { 0xf0000000 } 34309+ }, 34310+/* l.cust6 */ 34311+ { 34312+ { 0, 0, 0, 0 }, 34313+ { { MNEM, 0 } }, 34314+ & ifmt_l_rfe, { 0xf4000000 } 34315+ }, 34316+/* l.cust7 */ 34317+ { 34318+ { 0, 0, 0, 0 }, 34319+ { { MNEM, 0 } }, 34320+ & ifmt_l_rfe, { 0xf8000000 } 34321+ }, 34322+/* l.cust8 */ 34323+ { 34324+ { 0, 0, 0, 0 }, 34325+ { { MNEM, 0 } }, 34326+ & ifmt_l_rfe, { 0xfc000000 } 34327+ }, 34328+/* lf.add.s $rDSF,$rASF,$rBSF */ 34329+ { 34330+ { 0, 0, 0, 0 }, 34331+ { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, 34332+ & ifmt_lf_add_s, { 0xc8000000 } 34333+ }, 34334+/* lf.add.d $rDDF,$rADF,$rBDF */ 34335+ { 34336+ { 0, 0, 0, 0 }, 34337+ { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, 34338+ & ifmt_lf_add_d, { 0xc8000010 } 34339+ }, 34340+/* lf.sub.s $rDSF,$rASF,$rBSF */ 34341+ { 34342+ { 0, 0, 0, 0 }, 34343+ { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, 34344+ & ifmt_lf_add_s, { 0xc8000001 } 34345+ }, 34346+/* lf.sub.d $rDDF,$rADF,$rBDF */ 34347+ { 34348+ { 0, 0, 0, 0 }, 34349+ { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, 34350+ & ifmt_lf_add_d, { 0xc8000011 } 34351+ }, 34352+/* lf.mul.s $rDSF,$rASF,$rBSF */ 34353+ { 34354+ { 0, 0, 0, 0 }, 34355+ { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, 34356+ & ifmt_lf_add_s, { 0xc8000002 } 34357+ }, 34358+/* lf.mul.d $rDDF,$rADF,$rBDF */ 34359+ { 34360+ { 0, 0, 0, 0 }, 34361+ { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, 34362+ & ifmt_lf_add_d, { 0xc8000012 } 34363+ }, 34364+/* lf.div.s $rDSF,$rASF,$rBSF */ 34365+ { 34366+ { 0, 0, 0, 0 }, 34367+ { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, 34368+ & ifmt_lf_add_s, { 0xc8000003 } 34369+ }, 34370+/* lf.div.d $rDDF,$rADF,$rBDF */ 34371+ { 34372+ { 0, 0, 0, 0 }, 34373+ { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, 34374+ & ifmt_lf_add_d, { 0xc8000013 } 34375+ }, 34376+/* lf.rem.s $rDSF,$rASF,$rBSF */ 34377+ { 34378+ { 0, 0, 0, 0 }, 34379+ { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, 34380+ & ifmt_lf_add_s, { 0xc8000006 } 34381+ }, 34382+/* lf.rem.d $rDDF,$rADF,$rBDF */ 34383+ { 34384+ { 0, 0, 0, 0 }, 34385+ { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, 34386+ & ifmt_lf_add_d, { 0xc8000016 } 34387+ }, 34388+/* lf.itof.s $rDSF,$rA */ 34389+ { 34390+ { 0, 0, 0, 0 }, 34391+ { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } }, 34392+ & ifmt_lf_itof_s, { 0xc8000004 } 34393+ }, 34394+/* lf.itof.d $rDSF,$rA */ 34395+ { 34396+ { 0, 0, 0, 0 }, 34397+ { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } }, 34398+ & ifmt_lf_itof_s, { 0xc8000014 } 34399+ }, 34400+/* lf.ftoi.s $rD,$rASF */ 34401+ { 34402+ { 0, 0, 0, 0 }, 34403+ { { MNEM, ' ', OP (RD), ',', OP (RASF), 0 } }, 34404+ & ifmt_lf_ftoi_s, { 0xc8000005 } 34405+ }, 34406+/* lf.ftoi.d $rD,$rADF */ 34407+ { 34408+ { 0, 0, 0, 0 }, 34409+ { { MNEM, ' ', OP (RD), ',', OP (RADF), 0 } }, 34410+ & ifmt_lf_ftoi_d, { 0xc8000015 } 34411+ }, 34412+/* lf.sfeq.s $rASF,$rBSF */ 34413+ { 34414+ { 0, 0, 0, 0 }, 34415+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34416+ & ifmt_lf_eq_s, { 0xc8000008 } 34417+ }, 34418+/* lf.sfeq.d $rASF,$rBSF */ 34419+ { 34420+ { 0, 0, 0, 0 }, 34421+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34422+ & ifmt_lf_eq_s, { 0xc8000018 } 34423+ }, 34424+/* lf.sfne.s $rASF,$rBSF */ 34425+ { 34426+ { 0, 0, 0, 0 }, 34427+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34428+ & ifmt_lf_eq_s, { 0xc8000009 } 34429+ }, 34430+/* lf.sfne.d $rASF,$rBSF */ 34431+ { 34432+ { 0, 0, 0, 0 }, 34433+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34434+ & ifmt_lf_eq_s, { 0xc8000019 } 34435+ }, 34436+/* lf.sfge.s $rASF,$rBSF */ 34437+ { 34438+ { 0, 0, 0, 0 }, 34439+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34440+ & ifmt_lf_eq_s, { 0xc800000b } 34441+ }, 34442+/* lf.sfge.d $rASF,$rBSF */ 34443+ { 34444+ { 0, 0, 0, 0 }, 34445+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34446+ & ifmt_lf_eq_s, { 0xc800001b } 34447+ }, 34448+/* lf.sfgt.s $rASF,$rBSF */ 34449+ { 34450+ { 0, 0, 0, 0 }, 34451+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34452+ & ifmt_lf_eq_s, { 0xc800000a } 34453+ }, 34454+/* lf.sfgt.d $rASF,$rBSF */ 34455+ { 34456+ { 0, 0, 0, 0 }, 34457+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34458+ & ifmt_lf_eq_s, { 0xc800001a } 34459+ }, 34460+/* lf.sflt.s $rASF,$rBSF */ 34461+ { 34462+ { 0, 0, 0, 0 }, 34463+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34464+ & ifmt_lf_eq_s, { 0xc800000c } 34465+ }, 34466+/* lf.sflt.d $rASF,$rBSF */ 34467+ { 34468+ { 0, 0, 0, 0 }, 34469+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34470+ & ifmt_lf_eq_s, { 0xc800001c } 34471+ }, 34472+/* lf.sfle.s $rASF,$rBSF */ 34473+ { 34474+ { 0, 0, 0, 0 }, 34475+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34476+ & ifmt_lf_eq_s, { 0xc800000d } 34477+ }, 34478+/* lf.sfle.d $rASF,$rBSF */ 34479+ { 34480+ { 0, 0, 0, 0 }, 34481+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34482+ & ifmt_lf_eq_s, { 0xc800001d } 34483+ }, 34484+/* lf.madd.s $rDSF,$rASF,$rBSF */ 34485+ { 34486+ { 0, 0, 0, 0 }, 34487+ { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, 34488+ & ifmt_lf_add_s, { 0xc8000007 } 34489+ }, 34490+/* lf.madd.d $rDDF,$rADF,$rBDF */ 34491+ { 34492+ { 0, 0, 0, 0 }, 34493+ { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, 34494+ & ifmt_lf_add_d, { 0xc8000017 } 34495+ }, 34496+/* lf.cust1.s $rASF,$rBSF */ 34497+ { 34498+ { 0, 0, 0, 0 }, 34499+ { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, 34500+ & ifmt_lf_cust1_s, { 0xc80000d0 } 34501+ }, 34502+/* lf.cust1.d */ 34503+ { 34504+ { 0, 0, 0, 0 }, 34505+ { { MNEM, 0 } }, 34506+ & ifmt_lf_cust1_d, { 0xc80000e0 } 34507+ }, 34508+}; 34509+ 34510+#undef A 34511+#undef OPERAND 34512+#undef MNEM 34513+#undef OP 34514+ 34515+/* Formats for ALIAS macro-insns. */ 34516+ 34517+#define F(f) & or1k_cgen_ifld_table[OR1K_##f] 34518+#undef F 34519+ 34520+/* Each non-simple macro entry points to an array of expansion possibilities. */ 34521+ 34522+#define A(a) (1 << CGEN_INSN_##a) 34523+#define OPERAND(op) OR1K_OPERAND_##op 34524+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 34525+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 34526+ 34527+/* The macro instruction table. */ 34528+ 34529+static const CGEN_IBASE or1k_cgen_macro_insn_table[] = 34530+{ 34531+}; 34532+ 34533+/* The macro instruction opcode table. */ 34534+ 34535+static const CGEN_OPCODE or1k_cgen_macro_insn_opcode_table[] = 34536+{ 34537+}; 34538+ 34539+#undef A 34540+#undef OPERAND 34541+#undef MNEM 34542+#undef OP 34543+ 34544+#ifndef CGEN_ASM_HASH_P 34545+#define CGEN_ASM_HASH_P(insn) 1 34546+#endif 34547+ 34548+#ifndef CGEN_DIS_HASH_P 34549+#define CGEN_DIS_HASH_P(insn) 1 34550+#endif 34551+ 34552+/* Return non-zero if INSN is to be added to the hash table. 34553+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ 34554+ 34555+static int 34556+asm_hash_insn_p (insn) 34557+ const CGEN_INSN *insn ATTRIBUTE_UNUSED; 34558+{ 34559+ return CGEN_ASM_HASH_P (insn); 34560+} 34561+ 34562+static int 34563+dis_hash_insn_p (insn) 34564+ const CGEN_INSN *insn; 34565+{ 34566+ /* If building the hash table and the NO-DIS attribute is present, 34567+ ignore. */ 34568+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) 34569+ return 0; 34570+ return CGEN_DIS_HASH_P (insn); 34571+} 34572+ 34573+#ifndef CGEN_ASM_HASH 34574+#define CGEN_ASM_HASH_SIZE 127 34575+#ifdef CGEN_MNEMONIC_OPERANDS 34576+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) 34577+#else 34578+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ 34579+#endif 34580+#endif 34581+ 34582+/* It doesn't make much sense to provide a default here, 34583+ but while this is under development we do. 34584+ BUFFER is a pointer to the bytes of the insn, target order. 34585+ VALUE is the first base_insn_bitsize bits as an int in host order. */ 34586+ 34587+#ifndef CGEN_DIS_HASH 34588+#define CGEN_DIS_HASH_SIZE 256 34589+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) 34590+#endif 34591+ 34592+/* The result is the hash value of the insn. 34593+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ 34594+ 34595+static unsigned int 34596+asm_hash_insn (mnem) 34597+ const char * mnem; 34598+{ 34599+ return CGEN_ASM_HASH (mnem); 34600+} 34601+ 34602+/* BUF is a pointer to the bytes of the insn, target order. 34603+ VALUE is the first base_insn_bitsize bits as an int in host order. */ 34604+ 34605+static unsigned int 34606+dis_hash_insn (buf, value) 34607+ const char * buf ATTRIBUTE_UNUSED; 34608+ CGEN_INSN_INT value ATTRIBUTE_UNUSED; 34609+{ 34610+ return CGEN_DIS_HASH (buf, value); 34611+} 34612+ 34613+/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ 34614+ 34615+static void 34616+set_fields_bitsize (CGEN_FIELDS *fields, int size) 34617+{ 34618+ CGEN_FIELDS_BITSIZE (fields) = size; 34619+} 34620+ 34621+/* Function to call before using the operand instance table. 34622+ This plugs the opcode entries and macro instructions into the cpu table. */ 34623+ 34624+void 34625+or1k_cgen_init_opcode_table (CGEN_CPU_DESC cd) 34626+{ 34627+ int i; 34628+ int num_macros = (sizeof (or1k_cgen_macro_insn_table) / 34629+ sizeof (or1k_cgen_macro_insn_table[0])); 34630+ const CGEN_IBASE *ib = & or1k_cgen_macro_insn_table[0]; 34631+ const CGEN_OPCODE *oc = & or1k_cgen_macro_insn_opcode_table[0]; 34632+ CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); 34633+ 34634+ /* This test has been added to avoid a warning generated 34635+ if memset is called with a third argument of value zero. */ 34636+ if (num_macros >= 1) 34637+ memset (insns, 0, num_macros * sizeof (CGEN_INSN)); 34638+ for (i = 0; i < num_macros; ++i) 34639+ { 34640+ insns[i].base = &ib[i]; 34641+ insns[i].opcode = &oc[i]; 34642+ or1k_cgen_build_insn_regex (& insns[i]); 34643+ } 34644+ cd->macro_insn_table.init_entries = insns; 34645+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); 34646+ cd->macro_insn_table.num_init_entries = num_macros; 34647+ 34648+ oc = & or1k_cgen_insn_opcode_table[0]; 34649+ insns = (CGEN_INSN *) cd->insn_table.init_entries; 34650+ for (i = 0; i < MAX_INSNS; ++i) 34651+ { 34652+ insns[i].opcode = &oc[i]; 34653+ or1k_cgen_build_insn_regex (& insns[i]); 34654+ } 34655+ 34656+ cd->sizeof_fields = sizeof (CGEN_FIELDS); 34657+ cd->set_fields_bitsize = set_fields_bitsize; 34658+ 34659+ cd->asm_hash_p = asm_hash_insn_p; 34660+ cd->asm_hash = asm_hash_insn; 34661+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE; 34662+ 34663+ cd->dis_hash_p = dis_hash_insn_p; 34664+ cd->dis_hash = dis_hash_insn; 34665+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE; 34666+} 34667diff -rNU3 dist.orig/opcodes/or1k-opc.h dist/opcodes/or1k-opc.h 34668--- dist.orig/opcodes/or1k-opc.h 1970-01-01 01:00:00.000000000 +0100 34669+++ dist/opcodes/or1k-opc.h 2015-10-18 13:11:20.000000000 +0200 34670@@ -0,0 +1,135 @@ 34671+/* Instruction opcode header for or1k. 34672+ 34673+THIS FILE IS MACHINE GENERATED WITH CGEN. 34674+ 34675+Copyright (C) 1996-2014 Free Software Foundation, Inc. 34676+ 34677+This file is part of the GNU Binutils and/or GDB, the GNU debugger. 34678+ 34679+ This file is free software; you can redistribute it and/or modify 34680+ it under the terms of the GNU General Public License as published by 34681+ the Free Software Foundation; either version 3, or (at your option) 34682+ any later version. 34683+ 34684+ It is distributed in the hope that it will be useful, but WITHOUT 34685+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 34686+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 34687+ License for more details. 34688+ 34689+ You should have received a copy of the GNU General Public License along 34690+ with this program; if not, write to the Free Software Foundation, Inc., 34691+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 34692+ 34693+*/ 34694+ 34695+#ifndef OR1K_OPC_H 34696+#define OR1K_OPC_H 34697+ 34698+/* -- opc.h */ 34699+ 34700+#undef CGEN_DIS_HASH_SIZE 34701+#define CGEN_DIS_HASH_SIZE 256 34702+#undef CGEN_DIS_HASH 34703+#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) 34704+ 34705+/* -- */ 34706+/* Enum declaration for or1k instruction types. */ 34707+typedef enum cgen_insn_type { 34708+ OR1K_INSN_INVALID, OR1K_INSN_L_J, OR1K_INSN_L_JAL, OR1K_INSN_L_JR 34709+ , OR1K_INSN_L_JALR, OR1K_INSN_L_BNF, OR1K_INSN_L_BF, OR1K_INSN_L_TRAP 34710+ , OR1K_INSN_L_SYS, OR1K_INSN_L_MSYNC, OR1K_INSN_L_PSYNC, OR1K_INSN_L_CSYNC 34711+ , OR1K_INSN_L_RFE, OR1K_INSN_L_NOP_IMM, OR1K_INSN_L_NOP, OR1K_INSN_L_MOVHI 34712+ , OR1K_INSN_L_MACRC, OR1K_INSN_L_MFSPR, OR1K_INSN_L_MTSPR, OR1K_INSN_L_LWZ 34713+ , OR1K_INSN_L_LWS, OR1K_INSN_L_LWA, OR1K_INSN_L_LBZ, OR1K_INSN_L_LBS 34714+ , OR1K_INSN_L_LHZ, OR1K_INSN_L_LHS, OR1K_INSN_L_SW, OR1K_INSN_L_SB 34715+ , OR1K_INSN_L_SH, OR1K_INSN_L_SWA, OR1K_INSN_L_SLL, OR1K_INSN_L_SLLI 34716+ , OR1K_INSN_L_SRL, OR1K_INSN_L_SRLI, OR1K_INSN_L_SRA, OR1K_INSN_L_SRAI 34717+ , OR1K_INSN_L_ROR, OR1K_INSN_L_RORI, OR1K_INSN_L_AND, OR1K_INSN_L_OR 34718+ , OR1K_INSN_L_XOR, OR1K_INSN_L_ADD, OR1K_INSN_L_SUB, OR1K_INSN_L_ADDC 34719+ , OR1K_INSN_L_MUL, OR1K_INSN_L_MULU, OR1K_INSN_L_DIV, OR1K_INSN_L_DIVU 34720+ , OR1K_INSN_L_FF1, OR1K_INSN_L_FL1, OR1K_INSN_L_ANDI, OR1K_INSN_L_ORI 34721+ , OR1K_INSN_L_XORI, OR1K_INSN_L_ADDI, OR1K_INSN_L_ADDIC, OR1K_INSN_L_MULI 34722+ , OR1K_INSN_L_EXTHS, OR1K_INSN_L_EXTBS, OR1K_INSN_L_EXTHZ, OR1K_INSN_L_EXTBZ 34723+ , OR1K_INSN_L_EXTWS, OR1K_INSN_L_EXTWZ, OR1K_INSN_L_CMOV, OR1K_INSN_L_SFGTS 34724+ , OR1K_INSN_L_SFGTSI, OR1K_INSN_L_SFGTU, OR1K_INSN_L_SFGTUI, OR1K_INSN_L_SFGES 34725+ , OR1K_INSN_L_SFGESI, OR1K_INSN_L_SFGEU, OR1K_INSN_L_SFGEUI, OR1K_INSN_L_SFLTS 34726+ , OR1K_INSN_L_SFLTSI, OR1K_INSN_L_SFLTU, OR1K_INSN_L_SFLTUI, OR1K_INSN_L_SFLES 34727+ , OR1K_INSN_L_SFLESI, OR1K_INSN_L_SFLEU, OR1K_INSN_L_SFLEUI, OR1K_INSN_L_SFEQ 34728+ , OR1K_INSN_L_SFEQI, OR1K_INSN_L_SFNE, OR1K_INSN_L_SFNEI, OR1K_INSN_L_MAC 34729+ , OR1K_INSN_L_MSB, OR1K_INSN_L_MACI, OR1K_INSN_L_CUST1, OR1K_INSN_L_CUST2 34730+ , OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5, OR1K_INSN_L_CUST6 34731+ , OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S, OR1K_INSN_LF_ADD_D 34732+ , OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D 34733+ , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S, OR1K_INSN_LF_REM_D 34734+ , OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D 34735+ , OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S, OR1K_INSN_LF_NE_D 34736+ , OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S, OR1K_INSN_LF_GT_D 34737+ , OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S, OR1K_INSN_LF_LE_D 34738+ , OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D 34739+} CGEN_INSN_TYPE; 34740+ 34741+/* Index of `invalid' insn place holder. */ 34742+#define CGEN_INSN_INVALID OR1K_INSN_INVALID 34743+ 34744+/* Total number of insns in table. */ 34745+#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D + 1) 34746+ 34747+/* This struct records data prior to insertion or after extraction. */ 34748+struct cgen_fields 34749+{ 34750+ int length; 34751+ long f_nil; 34752+ long f_anyof; 34753+ long f_opcode; 34754+ long f_r1; 34755+ long f_r2; 34756+ long f_r3; 34757+ long f_op_25_2; 34758+ long f_op_25_5; 34759+ long f_op_16_1; 34760+ long f_op_7_4; 34761+ long f_op_3_4; 34762+ long f_op_9_2; 34763+ long f_op_9_4; 34764+ long f_op_7_8; 34765+ long f_op_7_2; 34766+ long f_resv_25_26; 34767+ long f_resv_25_10; 34768+ long f_resv_25_5; 34769+ long f_resv_23_8; 34770+ long f_resv_20_21; 34771+ long f_resv_20_5; 34772+ long f_resv_20_4; 34773+ long f_resv_15_8; 34774+ long f_resv_15_6; 34775+ long f_resv_10_11; 34776+ long f_resv_10_7; 34777+ long f_resv_10_3; 34778+ long f_resv_10_1; 34779+ long f_resv_7_4; 34780+ long f_resv_5_2; 34781+ long f_imm16_25_5; 34782+ long f_imm16_10_11; 34783+ long f_disp26; 34784+ long f_uimm16; 34785+ long f_simm16; 34786+ long f_uimm6; 34787+ long f_uimm16_split; 34788+ long f_simm16_split; 34789+}; 34790+ 34791+#define CGEN_INIT_PARSE(od) \ 34792+{\ 34793+} 34794+#define CGEN_INIT_INSERT(od) \ 34795+{\ 34796+} 34797+#define CGEN_INIT_EXTRACT(od) \ 34798+{\ 34799+} 34800+#define CGEN_INIT_PRINT(od) \ 34801+{\ 34802+} 34803+ 34804+ 34805+#endif /* OR1K_OPC_H */ 34806diff -rNU3 dist.orig/opcodes/or1k-opinst.c dist/opcodes/or1k-opinst.c 34807--- dist.orig/opcodes/or1k-opinst.c 1970-01-01 01:00:00.000000000 +0100 34808+++ dist/opcodes/or1k-opinst.c 2015-10-18 13:11:20.000000000 +0200 34809@@ -0,0 +1,590 @@ 34810+/* Semantic operand instances for or1k. 34811+ 34812+THIS FILE IS MACHINE GENERATED WITH CGEN. 34813+ 34814+Copyright (C) 1996-2014 Free Software Foundation, Inc. 34815+ 34816+This file is part of the GNU Binutils and/or GDB, the GNU debugger. 34817+ 34818+ This file is free software; you can redistribute it and/or modify 34819+ it under the terms of the GNU General Public License as published by 34820+ the Free Software Foundation; either version 3, or (at your option) 34821+ any later version. 34822+ 34823+ It is distributed in the hope that it will be useful, but WITHOUT 34824+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 34825+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 34826+ License for more details. 34827+ 34828+ You should have received a copy of the GNU General Public License along 34829+ with this program; if not, write to the Free Software Foundation, Inc., 34830+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 34831+ 34832+*/ 34833+ 34834+#include "sysdep.h" 34835+#include "ansidecl.h" 34836+#include "bfd.h" 34837+#include "symcat.h" 34838+#include "or1k-desc.h" 34839+#include "or1k-opc.h" 34840+ 34841+/* Operand references. */ 34842+ 34843+#define OP_ENT(op) OR1K_OPERAND_##op 34844+#define INPUT CGEN_OPINST_INPUT 34845+#define OUTPUT CGEN_OPINST_OUTPUT 34846+#define END CGEN_OPINST_END 34847+#define COND_REF CGEN_OPINST_COND_REF 34848+ 34849+static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = { 34850+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34851+}; 34852+ 34853+static const CGEN_OPINST sfmt_l_j_ops[] ATTRIBUTE_UNUSED = { 34854+ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 }, 34855+ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, 34856+ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, 34857+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34858+}; 34859+ 34860+static const CGEN_OPINST sfmt_l_jal_ops[] ATTRIBUTE_UNUSED = { 34861+ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 }, 34862+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, 34863+ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, 34864+ { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 }, 34865+ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, 34866+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34867+}; 34868+ 34869+static const CGEN_OPINST sfmt_l_jr_ops[] ATTRIBUTE_UNUSED = { 34870+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 34871+ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, 34872+ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, 34873+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34874+}; 34875+ 34876+static const CGEN_OPINST sfmt_l_jalr_ops[] ATTRIBUTE_UNUSED = { 34877+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, 34878+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 34879+ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, 34880+ { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 }, 34881+ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, 34882+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34883+}; 34884+ 34885+static const CGEN_OPINST sfmt_l_bnf_ops[] ATTRIBUTE_UNUSED = { 34886+ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, COND_REF }, 34887+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, 34888+ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, COND_REF }, 34889+ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 34890+ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, 34891+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34892+}; 34893+ 34894+static const CGEN_OPINST sfmt_l_trap_ops[] ATTRIBUTE_UNUSED = { 34895+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, 34896+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34897+}; 34898+ 34899+static const CGEN_OPINST sfmt_l_msync_ops[] ATTRIBUTE_UNUSED = { 34900+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34901+}; 34902+ 34903+static const CGEN_OPINST sfmt_l_nop_imm_ops[] ATTRIBUTE_UNUSED = { 34904+ { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, 34905+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34906+}; 34907+ 34908+static const CGEN_OPINST sfmt_l_movhi_ops[] ATTRIBUTE_UNUSED = { 34909+ { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, 34910+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34911+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34912+}; 34913+ 34914+static const CGEN_OPINST sfmt_l_macrc_ops[] ATTRIBUTE_UNUSED = { 34915+ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, 34916+ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, 34917+ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, 34918+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34919+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34920+}; 34921+ 34922+static const CGEN_OPINST sfmt_l_mfspr_ops[] ATTRIBUTE_UNUSED = { 34923+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34924+ { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, 34925+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34926+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34927+}; 34928+ 34929+static const CGEN_OPINST sfmt_l_mtspr_ops[] ATTRIBUTE_UNUSED = { 34930+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34931+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 34932+ { INPUT, "uimm16_split", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16_SPLIT), 0, 0 }, 34933+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34934+}; 34935+ 34936+static const CGEN_OPINST sfmt_l_lwz_ops[] ATTRIBUTE_UNUSED = { 34937+ { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, 34938+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34939+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 34940+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34941+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34942+}; 34943+ 34944+static const CGEN_OPINST sfmt_l_lws_ops[] ATTRIBUTE_UNUSED = { 34945+ { INPUT, "h_memory_SI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, 34946+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34947+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 34948+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34949+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34950+}; 34951+ 34952+static const CGEN_OPINST sfmt_l_lwa_ops[] ATTRIBUTE_UNUSED = { 34953+ { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, 34954+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34955+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 34956+ { OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, 34957+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, 34958+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34959+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34960+}; 34961+ 34962+static const CGEN_OPINST sfmt_l_lbz_ops[] ATTRIBUTE_UNUSED = { 34963+ { INPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 }, 34964+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34965+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 34966+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34967+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34968+}; 34969+ 34970+static const CGEN_OPINST sfmt_l_lbs_ops[] ATTRIBUTE_UNUSED = { 34971+ { INPUT, "h_memory_QI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, 34972+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34973+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 34974+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34975+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34976+}; 34977+ 34978+static const CGEN_OPINST sfmt_l_lhz_ops[] ATTRIBUTE_UNUSED = { 34979+ { INPUT, "h_memory_UHI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 }, 34980+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34981+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 34982+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34983+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34984+}; 34985+ 34986+static const CGEN_OPINST sfmt_l_lhs_ops[] ATTRIBUTE_UNUSED = { 34987+ { INPUT, "h_memory_HI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, 34988+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34989+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 34990+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 34991+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 34992+}; 34993+ 34994+static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = { 34995+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, 34996+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 34997+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 34998+ { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, 34999+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, 35000+ { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, 35001+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35002+}; 35003+ 35004+static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = { 35005+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, 35006+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35007+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35008+ { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, 35009+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, 35010+ { OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 }, 35011+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35012+}; 35013+ 35014+static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = { 35015+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, 35016+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35017+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35018+ { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, 35019+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, 35020+ { OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 }, 35021+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35022+}; 35023+ 35024+static const CGEN_OPINST sfmt_l_swa_ops[] ATTRIBUTE_UNUSED = { 35025+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, 35026+ { INPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, 35027+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35028+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF }, 35029+ { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, 35030+ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 35031+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, 35032+ { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF }, 35033+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 35034+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35035+}; 35036+ 35037+static const CGEN_OPINST sfmt_l_sll_ops[] ATTRIBUTE_UNUSED = { 35038+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35039+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35040+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35041+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35042+}; 35043+ 35044+static const CGEN_OPINST sfmt_l_slli_ops[] ATTRIBUTE_UNUSED = { 35045+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35046+ { INPUT, "uimm6", HW_H_UIMM6, CGEN_MODE_UINT, OP_ENT (UIMM6), 0, 0 }, 35047+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35048+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35049+}; 35050+ 35051+static const CGEN_OPINST sfmt_l_and_ops[] ATTRIBUTE_UNUSED = { 35052+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35053+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35054+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35055+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35056+}; 35057+ 35058+static const CGEN_OPINST sfmt_l_add_ops[] ATTRIBUTE_UNUSED = { 35059+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, 35060+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35061+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35062+ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35063+ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, 35064+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35065+ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, 35066+ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35067+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35068+}; 35069+ 35070+static const CGEN_OPINST sfmt_l_addc_ops[] ATTRIBUTE_UNUSED = { 35071+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, 35072+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35073+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35074+ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, 35075+ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35076+ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, 35077+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35078+ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, 35079+ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35080+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35081+}; 35082+ 35083+static const CGEN_OPINST sfmt_l_div_ops[] ATTRIBUTE_UNUSED = { 35084+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, 35085+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, 35086+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35087+ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, 35088+ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, 35089+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, 35090+ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, COND_REF }, 35091+ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35092+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35093+}; 35094+ 35095+static const CGEN_OPINST sfmt_l_ff1_ops[] ATTRIBUTE_UNUSED = { 35096+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35097+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35098+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35099+}; 35100+ 35101+static const CGEN_OPINST sfmt_l_xori_ops[] ATTRIBUTE_UNUSED = { 35102+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35103+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 35104+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35105+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35106+}; 35107+ 35108+static const CGEN_OPINST sfmt_l_addi_ops[] ATTRIBUTE_UNUSED = { 35109+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, 35110+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35111+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 35112+ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35113+ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, 35114+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35115+ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, 35116+ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35117+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35118+}; 35119+ 35120+static const CGEN_OPINST sfmt_l_addic_ops[] ATTRIBUTE_UNUSED = { 35121+ { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, 35122+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35123+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 35124+ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, 35125+ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35126+ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, 35127+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35128+ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, 35129+ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, 35130+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35131+}; 35132+ 35133+static const CGEN_OPINST sfmt_l_exths_ops[] ATTRIBUTE_UNUSED = { 35134+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35135+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35136+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35137+}; 35138+ 35139+static const CGEN_OPINST sfmt_l_cmov_ops[] ATTRIBUTE_UNUSED = { 35140+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, 35141+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF }, 35142+ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 35143+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, 35144+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35145+}; 35146+ 35147+static const CGEN_OPINST sfmt_l_sfgts_ops[] ATTRIBUTE_UNUSED = { 35148+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35149+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35150+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 35151+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35152+}; 35153+ 35154+static const CGEN_OPINST sfmt_l_sfgtsi_ops[] ATTRIBUTE_UNUSED = { 35155+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35156+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 35157+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 35158+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35159+}; 35160+ 35161+static const CGEN_OPINST sfmt_l_mac_ops[] ATTRIBUTE_UNUSED = { 35162+ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, 35163+ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, 35164+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35165+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 35166+ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, 35167+ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, 35168+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35169+}; 35170+ 35171+static const CGEN_OPINST sfmt_l_maci_ops[] ATTRIBUTE_UNUSED = { 35172+ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, 35173+ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, 35174+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35175+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, 35176+ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, 35177+ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, 35178+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35179+}; 35180+ 35181+static const CGEN_OPINST sfmt_lf_add_s_ops[] ATTRIBUTE_UNUSED = { 35182+ { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, 35183+ { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, 35184+ { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 }, 35185+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35186+}; 35187+ 35188+static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = { 35189+ { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, 35190+ { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, 35191+ { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, 35192+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35193+}; 35194+ 35195+static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = { 35196+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35197+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, 35198+ { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 }, 35199+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35200+}; 35201+ 35202+static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = { 35203+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 35204+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, 35205+ { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, 35206+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35207+}; 35208+ 35209+static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = { 35210+ { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, 35211+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, 35212+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35213+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35214+}; 35215+ 35216+static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = { 35217+ { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, 35218+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, 35219+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 35220+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35221+}; 35222+ 35223+static const CGEN_OPINST sfmt_lf_eq_s_ops[] ATTRIBUTE_UNUSED = { 35224+ { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, 35225+ { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, 35226+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 35227+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35228+}; 35229+ 35230+static const CGEN_OPINST sfmt_lf_eq_d_ops[] ATTRIBUTE_UNUSED = { 35231+ { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, 35232+ { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, 35233+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, 35234+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35235+}; 35236+ 35237+static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = { 35238+ { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, 35239+ { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, 35240+ { INPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 }, 35241+ { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 }, 35242+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35243+}; 35244+ 35245+static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = { 35246+ { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, 35247+ { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, 35248+ { INPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, 35249+ { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, 35250+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } 35251+}; 35252+ 35253+#undef OP_ENT 35254+#undef INPUT 35255+#undef OUTPUT 35256+#undef END 35257+#undef COND_REF 35258+ 35259+/* Operand instance lookup table. */ 35260+ 35261+static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = { 35262+ 0, 35263+ & sfmt_l_j_ops[0], 35264+ & sfmt_l_jal_ops[0], 35265+ & sfmt_l_jr_ops[0], 35266+ & sfmt_l_jalr_ops[0], 35267+ & sfmt_l_bnf_ops[0], 35268+ & sfmt_l_bnf_ops[0], 35269+ & sfmt_l_trap_ops[0], 35270+ & sfmt_l_trap_ops[0], 35271+ & sfmt_l_msync_ops[0], 35272+ & sfmt_l_msync_ops[0], 35273+ & sfmt_l_msync_ops[0], 35274+ & sfmt_l_msync_ops[0], 35275+ & sfmt_l_nop_imm_ops[0], 35276+ & sfmt_l_msync_ops[0], 35277+ & sfmt_l_movhi_ops[0], 35278+ & sfmt_l_macrc_ops[0], 35279+ & sfmt_l_mfspr_ops[0], 35280+ & sfmt_l_mtspr_ops[0], 35281+ & sfmt_l_lwz_ops[0], 35282+ & sfmt_l_lws_ops[0], 35283+ & sfmt_l_lwa_ops[0], 35284+ & sfmt_l_lbz_ops[0], 35285+ & sfmt_l_lbs_ops[0], 35286+ & sfmt_l_lhz_ops[0], 35287+ & sfmt_l_lhs_ops[0], 35288+ & sfmt_l_sw_ops[0], 35289+ & sfmt_l_sb_ops[0], 35290+ & sfmt_l_sh_ops[0], 35291+ & sfmt_l_swa_ops[0], 35292+ & sfmt_l_sll_ops[0], 35293+ & sfmt_l_slli_ops[0], 35294+ & sfmt_l_sll_ops[0], 35295+ & sfmt_l_slli_ops[0], 35296+ & sfmt_l_sll_ops[0], 35297+ & sfmt_l_slli_ops[0], 35298+ & sfmt_l_sll_ops[0], 35299+ & sfmt_l_slli_ops[0], 35300+ & sfmt_l_and_ops[0], 35301+ & sfmt_l_and_ops[0], 35302+ & sfmt_l_and_ops[0], 35303+ & sfmt_l_add_ops[0], 35304+ & sfmt_l_add_ops[0], 35305+ & sfmt_l_addc_ops[0], 35306+ & sfmt_l_add_ops[0], 35307+ & sfmt_l_add_ops[0], 35308+ & sfmt_l_div_ops[0], 35309+ & sfmt_l_div_ops[0], 35310+ & sfmt_l_ff1_ops[0], 35311+ & sfmt_l_ff1_ops[0], 35312+ & sfmt_l_mfspr_ops[0], 35313+ & sfmt_l_mfspr_ops[0], 35314+ & sfmt_l_xori_ops[0], 35315+ & sfmt_l_addi_ops[0], 35316+ & sfmt_l_addic_ops[0], 35317+ & sfmt_l_addi_ops[0], 35318+ & sfmt_l_exths_ops[0], 35319+ & sfmt_l_exths_ops[0], 35320+ & sfmt_l_exths_ops[0], 35321+ & sfmt_l_exths_ops[0], 35322+ & sfmt_l_exths_ops[0], 35323+ & sfmt_l_exths_ops[0], 35324+ & sfmt_l_cmov_ops[0], 35325+ & sfmt_l_sfgts_ops[0], 35326+ & sfmt_l_sfgtsi_ops[0], 35327+ & sfmt_l_sfgts_ops[0], 35328+ & sfmt_l_sfgtsi_ops[0], 35329+ & sfmt_l_sfgts_ops[0], 35330+ & sfmt_l_sfgtsi_ops[0], 35331+ & sfmt_l_sfgts_ops[0], 35332+ & sfmt_l_sfgtsi_ops[0], 35333+ & sfmt_l_sfgts_ops[0], 35334+ & sfmt_l_sfgtsi_ops[0], 35335+ & sfmt_l_sfgts_ops[0], 35336+ & sfmt_l_sfgtsi_ops[0], 35337+ & sfmt_l_sfgts_ops[0], 35338+ & sfmt_l_sfgtsi_ops[0], 35339+ & sfmt_l_sfgts_ops[0], 35340+ & sfmt_l_sfgtsi_ops[0], 35341+ & sfmt_l_sfgts_ops[0], 35342+ & sfmt_l_sfgtsi_ops[0], 35343+ & sfmt_l_sfgts_ops[0], 35344+ & sfmt_l_sfgtsi_ops[0], 35345+ & sfmt_l_mac_ops[0], 35346+ & sfmt_l_mac_ops[0], 35347+ & sfmt_l_maci_ops[0], 35348+ & sfmt_l_msync_ops[0], 35349+ & sfmt_l_msync_ops[0], 35350+ & sfmt_l_msync_ops[0], 35351+ & sfmt_l_msync_ops[0], 35352+ & sfmt_l_msync_ops[0], 35353+ & sfmt_l_msync_ops[0], 35354+ & sfmt_l_msync_ops[0], 35355+ & sfmt_l_msync_ops[0], 35356+ & sfmt_lf_add_s_ops[0], 35357+ & sfmt_lf_add_d_ops[0], 35358+ & sfmt_lf_add_s_ops[0], 35359+ & sfmt_lf_add_d_ops[0], 35360+ & sfmt_lf_add_s_ops[0], 35361+ & sfmt_lf_add_d_ops[0], 35362+ & sfmt_lf_add_s_ops[0], 35363+ & sfmt_lf_add_d_ops[0], 35364+ & sfmt_lf_add_s_ops[0], 35365+ & sfmt_lf_add_d_ops[0], 35366+ & sfmt_lf_itof_s_ops[0], 35367+ & sfmt_lf_itof_d_ops[0], 35368+ & sfmt_lf_ftoi_s_ops[0], 35369+ & sfmt_lf_ftoi_d_ops[0], 35370+ & sfmt_lf_eq_s_ops[0], 35371+ & sfmt_lf_eq_d_ops[0], 35372+ & sfmt_lf_eq_s_ops[0], 35373+ & sfmt_lf_eq_d_ops[0], 35374+ & sfmt_lf_eq_s_ops[0], 35375+ & sfmt_lf_eq_d_ops[0], 35376+ & sfmt_lf_eq_s_ops[0], 35377+ & sfmt_lf_eq_d_ops[0], 35378+ & sfmt_lf_eq_s_ops[0], 35379+ & sfmt_lf_eq_d_ops[0], 35380+ & sfmt_lf_eq_s_ops[0], 35381+ & sfmt_lf_eq_d_ops[0], 35382+ & sfmt_lf_madd_s_ops[0], 35383+ & sfmt_lf_madd_d_ops[0], 35384+ & sfmt_l_msync_ops[0], 35385+ & sfmt_l_msync_ops[0], 35386+}; 35387+ 35388+/* Function to call before using the operand instance table. */ 35389+ 35390+void 35391+or1k_cgen_init_opinst_table (cd) 35392+ CGEN_CPU_DESC cd; 35393+{ 35394+ int i; 35395+ const CGEN_OPINST **oi = & or1k_cgen_opinst_table[0]; 35396+ CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries; 35397+ for (i = 0; i < MAX_INSNS; ++i) 35398+ insns[i].opinst = oi[i]; 35399+} 35400diff -rNU3 dist.orig/opcodes/or32-dis.c dist/opcodes/or32-dis.c 35401--- dist.orig/opcodes/or32-dis.c 2012-05-18 03:59:38.000000000 +0200 35402+++ dist/opcodes/or32-dis.c 1970-01-01 01:00:00.000000000 +0100 35403@@ -1,325 +0,0 @@ 35404-/* Instruction printing code for the OpenRISC 1000 35405- Copyright (C) 2002, 2005, 2007, 2012 Free Software Foundation, Inc. 35406- Contributed by Damjan Lampret <lampret@opencores.org>. 35407- Modified from a29k port. 35408- 35409- This file is part of the GNU opcodes library. 35410- 35411- This library is free software; you can redistribute it and/or modify 35412- it under the terms of the GNU General Public License as published by 35413- the Free Software Foundation; either version 3, or (at your option) 35414- any later version. 35415- 35416- It is distributed in the hope that it will be useful, but WITHOUT 35417- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 35418- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 35419- License for more details. 35420- 35421- You should have received a copy of the GNU General Public License 35422- along with this program; if not, write to the Free Software 35423- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 35424- MA 02110-1301, USA. */ 35425- 35426-#ifndef DEBUG 35427-#define DEBUG 0 35428-#endif 35429- 35430-#include "sysdep.h" 35431-#include "dis-asm.h" 35432-#include "opcode/or32.h" 35433-#include "safe-ctype.h" 35434- 35435-#define EXTEND29(x) ((x) & (unsigned long) 0x10000000 ? ((x) | (unsigned long) 0xf0000000) : ((x))) 35436- 35437-/* Now find the four bytes of INSN_CH and put them in *INSN. */ 35438- 35439-static void 35440-find_bytes_big (unsigned char *insn_ch, unsigned long *insn) 35441-{ 35442- *insn = 35443- ((unsigned long) insn_ch[0] << 24) + 35444- ((unsigned long) insn_ch[1] << 16) + 35445- ((unsigned long) insn_ch[2] << 8) + 35446- ((unsigned long) insn_ch[3]); 35447-#if DEBUG 35448- printf ("find_bytes_big3: %lx\n", *insn); 35449-#endif 35450-} 35451- 35452-static void 35453-find_bytes_little (unsigned char *insn_ch, unsigned long *insn) 35454-{ 35455- *insn = 35456- ((unsigned long) insn_ch[3] << 24) + 35457- ((unsigned long) insn_ch[2] << 16) + 35458- ((unsigned long) insn_ch[1] << 8) + 35459- ((unsigned long) insn_ch[0]); 35460-} 35461- 35462-typedef void (*find_byte_func_type) (unsigned char *, unsigned long *); 35463- 35464-static unsigned long 35465-or32_extract (char param_ch, char *enc_initial, unsigned long insn) 35466-{ 35467- char *enc; 35468- unsigned long ret = 0; 35469- int opc_pos = 0; 35470- int param_pos = 0; 35471- 35472- for (enc = enc_initial; *enc != '\0'; enc++) 35473- if (*enc == param_ch) 35474- { 35475- if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) 35476- continue; 35477- else 35478- param_pos++; 35479- } 35480- 35481-#if DEBUG 35482- printf ("or32_extract: %c %x ", param_ch, param_pos); 35483-#endif 35484- opc_pos = 32; 35485- 35486- for (enc = enc_initial; *enc != '\0'; ) 35487- if ((*enc == '0') && (*(enc + 1) == 'x')) 35488- { 35489- opc_pos -= 4; 35490- 35491- if ((param_ch == '0') || (param_ch == '1')) 35492- { 35493- unsigned long tmp = strtoul (enc, NULL, 16); 35494-#if DEBUG 35495- printf (" enc=%s, tmp=%lx ", enc, tmp); 35496-#endif 35497- if (param_ch == '0') 35498- tmp = 15 - tmp; 35499- ret |= tmp << opc_pos; 35500- } 35501- enc += 3; 35502- } 35503- else if ((*enc == '0') || (*enc == '1')) 35504- { 35505- opc_pos--; 35506- if (param_ch == *enc) 35507- ret |= 1 << opc_pos; 35508- enc++; 35509- } 35510- else if (*enc == param_ch) 35511- { 35512- opc_pos--; 35513- param_pos--; 35514-#if DEBUG 35515- printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); 35516-#endif 35517- ret += ((insn >> opc_pos) & 0x1) << param_pos; 35518- 35519- if (!param_pos 35520- && letter_signed (param_ch) 35521- && ret >> (letter_range (param_ch) - 1)) 35522- { 35523-#if DEBUG 35524- printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", 35525- ret, opc_pos, param_pos); 35526-#endif 35527- ret |= 0xffffffff << letter_range(param_ch); 35528-#if DEBUG 35529- printf ("\n after conversion to signed: ret=%lx\n", ret); 35530-#endif 35531- } 35532- enc++; 35533- } 35534- else if (ISALPHA (*enc)) 35535- { 35536- opc_pos--; 35537- enc++; 35538- } 35539- else if (*enc == '-') 35540- { 35541- opc_pos--; 35542- enc++; 35543- } 35544- else 35545- enc++; 35546- 35547-#if DEBUG 35548- printf ("ret=%lx\n", ret); 35549-#endif 35550- return ret; 35551-} 35552- 35553-static int 35554-or32_opcode_match (unsigned long insn, char *encoding) 35555-{ 35556- unsigned long ones, zeros; 35557- 35558-#if DEBUG 35559- printf ("or32_opcode_match: %.8lx\n", insn); 35560-#endif 35561- ones = or32_extract ('1', encoding, insn); 35562- zeros = or32_extract ('0', encoding, insn); 35563- 35564-#if DEBUG 35565- printf ("ones: %lx \n", ones); 35566- printf ("zeros: %lx \n", zeros); 35567-#endif 35568- if ((insn & ones) != ones) 35569- { 35570-#if DEBUG 35571- printf ("ret1\n"); 35572-#endif 35573- return 0; 35574- } 35575- 35576- if ((~insn & zeros) != zeros) 35577- { 35578-#if DEBUG 35579- printf ("ret2\n"); 35580-#endif 35581- return 0; 35582- } 35583- 35584-#if DEBUG 35585- printf ("ret3\n"); 35586-#endif 35587- return 1; 35588-} 35589- 35590-/* Print register to INFO->STREAM. Used only by print_insn. */ 35591- 35592-static void 35593-or32_print_register (char param_ch, 35594- char *encoding, 35595- unsigned long insn, 35596- struct disassemble_info *info) 35597-{ 35598- int regnum = or32_extract (param_ch, encoding, insn); 35599- 35600-#if DEBUG 35601- printf ("or32_print_register: %c, %s, %lx\n", param_ch, encoding, insn); 35602-#endif 35603- if (param_ch == 'A') 35604- (*info->fprintf_func) (info->stream, "r%d", regnum); 35605- else if (param_ch == 'B') 35606- (*info->fprintf_func) (info->stream, "r%d", regnum); 35607- else if (param_ch == 'D') 35608- (*info->fprintf_func) (info->stream, "r%d", regnum); 35609- else if (regnum < 16) 35610- (*info->fprintf_func) (info->stream, "r%d", regnum); 35611- else if (regnum < 32) 35612- (*info->fprintf_func) (info->stream, "r%d", regnum-16); 35613- else 35614- (*info->fprintf_func) (info->stream, "X%d", regnum); 35615-} 35616- 35617-/* Print immediate to INFO->STREAM. Used only by print_insn. */ 35618- 35619-static void 35620-or32_print_immediate (char param_ch, 35621- char *encoding, 35622- unsigned long insn, 35623- struct disassemble_info *info) 35624-{ 35625- int imm = or32_extract(param_ch, encoding, insn); 35626- 35627- if (letter_signed(param_ch)) 35628- (*info->fprintf_func) (info->stream, "0x%x", imm); 35629-/* (*info->fprintf_func) (info->stream, "%d", imm); */ 35630- else 35631- (*info->fprintf_func) (info->stream, "0x%x", imm); 35632-} 35633- 35634-/* Print one instruction from MEMADDR on INFO->STREAM. 35635- Return the size of the instruction (always 4 on or32). */ 35636- 35637-static int 35638-print_insn (bfd_vma memaddr, struct disassemble_info *info) 35639-{ 35640- /* The raw instruction. */ 35641- unsigned char insn_ch[4]; 35642- /* Address. Will be sign extened 27-bit. */ 35643- unsigned long addr; 35644- /* The four bytes of the instruction. */ 35645- unsigned long insn; 35646- find_byte_func_type find_byte_func = (find_byte_func_type) info->private_data; 35647- struct or32_opcode const * opcode; 35648- 35649- { 35650- int status = 35651- (*info->read_memory_func) (memaddr, (bfd_byte *) &insn_ch[0], 4, info); 35652- 35653- if (status != 0) 35654- { 35655- (*info->memory_error_func) (status, memaddr, info); 35656- return -1; 35657- } 35658- } 35659- 35660- (*find_byte_func) (&insn_ch[0], &insn); 35661- 35662- for (opcode = &or32_opcodes[0]; 35663- opcode < &or32_opcodes[or32_num_opcodes]; 35664- ++opcode) 35665- { 35666- if (or32_opcode_match (insn, opcode->encoding)) 35667- { 35668- char *s; 35669- 35670- (*info->fprintf_func) (info->stream, "%s ", opcode->name); 35671- 35672- for (s = opcode->args; *s != '\0'; ++s) 35673- { 35674- switch (*s) 35675- { 35676- case '\0': 35677- return 4; 35678- 35679- case 'r': 35680- or32_print_register (*++s, opcode->encoding, insn, info); 35681- break; 35682- 35683- case 'X': 35684- addr = or32_extract ('X', opcode->encoding, insn) << 2; 35685- 35686- /* Calulate the correct address. XXX is this really correct ?? */ 35687- addr = memaddr + EXTEND29 (addr); 35688- 35689- (*info->print_address_func) 35690- (addr, info); 35691- break; 35692- 35693- default: 35694- if (strchr (opcode->encoding, *s)) 35695- or32_print_immediate (*s, opcode->encoding, insn, info); 35696- else 35697- (*info->fprintf_func) (info->stream, "%c", *s); 35698- } 35699- } 35700- 35701- return 4; 35702- } 35703- } 35704- 35705- /* This used to be %8x for binutils. */ 35706- (*info->fprintf_func) 35707- (info->stream, ".word 0x%08lx", insn); 35708- return 4; 35709-} 35710- 35711-/* Disassemble a big-endian or32 instruction. */ 35712- 35713-int 35714-print_insn_big_or32 (bfd_vma memaddr, struct disassemble_info *info) 35715-{ 35716- info->private_data = find_bytes_big; 35717- 35718- return print_insn (memaddr, info); 35719-} 35720- 35721-/* Disassemble a little-endian or32 instruction. */ 35722- 35723-int 35724-print_insn_little_or32 (bfd_vma memaddr, struct disassemble_info *info) 35725-{ 35726- info->private_data = find_bytes_little; 35727- return print_insn (memaddr, info); 35728-} 35729diff -rNU3 dist.orig/opcodes/or32-opc.c dist/opcodes/or32-opc.c 35730--- dist.orig/opcodes/or32-opc.c 2012-05-17 17:13:25.000000000 +0200 35731+++ dist/opcodes/or32-opc.c 1970-01-01 01:00:00.000000000 +0100 35732@@ -1,1031 +0,0 @@ 35733-/* Table of opcodes for the OpenRISC 1000 ISA. 35734- Copyright 2002, 2004, 2005, 2007, 2008, 2009, 2012 35735- Free Software Foundation, Inc. 35736- Contributed by Damjan Lampret (lampret@opencores.org). 35737- 35738- This file is part of the GNU opcodes library. 35739- 35740- This library is free software; you can redistribute it and/or modify 35741- it under the terms of the GNU General Public License as published by 35742- the Free Software Foundation; either version 3, or (at your option) 35743- any later version. 35744- 35745- It is distributed in the hope that it will be useful, but WITHOUT 35746- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 35747- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 35748- License for more details. 35749- 35750- You should have received a copy of the GNU General Public License 35751- along with this program; if not, write to the Free Software 35752- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 35753- MA 02110-1301, USA. */ 35754- 35755-#include "sysdep.h" 35756-#include <string.h> 35757-#include <stdio.h> 35758-#include <stdlib.h> 35759-#include "safe-ctype.h" 35760-#include "ansidecl.h" 35761-#include "opcode/or32.h" 35762- 35763-/* We treat all letters the same in encode/decode routines so 35764- we need to assign some characteristics to them like signess etc. */ 35765- 35766-const struct or32_letter or32_letters[] = 35767-{ 35768- { 'A', NUM_UNSIGNED }, 35769- { 'B', NUM_UNSIGNED }, 35770- { 'D', NUM_UNSIGNED }, 35771- { 'I', NUM_SIGNED }, 35772- { 'K', NUM_UNSIGNED }, 35773- { 'L', NUM_UNSIGNED }, 35774- { 'N', NUM_SIGNED }, 35775- { '0', NUM_UNSIGNED }, 35776- { '\0', 0 } /* Dummy entry. */ 35777-}; 35778- 35779-/* Opcode encoding: 35780- machine[31:30]: first two bits of opcode 35781- 00 - neither of source operands is GPR 35782- 01 - second source operand is GPR (rB) 35783- 10 - first source operand is GPR (rA) 35784- 11 - both source operands are GPRs (rA and rB) 35785- machine[29:26]: next four bits of opcode 35786- machine[25:00]: instruction operands (specific to individual instruction) 35787- 35788- Recommendation: irrelevant instruction bits should be set with a value of 35789- bits in same positions of instruction preceding current instruction in the 35790- code (when assembling). */ 35791- 35792-#define EFN &l_none 35793- 35794-#ifdef HAS_EXECUTION 35795-#define EF(func) &(func) 35796-#define EFI &l_invalid 35797-#else /* HAS_EXECUTION */ 35798-#define EF(func) EFN 35799-#define EFI EFN 35800-#endif /* HAS_EXECUTION */ 35801- 35802-const struct or32_opcode or32_opcodes[] = 35803-{ 35804- { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY }, 35805- { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY }, 35806- { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG}, 35807- { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG }, 35808- { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 }, 35809- { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/ 35810- { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/ 35811- 35812- { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 }, 35813- { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */ 35814- { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 }, 35815- { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 }, 35816- { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 }, 35817- { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY }, 35818- 35819- { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, 35820- { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, 35821- { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, 35822- { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, 35823- { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, 35824- { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, 35825- { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, 35826- { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, 35827- { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, 35828- { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, 35829- { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, 35830- { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, 35831- { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 }, 35832- { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 }, 35833- { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 }, 35834- { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 }, 35835- { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 }, 35836- { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 }, 35837- { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 }, 35838- { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 }, 35839- { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 }, 35840- { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 }, 35841- { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 }, 35842- { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 }, 35843- { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 }, 35844- { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 }, 35845- { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 }, 35846- { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 }, 35847- { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 }, 35848- { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 }, 35849- { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 }, 35850- { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 }, 35851- { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 }, 35852- { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 }, 35853- { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 }, 35854- { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 }, 35855- { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 }, 35856- { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 }, 35857- { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 }, 35858- { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 }, 35859- { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 }, 35860- { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 }, 35861- { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 }, 35862- { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 }, 35863- { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 }, 35864- { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 }, 35865- { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 }, 35866- { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 }, 35867- { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 }, 35868- { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 }, 35869- { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 }, 35870- { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 }, 35871- { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 }, 35872- { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 }, 35873- { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 }, 35874- { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 }, 35875- { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 }, 35876- { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 }, 35877- { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 }, 35878- { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 }, 35879- { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 }, 35880- { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 }, 35881- { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 }, 35882- { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 }, 35883- { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 }, 35884- { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 }, 35885- { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 }, 35886- { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 }, 35887- { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 }, 35888- { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 }, 35889- { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 }, 35890- { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 }, 35891- { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 }, 35892- { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 }, 35893- { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 }, 35894- { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 }, 35895- { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 }, 35896- { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 }, 35897- { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 }, 35898- { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 }, 35899- { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 }, 35900- { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 }, 35901- { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 }, 35902- { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 }, 35903- { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 }, 35904- { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 }, 35905- { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 }, 35906- { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 }, 35907- { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 }, 35908- { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 }, 35909- { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 }, 35910- 35911- { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, 35912- { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, 35913- { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, 35914- { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, 35915- { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, 35916- { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, 35917- { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, 35918- { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, 35919- { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, 35920- { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, 35921- { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, 35922- { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, 35923- { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, 35924- { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, 35925- { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 }, 35926- 35927- { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, 35928- { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, 35929- { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, 35930- { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, 35931- { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, 35932- { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, 35933- { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, 35934- { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, 35935- { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, 35936- { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, 35937- { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, 35938- { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, 35939- { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, 35940- { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, 35941- { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 }, 35942- 35943- { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 }, 35944- { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 }, 35945- { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, 35946- { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, 35947- 35948- { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY }, 35949- { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY }, 35950- { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 }, 35951- { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 }, 35952- { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 }, 35953- { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 }, 35954- { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 }, 35955- 35956- { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, 35957- { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 }, 35958- { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, 35959- { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 }, 35960- { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 }, 35961- { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 }, 35962- { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 }, 35963- 35964- { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 }, 35965- { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, 35966- { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 }, 35967- { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 }, 35968- { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 }, 35969- { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, 35970- { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 }, 35971- { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 }, 35972- { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 }, 35973- { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 }, 35974- { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 }, 35975- 35976- { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG }, 35977- { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG }, 35978- { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG }, 35979- { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG }, 35980- { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG }, 35981- { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG }, 35982- { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG }, 35983- { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG }, 35984- { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG }, 35985- { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG }, 35986- 35987- { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 }, 35988- { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/ 35989- { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/ 35990- 35991- { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 }, 35992- { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 }, 35993- { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 }, 35994- { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 }, 35995- 35996- { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 }, 35997- { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 }, 35998- { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 }, 35999- { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 }, 36000- { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 }, 36001- { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 }, 36002- { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 }, 36003- 36004- { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 }, 36005- { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 }, 36006- { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 }, 36007- { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 }, 36008- { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 }, 36009- { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 }, 36010- { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 }, 36011- { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 }, 36012- { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 }, 36013- { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 }, 36014- { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 }, 36015- { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 }, 36016- { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 }, 36017- { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 }, 36018- { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 }, 36019- 36020- { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG }, 36021- { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG }, 36022- { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG }, 36023- { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG }, 36024- { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG }, 36025- { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG }, 36026- { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG }, 36027- { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG }, 36028- { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG }, 36029- { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG }, 36030- 36031- { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 }, 36032- { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 }, 36033- { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 }, 36034- { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 }, 36035- 36036- /* This section should not be defined in or1ksim, since it contains duplicates, 36037- which would cause machine builder to complain. */ 36038-#ifdef HAS_CUST 36039- { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 }, 36040- { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, 36041- { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, 36042- 36043- { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 }, 36044- { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, 36045- { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, 36046- 36047- { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 }, 36048- { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, 36049- { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, 36050- 36051- { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 }, 36052- { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, 36053- { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, 36054-#endif 36055- 36056- /* Dummy entry, not included in num_opcodes. This 36057- lets code examine entry i+1 without checking 36058- if we've run off the end of the table. */ 36059- { "", "", "", EFI, 0 } 36060-}; 36061- 36062-#undef EFI 36063-#undef EFN 36064-#undef EF 36065- 36066-/* Define dummy, if debug is not defined. */ 36067- 36068-#if !defined HAS_DEBUG 36069-static void ATTRIBUTE_PRINTF_2 36070-debug (int level ATTRIBUTE_UNUSED, const char *format ATTRIBUTE_UNUSED, ...) 36071-{ 36072-} 36073-#endif 36074- 36075-const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1; 36076- 36077-/* Calculates instruction length in bytes. Always 4 for OR32. */ 36078- 36079-int 36080-insn_len (int i_index ATTRIBUTE_UNUSED) 36081-{ 36082- return 4; 36083-} 36084- 36085-/* Is individual insn's operand signed or unsigned? */ 36086- 36087-int 36088-letter_signed (char l) 36089-{ 36090- const struct or32_letter *pletter; 36091- 36092- for (pletter = or32_letters; pletter->letter != '\0'; pletter++) 36093- if (pletter->letter == l) 36094- return pletter->sign; 36095- 36096- printf ("letter_signed(%c): Unknown letter.\n", l); 36097- return 0; 36098-} 36099- 36100-/* Number of letters in the individual lettered operand. */ 36101- 36102-int 36103-letter_range (char l) 36104-{ 36105- const struct or32_opcode *pinsn; 36106- char *enc; 36107- int range = 0; 36108- 36109- for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++) 36110- { 36111- if (strchr (pinsn->encoding,l)) 36112- { 36113- for (enc = pinsn->encoding; *enc != '\0'; enc ++) 36114- if ((*enc == '0') && (*(enc + 1) == 'x')) 36115- enc += 2; 36116- else if (*enc == l) 36117- range++; 36118- return range; 36119- } 36120- } 36121- 36122- printf ("\nABORT: letter_range(%c): Never used letter.\n", l); 36123- exit (1); 36124-} 36125- 36126-/* MM: Returns index of given instruction name. */ 36127- 36128-int 36129-insn_index (char *insn) 36130-{ 36131- unsigned int i; 36132- int found = -1; 36133- 36134- for (i = 0; i < or32_num_opcodes; i++) 36135- if (!strcmp (or32_opcodes[i].name, insn)) 36136- { 36137- found = i; 36138- break; 36139- } 36140- return found; 36141-} 36142- 36143-const char * 36144-insn_name (int op_index) 36145-{ 36146- if (op_index >= 0 && op_index < (int) or32_num_opcodes) 36147- return or32_opcodes[op_index].name; 36148- else 36149- return "???"; 36150-} 36151- 36152-void 36153-l_none (void) 36154-{ 36155-} 36156- 36157-/* Finite automata for instruction decoding building code. */ 36158- 36159-/* Find simbols in encoding. */ 36160- 36161-static unsigned long 36162-insn_extract (char param_ch, char *enc_initial) 36163-{ 36164- char *enc; 36165- unsigned long ret = 0; 36166- unsigned opc_pos = 32; 36167- 36168- for (enc = enc_initial; *enc != '\0'; ) 36169- if ((*enc == '0') && (*(enc + 1) == 'x')) 36170- { 36171- unsigned long tmp = strtol (enc+2, NULL, 16); 36172- 36173- opc_pos -= 4; 36174- if (param_ch == '0' || param_ch == '1') 36175- { 36176- if (param_ch == '0') 36177- tmp = 15 - tmp; 36178- ret |= tmp << opc_pos; 36179- } 36180- enc += 3; 36181- } 36182- else 36183- { 36184- if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc)) 36185- { 36186- opc_pos--; 36187- if (param_ch == *enc) 36188- ret |= 1 << opc_pos; 36189- } 36190- enc++; 36191- } 36192- return ret; 36193-} 36194- 36195-#define MAX_AUTOMATA_SIZE 1200 36196-#define MAX_OP_TABLE_SIZE 1200 36197-#define LEAF_FLAG 0x80000000 36198-#define MAX_LEN 8 36199- 36200-#ifndef MIN 36201-#define MIN(x, y) ((x) < (y) ? (x) : (y)) 36202-#endif 36203- 36204-unsigned long *automata; 36205-int nuncovered; 36206-int curpass = 0; 36207- 36208-/* MM: Struct that hold runtime build information about instructions. */ 36209-struct temp_insn_struct 36210-{ 36211- unsigned long insn; 36212- unsigned long insn_mask; 36213- int in_pass; 36214-} *ti; 36215- 36216-struct insn_op_struct *op_data, **op_start; 36217- 36218-/* Recursive utility function used to find best match and to build automata. */ 36219- 36220-static unsigned long * 36221-cover_insn (unsigned long * cur, int pass, unsigned int mask) 36222-{ 36223- int best_first = 0, last_match = -1, ninstr = 0; 36224- unsigned int best_len = 0; 36225- unsigned int i; 36226- unsigned long cur_mask = mask; 36227- unsigned long *next; 36228- 36229- for (i = 0; i < or32_num_opcodes; i++) 36230- if (ti[i].in_pass == pass) 36231- { 36232- cur_mask &= ti[i].insn_mask; 36233- ninstr++; 36234- last_match = i; 36235- } 36236- 36237- debug (8, "%08X %08lX\n", mask, cur_mask); 36238- 36239- if (ninstr == 0) 36240- return 0; 36241- 36242- if (ninstr == 1) 36243- { 36244- /* Leaf holds instruction index. */ 36245- debug (8, "%li>I%i %s\n", 36246- (long)(cur - automata), last_match, or32_opcodes[last_match].name); 36247- 36248- *cur = LEAF_FLAG | last_match; 36249- cur++; 36250- nuncovered--; 36251- } 36252- else 36253- { 36254- /* Find longest match. */ 36255- for (i = 0; i < 32; i++) 36256- { 36257- unsigned int len; 36258- 36259- for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++) 36260- { 36261- unsigned long m = (1UL << ((unsigned long) len)) - 1; 36262- 36263- debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)", 36264- len,m, cur_mask, i, (cur_mask >> (unsigned)i), 36265- (cur_mask >> (unsigned) i) & m); 36266- 36267- if ((m & (cur_mask >> (unsigned) i)) == m) 36268- { 36269- best_len = len; 36270- best_first = i; 36271- debug (9, "!"); 36272- } 36273- else 36274- break; 36275- } 36276- } 36277- 36278- debug (9, "\n"); 36279- 36280- if (!best_len) 36281- { 36282- fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask); 36283- 36284- for (i = 0; i < or32_num_opcodes; i++) 36285- if (ti[i].in_pass == pass) 36286- fprintf (stderr, "%s ", or32_opcodes[i].name); 36287- 36288- fprintf (stderr, "\n"); 36289- exit (1); 36290- } 36291- 36292- debug (8, "%li> #### %i << %i (%i) ####\n", 36293- (long)(cur - automata), best_len, best_first, ninstr); 36294- 36295- *cur = best_first; 36296- cur++; 36297- *cur = (1 << best_len) - 1; 36298- cur++; 36299- next = cur; 36300- 36301- /* Allocate space for pointers. */ 36302- cur += 1 << best_len; 36303- cur_mask = (1 << (unsigned long) best_len) - 1; 36304- 36305- for (i = 0; i < ((unsigned) 1 << best_len); i++) 36306- { 36307- unsigned int j; 36308- unsigned long *c; 36309- 36310- curpass++; 36311- for (j = 0; j < or32_num_opcodes; j++) 36312- if (ti[j].in_pass == pass 36313- && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i 36314- && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask) 36315- ti[j].in_pass = curpass; 36316- 36317- debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first); 36318- c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first))); 36319- if (c) 36320- { 36321- debug (8, "%li> #%X -> %lu\n", (long)(next - automata), i, 36322- (unsigned long)(cur - automata)); 36323- *next = cur - automata; 36324- cur = c; 36325- } 36326- else 36327- { 36328- debug (8, "%li> N/A\n", (long)(next - automata)); 36329- *next = 0; 36330- } 36331- next++; 36332- } 36333- } 36334- return cur; 36335-} 36336- 36337-/* Returns number of nonzero bits. */ 36338- 36339-static int 36340-num_ones (unsigned long value) 36341-{ 36342- int c = 0; 36343- 36344- while (value) 36345- { 36346- if (value & 1) 36347- c++; 36348- value >>= 1; 36349- } 36350- return c; 36351-} 36352- 36353-/* Utility function, which converts parameters from or32_opcode 36354- format to more binary form. Parameters are stored in ti struct. */ 36355- 36356-static struct insn_op_struct * 36357-parse_params (const struct or32_opcode * opcode, 36358- struct insn_op_struct * cur) 36359-{ 36360- char *args = opcode->args; 36361- int i, type; 36362- 36363- i = 0; 36364- type = 0; 36365- /* In case we don't have any parameters, we add dummy read from r0. */ 36366- 36367- if (!(*args)) 36368- { 36369- cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST; 36370- cur->data = 0; 36371- debug (9, "#%08lX %08lX\n", cur->type, cur->data); 36372- cur++; 36373- return cur; 36374- } 36375- 36376- while (*args != '\0') 36377- { 36378- if (*args == 'r') 36379- { 36380- args++; 36381- type |= OPTYPE_REG; 36382- } 36383- else if (ISALPHA (*args)) 36384- { 36385- unsigned long arg; 36386- 36387- arg = insn_extract (*args, opcode->encoding); 36388- debug (9, "%s : %08lX ------\n", opcode->name, arg); 36389- if (letter_signed (*args)) 36390- { 36391- type |= OPTYPE_SIG; 36392- type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT; 36393- } 36394- 36395- /* Split argument to sequences of consecutive ones. */ 36396- while (arg) 36397- { 36398- int shr = 0; 36399- unsigned long tmp = arg, mask = 0; 36400- 36401- while ((tmp & 1) == 0) 36402- { 36403- shr++; 36404- tmp >>= 1; 36405- } 36406- while (tmp & 1) 36407- { 36408- mask++; 36409- tmp >>= 1; 36410- } 36411- cur->type = type | shr; 36412- cur->data = mask; 36413- arg &= ~(((1 << mask) - 1) << shr); 36414- debug (6, "|%08lX %08lX\n", cur->type, cur->data); 36415- cur++; 36416- } 36417- args++; 36418- } 36419- else if (*args == '(') 36420- { 36421- /* Next param is displacement. 36422- Later we will treat them as one operand. */ 36423- cur--; 36424- cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP; 36425- debug (9, ">%08lX %08lX\n", cur->type, cur->data); 36426- cur++; 36427- type = 0; 36428- i++; 36429- args++; 36430- } 36431- else if (*args == OPERAND_DELIM) 36432- { 36433- cur--; 36434- cur->type = type | cur->type | OPTYPE_OP; 36435- debug (9, ">%08lX %08lX\n", cur->type, cur->data); 36436- cur++; 36437- type = 0; 36438- i++; 36439- args++; 36440- } 36441- else if (*args == '0') 36442- { 36443- cur->type = type; 36444- cur->data = 0; 36445- debug (9, ">%08lX %08lX\n", cur->type, cur->data); 36446- cur++; 36447- type = 0; 36448- i++; 36449- args++; 36450- } 36451- else if (*args == ')') 36452- args++; 36453- else 36454- { 36455- fprintf (stderr, "%s : parse error in args.\n", opcode->name); 36456- exit (1); 36457- } 36458- } 36459- 36460- cur--; 36461- cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST; 36462- debug (9, "#%08lX %08lX\n", cur->type, cur->data); 36463- cur++; 36464- 36465- return cur; 36466-} 36467- 36468-/* Constructs new automata based on or32_opcodes array. */ 36469- 36470-void 36471-build_automata (void) 36472-{ 36473- unsigned int i; 36474- unsigned long *end; 36475- struct insn_op_struct *cur; 36476- 36477- automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long)); 36478- ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes); 36479- 36480- nuncovered = or32_num_opcodes; 36481- printf ("Building automata... "); 36482- /* Build temporary information about instructions. */ 36483- for (i = 0; i < or32_num_opcodes; i++) 36484- { 36485- unsigned long ones, zeros; 36486- char *encoding = or32_opcodes[i].encoding; 36487- 36488- ones = insn_extract('1', encoding); 36489- zeros = insn_extract('0', encoding); 36490- 36491- ti[i].insn_mask = ones | zeros; 36492- ti[i].insn = ones; 36493- ti[i].in_pass = curpass = 0; 36494- 36495- /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name, 36496- or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/ 36497- } 36498- 36499- /* Until all are covered search for best criteria to separate them. */ 36500- end = cover_insn (automata, curpass, 0xFFFFFFFF); 36501- 36502- if (end - automata > MAX_AUTOMATA_SIZE) 36503- { 36504- fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE."); 36505- exit (1); 36506- } 36507- 36508- printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes); 36509- printf ("Parsing operands data... "); 36510- 36511- op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct)); 36512- op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *)); 36513- cur = op_data; 36514- 36515- for (i = 0; i < or32_num_opcodes; i++) 36516- { 36517- op_start[i] = cur; 36518- cur = parse_params (&or32_opcodes[i], cur); 36519- 36520- if (cur - op_data > MAX_OP_TABLE_SIZE) 36521- { 36522- fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n"); 36523- exit (1); 36524- } 36525- } 36526- printf ("done.\n"); 36527-} 36528- 36529-void 36530-destruct_automata (void) 36531-{ 36532- free (ti); 36533- free (automata); 36534- free (op_data); 36535- free (op_start); 36536-} 36537- 36538-/* Decodes instruction and returns instruction index. */ 36539- 36540-int 36541-insn_decode (unsigned int insn) 36542-{ 36543- unsigned long *a = automata; 36544- int i; 36545- 36546- while (!(*a & LEAF_FLAG)) 36547- { 36548- unsigned int first = *a; 36549- 36550- debug (9, "%li ", (long)(a - automata)); 36551- 36552- a++; 36553- i = (insn >> first) & *a; 36554- a++; 36555- if (!*(a + i)) 36556- { 36557- /* Invalid instruction found? */ 36558- debug (9, "XXX\n"); 36559- return -1; 36560- } 36561- a = automata + *(a + i); 36562- } 36563- 36564- i = *a & ~LEAF_FLAG; 36565- 36566- debug (9, "%i\n", i); 36567- 36568- /* Final check - do we have direct match? 36569- (based on or32_opcodes this should be the only possibility, 36570- but in case of invalid/missing instruction we must perform a check) */ 36571- if ((ti[i].insn_mask & insn) == ti[i].insn) 36572- return i; 36573- else 36574- return -1; 36575-} 36576- 36577-static char disassembled_str[50]; 36578-char *disassembled = &disassembled_str[0]; 36579- 36580-/* Automagically does zero- or sign- extension and also finds correct 36581- sign bit position if sign extension is correct extension. Which extension 36582- is proper is figured out from letter description. */ 36583- 36584-static unsigned long 36585-extend_imm (unsigned long imm, char l) 36586-{ 36587- unsigned long mask; 36588- int letter_bits; 36589- 36590- /* First truncate all bits above valid range for this letter 36591- in case it is zero extend. */ 36592- letter_bits = letter_range (l); 36593- mask = (1 << letter_bits) - 1; 36594- imm &= mask; 36595- 36596- /* Do sign extend if this is the right one. */ 36597- if (letter_signed(l) && (imm >> (letter_bits - 1))) 36598- imm |= (~mask); 36599- 36600- return imm; 36601-} 36602- 36603-static unsigned long 36604-or32_extract (char param_ch, char *enc_initial, unsigned long insn) 36605-{ 36606- char *enc; 36607- unsigned long ret = 0; 36608- int opc_pos = 0; 36609- int param_pos = 0; 36610- 36611- for (enc = enc_initial; *enc != '\0'; enc++) 36612- if (*enc == param_ch) 36613- { 36614- if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) 36615- continue; 36616- else 36617- param_pos++; 36618- } 36619- 36620-#if DEBUG 36621- printf ("or32_extract: %x ", param_pos); 36622-#endif 36623- opc_pos = 32; 36624- 36625- for (enc = enc_initial; *enc != '\0'; ) 36626- if ((*enc == '0') && (*(enc + 1) == 'x')) 36627- { 36628- opc_pos -= 4; 36629- if ((param_ch == '0') || (param_ch == '1')) 36630- { 36631- unsigned long tmp = strtol (enc, NULL, 16); 36632-#if DEBUG 36633- printf (" enc=%s, tmp=%lx ", enc, tmp); 36634-#endif 36635- if (param_ch == '0') 36636- tmp = 15 - tmp; 36637- ret |= tmp << opc_pos; 36638- } 36639- enc += 3; 36640- } 36641- else if ((*enc == '0') || (*enc == '1')) 36642- { 36643- opc_pos--; 36644- if (param_ch == *enc) 36645- ret |= 1 << opc_pos; 36646- enc++; 36647- } 36648- else if (*enc == param_ch) 36649- { 36650- opc_pos--; 36651- param_pos--; 36652-#if DEBUG 36653- printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); 36654-#endif 36655- if (ISLOWER (param_ch)) 36656- ret -= ((insn >> opc_pos) & 0x1) << param_pos; 36657- else 36658- ret += ((insn >> opc_pos) & 0x1) << param_pos; 36659- enc++; 36660- } 36661- else if (ISALPHA (*enc)) 36662- { 36663- opc_pos--; 36664- enc++; 36665- } 36666- else if (*enc == '-') 36667- { 36668- opc_pos--; 36669- enc++; 36670- } 36671- else 36672- enc++; 36673- 36674-#if DEBUG 36675- printf ("ret=%lx\n", ret); 36676-#endif 36677- return ret; 36678-} 36679- 36680-/* Print register. Used only by print_insn. */ 36681- 36682-static void 36683-or32_print_register (char param_ch, char *encoding, unsigned long insn) 36684-{ 36685- int regnum = or32_extract(param_ch, encoding, insn); 36686- char s_regnum[20]; 36687- 36688- sprintf (s_regnum, "r%d", regnum); 36689- strcat (disassembled, s_regnum); 36690-} 36691- 36692-/* Print immediate. Used only by print_insn. */ 36693- 36694-static void 36695-or32_print_immediate (char param_ch, char *encoding, unsigned long insn) 36696-{ 36697- int imm = or32_extract (param_ch, encoding, insn); 36698- char s_imm[20]; 36699- 36700- imm = extend_imm (imm, param_ch); 36701- 36702- if (letter_signed (param_ch)) 36703- { 36704- if (imm < 0) 36705- sprintf (s_imm, "%d", imm); 36706- else 36707- sprintf (s_imm, "0x%x", imm); 36708- } 36709- else 36710- sprintf (s_imm, "%#x", imm); 36711- strcat (disassembled, s_imm); 36712-} 36713- 36714-/* Disassemble one instruction from insn to disassemble. 36715- Return the size of the instruction. */ 36716- 36717-int 36718-disassemble_insn (unsigned long insn) 36719-{ 36720- int op_index; 36721- op_index = insn_decode (insn); 36722- 36723- if (op_index >= 0) 36724- { 36725- struct or32_opcode const *opcode = &or32_opcodes[op_index]; 36726- char *s; 36727- 36728- sprintf (disassembled, "%s ", opcode->name); 36729- for (s = opcode->args; *s != '\0'; ++s) 36730- { 36731- switch (*s) 36732- { 36733- case '\0': 36734- return 4; 36735- 36736- case 'r': 36737- or32_print_register (*++s, opcode->encoding, insn); 36738- break; 36739- 36740- default: 36741- if (strchr (opcode->encoding, *s)) 36742- or32_print_immediate (*s, opcode->encoding, insn); 36743- else 36744- { 36745- char s_encoding[2] = { *s, '\0' }; 36746- 36747- strcat (disassembled, s_encoding); 36748- } 36749- 36750- } 36751- } 36752- } 36753- else 36754- { 36755- char s_insn[20]; 36756- 36757- /* This used to be %8x for binutils. */ 36758- sprintf (s_insn, ".word 0x%08lx", insn); 36759- strcat (disassembled, s_insn); 36760- } 36761- 36762- return insn_len (insn); 36763-} 36764diff -rNU3 dist.orig/opcodes/riscv-dis.c dist/opcodes/riscv-dis.c 36765--- dist.orig/opcodes/riscv-dis.c 1970-01-01 01:00:00.000000000 +0100 36766+++ dist/opcodes/riscv-dis.c 2015-10-18 13:11:20.000000000 +0200 36767@@ -0,0 +1,492 @@ 36768+/* RISC-V disassembler 36769+ Copyright 2011-2014 Free Software Foundation, Inc. 36770+ 36771+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 36772+ Based on MIPS target. 36773+ 36774+ This file is part of the GNU opcodes library. 36775+ 36776+ This library is free software; you can redistribute it and/or modify 36777+ it under the terms of the GNU General Public License as published by 36778+ the Free Software Foundation; either version 3, or (at your option) 36779+ any later version. 36780+ 36781+ It is distributed in the hope that it will be useful, but WITHOUT 36782+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 36783+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 36784+ License for more details. 36785+ 36786+ You should have received a copy of the GNU General Public License 36787+ along with this program; if not, write to the Free Software 36788+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 36789+ MA 02110-1301, USA. */ 36790+ 36791+#include "sysdep.h" 36792+#include "dis-asm.h" 36793+#include "libiberty.h" 36794+#include "opcode/riscv.h" 36795+#include "opintl.h" 36796+#include "elf-bfd.h" 36797+#include "elf/riscv.h" 36798+ 36799+#include <stdint.h> 36800+#include <assert.h> 36801+ 36802+struct riscv_private_data 36803+{ 36804+ bfd_vma gp; 36805+ bfd_vma print_addr; 36806+ bfd_vma hi_addr[OP_MASK_RD + 1]; 36807+}; 36808+ 36809+static const char * const *riscv_gpr_names; 36810+static const char * const *riscv_fpr_names; 36811+ 36812+/* Other options */ 36813+static int no_aliases; /* If set disassemble as most general inst. */ 36814+ 36815+static void 36816+set_default_riscv_dis_options (void) 36817+{ 36818+ riscv_gpr_names = riscv_gpr_names_abi; 36819+ riscv_fpr_names = riscv_fpr_names_abi; 36820+ no_aliases = 0; 36821+} 36822+ 36823+static void 36824+parse_riscv_dis_option (const char *option) 36825+{ 36826+ if (CONST_STRNEQ (option, "no-aliases")) 36827+ no_aliases = 1; 36828+ else if (CONST_STRNEQ (option, "numeric")) 36829+ { 36830+ riscv_gpr_names = riscv_gpr_names_numeric; 36831+ riscv_fpr_names = riscv_fpr_names_numeric; 36832+ } 36833+ 36834+ /* Invalid option. */ 36835+ fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option); 36836+} 36837+ 36838+static void 36839+parse_riscv_dis_options (const char *opts_in) 36840+{ 36841+ char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; 36842+ 36843+ set_default_riscv_dis_options (); 36844+ 36845+ for ( ; opt_end != NULL; opt = opt_end + 1) 36846+ { 36847+ if ((opt_end = strchr (opt, ',')) != NULL) 36848+ *opt_end = 0; 36849+ parse_riscv_dis_option (opt); 36850+ } 36851+ 36852+ free (opts); 36853+} 36854+ 36855+/* Print one argument from an array. */ 36856+ 36857+static void 36858+arg_print (struct disassemble_info *info, unsigned long val, 36859+ const char* const* array, size_t size) 36860+{ 36861+ const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; 36862+ (*info->fprintf_func) (info->stream, "%s", s); 36863+} 36864+ 36865+static void 36866+maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) 36867+{ 36868+ if (pd->hi_addr[base_reg] != (bfd_vma)-1) 36869+ { 36870+ pd->print_addr = pd->hi_addr[base_reg] + offset; 36871+ pd->hi_addr[base_reg] = -1; 36872+ } 36873+ else if (base_reg == X_GP && pd->gp != (bfd_vma)-1) 36874+ pd->print_addr = pd->gp + offset; 36875+ else if (base_reg == X_TP) 36876+ pd->print_addr = offset; 36877+} 36878+ 36879+/* Print insn arguments for 32/64-bit code. */ 36880+ 36881+static void 36882+print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) 36883+{ 36884+ struct riscv_private_data *pd = info->private_data; 36885+ int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; 36886+ int rd = (l >> OP_SH_RD) & OP_MASK_RD; 36887+ 36888+ if (*d != '\0') 36889+ (*info->fprintf_func) (info->stream, "\t"); 36890+ 36891+ for (; *d != '\0'; d++) 36892+ { 36893+ switch (*d) 36894+ { 36895+ /* Xcustom */ 36896+ case '^': 36897+ switch (*++d) 36898+ { 36899+ case 'd': 36900+ (*info->fprintf_func) (info->stream, "%d", rd); 36901+ break; 36902+ case 's': 36903+ (*info->fprintf_func) (info->stream, "%d", rs1); 36904+ break; 36905+ case 't': 36906+ (*info->fprintf_func) 36907+ ( info->stream, "%d", (int)((l >> OP_SH_RS2) & OP_MASK_RS2)); 36908+ break; 36909+ case 'j': 36910+ (*info->fprintf_func) 36911+ ( info->stream, "%d", (int)((l >> OP_SH_CUSTOM_IMM) & OP_MASK_CUSTOM_IMM)); 36912+ break; 36913+ } 36914+ break; 36915+ 36916+ /* Xhwacha */ 36917+ case '#': 36918+ switch ( *++d ) { 36919+ case 'g': 36920+ (*info->fprintf_func) 36921+ ( info->stream, "%d", 36922+ (int)((l >> OP_SH_IMMNGPR) & OP_MASK_IMMNGPR)); 36923+ break; 36924+ case 'f': 36925+ (*info->fprintf_func) 36926+ ( info->stream, "%d", 36927+ (int)((l >> OP_SH_IMMNFPR) & OP_MASK_IMMNFPR)); 36928+ break; 36929+ case 'p': 36930+ (*info->fprintf_func) 36931+ ( info->stream, "%d", 36932+ (int)((l >> OP_SH_CUSTOM_IMM) & OP_MASK_CUSTOM_IMM)); 36933+ break; 36934+ case 'n': 36935+ (*info->fprintf_func) 36936+ ( info->stream, "%d", 36937+ (int)(((l >> OP_SH_IMMSEGNELM) & OP_MASK_IMMSEGNELM) + 1)); 36938+ break; 36939+ case 'd': 36940+ (*info->fprintf_func) 36941+ ( info->stream, "%s", 36942+ riscv_vec_gpr_names[(l >> OP_SH_VRD) & OP_MASK_VRD]); 36943+ break; 36944+ case 's': 36945+ (*info->fprintf_func) 36946+ ( info->stream, "%s", 36947+ riscv_vec_gpr_names[(l >> OP_SH_VRS) & OP_MASK_VRS]); 36948+ break; 36949+ case 't': 36950+ (*info->fprintf_func) 36951+ ( info->stream, "%s", 36952+ riscv_vec_gpr_names[(l >> OP_SH_VRT) & OP_MASK_VRT]); 36953+ break; 36954+ case 'r': 36955+ (*info->fprintf_func) 36956+ ( info->stream, "%s", 36957+ riscv_vec_gpr_names[(l >> OP_SH_VRR) & OP_MASK_VRR]); 36958+ break; 36959+ case 'D': 36960+ (*info->fprintf_func) 36961+ ( info->stream, "%s", 36962+ riscv_vec_fpr_names[(l >> OP_SH_VFD) & OP_MASK_VFD]); 36963+ break; 36964+ case 'S': 36965+ (*info->fprintf_func) 36966+ ( info->stream, "%s", 36967+ riscv_vec_fpr_names[(l >> OP_SH_VFS) & OP_MASK_VFS]); 36968+ break; 36969+ case 'T': 36970+ (*info->fprintf_func) 36971+ ( info->stream, "%s", 36972+ riscv_vec_fpr_names[(l >> OP_SH_VFT) & OP_MASK_VFT]); 36973+ break; 36974+ case 'R': 36975+ (*info->fprintf_func) 36976+ ( info->stream, "%s", 36977+ riscv_vec_fpr_names[(l >> OP_SH_VFR) & OP_MASK_VFR]); 36978+ break; 36979+ } 36980+ break; 36981+ 36982+ case ',': 36983+ case '(': 36984+ case ')': 36985+ case '[': 36986+ case ']': 36987+ (*info->fprintf_func) (info->stream, "%c", *d); 36988+ break; 36989+ 36990+ case '0': 36991+ break; 36992+ 36993+ case 'b': 36994+ case 's': 36995+ (*info->fprintf_func) (info->stream, "%s", riscv_gpr_names[rs1]); 36996+ break; 36997+ 36998+ case 't': 36999+ (*info->fprintf_func) (info->stream, "%s", 37000+ riscv_gpr_names[(l >> OP_SH_RS2) & OP_MASK_RS2]); 37001+ break; 37002+ 37003+ case 'u': 37004+ (*info->fprintf_func) (info->stream, "0x%x", (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); 37005+ break; 37006+ 37007+ case 'm': 37008+ arg_print(info, (l >> OP_SH_RM) & OP_MASK_RM, 37009+ riscv_rm, ARRAY_SIZE(riscv_rm)); 37010+ break; 37011+ 37012+ case 'P': 37013+ arg_print(info, (l >> OP_SH_PRED) & OP_MASK_PRED, 37014+ riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ)); 37015+ break; 37016+ 37017+ case 'Q': 37018+ arg_print(info, (l >> OP_SH_SUCC) & OP_MASK_SUCC, 37019+ riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ)); 37020+ break; 37021+ 37022+ case 'o': 37023+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); 37024+ case 'j': 37025+ if ((l & MASK_ADDI) == MATCH_ADDI || (l & MASK_JALR) == MATCH_JALR) 37026+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); 37027+ (*info->fprintf_func) (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l)); 37028+ break; 37029+ 37030+ case 'q': 37031+ maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); 37032+ (*info->fprintf_func) (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); 37033+ break; 37034+ 37035+ case 'a': 37036+ info->target = EXTRACT_UJTYPE_IMM (l) + pc; 37037+ (*info->print_address_func) (info->target, info); 37038+ break; 37039+ 37040+ case 'p': 37041+ info->target = EXTRACT_SBTYPE_IMM (l) + pc; 37042+ (*info->print_address_func) (info->target, info); 37043+ break; 37044+ 37045+ case 'd': 37046+ if ((l & MASK_AUIPC) == MATCH_AUIPC) 37047+ pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l); 37048+ else if ((l & MASK_LUI) == MATCH_LUI) 37049+ pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); 37050+ (*info->fprintf_func) (info->stream, "%s", riscv_gpr_names[rd]); 37051+ break; 37052+ 37053+ case 'z': 37054+ (*info->fprintf_func) (info->stream, "%s", riscv_gpr_names[0]); 37055+ break; 37056+ 37057+ case '>': 37058+ (*info->fprintf_func) (info->stream, "0x%x", 37059+ (unsigned)((l >> OP_SH_SHAMT) & OP_MASK_SHAMT)); 37060+ break; 37061+ 37062+ case '<': 37063+ (*info->fprintf_func) (info->stream, "0x%x", 37064+ (unsigned)((l >> OP_SH_SHAMTW) & OP_MASK_SHAMTW)); 37065+ break; 37066+ 37067+ case 'S': 37068+ case 'U': 37069+ (*info->fprintf_func) (info->stream, "%s", riscv_fpr_names[rs1]); 37070+ break; 37071+ 37072+ case 'T': 37073+ (*info->fprintf_func) (info->stream, "%s", 37074+ riscv_fpr_names[(l >> OP_SH_RS2) & OP_MASK_RS2]); 37075+ break; 37076+ 37077+ case 'D': 37078+ (*info->fprintf_func) (info->stream, "%s", riscv_fpr_names[rd]); 37079+ break; 37080+ 37081+ case 'R': 37082+ (*info->fprintf_func) (info->stream, "%s", 37083+ riscv_fpr_names[(l >> OP_SH_RS3) & OP_MASK_RS3]); 37084+ break; 37085+ 37086+ case 'E': 37087+ { 37088+ const char* csr_name = NULL; 37089+ unsigned int csr = (l >> OP_SH_CSR) & OP_MASK_CSR; 37090+ switch (csr) 37091+ { 37092+ #define DECLARE_CSR(name, num) case num: csr_name = #name; break; 37093+ #include "opcode/riscv-opc.h" 37094+ #undef DECLARE_CSR 37095+ } 37096+ if (csr_name) 37097+ (*info->fprintf_func) (info->stream, "%s", csr_name); 37098+ else 37099+ (*info->fprintf_func) (info->stream, "0x%x", csr); 37100+ break; 37101+ } 37102+ 37103+ case 'Z': 37104+ (*info->fprintf_func) (info->stream, "%d", rs1); 37105+ break; 37106+ 37107+ default: 37108+ /* xgettext:c-format */ 37109+ (*info->fprintf_func) (info->stream, 37110+ _("# internal error, undefined modifier (%c)"), 37111+ *d); 37112+ return; 37113+ } 37114+ } 37115+} 37116+ 37117+/* Print the RISC-V instruction at address MEMADDR in debugged memory, 37118+ on using INFO. Returns length of the instruction, in bytes. 37119+ BIGENDIAN must be 1 if this is big-endian code, 0 if 37120+ this is little-endian code. */ 37121+ 37122+static int 37123+riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) 37124+{ 37125+ const struct riscv_opcode *op; 37126+ static bfd_boolean init = 0; 37127+ static const char *extension = NULL; 37128+ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; 37129+ struct riscv_private_data *pd; 37130+ int insnlen; 37131+ 37132+ /* Build a hash table to shorten the search time. */ 37133+ if (! init) 37134+ { 37135+ unsigned int i; 37136+ unsigned int e_flags = elf_elfheader (info->section->owner)->e_flags; 37137+ extension = riscv_elf_flag_to_name(EF_GET_RISCV_EXT(e_flags)); 37138+ 37139+ for (i = 0; i <= OP_MASK_OP; i++) 37140+ for (op = riscv_opcodes; op < &riscv_opcodes[NUMOPCODES]; op++) 37141+ if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 37142+ { 37143+ riscv_hash[i] = op; 37144+ break; 37145+ } 37146+ 37147+ init = 1; 37148+ } 37149+ 37150+ if (info->private_data == NULL) 37151+ { 37152+ int i; 37153+ 37154+ pd = info->private_data = calloc(1, sizeof (struct riscv_private_data)); 37155+ pd->gp = -1; 37156+ pd->print_addr = -1; 37157+ for (i = 0; i < (int) ARRAY_SIZE(pd->hi_addr); i++) 37158+ pd->hi_addr[i] = -1; 37159+ 37160+ for (i = 0; i < info->symtab_size; i++) 37161+ if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0) 37162+ pd->gp = bfd_asymbol_value (info->symtab[i]); 37163+ } 37164+ else 37165+ pd = info->private_data; 37166+ 37167+ insnlen = riscv_insn_length (word); 37168+ 37169+ info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; 37170+ info->bytes_per_line = 8; 37171+ info->display_endian = info->endian; 37172+ info->insn_info_valid = 1; 37173+ info->branch_delay_insns = 0; 37174+ info->data_size = 0; 37175+ info->insn_type = dis_nonbranch; 37176+ info->target = 0; 37177+ info->target2 = 0; 37178+ 37179+ op = riscv_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 37180+ if (op != NULL) 37181+ { 37182+ for (; op < &riscv_opcodes[NUMOPCODES]; op++) 37183+ { 37184+ if ((op->match_func) (op, word) 37185+ && !(no_aliases && (op->pinfo & INSN_ALIAS)) 37186+ && !(op->subset[0] == 'X' && strcmp(op->subset, extension))) 37187+ { 37188+ (*info->fprintf_func) (info->stream, "%s", op->name); 37189+ print_insn_args (op->args, word, memaddr, info); 37190+ if (pd->print_addr != (bfd_vma)-1) 37191+ { 37192+ info->target = pd->print_addr; 37193+ (*info->fprintf_func) (info->stream, " # "); 37194+ (*info->print_address_func) (info->target, info); 37195+ pd->print_addr = -1; 37196+ } 37197+ return insnlen; 37198+ } 37199+ } 37200+ } 37201+ 37202+ /* Handle undefined instructions. */ 37203+ info->insn_type = dis_noninsn; 37204+ (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word); 37205+ return insnlen; 37206+} 37207+ 37208+int 37209+print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) 37210+{ 37211+ uint16_t i2; 37212+ insn_t insn = 0; 37213+ bfd_vma n; 37214+ int status; 37215+ 37216+ if (info->disassembler_options != NULL) 37217+ { 37218+ parse_riscv_dis_options (info->disassembler_options); 37219+ /* Avoid repeatedly parsing the options. */ 37220+ info->disassembler_options = NULL; 37221+ } 37222+ else if (riscv_gpr_names == NULL) 37223+ set_default_riscv_dis_options (); 37224+ 37225+ /* Instructions are a sequence of 2-byte packets in little-endian order. */ 37226+ for (n = 0; n < sizeof(insn) && n < riscv_insn_length (insn); n += 2) 37227+ { 37228+ status = (*info->read_memory_func) (memaddr + n, (bfd_byte*)&i2, 2, info); 37229+ if (status != 0) 37230+ { 37231+ if (n > 0) /* Don't fail just because we fell off the end. */ 37232+ break; 37233+ (*info->memory_error_func) (status, memaddr, info); 37234+ return status; 37235+ } 37236+ 37237+ i2 = bfd_getl16 (&i2); 37238+ insn |= (insn_t)i2 << (8*n); 37239+ } 37240+ 37241+ return riscv_disassemble_insn (memaddr, insn, info); 37242+} 37243+ 37244+void 37245+print_riscv_disassembler_options (FILE *stream) 37246+{ 37247+ fprintf (stream, _("\n\ 37248+The following RISC-V-specific disassembler options are supported for use\n\ 37249+with the -M switch (multiple options should be separated by commas):\n")); 37250+ 37251+ fprintf (stream, _("\n\ 37252+ numeric Print numeric reigster names, rather than ABI names.\n")); 37253+ 37254+ fprintf (stream, _("\n\ 37255+ no-aliases Disassemble only into canonical instructions, rather\n\ 37256+ than into pseudoinstructions.\n")); 37257+ 37258+ fprintf (stream, _("\n")); 37259+} 37260diff -rNU3 dist.orig/opcodes/riscv-opc.c dist/opcodes/riscv-opc.c 37261--- dist.orig/opcodes/riscv-opc.c 1970-01-01 01:00:00.000000000 +0100 37262+++ dist/opcodes/riscv-opc.c 2015-10-18 13:11:20.000000000 +0200 37263@@ -0,0 +1,734 @@ 37264+/* RISC-V opcode list 37265+ Copyright 2011-2014 Free Software Foundation, Inc. 37266+ 37267+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 37268+ Based on MIPS target. 37269+ 37270+ This file is part of the GNU opcodes library. 37271+ 37272+ This library is free software; you can redistribute it and/or modify 37273+ it under the terms of the GNU General Public License as published by 37274+ the Free Software Foundation; either version 3, or (at your option) 37275+ any later version. 37276+ 37277+ It is distributed in the hope that it will be useful, but WITHOUT 37278+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 37279+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 37280+ License for more details. 37281+ 37282+ You should have received a copy of the GNU General Public License 37283+ along with this file; see the file COPYING. If not, write to the 37284+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 37285+ MA 02110-1301, USA. */ 37286+ 37287+#include "sysdep.h" 37288+#include "opcode/riscv.h" 37289+#include <stdio.h> 37290+ 37291+/* Register names used by gas and objdump. */ 37292+ 37293+const char * const riscv_gpr_names_numeric[32] = 37294+{ 37295+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 37296+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 37297+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 37298+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31" 37299+}; 37300+ 37301+const char * const riscv_gpr_names_abi[32] = { 37302+ "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 37303+ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 37304+ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 37305+ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" 37306+}; 37307+ 37308+const char * const riscv_fpr_names_numeric[32] = 37309+{ 37310+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 37311+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 37312+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 37313+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 37314+}; 37315+ 37316+const char * const riscv_fpr_names_abi[32] = { 37317+ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 37318+ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 37319+ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 37320+ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" 37321+}; 37322+ 37323+const char * const riscv_vec_gpr_names[32] = 37324+{ 37325+ "vx0", "vx1", "vx2", "vx3", "vx4", "vx5", "vx6", "vx7", 37326+ "vx8", "vx9", "vx10", "vx11", "vx12", "vx13", "vx14", "vx15", 37327+ "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23", 37328+ "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31" 37329+}; 37330+ 37331+const char * const riscv_vec_fpr_names[32] = 37332+{ 37333+ "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", 37334+ "vf8", "vf9", "vf10", "vf11", "vf12", "vf13", "vf14", "vf15", 37335+ "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23", 37336+ "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31" 37337+}; 37338+ 37339+/* The order of overloaded instructions matters. Label arguments and 37340+ register arguments look the same. Instructions that can have either 37341+ for arguments must apear in the correct order in this table for the 37342+ assembler to pick the right one. In other words, entries with 37343+ immediate operands must apear after the same instruction with 37344+ registers. 37345+ 37346+ Because of the lookup algorithm used, entries with the same opcode 37347+ name must be contiguous. */ 37348+ 37349+#define WR_xd INSN_WRITE_GPR_D 37350+#define WR_fd INSN_WRITE_FPR_D 37351+#define RD_xs1 INSN_READ_GPR_S 37352+#define RD_xs2 INSN_READ_GPR_T 37353+#define RD_fs1 INSN_READ_FPR_S 37354+#define RD_fs2 INSN_READ_FPR_T 37355+#define RD_fs3 INSN_READ_FPR_R 37356+ 37357+#define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) 37358+#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) 37359+#define MASK_RD (OP_MASK_RD << OP_SH_RD) 37360+#define MASK_IMM ENCODE_ITYPE_IMM(-1U) 37361+#define MASK_UIMM ENCODE_UTYPE_IMM(-1U) 37362+#define MASK_RM (OP_MASK_RM << OP_SH_RM) 37363+#define MASK_PRED (OP_MASK_PRED << OP_SH_PRED) 37364+#define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC) 37365+#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ) 37366+#define MASK_RL (OP_MASK_RL << OP_SH_RL) 37367+#define MASK_AQRL (MASK_AQ | MASK_RL) 37368+ 37369+static int match_opcode(const struct riscv_opcode *op, insn_t insn) 37370+{ 37371+ return (insn & op->mask) == op->match; 37372+} 37373+ 37374+static int match_never(const struct riscv_opcode *op ATTRIBUTE_UNUSED, 37375+ insn_t insn ATTRIBUTE_UNUSED) 37376+{ 37377+ return 0; 37378+} 37379+ 37380+static int match_rs1_eq_rs2(const struct riscv_opcode *op, insn_t insn) 37381+{ 37382+ return match_opcode(op, insn) && 37383+ ((insn & MASK_RS1) >> OP_SH_RS1) == ((insn & MASK_RS2) >> OP_SH_RS2); 37384+} 37385+ 37386+const struct riscv_opcode riscv_builtin_opcodes[] = 37387+{ 37388+/* These instructions appear first so that the disassembler will find 37389+ them first. The assemblers uses a hash table based on the 37390+ instruction name anyhow. */ 37391+/* name, isa, operands, match, mask, pinfo */ 37392+{"unimp", "I", "", 0, 0xffff, match_opcode, 0 }, 37393+{"nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, 37394+{"li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd }, /* addi */ 37395+{"li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, 37396+{"mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37397+{"move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37398+{"andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, WR_xd|RD_xs1 }, 37399+{"and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37400+{"and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37401+{"beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, 37402+{"beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, RD_xs1|RD_xs2 }, 37403+{"blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|RD_xs2 }, 37404+{"bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, 37405+{"ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, 37406+{"bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, 37407+{"bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, RD_xs1|RD_xs2 }, 37408+{"bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, RD_xs1|RD_xs2 }, 37409+{"bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, 37410+{"bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS|RD_xs2 }, 37411+{"blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, RD_xs1|RD_xs2 }, 37412+{"bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, RD_xs1|RD_xs2 }, 37413+{"bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, 37414+{"bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, 37415+{"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, 37416+{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, RD_xs1|RD_xs2 }, 37417+{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, WR_xd|RD_xs1 }, 37418+{"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37419+{"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37420+{"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37421+{"la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO }, 37422+{"lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO }, 37423+{"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, 37424+{"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, 37425+{"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */ 37426+{"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, WR_xd|RD_xs1 }, 37427+{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37428+{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37429+{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, WR_xd|RD_xs1 }, 37430+{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37431+{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37432+{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, WR_xd|RD_xs1 }, 37433+{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37434+{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37435+{"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37436+{"ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37437+{"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, 37438+{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|WR_xd }, 37439+{"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, WR_xd }, 37440+{"call", "I", "c", (X_T0 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, 37441+{"tail", "I", "c", (X_T0 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, 37442+{"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, 37443+{"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37444+{"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37445+{"jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37446+{"jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37447+{"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37448+{"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, WR_xd|RD_xs1 }, 37449+{"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, WR_xd|RD_xs1 }, 37450+{"lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, 37451+{"lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, WR_xd|RD_xs1 }, 37452+{"lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, 37453+{"lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, WR_xd|RD_xs1 }, 37454+{"lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, 37455+{"lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, WR_xd|RD_xs1 }, 37456+{"lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, 37457+{"lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, WR_xd|RD_xs1 }, 37458+{"lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, 37459+{"lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, WR_xd }, 37460+{"not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37461+{"ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, WR_xd|RD_xs1 }, 37462+{"or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37463+{"or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37464+{"auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, WR_xd }, 37465+{"seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37466+{"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, 37467+{"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37468+{"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, 37469+{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37470+{"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37471+{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, WR_xd|RD_xs1 }, 37472+{"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, WR_xd|RD_xs1 }, 37473+{"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37474+{"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37475+{"sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS|WR_xd|RD_xs1|RD_xs2 }, 37476+{"sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS|WR_xd|RD_xs1|RD_xs2 }, 37477+{"sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, RD_xs1|RD_xs2 }, 37478+{"sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, 37479+{"sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, RD_xs1|RD_xs2 }, 37480+{"sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, 37481+{"sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, RD_xs1|RD_xs2 }, 37482+{"sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, 37483+{"fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, 37484+{"fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, 37485+{"fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, 37486+{"rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, WR_xd }, 37487+{"rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, WR_xd }, 37488+{"rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, WR_xd }, 37489+{"rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, WR_xd }, 37490+{"rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, WR_xd }, 37491+{"rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, WR_xd }, 37492+{"sbreak", "I", "", MATCH_SBREAK, MASK_SBREAK, match_opcode, 0 }, 37493+{"scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, 37494+{"ecall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, 37495+{"xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, WR_xd|RD_xs1 }, 37496+{"xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37497+{"xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37498+{"lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, WR_xd|RD_xs1 }, 37499+{"lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO }, 37500+{"ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, WR_xd|RD_xs1 }, 37501+{"ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO }, 37502+{"sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, RD_xs1|RD_xs2 }, 37503+{"sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO }, 37504+{"sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37505+{"addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, WR_xd|RD_xs1 }, 37506+{"addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37507+{"addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37508+{"negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */ 37509+{"slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, WR_xd|RD_xs1 }, 37510+{"sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37511+{"sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37512+{"srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, WR_xd|RD_xs1 }, 37513+{"srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37514+{"srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37515+{"sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, WR_xd|RD_xs1 }, 37516+{"sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37517+{"sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, 37518+{"subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37519+ 37520+/* Atomic memory operation instruction subset */ 37521+{"lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37522+{"sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37523+{"amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37524+{"amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37525+{"amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37526+{"amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37527+{"amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37528+{"amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37529+{"amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37530+{"amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37531+{"amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37532+{"lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37533+{"sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37534+{"amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37535+{"amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37536+{"amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37537+{"amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37538+{"amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37539+{"amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37540+{"amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37541+{"amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37542+{"amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37543+{"lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37544+{"sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37545+{"amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37546+{"amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37547+{"amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37548+{"amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37549+{"amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37550+{"amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37551+{"amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37552+{"amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37553+{"amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37554+{"lr.w.sc", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37555+{"sc.w.sc", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37556+{"amoadd.w.sc", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37557+{"amoswap.w.sc", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37558+{"amoand.w.sc", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37559+{"amoor.w.sc", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37560+{"amoxor.w.sc", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37561+{"amomax.w.sc", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37562+{"amomaxu.w.sc", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37563+{"amomin.w.sc", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37564+{"amominu.w.sc", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37565+{"lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37566+{"sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37567+{"amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37568+{"amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37569+{"amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37570+{"amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37571+{"amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37572+{"amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37573+{"amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37574+{"amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37575+{"amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37576+{"lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37577+{"sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37578+{"amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37579+{"amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37580+{"amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37581+{"amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37582+{"amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37583+{"amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37584+{"amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37585+{"amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37586+{"amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37587+{"lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37588+{"sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37589+{"amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37590+{"amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37591+{"amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37592+{"amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37593+{"amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37594+{"amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37595+{"amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37596+{"amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37597+{"amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37598+{"lr.d.sc", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, 37599+{"sc.d.sc", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37600+{"amoadd.d.sc", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37601+{"amoswap.d.sc", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37602+{"amoand.d.sc", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37603+{"amoor.d.sc", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37604+{"amoxor.d.sc", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37605+{"amomax.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37606+{"amomaxu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37607+{"amomin.d.sc", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37608+{"amominu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37609+ 37610+/* Multiply/Divide instruction subset */ 37611+{"mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37612+{"mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37613+{"mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37614+{"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37615+{"div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37616+{"divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37617+{"rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37618+{"remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37619+{"mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37620+{"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37621+{"divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37622+{"remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37623+{"remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, 37624+ 37625+/* Single-precision floating-point instruction subset */ 37626+{"frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, WR_xd }, 37627+{"fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, RD_xs1 }, 37628+{"fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, WR_xd|RD_xs1 }, 37629+{"frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, WR_xd }, 37630+{"fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, RD_xs1 }, 37631+{"fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, WR_xd|RD_xs1 }, 37632+{"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, WR_xd }, 37633+{"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, RD_xs1 }, 37634+{"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, WR_xd|RD_xs1 }, 37635+{"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, WR_xd }, 37636+{"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, RD_xs1 }, 37637+{"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, WR_xd|RD_xs1 }, 37638+{"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, WR_fd|RD_xs1 }, 37639+{"flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, 37640+{"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, RD_xs1|RD_fs2 }, 37641+{"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, 37642+{"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, WR_xd|RD_fs1 }, 37643+{"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, WR_fd|RD_xs1 }, 37644+{"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, 37645+{"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, 37646+{"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, 37647+{"fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37648+{"fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37649+{"fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37650+{"fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37651+{"fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37652+{"fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37653+{"fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37654+{"fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37655+{"fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37656+{"fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37657+{"fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37658+{"fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37659+{"fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, WR_fd|RD_fs1 }, 37660+{"fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37661+{"fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37662+{"fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37663+{"fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37664+{"fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37665+{"fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37666+{"fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37667+{"fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37668+{"fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37669+{"fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37670+{"fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37671+{"fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, WR_xd|RD_fs1 }, 37672+{"fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37673+{"fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, WR_xd|RD_fs1 }, 37674+{"fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37675+{"fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, WR_fd|RD_xs1 }, 37676+{"fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37677+{"fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, WR_fd|RD_xs1 }, 37678+{"fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, WR_xd|RD_fs1 }, 37679+{"feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37680+{"flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37681+{"fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37682+{"fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37683+{"fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37684+{"fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37685+{"fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, WR_xd|RD_fs1 }, 37686+{"fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37687+{"fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, WR_xd|RD_fs1 }, 37688+{"fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37689+{"fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, WR_fd|RD_xs1 }, 37690+{"fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37691+{"fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, WR_fd|RD_xs1 }, 37692+ 37693+/* Double-precision floating-point instruction subset */ 37694+{"fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, WR_fd|RD_xs1 }, 37695+{"fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, 37696+{"fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, RD_xs1|RD_fs2 }, 37697+{"fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, 37698+{"fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, 37699+{"fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, 37700+{"fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, 37701+{"fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37702+{"fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37703+{"fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37704+{"fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37705+{"fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37706+{"fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37707+{"fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37708+{"fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37709+{"fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37710+{"fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37711+{"fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37712+{"fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37713+{"fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, WR_fd|RD_fs1 }, 37714+{"fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37715+{"fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37716+{"fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37717+{"fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37718+{"fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37719+{"fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37720+{"fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37721+{"fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37722+{"fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37723+{"fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37724+{"fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37725+{"fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, WR_xd|RD_fs1 }, 37726+{"fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37727+{"fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, WR_xd|RD_fs1 }, 37728+{"fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37729+{"fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37730+{"fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37731+{"fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37732+{"fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, WR_fd|RD_fs1 }, 37733+{"fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, WR_xd|RD_fs1 }, 37734+{"feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37735+{"flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37736+{"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37737+{"fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37738+{"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37739+{"fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, WR_xd|RD_fs1 }, 37740+{"fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, WR_fd|RD_xs1 }, 37741+{"fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37742+{"fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, WR_xd|RD_fs1 }, 37743+{"fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37744+{"fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, WR_xd|RD_fs1 }, 37745+{"fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37746+{"fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, WR_fd|RD_xs1 }, 37747+{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37748+{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, WR_fd|RD_xs1 }, 37749+ 37750+/* Supervisor instructions */ 37751+{"csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, WR_xd }, 37752+{"csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37753+{"csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, RD_xs1 }, 37754+{"csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37755+{"csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37756+{"csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37757+{"csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37758+{"csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37759+{"csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37760+{"csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, 37761+{"csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, WR_xd|RD_xs1 }, 37762+{"csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, WR_xd|RD_xs1 }, 37763+{"csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, WR_xd|RD_xs1 }, 37764+{"csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, WR_xd|RD_xs1 }, 37765+{"csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, WR_xd|RD_xs1 }, 37766+{"csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, WR_xd|RD_xs1 }, 37767+{"csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, WR_xd|RD_xs1 }, 37768+{"csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, WR_xd|RD_xs1 }, 37769+{"csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, WR_xd|RD_xs1 }, 37770+{"sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, 37771+{"eret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, 37772+{"mrts", "I", "", MATCH_MRTS, MASK_MRTS, match_opcode, 0 }, 37773+{"sfence.vm", "I", "", MATCH_SFENCE_VM | MASK_RS1, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, 37774+{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, RD_xs1 }, 37775+ 37776+/* Half-precision floating-point instruction subset */ 37777+{"flh", "Xhwacha", "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, WR_fd|RD_xs1 }, 37778+{"fsh", "Xhwacha", "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, RD_xs1|RD_fs2 }, 37779+{"fsgnj.h", "Xhwacha", "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37780+{"fsgnjn.h", "Xhwacha", "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37781+{"fsgnjx.h", "Xhwacha", "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37782+{"fadd.h", "Xhwacha", "D,S,T", MATCH_FADD_H | MASK_RM, MASK_FADD_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37783+{"fadd.h", "Xhwacha", "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37784+{"fsub.h", "Xhwacha", "D,S,T", MATCH_FSUB_H | MASK_RM, MASK_FSUB_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37785+{"fsub.h", "Xhwacha", "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37786+{"fmul.h", "Xhwacha", "D,S,T", MATCH_FMUL_H | MASK_RM, MASK_FMUL_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37787+{"fmul.h", "Xhwacha", "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37788+{"fdiv.h", "Xhwacha", "D,S,T", MATCH_FDIV_H | MASK_RM, MASK_FDIV_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37789+{"fdiv.h", "Xhwacha", "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37790+{"fsqrt.h", "Xhwacha", "D,S", MATCH_FSQRT_H | MASK_RM, MASK_FSQRT_H | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37791+{"fsqrt.h", "Xhwacha", "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, WR_fd|RD_fs1 }, 37792+{"fmin.h", "Xhwacha", "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37793+{"fmax.h", "Xhwacha", "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, 37794+{"fmadd.h", "Xhwacha", "D,S,T,R", MATCH_FMADD_H | MASK_RM, MASK_FMADD_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37795+{"fmadd.h", "Xhwacha", "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37796+{"fnmadd.h", "Xhwacha", "D,S,T,R", MATCH_FNMADD_H | MASK_RM, MASK_FNMADD_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37797+{"fnmadd.h", "Xhwacha", "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37798+{"fmsub.h", "Xhwacha", "D,S,T,R", MATCH_FMSUB_H | MASK_RM, MASK_FMSUB_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37799+{"fmsub.h", "Xhwacha", "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37800+{"fnmsub.h", "Xhwacha", "D,S,T,R", MATCH_FNMSUB_H | MASK_RM, MASK_FNMSUB_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37801+{"fnmsub.h", "Xhwacha", "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, 37802+{"fcvt.s.h", "Xhwacha", "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37803+{"fcvt.h.s", "Xhwacha", "D,S", MATCH_FCVT_H_S | MASK_RM, MASK_FCVT_H_S | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37804+{"fcvt.h.s", "Xhwacha", "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, WR_fd|RD_fs1 }, 37805+{"fcvt.d.h", "Xhwacha", "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37806+{"fcvt.h.d", "Xhwacha", "D,S", MATCH_FCVT_H_D | MASK_RM, MASK_FCVT_H_D | MASK_RM, match_opcode, WR_fd|RD_fs1 }, 37807+{"fcvt.h.d", "Xhwacha", "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, WR_fd|RD_fs1 }, 37808+{"feq.h", "Xhwacha", "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37809+{"flt.h", "Xhwacha", "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37810+{"fle.h", "Xhwacha", "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37811+{"fgt.h", "Xhwacha", "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37812+{"fge.h", "Xhwacha", "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, 37813+{"fmv.x.h", "Xhwacha", "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, WR_xd|RD_fs1 }, 37814+{"fmv.h.x", "Xhwacha", "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, WR_fd|RD_xs1 }, 37815+{"fcvt.w.h", "Xhwacha", "d,S", MATCH_FCVT_W_H | MASK_RM, MASK_FCVT_W_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37816+{"fcvt.w.h", "Xhwacha", "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, WR_xd|RD_fs1 }, 37817+{"fcvt.wu.h", "Xhwacha", "d,S", MATCH_FCVT_WU_H | MASK_RM, MASK_FCVT_WU_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37818+{"fcvt.wu.h", "Xhwacha", "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, WR_xd|RD_fs1 }, 37819+{"fcvt.h.w", "Xhwacha", "D,s", MATCH_FCVT_H_W, MASK_FCVT_H_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37820+{"fcvt.h.wu", "Xhwacha", "D,s", MATCH_FCVT_H_WU, MASK_FCVT_H_WU | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37821+{"fcvt.l.h", "Xhwacha", "d,S", MATCH_FCVT_L_H | MASK_RM, MASK_FCVT_L_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37822+{"fcvt.l.h", "Xhwacha", "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, WR_xd|RD_fs1 }, 37823+{"fcvt.lu.h", "Xhwacha", "d,S", MATCH_FCVT_LU_H | MASK_RM, MASK_FCVT_LU_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, 37824+{"fcvt.lu.h", "Xhwacha", "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, WR_xd|RD_fs1 }, 37825+{"fcvt.h.l", "Xhwacha", "D,s", MATCH_FCVT_H_L | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37826+{"fcvt.h.l", "Xhwacha", "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, WR_fd|RD_xs1 }, 37827+{"fcvt.h.lu", "Xhwacha", "D,s", MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, 37828+{"fcvt.h.lu", "Xhwacha", "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, WR_fd|RD_xs1 }, 37829+ 37830+/* Rocket Custom Coprocessor extension */ 37831+{"custom0", "Xcustom", "d,s,t,^j", MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2, match_opcode, 0}, 37832+{"custom0", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1, match_opcode, 0}, 37833+{"custom0", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD, match_opcode, 0}, 37834+{"custom0", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2, match_opcode, 0}, 37835+{"custom0", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1, match_opcode, 0}, 37836+{"custom0", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM0, MASK_CUSTOM0, match_opcode, 0}, 37837+{"custom1", "Xcustom", "d,s,t,^j", MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2, match_opcode, 0}, 37838+{"custom1", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1, match_opcode, 0}, 37839+{"custom1", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD, match_opcode, 0}, 37840+{"custom1", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2, match_opcode, 0}, 37841+{"custom1", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1, match_opcode, 0}, 37842+{"custom1", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM1, MASK_CUSTOM1, match_opcode, 0}, 37843+{"custom2", "Xcustom", "d,s,t,^j", MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2, match_opcode, 0}, 37844+{"custom2", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1, match_opcode, 0}, 37845+{"custom2", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD, match_opcode, 0}, 37846+{"custom2", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2, match_opcode, 0}, 37847+{"custom2", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1, match_opcode, 0}, 37848+{"custom2", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM2, MASK_CUSTOM2, match_opcode, 0}, 37849+{"custom3", "Xcustom", "d,s,t,^j", MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2, match_opcode, 0}, 37850+{"custom3", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1, match_opcode, 0}, 37851+{"custom3", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD, match_opcode, 0}, 37852+{"custom3", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2, match_opcode, 0}, 37853+{"custom3", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1, match_opcode, 0}, 37854+{"custom3", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM3, MASK_CUSTOM3, match_opcode, 0}, 37855+ 37856+/* Xhwacha extension */ 37857+{"stop", "Xhwacha", "", MATCH_STOP, MASK_STOP, match_opcode, 0}, 37858+{"utidx", "Xhwacha", "d", MATCH_UTIDX, MASK_UTIDX, match_opcode, WR_xd}, 37859+{"movz", "Xhwacha", "d,s,t", MATCH_MOVZ, MASK_MOVZ, match_opcode, WR_xd|RD_xs1|RD_xs2}, 37860+{"movn", "Xhwacha", "d,s,t", MATCH_MOVN, MASK_MOVN, match_opcode, WR_xd|RD_xs1|RD_xs2}, 37861+{"fmovz", "Xhwacha", "D,s,T", MATCH_FMOVZ, MASK_FMOVZ, match_opcode, WR_fd|RD_xs1|RD_fs2}, 37862+{"fmovn", "Xhwacha", "D,s,T", MATCH_FMOVN, MASK_FMOVN, match_opcode, WR_fd|RD_xs1|RD_fs2}, 37863+ 37864+/* unit stride */ 37865+/* xloads */ 37866+{"vld", "Xhwacha", "#d,s", MATCH_VLD, MASK_VLD, match_opcode, 0}, 37867+{"vlw", "Xhwacha", "#d,s", MATCH_VLW, MASK_VLW, match_opcode, 0}, 37868+{"vlwu", "Xhwacha", "#d,s", MATCH_VLWU, MASK_VLWU, match_opcode, 0}, 37869+{"vlh", "Xhwacha", "#d,s", MATCH_VLH, MASK_VLH, match_opcode, 0}, 37870+{"vlhu", "Xhwacha", "#d,s", MATCH_VLHU, MASK_VLHU, match_opcode, 0}, 37871+{"vlb", "Xhwacha", "#d,s", MATCH_VLB, MASK_VLB, match_opcode, 0}, 37872+{"vlbu", "Xhwacha", "#d,s", MATCH_VLBU, MASK_VLBU, match_opcode, 0}, 37873+/* floads */ 37874+{"vfld", "Xhwacha", "#D,s", MATCH_VFLD, MASK_VFLD, match_opcode, 0}, 37875+{"vflw", "Xhwacha", "#D,s", MATCH_VFLW, MASK_VFLW, match_opcode, 0}, 37876+ 37877+/* stride */ 37878+/* xloads */ 37879+{"vlstd", "Xhwacha", "#d,s,t", MATCH_VLSTD, MASK_VLSTD, match_opcode, 0}, 37880+{"vlstw", "Xhwacha", "#d,s,t", MATCH_VLSTW, MASK_VLSTW, match_opcode, 0}, 37881+{"vlstwu", "Xhwacha", "#d,s,t", MATCH_VLSTWU, MASK_VLSTWU, match_opcode, 0}, 37882+{"vlsth", "Xhwacha", "#d,s,t", MATCH_VLSTH, MASK_VLSTH, match_opcode, 0}, 37883+{"vlsthu", "Xhwacha", "#d,s,t", MATCH_VLSTHU, MASK_VLSTHU, match_opcode, 0}, 37884+{"vlstb", "Xhwacha", "#d,s,t", MATCH_VLSTB, MASK_VLSTB, match_opcode, 0}, 37885+{"vlstbu", "Xhwacha", "#d,s,t", MATCH_VLSTBU, MASK_VLSTBU, match_opcode, 0}, 37886+/* floads */ 37887+{"vflstd", "Xhwacha", "#D,s,t", MATCH_VFLSTD, MASK_VFLSTD, match_opcode, 0}, 37888+{"vflstw", "Xhwacha", "#D,s,t", MATCH_VFLSTW, MASK_VFLSTW, match_opcode, 0}, 37889+ 37890+/* segment */ 37891+/* xloads */ 37892+{"vlsegd", "Xhwacha", "#d,s,#n", MATCH_VLSEGD, MASK_VLSEGD, match_opcode, 0}, 37893+{"vlsegw", "Xhwacha", "#d,s,#n", MATCH_VLSEGW, MASK_VLSEGW, match_opcode, 0}, 37894+{"vlsegwu", "Xhwacha", "#d,s,#n", MATCH_VLSEGWU, MASK_VLSEGWU, match_opcode, 0}, 37895+{"vlsegh", "Xhwacha", "#d,s,#n", MATCH_VLSEGH, MASK_VLSEGH, match_opcode, 0}, 37896+{"vlseghu", "Xhwacha", "#d,s,#n", MATCH_VLSEGHU, MASK_VLSEGHU, match_opcode, 0}, 37897+{"vlsegb", "Xhwacha", "#d,s,#n", MATCH_VLSEGB, MASK_VLSEGB, match_opcode, 0}, 37898+{"vlsegbu", "Xhwacha", "#d,s,#n", MATCH_VLSEGBU, MASK_VLSEGBU, match_opcode, 0}, 37899+/* floads */ 37900+{"vflsegd", "Xhwacha", "#D,s,#n", MATCH_VFLSEGD, MASK_VFLSEGD, match_opcode, 0}, 37901+{"vflsegw", "Xhwacha", "#D,s,#n", MATCH_VFLSEGW, MASK_VFLSEGW, match_opcode, 0}, 37902+ 37903+/* stride segment */ 37904+/* xloads */ 37905+{"vlsegstd", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTD, MASK_VLSEGSTD, match_opcode, 0}, 37906+{"vlsegstw", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTW, MASK_VLSEGSTW, match_opcode, 0}, 37907+{"vlsegstwu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTWU, MASK_VLSEGSTWU, match_opcode, 0}, 37908+{"vlsegsth", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTH, MASK_VLSEGSTH, match_opcode, 0}, 37909+{"vlsegsthu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTHU, MASK_VLSEGSTHU, match_opcode, 0}, 37910+{"vlsegstb", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTB, MASK_VLSEGSTB, match_opcode, 0}, 37911+{"vlsegstbu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTBU, MASK_VLSEGSTBU, match_opcode, 0}, 37912+/* floads */ 37913+{"vflsegstd", "Xhwacha", "#D,s,t,#n", MATCH_VFLSEGSTD, MASK_VFLSEGSTD, match_opcode, 0}, 37914+{"vflsegstw", "Xhwacha", "#D,s,t,#n", MATCH_VFLSEGSTW, MASK_VFLSEGSTW, match_opcode, 0}, 37915+ 37916+/* unit stride */ 37917+/* xstores */ 37918+{"vsd", "Xhwacha", "#d,s", MATCH_VSD, MASK_VSD, match_opcode, 0}, 37919+{"vsw", "Xhwacha", "#d,s", MATCH_VSW, MASK_VSW, match_opcode, 0}, 37920+{"vsh", "Xhwacha", "#d,s", MATCH_VSH, MASK_VSH, match_opcode, 0}, 37921+{"vsb", "Xhwacha", "#d,s", MATCH_VSB, MASK_VSB, match_opcode, 0}, 37922+/* fstores */ 37923+{"vfsd", "Xhwacha", "#D,s", MATCH_VFSD, MASK_VFSD, match_opcode, 0}, 37924+{"vfsw", "Xhwacha", "#D,s", MATCH_VFSW, MASK_VFSW, match_opcode, 0}, 37925+ 37926+/* stride */ 37927+/* xstores */ 37928+{"vsstd", "Xhwacha", "#d,s,t", MATCH_VSSTD, MASK_VSSTD, match_opcode, 0}, 37929+{"vsstw", "Xhwacha", "#d,s,t", MATCH_VSSTW, MASK_VSSTW, match_opcode, 0}, 37930+{"vssth", "Xhwacha", "#d,s,t", MATCH_VSSTH, MASK_VSSTH, match_opcode, 0}, 37931+{"vsstb", "Xhwacha", "#d,s,t", MATCH_VSSTB, MASK_VSSTB, match_opcode, 0}, 37932+/* fstores */ 37933+{"vfsstd", "Xhwacha", "#D,s,t", MATCH_VFSSTD, MASK_VFSSTD, match_opcode, 0}, 37934+{"vfsstw", "Xhwacha", "#D,s,t", MATCH_VFSSTW, MASK_VFSSTW, match_opcode, 0}, 37935+ 37936+/* segment */ 37937+/* xstores */ 37938+{"vssegd", "Xhwacha", "#d,s,#n", MATCH_VSSEGD, MASK_VSSEGD, match_opcode, 0}, 37939+{"vssegw", "Xhwacha", "#d,s,#n", MATCH_VSSEGW, MASK_VSSEGW, match_opcode, 0}, 37940+{"vssegh", "Xhwacha", "#d,s,#n", MATCH_VSSEGH, MASK_VSSEGH, match_opcode, 0}, 37941+{"vssegb", "Xhwacha", "#d,s,#n", MATCH_VSSEGB, MASK_VSSEGB, match_opcode, 0}, 37942+/* fstores */ 37943+{"vfssegd", "Xhwacha", "#D,s,#n", MATCH_VFSSEGD, MASK_VFSSEGD, match_opcode, 0}, 37944+{"vfssegw", "Xhwacha", "#D,s,#n", MATCH_VFSSEGW, MASK_VFSSEGW, match_opcode, 0}, 37945+ 37946+/* stride segment */ 37947+/* xsegstores */ 37948+{"vssegstd", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTD, MASK_VSSEGSTD, match_opcode, 0}, 37949+{"vssegstw", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTW, MASK_VSSEGSTW, match_opcode, 0}, 37950+{"vssegsth", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTH, MASK_VSSEGSTH, match_opcode, 0}, 37951+{"vssegstb", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTB, MASK_VSSEGSTB, match_opcode, 0}, 37952+/* fsegstores */ 37953+{"vfssegstd", "Xhwacha", "#D,s,t,#n", MATCH_VFSSEGSTD, MASK_VFSSEGSTD, match_opcode, 0}, 37954+{"vfssegstw", "Xhwacha", "#D,s,t,#n", MATCH_VFSSEGSTW, MASK_VFSSEGSTW, match_opcode, 0}, 37955+ 37956+{"vsetcfg", "Xhwacha", "s", MATCH_VSETCFG, MASK_VSETCFG | MASK_IMM, match_opcode, 0}, 37957+{"vsetcfg", "Xhwacha", "#g,#f", MATCH_VSETCFG, MASK_VSETCFG | MASK_RS1, match_opcode, 0}, 37958+{"vsetcfg", "Xhwacha", "s,#g,#f", MATCH_VSETCFG, MASK_VSETCFG, match_opcode, 0}, 37959+{"vsetucfg", "Xhwacha", "d,u", MATCH_LUI, MASK_LUI, match_opcode, INSN_ALIAS | WR_xd}, 37960+{"vsetvl", "Xhwacha", "d,s", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0}, 37961+{"vgetcfg", "Xhwacha", "d", MATCH_VGETCFG, MASK_VGETCFG, match_opcode, 0}, 37962+{"vgetvl", "Xhwacha", "d", MATCH_VGETVL, MASK_VGETVL, match_opcode, 0}, 37963+ 37964+{"vmvv", "Xhwacha", "#d,#s", MATCH_VMVV, MASK_VMVV, match_opcode, 0}, 37965+{"vmsv", "Xhwacha", "#d,s", MATCH_VMSV, MASK_VMSV, match_opcode, 0}, 37966+{"vfmvv", "Xhwacha", "#D,#S", MATCH_VFMVV, MASK_VFMVV, match_opcode, 0}, 37967+{"vfmsv.d", "Xhwacha", "#D,s", MATCH_VFMSV_D, MASK_VFMSV_D, match_opcode, 0}, 37968+{"vfmsv.s", "Xhwacha", "#D,s", MATCH_VFMSV_S, MASK_VFMSV_S, match_opcode, 0}, 37969+ 37970+{"vf", "Xhwacha", "q(s)", MATCH_VF, MASK_VF, match_opcode, 0}, 37971+{"vf", "Xhwacha", "A,s", 0, (int) M_VF, match_never, INSN_MACRO }, 37972+ 37973+{"vxcptcause", "Xhwacha", "d", MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE, match_opcode, 0}, 37974+{"vxcptaux", "Xhwacha", "d", MATCH_VXCPTAUX, MASK_VXCPTAUX, match_opcode, 0}, 37975+ 37976+{"vxcptsave", "Xhwacha", "s", MATCH_VXCPTSAVE, MASK_VXCPTSAVE, match_opcode, 0}, 37977+{"vxcptrestore", "Xhwacha", "s", MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE, match_opcode, 0}, 37978+{"vxcptkill", "Xhwacha", "", MATCH_VXCPTKILL, MASK_VXCPTKILL, match_opcode, 0}, 37979+ 37980+{"vxcptevac", "Xhwacha", "s", MATCH_VXCPTEVAC, MASK_VXCPTEVAC, match_opcode, 0}, 37981+{"vxcpthold", "Xhwacha", "s", MATCH_VXCPTHOLD, MASK_VXCPTHOLD, match_opcode, 0}, 37982+{"venqcmd", "Xhwacha", "s,t", MATCH_VENQCMD, MASK_VENQCMD, match_opcode, 0}, 37983+{"venqimm1", "Xhwacha", "s,t", MATCH_VENQIMM1, MASK_VENQIMM1, match_opcode, 0}, 37984+{"venqimm2", "Xhwacha", "s,t", MATCH_VENQIMM2, MASK_VENQIMM2, match_opcode, 0}, 37985+{"venqcnt", "Xhwacha", "s,t", MATCH_VENQCNT, MASK_VENQCNT, match_opcode, 0}, 37986+}; 37987+ 37988+#define RISCV_NUM_OPCODES \ 37989+ ((sizeof riscv_builtin_opcodes) / (sizeof (riscv_builtin_opcodes[0]))) 37990+const int bfd_riscv_num_builtin_opcodes = RISCV_NUM_OPCODES; 37991+ 37992+/* const removed from the following to allow for dynamic extensions to the 37993+ * built-in instruction set. */ 37994+struct riscv_opcode *riscv_opcodes = 37995+ (struct riscv_opcode *) riscv_builtin_opcodes; 37996+int bfd_riscv_num_opcodes = RISCV_NUM_OPCODES; 37997+#undef RISCV_NUM_OPCODES 37998