1 #include "cmi8738.h" 2 #include "mixer.h" 3 4 /* global value */ 5 DEV_STRUCT dev; 6 aud_sub_dev_conf_t aud_conf[3]; 7 sub_dev_t sub_dev[3]; 8 special_file_t special_file[3]; 9 drv_t drv; 10 11 /* internal function */ 12 static int dev_probe(void); 13 static int set_sample_rate(u32_t rate, int num); 14 static int set_stereo(u32_t stereo, int num); 15 static int set_bits(u32_t bits, int sub_dev); 16 static int set_frag_size(u32_t frag_size, int num); 17 static int set_sign(u32_t val, int num); 18 static int get_frag_size(u32_t *val, int *len, int num); 19 static int free_buf(u32_t *val, int *len, int num); 20 21 /* developer interface */ 22 static int dev_reset(u32_t *base); 23 static void dev_configure(u32_t *base); 24 static void dev_init_mixer(u32_t *base); 25 static void dev_set_sample_rate(u32_t *base, u16_t sample_rate); 26 static void dev_set_format(u32_t *base, u32_t bits, u32_t sign, 27 u32_t stereo, u32_t sample_count); 28 static void dev_start_channel(u32_t *base, int sub_dev); 29 static void dev_stop_channel(u32_t *base, int sub_dev); 30 static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev); 31 static u32_t dev_read_dma_current(u32_t *base, int sub_dev); 32 static void dev_pause_dma(u32_t *base, int sub_dev); 33 static void dev_resume_dma(u32_t *base, int sub_dev); 34 static void dev_intr_other(u32_t *base, u32_t status); 35 static u32_t dev_read_clear_intr_status(u32_t *base); 36 static void dev_intr_enable(u32_t *base, int flag); 37 38 /* ======= Developer implemented function ======= */ 39 /* ====== Self-defined function ====== */ 40 void dev_io_set_clear(u32_t base, u32_t reg, u32_t val, int flag) { 41 u32_t data; 42 data = sdr_in32(base, reg); 43 if (flag == 0) 44 data &= ~val; 45 else if (flag == 1) 46 data |= val; 47 sdr_out32(base, reg, data); 48 } 49 50 /* ====== Mixer handling interface ======*/ 51 /* Write the data to mixer register (### WRITE_MIXER_REG ###) */ 52 void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) { 53 u32_t base0 = base[0]; 54 sdr_out8(base0, REG_SB_ADDR, reg); 55 sdr_out8(base0, REG_SB_DATA, val); 56 } 57 58 /* Read the data from mixer register (### READ_MIXER_REG ###) */ 59 u32_t dev_mixer_read(u32_t *base, u32_t reg) { 60 u32_t base0 = base[0]; 61 sdr_out8(base0, REG_SB_ADDR, reg); 62 return sdr_in8(base0, REG_SB_DATA); 63 } 64 65 /* ====== Developer interface ======*/ 66 67 /* Reset the device (### RESET_HARDWARE_CAN_FAIL ###) 68 * -- Return OK means success, Others means failure */ 69 static int dev_reset(u32_t *base) { 70 u32_t data, base0 = base[0]; 71 dev_io_set_clear(base0, REG_MISC_CTRL, CMD_POWER_DOWN, 0); 72 dev_io_set_clear(base0, REG_MISC_CTRL, CMD_RESET, 1); 73 micro_delay(100); 74 dev_io_set_clear(base0, REG_MISC_CTRL, CMD_RESET, 0); 75 return OK; 76 } 77 78 /* Configure hardware registers (### CONF_HARDWARE ###) */ 79 static void dev_configure(u32_t *base) { 80 u32_t data, base0 = base[0]; 81 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ADC_C0, 0); 82 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ADC_C1, 1); 83 dev_io_set_clear(base0, REG_MISC_CTRL, CMD_N4SPK3D, 1); 84 dev_io_set_clear(base0, REG_FUNC_CTRL1, CMD_SPDIF_ENA, 0); 85 dev_io_set_clear(base0, REG_FUNC_CTRL1, CMD_SPDIF_LOOP, 0); 86 sdr_out8(base0, REG_EXT_INDEX, 0x03); 87 sdr_out8(base0, REG_MIX_INPUT, 0x0f); 88 } 89 90 /* Initialize the mixer (### INIT_MIXER ###) */ 91 static void dev_init_mixer(u32_t *base) { 92 dev_mixer_write(base, 0, 0); 93 dev_mixer_write(base, MIXER_ADCL, 0x1f); 94 dev_mixer_write(base, MIXER_ADCR, 0x7f); 95 dev_mixer_write(base, MIXER_OUT_MUTE, 0x7f); 96 } 97 98 /* Set DAC and ADC sample rate (### SET_SAMPLE_RATE ###) */ 99 static void dev_set_sample_rate(u32_t *base, u16_t sample_rate) { 100 int i; 101 u32_t data, rate = 0, base0 = base[0]; 102 for (i = 0; i < 8; i++) { 103 if (sample_rate == g_sample_rate[i]) { 104 rate = i; 105 break; 106 } 107 } 108 data = sdr_in32(base0, REG_FUNC_CTRL1); 109 data &=~ (0xe000 | 0x1c00); 110 data |= (rate << 13) & 0xe000; 111 data |= (rate << 10) & 0x1c00; 112 sdr_out32(base0, REG_FUNC_CTRL1, data); 113 } 114 115 /* Set DAC and ADC format (### SET_FORMAT ###)*/ 116 static void dev_set_format(u32_t *base, u32_t bits, u32_t sign, 117 u32_t stereo, u32_t sample_count) { 118 u32_t format = 0, data, base0 = base[0]; 119 if (stereo == 1) 120 format |= FMT_STEREO; 121 if (bits == 16) 122 format |= FMT_BIT16; 123 data = sdr_in32(base0, REG_FORMAT); 124 data &= ~0x00000003; 125 data |= format << 0; 126 data &= ~0x0000000c; 127 data |= format << 2; 128 sdr_out32(base0, REG_FORMAT, data); 129 dev_io_set_clear(base0, REG_EXT_MISC, 0x10000000, 0); 130 sdr_out16(base0, REG_DAC_SAMPLE_COUNT, sample_count - 1); 131 sdr_out16(base0, REG_ADC_SAMPLE_COUNT, sample_count - 1); 132 } 133 134 /* Start the channel (### START_CHANNEL ###) */ 135 static void dev_start_channel(u32_t *base, int sub_dev) { 136 u32_t data, base0 = base[0]; 137 if (sub_dev == DAC) { 138 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ENA_C0, 1); 139 } 140 else if (sub_dev == ADC) { 141 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ENA_C1, 1); 142 } 143 } 144 145 /* Stop the channel (### STOP_CHANNEL ###) */ 146 static void dev_stop_channel(u32_t *base, int sub_dev) { 147 u32_t data, base0 = base[0]; 148 if (sub_dev == DAC) { 149 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ENA_C0, 0); 150 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_RESET_C0, 1); 151 micro_delay(100); 152 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_RESET_C0, 0); 153 } 154 else if (sub_dev == ADC) { 155 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ENA_C1, 0); 156 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_RESET_C1, 1); 157 micro_delay(100); 158 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_RESET_C1, 0); 159 } 160 } 161 162 /* Set DMA address and length (### SET_DMA ###) */ 163 static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) { 164 u32_t base0 = base[0]; 165 if (sub_dev == DAC) { 166 sdr_out32(base0, REG_DAC_DMA_ADDR, dma); 167 sdr_out16(base0, REG_DAC_DMA_LEN, len - 1); 168 } 169 else if (sub_dev == ADC) { 170 sdr_out32(base0, REG_ADC_DMA_ADDR, dma); 171 sdr_out16(base0, REG_ADC_DMA_LEN, len - 1); 172 } 173 } 174 175 /* Read current address (### READ_DMA_CURRENT_ADDR ###) */ 176 static u32_t dev_read_dma_current(u32_t *base, int sub_dev) { 177 u32_t data, base0 = base[0]; 178 if (sub_dev == DAC) 179 data = sdr_in16(base0, REG_DAC_CUR_ADDR); 180 else if (sub_dev == ADC) 181 data = sdr_in16(base0, REG_ADC_CUR_ADDR); 182 return data; 183 } 184 185 /* Pause the DMA (### PAUSE_DMA ###) */ 186 static void dev_pause_dma(u32_t *base, int sub_dev) { 187 u32_t base0 = base[0]; 188 if (sub_dev == DAC) 189 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_PAUSE_C0, 1); 190 else if (sub_dev == ADC) 191 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_PAUSE_C1, 1); 192 } 193 194 /* Resume the DMA (### RESUME_DMA ###) */ 195 static void dev_resume_dma(u32_t *base, int sub_dev) { 196 u32_t base0 = base[0]; 197 if (sub_dev == DAC) 198 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_PAUSE_C0, 0); 199 else if (sub_dev == ADC) 200 dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_PAUSE_C1, 0); 201 } 202 203 /* Read and clear interrupt status (### READ_CLEAR_INTR_STS ###) 204 * -- Return interrupt status */ 205 static u32_t dev_read_clear_intr_status(u32_t *base) { 206 u32_t data, base0 = base[0]; 207 data = sdr_in32(base0, REG_INTR_STS); 208 dev_intr_enable(base, INTR_DISABLE); 209 dev_intr_enable(base, INTR_ENABLE); 210 return data; 211 } 212 213 /* Enable or disable interrupt (### INTR_ENBALE_DISABLE ###) */ 214 static void dev_intr_enable(u32_t *base, int flag) { 215 u32_t data, base0 = base[0]; 216 data = sdr_in32(base0, REG_INTR_STS); 217 if (flag == INTR_ENABLE) 218 sdr_out32(base0, REG_INTR_CTRL, data | CMD_INTR_ENABLE); 219 else if (flag == INTR_DISABLE) 220 sdr_out32(base0, REG_INTR_CTRL, data & ~CMD_INTR_ENABLE); 221 } 222 223 /* ======= Common driver function ======= */ 224 /* Probe the device */ 225 static int dev_probe(void) { 226 int devind, i, ioflag; 227 u32_t device, bar, size, base; 228 u16_t vid, did, temp; 229 u8_t *reg; 230 231 pci_init(); 232 device = pci_first_dev(&devind, &vid, &did); 233 while (device > 0) { 234 if (vid == VENDOR_ID && did == DEVICE_ID) 235 break; 236 device = pci_next_dev(&devind, &vid, &did); 237 } 238 if (vid != VENDOR_ID || did != DEVICE_ID) 239 return EIO; 240 pci_reserve(devind); 241 242 for (i = 0; i < 6; i++) 243 dev.base[i] = 0; 244 #ifdef DMA_BASE_IOMAP 245 for (i = 0; i < 6; i++) { 246 if (pci_get_bar(devind, PCI_BAR + i * 4, &base, &size, &ioflag)) { 247 /* printf("SDR: Fail to get PCI BAR %d\n", i); */ 248 continue; 249 } 250 if (ioflag) { 251 /* printf("SDR: PCI BAR %d is not for memory\n", i); */ 252 continue; 253 } 254 if ((reg = vm_map_phys(SELF, (void *)base, size)) == MAP_FAILED) { 255 printf("SDR: Fail to map hardware registers from PCI\n"); 256 return -EIO; 257 } 258 dev.base[i] = (u32_t)reg; 259 } 260 #else 261 /* Get PCI BAR0-5 */ 262 for (i = 0; i < 6; i++) 263 dev.base[i] = pci_attr_r32(devind, PCI_BAR + i * 4) & 0xffffffe0; 264 #endif 265 dev.name = pci_dev_name(vid, did); 266 dev.irq = pci_attr_r8(devind, PCI_ILR); 267 dev.revision = pci_attr_r8(devind, PCI_REV); 268 dev.did = did; 269 dev.vid = vid; 270 dev.devind = devind; 271 temp = pci_attr_r16(devind, PCI_CR); 272 pci_attr_w16(devind, PCI_CR, temp | 0x105); 273 274 #ifdef MY_DEBUG 275 printf("SDR: Hardware name is %s\n", dev.name); 276 for (i = 0; i < 6; i++) 277 printf("SDR: PCI BAR%d is 0x%08x\n", i, dev.base[i]); 278 printf("SDR: IRQ number is 0x%02x\n", dev.irq); 279 #endif 280 return OK; 281 } 282 283 /* Set sample rate in configuration */ 284 static int set_sample_rate(u32_t rate, int num) { 285 aud_conf[num].sample_rate = rate; 286 return OK; 287 } 288 289 /* Set stereo in configuration */ 290 static int set_stereo(u32_t stereo, int num) { 291 aud_conf[num].stereo = stereo; 292 return OK; 293 } 294 295 /* Set sample bits in configuration */ 296 static int set_bits(u32_t bits, int num) { 297 aud_conf[num].nr_of_bits = bits; 298 return OK; 299 } 300 301 /* Set fragment size in configuration */ 302 static int set_frag_size(u32_t frag_size, int num) { 303 if (frag_size > (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments) || 304 frag_size < sub_dev[num].MinFragmentSize) { 305 return EINVAL; 306 } 307 aud_conf[num].fragment_size = frag_size; 308 return OK; 309 } 310 311 /* Set frame sign in configuration */ 312 static int set_sign(u32_t val, int num) { 313 aud_conf[num].sign = val; 314 return OK; 315 } 316 317 /* Get maximum fragment size */ 318 static int get_max_frag_size(u32_t *val, int *len, int num) { 319 *len = sizeof(*val); 320 *val = (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments); 321 return OK; 322 } 323 324 /* Return 1 if there are free buffers */ 325 static int free_buf(u32_t *val, int *len, int num) { 326 *len = sizeof(*val); 327 if (sub_dev[num].BufLength == sub_dev[num].NrOfExtraBuffers) 328 *val = 0; 329 else 330 *val = 1; 331 return OK; 332 } 333 334 /* Get the current sample counter */ 335 static int get_samples_in_buf(u32_t *result, int *len, int chan) { 336 u32_t res; 337 /* READ_DMA_CURRENT_ADDR */ 338 res = dev_read_dma_current(dev.base, chan); 339 *result = (u32_t)(sub_dev[chan].BufLength * 8192) + res; 340 return OK; 341 } 342 343 /* ======= [Audio interface] Initialize data structure ======= */ 344 int drv_init(void) { 345 drv.DriverName = DRIVER_NAME; 346 drv.NrOfSubDevices = 3; 347 drv.NrOfSpecialFiles = 3; 348 349 sub_dev[DAC].readable = 0; 350 sub_dev[DAC].writable = 1; 351 sub_dev[DAC].DmaSize = 64 * 1024; 352 sub_dev[DAC].NrOfDmaFragments = 2; 353 sub_dev[DAC].MinFragmentSize = 1024; 354 sub_dev[DAC].NrOfExtraBuffers = 4; 355 356 sub_dev[ADC].readable = 1; 357 sub_dev[ADC].writable = 0; 358 sub_dev[ADC].DmaSize = 64 * 1024; 359 sub_dev[ADC].NrOfDmaFragments = 2; 360 sub_dev[ADC].MinFragmentSize = 1024; 361 sub_dev[ADC].NrOfExtraBuffers = 4; 362 363 sub_dev[MIX].writable = 0; 364 sub_dev[MIX].readable = 0; 365 366 special_file[0].minor_dev_nr = 0; 367 special_file[0].write_chan = DAC; 368 special_file[0].read_chan = NO_CHANNEL; 369 special_file[0].io_ctl = DAC; 370 371 special_file[1].minor_dev_nr = 1; 372 special_file[1].write_chan = NO_CHANNEL; 373 special_file[1].read_chan = ADC; 374 special_file[1].io_ctl = ADC; 375 376 special_file[2].minor_dev_nr = 2; 377 special_file[2].write_chan = NO_CHANNEL; 378 special_file[2].read_chan = NO_CHANNEL; 379 special_file[2].io_ctl = MIX; 380 381 return OK; 382 } 383 384 /* ======= [Audio interface] Initialize hardware ======= */ 385 int drv_init_hw(void) { 386 int i; 387 388 /* Match the device */ 389 if (dev_probe()) { 390 printf("SDR: No sound card found\n"); 391 return EIO; 392 } 393 394 /* Reset the device */ 395 /* ### RESET_HARDWARE_CAN_FAIL ### */ 396 if (dev_reset(dev.base)) { 397 printf("SDR: Fail to reset the device\n"); 398 return EIO; 399 } 400 401 /* Configure the hardware */ 402 /* ### CONF_HARDWARE ### */ 403 dev_configure(dev.base); 404 405 /* Initialize the mixer */ 406 /* ### INIT_MIXER ### */ 407 dev_init_mixer(dev.base); 408 409 /* Set default mixer volume */ 410 dev_set_default_volume(dev.base); 411 412 /* Initialize subdevice data */ 413 for (i = 0; i < drv.NrOfSubDevices; i++) { 414 if (i == MIX) 415 continue; 416 aud_conf[i].busy = 0; 417 aud_conf[i].stereo = 1; 418 aud_conf[i].sample_rate = 44100; 419 aud_conf[i].nr_of_bits = 16; 420 aud_conf[i].sign = 1; 421 aud_conf[i].fragment_size = 422 sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments; 423 } 424 return OK; 425 } 426 427 /* ======= [Audio interface] Driver reset =======*/ 428 int drv_reset(void) { 429 /* ### RESET_HARDWARE_CAN_FAIL ### */ 430 return dev_reset(dev.base); 431 } 432 433 /* ======= [Audio interface] Driver start ======= */ 434 int drv_start(int sub_dev, int DmaMode) { 435 int sample_count; 436 437 /* Set DAC and ADC sample rate */ 438 /* ### SET_SAMPLE_RATE ### */ 439 dev_set_sample_rate(dev.base, aud_conf[sub_dev].sample_rate); 440 441 sample_count = aud_conf[sub_dev].fragment_size; 442 #ifdef DMA_LENGTH_BY_FRAME 443 sample_count = sample_count / (aud_conf[sub_dev].nr_of_bits * (aud_conf[sub_dev].stereo + 1) / 8); 444 #endif 445 /* Set DAC and ADC format */ 446 /* ### SET_FORMAT ### */ 447 dev_set_format(dev.base, aud_conf[sub_dev].nr_of_bits, 448 aud_conf[sub_dev].sign, aud_conf[sub_dev].stereo, sample_count); 449 450 drv_reenable_int(sub_dev); 451 452 /* Start the channel */ 453 /* ### START_CHANNEL ### */ 454 dev_start_channel(dev.base, sub_dev); 455 aud_conf[sub_dev].busy = 1; 456 457 return OK; 458 } 459 460 /* ======= [Audio interface] Driver start ======= */ 461 int drv_stop(int sub_dev) { 462 u32_t data; 463 464 /* INTR_ENABLE_DISABLE */ 465 dev_intr_enable(dev.base, INTR_DISABLE); 466 467 /* ### STOP_CHANNEL ### */ 468 dev_stop_channel(dev.base, sub_dev); 469 470 aud_conf[sub_dev].busy = 0; 471 return OK; 472 } 473 474 /* ======= [Audio interface] Enable interrupt ======= */ 475 int drv_reenable_int(int chan) { 476 /* INTR_ENABLE_DISABLE */ 477 dev_intr_enable(dev.base, INTR_ENABLE); 478 return OK; 479 } 480 481 /* ======= [Audio interface] I/O control ======= */ 482 int drv_io_ctl(unsigned long request, void *val, int *len, int sub_dev) { 483 int status; 484 switch (request) { 485 case DSPIORATE: 486 status = set_sample_rate(*((u32_t *)val), sub_dev); 487 break; 488 case DSPIOSTEREO: 489 status = set_stereo(*((u32_t *)val), sub_dev); 490 break; 491 case DSPIOBITS: 492 status = set_bits(*((u32_t *)val), sub_dev); 493 break; 494 case DSPIOSIZE: 495 status = set_frag_size(*((u32_t *)val), sub_dev); 496 break; 497 case DSPIOSIGN: 498 status = set_sign(*((u32_t *)val), sub_dev); 499 break; 500 case DSPIOMAX: 501 status = get_max_frag_size(val, len, sub_dev); 502 break; 503 case DSPIORESET: 504 status = drv_reset(); 505 break; 506 case DSPIOFREEBUF: 507 status = free_buf(val, len, sub_dev); 508 break; 509 case DSPIOSAMPLESINBUF: 510 status = get_samples_in_buf(val, len, sub_dev); 511 break; 512 case DSPIOPAUSE: 513 status = drv_pause(sub_dev); 514 break; 515 case DSPIORESUME: 516 status = drv_resume(sub_dev); 517 break; 518 case MIXIOGETVOLUME: 519 /* ### GET_SET_VOLUME ### */ 520 status = get_set_volume(dev.base, val, GET_VOL); 521 break; 522 case MIXIOSETVOLUME: 523 /* ### GET_SET_VOLUME ### */ 524 status = get_set_volume(dev.base, val, SET_VOL); 525 break; 526 default: 527 status = EINVAL; 528 break; 529 } 530 return status; 531 } 532 533 /* ======= [Audio interface] Get request number ======= */ 534 int drv_get_irq(char *irq) { 535 *irq = dev.irq; 536 return OK; 537 } 538 539 /* ======= [Audio interface] Get fragment size ======= */ 540 int drv_get_frag_size(u32_t *frag_size, int sub_dev) { 541 *frag_size = aud_conf[sub_dev].fragment_size; 542 return OK; 543 } 544 545 /* ======= [Audio interface] Set DMA channel ======= */ 546 int drv_set_dma(u32_t dma, u32_t length, int chan) { 547 #ifdef DMA_LENGTH_BY_FRAME 548 length = length / (aud_conf[chan].nr_of_bits * (aud_conf[chan].stereo + 1) / 8); 549 #endif 550 /* ### SET_DMA ### */ 551 dev_set_dma(dev.base, dma, length, chan); 552 return OK; 553 } 554 555 /* ======= [Audio interface] Get interrupt summary status ======= */ 556 int drv_int_sum(void) { 557 u32_t status; 558 /* ### READ_CLEAR_INTR_STS ### */ 559 status = dev_read_clear_intr_status(dev.base); 560 dev.intr_status = status; 561 #ifdef MY_DEBUG 562 printf("SDR: Interrupt status is 0x%08x\n", status); 563 #endif 564 return (status & (INTR_STS_DAC | INTR_STS_ADC)); 565 } 566 567 /* ======= [Audio interface] Handle interrupt status ======= */ 568 int drv_int(int sub_dev) { 569 u32_t mask; 570 571 /* ### CHECK_INTR_DAC ### */ 572 if (sub_dev == DAC) 573 mask = INTR_STS_DAC; 574 /* ### CHECK_INTR_ADC ### */ 575 else if (sub_dev == ADC) 576 mask = INTR_STS_ADC; 577 else 578 return 0; 579 580 return dev.intr_status & mask; 581 } 582 583 /* ======= [Audio interface] Pause DMA ======= */ 584 int drv_pause(int sub_dev) { 585 /* ### PAUSE_DMA ### */ 586 dev_pause_dma(dev.base, sub_dev); 587 return OK; 588 } 589 590 /* ======= [Audio interface] Resume DMA ======= */ 591 int drv_resume(int sub_dev) { 592 /* ### RESUME_DMA ### */ 593 dev_resume_dma(dev.base, sub_dev); 594 return OK; 595 } 596