1 #ifndef ES1371_H 2 #define ES1371_H 3 /* best viewed with tabsize=4 */ 4 5 #include <minix/audio_fw.h> 6 #include <sys/types.h> 7 #include <sys/ioc_sound.h> 8 #include <minix/sound.h> 9 10 11 /* set your vendor and device ID's here */ 12 #define VENDOR_ID 0x1274 13 #define DEVICE_ID 0x1371 14 #define DRIVER_NAME "ES1371" 15 16 17 /* channels or subdevices */ 18 #define DAC1_CHAN 0 19 #define ADC1_CHAN 1 20 #define MIXER 2 21 #define DAC2_CHAN 3 22 23 24 /* PCI command register defines */ 25 #define SERR_EN 0x0100 26 #define PCI_MASTER 0x0004 27 #define IO_ACCESS 0x0001 28 29 30 /* Interrupt/Chip Select Control */ 31 #define CHIP_SEL_CTRL 0x00 32 #define ADC1_EN 0x0010 33 #define DAC1_EN 0x0040 34 #define DAC2_EN 0x0020 35 #define CCB_INTRM 0x0400 36 37 38 /* Interrupt/Chip Select Status */ 39 #define INTERRUPT_STATUS 0x04 40 #define ADC 0x0001 41 #define DAC2 0x0002 42 #define DAC1 0x0004 43 #define INTR 0x80000000 44 45 46 /* Sample Rate Converter */ 47 #define SAMPLE_RATE_CONV 0x10 48 49 50 /* CODEC Write/Read register */ 51 #define CODEC_WRITE 0x14 52 #define CODEC_READ 0x14 53 54 55 /* Legacy address */ 56 #define LEGACY 0x18 57 58 59 /* Memory related defines */ 60 #define MEM_PAGE 0x0c 61 #define ADC_MEM_PAGE 0x0d 62 #define DAC_MEM_PAGE 0x0c /* for DAC1 and DAC2 */ 63 64 #define MEMORY 0x30 65 #define ADC_BUFFER_SIZE 0x34 66 #define DAC1_BUFFER_SIZE 0x34 67 #define DAC2_BUFFER_SIZE 0X3c 68 #define ADC_PCI_ADDRESS 0x30 69 #define DAC1_PCI_ADDRESS 0x30 70 #define DAC2_PCI_ADDRESS 0x38 71 72 73 /* Serial Interface Control */ 74 #define SERIAL_INTERFACE_CTRL 0x20 75 #define P1_S_MB 0x0001 /* DAC1 Stereo/Mono bit */ 76 #define P1_S_EB 0x0002 /* DAC1 Sixteen/Eight bit */ 77 #define P2_S_MB 0x0004 /* DAC2 Stereo/Mono bit */ 78 #define P2_S_EB 0x0008 /* DAC2 Sixteen/Eight bit */ 79 #define R1_S_MB 0x0010 /* ADC Stereo/Mono bit */ 80 #define R1_S_EB 0x0020 /* ADC Sixteen/Eight bit */ 81 #define P1_INTR_EN 0x0100 82 #define P2_INTR_EN 0x0200 83 #define R1_INT_EN 0x0400 84 #define P1_PAUSE 0x0800 85 #define P2_PAUSE 0x1000 86 87 88 #define DAC1_SAMP_CT 0x24 89 #define DAC1_CURR_SAMP_CT 0x26 90 #define DAC2_SAMP_CT 0x28 91 #define DAC2_CURR_SAMP_CT 0x2a 92 #define ADC_SAMP_CT 0x2c 93 #define ADC_CURR_SAMP_CT 0x2e 94 95 96 typedef struct { 97 u32_t stereo; 98 u16_t sample_rate; 99 u32_t nr_of_bits; 100 u32_t sign; 101 u32_t busy; 102 u32_t fragment_size; 103 } aud_sub_dev_conf_t; 104 105 /* Some defaults for the aud_sub_dev_conf_t*/ 106 #define DEFAULT_RATE 44100 /* Sample rate */ 107 #define DEFAULT_NR_OF_BITS 16 /* Nr. of bits per sample per chan */ 108 #define DEFAULT_SIGNED 0 /* 0 = unsigned, 1 = signed */ 109 #define DEFAULT_STEREO 1 /* 0 = mono, 1 = stereo */ 110 #define MAX_RATE 44100 /* Max sample speed in KHz */ 111 #define MIN_RATE 4000 /* Min sample speed in KHz */ 112 113 114 typedef struct DEVSTRUCT { 115 char* name; 116 u16_t v_id; /* vendor id */ 117 u16_t d_id; /* device id */ 118 u32_t devind; /* minix pci device id, for 119 * pci configuration space */ 120 u32_t base; /* changed to 32 bits */ 121 char irq; 122 char revision; /* version of the device */ 123 } DEV_STRUCT; 124 125 #define SRC_ERR_NOT_BUSY_TIMEOUT -1 /* SRC not busy */ 126 #define SRC_SUCCESS 0 127 128 #endif /* ES1371_H */ 129