1 #ifndef __OMAP_RTC_REGISTERS_H 2 #define __OMAP_RTC_REGISTERS_H 3 4 /* RTC Addresses for am335x (BeagleBone White / BeagleBone Black) */ 5 6 /* Base Addresses */ 7 #define AM335X_RTC_SS_BASE 0x44e3e000 8 9 /* Size of RTC Register Address Range */ 10 #define AM335X_RTC_SS_SIZE 0x1000 11 12 /* Register Offsets */ 13 #define AM335X_RTC_SS_SECONDS_REG 0x0 14 #define AM335X_RTC_SS_MINUTES_REG 0x4 15 #define AM335X_RTC_SS_HOURS_REG 0x8 16 #define AM335X_RTC_SS_DAYS_REG 0xC 17 #define AM335X_RTC_SS_MONTHS_REG 0x10 18 #define AM335X_RTC_SS_YEARS_REG 0x14 19 #define AM335X_RTC_SS_WEEKS_REG 0x18 20 #define AM335X_RTC_SS_ALARM_SECONDS_REG 0x20 21 #define AM335X_RTC_SS_ALARM_MINUTES_REG 0x24 22 #define AM335X_RTC_SS_ALARM_HOURS_REG 0x28 23 #define AM335X_RTC_SS_ALARM_DAYS_REG 0x2C 24 #define AM335X_RTC_SS_ALARM_MONTHS_REG 0x30 25 #define AM335X_RTC_SS_ALARM_YEARS_REG 0x34 26 #define AM335X_RTC_SS_RTC_CTRL_REG 0x40 27 #define AM335X_RTC_SS_RTC_STATUS_REG 0x44 28 #define AM335X_RTC_SS_RTC_INTERRUPTS_REG 0x48 29 #define AM335X_RTC_SS_RTC_COMP_LSB_REG 0x4C 30 #define AM335X_RTC_SS_RTC_COMP_MSB_REG 0x50 31 #define AM335X_RTC_SS_RTC_OSC_REG 0x54 32 #define AM335X_RTC_SS_RTC_SCRATCH0_REG 0x60 33 #define AM335X_RTC_SS_RTC_SCRATCH1_REG 0x64 34 #define AM335X_RTC_SS_RTC_SCRATCH2_REG 0x68 35 #define AM335X_RTC_SS_KICK0R 0x6C 36 #define AM335X_RTC_SS_KICK1R 0x70 37 #define AM335X_RTC_SS_RTC_REVISION 0x74 38 #define AM335X_RTC_SS_RTC_SYSCONFIG 0x78 39 #define AM335X_RTC_SS_RTC_IRQWAKEEN 0x7C 40 #define AM335X_RTC_SS_ALARM2_SECONDS_REG 0x80 41 #define AM335X_RTC_SS_ALARM2_MINUTES_REG 0x84 42 #define AM335X_RTC_SS_ALARM2_HOURS_REG 0x88 43 #define AM335X_RTC_SS_ALARM2_DAYS_REG 0x8C 44 #define AM335X_RTC_SS_ALARM2_MONTHS_REG 0x90 45 #define AM335X_RTC_SS_ALARM2_YEARS_REG 0x94 46 #define AM335X_RTC_SS_RTC_PMIC 0x98 47 #define AM335X_RTC_SS_RTC_DEBOUNCE 0x9C 48 49 /* Constants */ 50 #define AM335X_RTC_SS_KICK0R_UNLOCK_MASK 0x83E70B13 51 #define AM335X_RTC_SS_KICK1R_UNLOCK_MASK 0x95A4F1E0 52 53 #define AM335X_RTC_SS_KICK0R_LOCK_MASK 0x546f6d20 54 #define AM335X_RTC_SS_KICK1R_LOCK_MASK 0x436f7274 55 56 /* Bits */ 57 58 /* RTC_SS_RTC_STATUS_REG */ 59 #define RTC_BUSY_BIT 0 60 61 /* RTC_SS_RTC_CTRL_REG */ 62 #define RTC_STOP_BIT 0 63 64 /* RTC_SS_RTC_SYSCONFIG */ 65 #define NOIDLE_BIT 0 66 67 /* RTC_SS_RTC_OSC_REG */ 68 #define EN_32KCLK_BIT 6 69 70 /* RTC_SS_RTC_PMIC */ 71 #define PWR_ENABLE_EN_BIT 16 72 73 /* RTC_SS_RTC_INTERRUPTS_REG */ 74 #define IT_ALARM2_BIT 4 75 76 /* Clocks */ 77 #define CM_RTC_RTC_CLKCTRL 0x800 78 #define CM_RTC_RTC_CLKCTRL_IDLEST ((0<<17)|(0<<16)) 79 #define CM_RTC_RTC_CLKCTRL_MODULEMODE ((1<<1)|(0<<0)) 80 #define CM_RTC_RTC_CLKCTRL_MASK (CM_RTC_RTC_CLKCTRL_IDLEST|CM_RTC_RTC_CLKCTRL_MODULEMODE) 81 82 #define CM_RTC_CLKSTCTRL 0x804 83 #define CLKACTIVITY_RTC_32KCLK (1<<9) 84 #define CLKACTIVITY_L4_RTC_GCLK (1<<8) 85 #define CLKTRCTRL ((0<<1)|(0<<0)) 86 #define CM_RTC_CLKSTCTRL_MASK (CLKACTIVITY_RTC_32KCLK|CLKACTIVITY_L4_RTC_GCLK|CLKTRCTRL) 87 88 int omap_rtc_init(void); 89 int omap_rtc_get_time(struct tm *t, int flags); 90 int omap_rtc_set_time(struct tm *t, int flags); 91 int omap_rtc_pwr_off(void); 92 void omap_rtc_exit(void); 93 94 #endif /* __OMAP_RTC_REGISTERS_H */ 95