1 /* 3Com 3C90xB/C EtherLink driver, by D.C. van Moolenbroek */ 2 #ifndef _DRIVERS_NET_3C90X_H 3 #define _DRIVERS_NET_3C90X_H 4 5 /* The following time values are in microseconds (us). */ 6 #define XLBC_CMD_TIMEOUT 1000 /* command timeout */ 7 #define XLBC_EEPROM_TIMEOUT 500 /* EEPROM read timeout */ 8 #define XLBC_AUTONEG_TIMEOUT 2000000 /* auto-negotiation timeout */ 9 #define XLBC_RESET_DELAY 1000 /* wait time for reset */ 10 #define XLBC_MII_DELAY 1 /* MII cycle response time */ 11 12 /* 13 * Transmission and receipt memory parameters. The current values allow for 14 * buffering of about 32 full-size packets, requiring 48KB of memory for each 15 * direction (and thus 96KB in total). For transmission, it is possible to 16 * queue many more small packets using the same memory area. For receipt, it 17 * is not, since each incoming packet may be of full size. This explains the 18 * seemingly huge difference in descriptor counts. 19 */ 20 #define XLBC_DPD_COUNT 256 /* TX descriptor count */ 21 #define XLBC_TXB_SIZE 48128 /* TX buffer size in bytes */ 22 #define XLBC_UPD_COUNT 32 /* RX descriptor count */ 23 24 #define XLBC_MIN_PKT_LEN NDEV_ETH_PACKET_MIN 25 #define XLBC_MAX_PKT_LEN NDEV_ETH_PACKET_MAX_TAGGED 26 27 #define XLBC_MIN_REG_SIZE 128 /* min. register memory size */ 28 29 #define XLBC_CMD_REG 0x0e /* command register */ 30 # define XLBC_CMD_GLOBAL_RESET 0x0000 /* perform overall NIC reset */ 31 # define XLBC_CMD_RX_RESET 0x2800 /* perform receiver reset */ 32 # define XLBC_CMD_TX_RESET 0x5800 /* perform transmitter reset */ 33 # define XLBC_CMD_DN_STALL 0x3002 /* stall download */ 34 # define XLBC_CMD_DN_UNSTALL 0x3003 /* unstall download */ 35 # define XLBC_CMD_TX_ENABLE 0x4800 /* enable transmission */ 36 # define XLBC_CMD_RX_ENABLE 0x2000 /* enable receipt */ 37 # define XLBC_CMD_SET_FILTER 0x8000 /* set receipt filter */ 38 # define XLBC_CMD_UP_UNSTALL 0x3001 /* unstall upload */ 39 # define XLBC_CMD_IND_ENABLE 0x7800 /* enable indications */ 40 # define XLBC_CMD_INT_ENABLE 0x7000 /* enable interrupts */ 41 # define XLBC_CMD_SELECT_WINDOW 0x0800 /* select register window */ 42 # define XLBC_CMD_STATS_ENABLE 0xa800 /* enable statistics */ 43 44 #define XLBC_FILTER_STATION 0x01 /* packets addressed to NIC */ 45 #define XLBC_FILTER_MULTI 0x02 /* multicast packets */ 46 #define XLBC_FILTER_BROAD 0x04 /* broadcast packets */ 47 #define XLBC_FILTER_PROMISC 0x08 /* all packets (promiscuous) */ 48 49 #define XLBC_STATUS_REG 0x0e /* interupt status register */ 50 # define XLBC_STATUS_HOST_ERROR 0x0002 /* catastrophic host error */ 51 # define XLBC_STATUS_TX_COMPLETE 0x0004 /* packet transmission done */ 52 # define XLBC_STATUS_UPDATE_STATS 0x0080 /* statistics need retrieval */ 53 # define XLBC_STATUS_LINK_EVENT 0x0100 /* link status change event */ 54 # define XLBC_STATUS_DN_COMPLETE 0x0200 /* packet download completed */ 55 # define XLBC_STATUS_UP_COMPLETE 0x0400 /* packet upload completed */ 56 # define XLBC_STATUS_IN_PROGRESS 0x1000 /* command still in progress */ 57 58 /* The mask of interrupts in which we are interested. */ 59 #define XLBC_STATUS_MASK \ 60 (XLBC_STATUS_HOST_ERROR | \ 61 XLBC_STATUS_TX_COMPLETE | \ 62 XLBC_STATUS_UPDATE_STATS | \ 63 XLBC_STATUS_LINK_EVENT | \ 64 XLBC_STATUS_DN_COMPLETE | \ 65 XLBC_STATUS_UP_COMPLETE) 66 67 #define XLBC_TX_STATUS_REG 0x1b /* TX status register */ 68 # define XLBC_TX_STATUS_OVERFLOW 0x04 /* TX status stack full */ 69 # define XLBC_TX_STATUS_MAX_COLL 0x08 /* max collisions reached */ 70 # define XLBC_TX_STATUS_UNDERRUN 0x10 /* packet transfer underrun */ 71 # define XLBC_TX_STATUS_JABBER 0x20 /* transmitting for too long */ 72 # define XLBC_TX_STATUS_COMPLETE 0x80 /* register contents valid */ 73 74 #define XLBC_STATUS_AUTO_REG 0x1e /* auto interrupt status reg */ 75 76 #define XLBC_DMA_CTRL_REG 0x20 /* DMA control register */ 77 # define XLBC_DMA_CTRL_DN_INPROG 0x00000080 /* dn in progress */ 78 # define XLBC_DMA_CTRL_UP_NOALT 0x00010000 /* disable up altseq */ 79 # define XLBC_DMA_CTRL_DN_NOALT 0x00020000 /* disable dn altseq */ 80 81 #define XLBC_DN_LIST_PTR_REG 0x24 /* download pointer register */ 82 83 #define XLBC_UP_LIST_PTR_REG 0x38 /* uplist pointer register */ 84 85 #define XLBC_EEPROM_WINDOW 0 /* EEPROM register window */ 86 #define XLBC_EEPROM_CMD_REG 0x0a /* EEPROM command register */ 87 # define XLBC_EEPROM_CMD_ADDR 0x003f /* address mask */ 88 # define XLBC_EEPROM_CMD_READ 0x0080 /* read register opcode */ 89 # define XLBC_EEPROM_CMD_BUSY 0x8000 /* command in progress */ 90 #define XLBC_EEPROM_DATA_REG 0x0c /* EEPROM data register */ 91 92 #define XLBC_EEPROM_WORD_OEM_ADDR0 0x0a /* OEM node address, word 0 */ 93 #define XLBC_EEPROM_WORD_OEM_ADDR1 0x0b /* OEM node address, word 1 */ 94 #define XLBC_EEPROM_WORD_OEM_ADDR2 0x0c /* OEM node address, word 2 */ 95 96 #define XLBC_STATION_WINDOW 2 /* station register window */ 97 #define XLBC_STATION_ADDR0_REG 0x00 /* station address, word 0 */ 98 #define XLBC_STATION_ADDR1_REG 0x02 /* station address, word 1 */ 99 #define XLBC_STATION_ADDR2_REG 0x04 /* station address, word 2 */ 100 #define XLBC_STATION_MASK0_REG 0x06 /* station mask, word 0 */ 101 #define XLBC_STATION_MASK1_REG 0x08 /* station mask, word 1 */ 102 #define XLBC_STATION_MASK2_REG 0x0a /* station mask, word 2 */ 103 104 #define XLBC_CONFIG_WINDOW 3 /* configuration window */ 105 #define XLBC_CONFIG_WORD1_REG 0x02 /* high-order 16 config bits */ 106 # define XLBC_CONFIG_XCVR_MASK 0x00f0 /* transceiver selection */ 107 # define XLBC_CONFIG_XCVR_AUTO 0x0080 /* auto-negotiation */ 108 109 #define XLBC_MAC_CTRL_WINDOW 3 /* MAC control window */ 110 #define XLBC_MAC_CTRL_REG 0x06 /* MAC control register */ 111 # define XLBC_MAC_CTRL_ENA_FD 0x0020 /* enable full duplex */ 112 113 #define XLBC_MEDIA_OPT_WINDOW 3 /* media options window */ 114 #define XLBC_MEDIA_OPT_REG 0x08 /* media options register */ 115 # define XLBC_MEDIA_OPT_BASE_TX 0x0002 /* 100BASE-TX available */ 116 # define XLBC_MEDIA_OPT_10_BT 0x0008 /* 10BASE-T available */ 117 118 #define XLBC_NET_DIAG_WINDOW 4 /* net diagnostics window */ 119 #define XLBC_NET_DIAG_REG 0x06 /* net diagnostics register */ 120 # define XLBC_NET_DIAG_UPPER 0x0040 /* enable upper stats bytes */ 121 122 #define XLBC_PHYS_MGMT_WINDOW 4 /* physical mgmt window */ 123 #define XLBC_PHYS_MGMT_REG 0x08 /* physical mgmt register */ 124 # define XLBC_PHYS_MGMT_CLK 0x0001 /* MII management clock */ 125 # define XLBC_PHYS_MGMT_DATA 0x0002 /* MII management data bit */ 126 # define XLBC_PHYS_MGMT_DIR 0x0004 /* MII data direction bit */ 127 128 #define XLBC_PHY_ADDR 0x18 /* internal PHY address */ 129 130 #define XLBC_MII_CONTROL 0x00 /* MII control register */ 131 # define XLBC_MII_CONTROL_AUTONEG 0x0200 /* restart auto-negotiation */ 132 # define XLBC_MII_CONTROL_RESET 0x8000 /* reset the PHY */ 133 #define XLBC_MII_STATUS 0x01 /* MII status register */ 134 # define XLBC_MII_STATUS_EXTCAP 0x0001 /* extended capability */ 135 # define XLBC_MII_STATUS_AUTONEG 0x0008 /* auto-neg capability */ 136 # define XLBC_MII_STATUS_COMPLETE 0x0020 /* auto-neg complete */ 137 #define XLBC_MII_AUTONEG_ADV 0x04 /* MII auto-neg advertise */ 138 # define XLBC_MII_LINK_T_HD 0x0020 /* 10BASE-T half-duplex */ 139 # define XLBC_MII_LINK_T_FD 0x0040 /* 10BASE-T full-duplex */ 140 # define XLBC_MII_LINK_TX_HD 0x0080 /* 100BASE-TX half-duplex */ 141 # define XLBC_MII_LINK_TX_FD 0x0100 /* 100BASE-TX full-duplex */ 142 #define XLBC_MII_LP_ABILITY 0x05 /* MII link partner ability */ 143 #define XLBC_MII_AUTONEG_EXP 0x06 /* MII auto-neg expansion */ 144 145 #define XLBC_MEDIA_STS_WINDOW 4 /* media status window */ 146 #define XLBC_MEDIA_STS_REG 0x0a /* media status register */ 147 # define XLBC_MEDIA_STS_LINK_DET 0x0800 /* link detected */ 148 # define XLBC_MEDIA_STS_TX_INPROG 0x1000 /* TX in progress */ 149 150 #define XLBC_SSD_STATS_WINDOW 4 /* SSD statistics window */ 151 #define XLBC_BAD_SSD_REG 0x0c /* bad start-of-stream delim */ 152 153 #define XLBC_STATS_WINDOW 6 /* statistics window */ 154 #define XLBC_CARRIER_LOST_REG 0x00 /* # packets w/ carrier lost */ 155 #define XLBC_SQE_ERR_REG 0x01 /* # SQE pulse errors */ 156 #define XLBC_MULTI_COLL_REG 0x02 /* # multiple collisions */ 157 #define XLBC_SINGLE_COLL_REG 0x03 /* # single collisions */ 158 #define XLBC_LATE_COLL_REG 0x04 /* # late collisions */ 159 #define XLBC_RX_OVERRUNS_REG 0x05 /* # receiver overruns */ 160 #define XLBC_FRAMES_XMIT_OK_REG 0x06 /* # frames transmitted */ 161 #define XLBC_FRAMES_RCVD_OK_REG 0x07 /* # frames received */ 162 #define XLBC_FRAMES_DEFERRED_REG 0x08 /* # frames deferred */ 163 #define XLBC_UPPER_FRAMES_REG 0x09 /* upper bits of frame stats */ 164 # define XLBC_UPPER_RX_MASK 0x03 /* mask for frames received */ 165 # define XLBC_UPPER_RX_SHIFT 0 /* shift for frames received */ 166 # define XLBC_UPPER_TX_MASK 0x30 /* mask for frames sent */ 167 # define XLBC_UPPER_TX_SHIFT 4 /* shift for frames sent */ 168 #define XLBC_BYTES_RCVD_OK_REG 0x0a /* # bytes received */ 169 #define XLBC_BYTES_XMIT_OK_REG 0x0c /* # bytes transmitted */ 170 171 typedef struct { 172 uint32_t next; /* physical address of next descriptor */ 173 uint32_t flags; /* frame start header or packet status */ 174 uint32_t addr; /* address of first (and only) fragment */ 175 uint32_t len; /* length of first (and only) fragment */ 176 } xlbc_pd_t; 177 178 /* Bits for the 'flags' field of download descriptors. */ 179 #define XLBC_DN_RNDUP_WORD 0x00000002 /* round up to word */ 180 #define XLBC_DN_DN_COMPLETE 0x00010000 /* download complete */ 181 #define XLBC_DN_DN_INDICATE 0x80000000 /* fire DN_COMPLETE */ 182 183 /* Bits for the 'flags' field of upload descriptors. */ 184 #define XLBC_UP_LEN 0x00001fff /* packet length */ 185 #define XLBC_UP_ERROR 0x00004000 /* receive error */ 186 #define XLBC_UP_COMPLETE 0x00008000 /* packet complete */ 187 #define XLBC_UP_OVERRUN 0x00010000 /* FIFO overrun */ 188 #define XLBC_UP_ALIGN_ERR 0x00040000 /* alignment error */ 189 #define XLBC_UP_CRC_ERR 0x00080000 /* CRC error */ 190 #define XLBC_UP_OVERFLOW 0x01000000 /* buffer too small */ 191 192 /* Bits for the 'len' field of upload and download descriptors. */ 193 #define XLBC_LEN_LAST 0x80000000 /* last fragment */ 194 195 #endif /* !_DRIVERS_NET_3C90X_H */ 196