1 #ifndef INCL_DEC21041_H_GUARD 2 #define INCL_DEC21041_H_GUARD 3 /* 4 de.h 5 6 Header for the driver of the DEC 21140A ethernet card as emulated 7 by VirtualPC 2007 8 9 Created: 09/01/2009 Nicolas Tittley (first.last @ gmail DOT com) 10 */ 11 12 #include <sys/null.h> 13 14 #if debug == 1 15 # define DEBUG(statm) statm 16 #else 17 # define DEBUG(statm) 18 #endif 19 20 #define DE_NB_SEND_DESCR 32 21 #define DE_SEND_BUF_SIZE (ETH_MAX_PACK_SIZE+2) 22 #define DE_NB_RECV_DESCR 32 23 #define DE_RECV_BUF_SIZE (ETH_MAX_PACK_SIZE+2) 24 25 #define DE_MIN_BASE_ADDR 0x0400 26 #define DE_SROM_EA_OFFSET 20 27 #define DE_SETUP_FRAME_SIZE 192 28 29 typedef struct de_descr { 30 u32_t des[4]; 31 } de_descr_t; 32 33 typedef struct de_local_descr { 34 de_descr_t *descr; 35 u8_t *buf1; 36 u8_t *buf2; 37 } de_loc_descr_t; 38 39 typedef struct dpeth { 40 char de_name[32]; /* Name of this interface */ 41 port_t de_base_port; /* Base port, for multiple card instance */ 42 int de_irq; /* IRQ line number */ 43 int de_hook; /* interrupt hook at kernel */ 44 45 int de_type; /* What kind of hardware */ 46 47 eth_stat_t de_stat; /* Stats */ 48 49 /* Space reservation. We will allocate all structures later in the code. 50 here we just make sure we have the space we need at compile time */ 51 u8_t sendrecv_descr_buf[(DE_NB_SEND_DESCR+DE_NB_RECV_DESCR)* 52 sizeof(de_descr_t)]; 53 u8_t sendrecv_buf[DE_NB_SEND_DESCR*DE_SEND_BUF_SIZE + 54 DE_NB_RECV_DESCR*DE_RECV_BUF_SIZE]; 55 phys_bytes sendrecv_descr_phys_addr[2]; 56 de_loc_descr_t descr[2][MAX(DE_NB_RECV_DESCR, DE_NB_SEND_DESCR)]; 57 int cur_descr[2]; 58 59 #define DESCR_RECV 0 60 #define DESCR_TRAN 1 61 62 /* Serial ROM */ 63 #define SROM_BITWIDTH 6 64 65 u8_t srom[((1<<SROM_BITWIDTH)-1)*2]; /* Space to read in 66 all the configuration ROM */ 67 } dpeth_t; 68 69 70 /************/ 71 /* Revisons */ 72 /************/ 73 74 #define DEC_21140A 0x20 75 #define DE_TYPE_UNKNOWN 0x0 76 /* #define CSR_ADDR(x, i) csraddr2(x->de_base_port + i) */ 77 #define CSR_ADDR(x, i) (x->de_base_port + i) 78 79 /* CSRs */ 80 #define CSR0 0x00 81 #define CSR0_SWR 0x00000001 /* sw reset */ 82 #define CSR0_BAR 0x00000002 /* bus arbitration */ 83 #define CSR0_CAL_8 0x00004000 /* cache align 8 long word */ 84 #define CSR0_TAP 0x00080000 /* trans auto polling */ 85 #define CSR1 0x08 /* transmit poll demand */ 86 #define CSR2 0x10 /* receive poll demand */ 87 #define CSR3 0x18 /* receive list address */ 88 #define CSR4 0x20 /* transmit list address */ 89 #define CSR5 0x28 /* status register */ 90 #define CSR5_EB 0x03800000 /* error bits */ 91 #define CSR5_TS 0x00700000 /* Transmit proc state */ 92 #define CSR5_RS 0x000E0000 /* Receive proc state */ 93 #define CSR5_NIS 0x00010000 /* Norm Int summ */ 94 #define CSR5_AIS 0x00008000 /* Abnorm Int sum */ 95 #define CSR5_FBE 0x00002000 /* Fatal bit error */ 96 #define CSR5_GTE 0x00000800 /* Gen-purp timer exp */ 97 #define CSR5_ETI 0x00000400 /* Early Trans int */ 98 #define CSR5_RWT 0x00000200 /* Recv watchdog timeout */ 99 #define CSR5_RPS 0x00000100 /* Recv proc stop */ 100 #define CSR5_RU 0x00000080 /* Recv buf unavail */ 101 #define CSR5_RI 0x00000040 /* Recv interrupt */ 102 #define CSR5_UNF 0x00000020 /* Trans underflow */ 103 #define CSR5_TJT 0x00000008 /* Trans Jabber Timeout */ 104 #define CSR5_TU 0x00000004 /* Trans buf unavail */ 105 #define CSR5_TPS 0x00000002 /* Trans proc stopped */ 106 #define CSR5_TI 0x00000001 /* Trans interrupt */ 107 #define CSR6 0x30 /* Operation mode */ 108 #define CSR6_SC 0x80000000 /* Special capt effect ena 31 */ 109 #define CSR6_RA 0x40000000 /* receive all 30 */ 110 #define CSR6_MBO 0x02000000 /* must be one 25 */ 111 #define CSR6_SCR 0x01000000 /* Scrambler mode 24 */ 112 #define CSR6_PCS 0x00800000 /* PCS function 23 */ 113 #define CSR6_TTM 0x00400000 /* Trans threshold mode 22 */ 114 #define CSR6_SF 0x00200000 /* store and forward 21 */ 115 #define CSR6_HBD 0x00080000 /* Heartbeat disable 19 */ 116 #define CSR6_PS 0x00040000 /* port select 18 */ 117 #define CSR6_CA 0x00020000 /* Capt effect ena 17 */ 118 #define CSR6_TR_00 0x00000000 /* Trans thresh 15:14 */ 119 #define CSR6_TR_01 0x00004000 /* Trans thresh 15:14 */ 120 #define CSR6_TR_10 0x00008000 /* Trans thresh 15:14 */ 121 #define CSR6_TR_11 0x0000C000 /* Trans thresh 15:14 */ 122 #define CSR6_ST 0x00002000 /* start/stop trans 13 */ 123 #define CSR6_FD 0x00000200 /* Full Duplex 9 */ 124 #define CSR6_PM 0x00000080 /* Pass all multicast 7 */ 125 #define CSR6_PR 0x00000040 /* Promisc mode 6 */ 126 #define CSR6_IF 0x00000010 /* Inv filtering 4 */ 127 #define CSR6_HO 0x00000004 /* Hash-only filtering 2 */ 128 #define CSR6_SR 0x00000002 /* start/stop recv 1 */ 129 #define CSR6_HP 0x00000001 /* Hash/perfect recv filt mode 0 */ 130 #define CSR7 0x38 /* Interrupt enable */ 131 #define CSR7_NI 0x00010000 /* Normal interrupt ena */ 132 #define CSR7_AI 0x00008000 /* Abnormal int ena */ 133 #define CSR7_TI 0x00000001 /* trans int ena */ 134 #define CSR7_TU 0x00000004 /* trans buf unavail ena */ 135 #define CSR7_RI 0x00000040 /* recv interp ena */ 136 #define CSR7_GPT 0x00000800 /* gen purpose timer ena */ 137 #define CSR9 0x48 /* Boot Rom, serial ROM, MII */ 138 #define CSR9_SR 0x0800 /* serial ROM select */ 139 #define CSR9_RD 0x4000 /* read */ 140 #define CSR9_DO 0x0008 /* data out */ 141 #define CSR9_DI 0x0004 /* data in */ 142 #define CSR9_SRC 0x0002 /* serial clock */ 143 #define CSR9_CS 0x0001 /* serial rom chip select */ 144 /* Send/Recv Descriptors */ 145 146 #define DES0 0 147 #define DES0_OWN 0x80000000 /* descr ownership. 1=211140A */ 148 #define DES0_FL 0x3FFF0000 /* frame length */ 149 #define DES0_FL_SHIFT 16 /* shift to fix frame length */ 150 #define DES0_ES 0x00008000 /* Error sum */ 151 #define DES0_TO 0x00004000 /* Trans jabber timeout */ 152 #define DES0_LO 0x00000800 /* Loss of carrier */ 153 #define DES0_NC 0x00000400 /* no carrier */ 154 #define DES0_LC 0x00000200 /* Late coll */ 155 #define DES0_EC 0x00000100 /* Excessive coll */ 156 #define DES0_UF 0x00000002 /* Underflow error */ 157 #define DES0_RE 0x00000008 /* MII error */ 158 #define DES0_FS 0x00000200 /* first descr */ 159 #define DES0_LS 0x00000100 /* last descr */ 160 #define DES1 1 161 #define DES1_ER 0x02000000 /* end of ring */ 162 #define DES1_SAC 0x01000000 /* 2nd address chained */ 163 #define DES1_BS2 0x003FF800 /* 2nd buffer size */ 164 #define DES1_BS2_SHFT 11 /* shift to obtain 2nd buffer size */ 165 #define DES1_BS1 0x000007FF /* 1nd buffer size */ 166 #define DES1_IC 0x80000000 /* Interrupt on completion 31 */ 167 #define DES1_LS 0x40000000 /* Last Segment 30 */ 168 #define DES1_FS 0x20000000 /* First Segment 29 */ 169 #define DES1_FT1 0x10000000 /* Filtering type 28 */ 170 #define DES1_SET 0x08000000 /* Setup frame 27 */ 171 #define DES1_AC 0x04000000 /* Add CRC disable 26 */ 172 #define DES1_DPD 0x00800000 /* Disabled padding 23 */ 173 #define DES1_FT0 0x00400000 /* Filtering type 22 */ 174 #define DES2 2 /* 1st buffer addr */ 175 #define DES3 3 /* 2nd buffer addr */ 176 177 #define DES_BUF1 DES2 178 #define DES_BUF2 DES3 179 180 #endif /* Include Guard */ 181