1 /* 2 ** File: 3c509.h Jun. 01, 2000 3 ** 4 ** Author: Giovanni Falzoni <gfalzoni@inwind.it> 5 ** 6 ** Interface description for 3Com Etherlink III board. 7 ** 8 ** $Log$ 9 ** Revision 1.1 2005/06/29 10:16:46 beng 10 ** Import of dpeth 3c501/3c509b/.. ethernet driver by 11 ** Giovanni Falzoni <fgalzoni@inwind.it>. 12 ** 13 ** Revision 2.0 2005/06/26 16:16:46 lsodgf0 14 ** Initial revision for Minix 3.0.6 15 */ 16 17 /* Command codes */ 18 #define CMD_GlobalReset 0x0000 /* resets adapter (power up status) */ 19 #define CMD_SelectWindow (1<<11) /* select register window */ 20 #define CMD_StartIntXcvr (2<<11) /* start internal transciver */ 21 #define CMD_RxDisable (3<<11) /* rx disable */ 22 #define CMD_RxEnable (4<<11) /* rx enable */ 23 #define CMD_RxReset (5<<11) /* rx reset */ 24 #define CMD_RxDiscard (8<<11) /* rx discard top packet */ 25 #define CMD_TxEnable (9<<11) /* tx enable */ 26 #define CMD_TxDisable (10<<11) /* tx disable */ 27 #define CMD_TxReset (11<<11) /* tx reset */ 28 #define CMD_Acknowledge (13<<11) /* acknowledge interrupt */ 29 #define CMD_SetIntMask (14<<11) /* set interrupt mask */ 30 #define CMD_SetStatusEnab (15<<11) /* set read zero mask */ 31 #define CMD_SetRxFilter (16<<11) /* set rx filter */ 32 #define CMD_SetTxAvailable (18<<11) /* set tx available threshold */ 33 #define CMD_StatsEnable (21<<11) /* statistics enable */ 34 #define CMD_StatsDisable (22<<11) /* statistics disable */ 35 #define CMD_StopIntXcvr (23<<11) /* start internal transciver */ 36 37 /* Status register bits (INT for interrupt sources, ST for the rest) */ 38 #define INT_Latch 0x0001 /* interrupt latch */ 39 #define INT_AdapterFail 0x0002 /* adapter failure */ 40 #define INT_TxComplete 0x0004 /* tx complete */ 41 #define INT_TxAvailable 0x0008 /* tx available */ 42 #define INT_RxComplete 0x0010 /* rx complete */ 43 #define INT_RxEarly 0x0020 /* rx early */ 44 #define INT_Requested 0x0040 /* interrupt requested */ 45 #define INT_UpdateStats 0x0080 /* update statistics */ 46 47 /* Rx Status register bits */ 48 #define RXS_Error 0x4000 /* error in packet */ 49 #define RXS_Length 0x07FF /* bytes in RxFIFO */ 50 #define RXS_ErrType 0x3800 /* Rx error type, bit 13-11 */ 51 #define RXS_Overrun 0x0000 /* overrun error */ 52 #define RXS_Oversize 0x0800 /* oversize packet error */ 53 #define RXS_Dribble 0x1000 /* dribble bit (not an error) */ 54 #define RXS_Runt 0x1800 /* runt packet error */ 55 #define RXS_Framing 0x2000 /* framing error */ 56 #define RXS_CRC 0x2800 /* CRC error */ 57 58 /* Tx Status register bits */ 59 60 /* Window Numbers */ 61 #define WNO_Setup 0x0000 /* setup/configuration */ 62 #define WNO_Operating 0x0001 /* operating set */ 63 #define WNO_StationAddress 0x0002 /* station address setup/read */ 64 #define WNO_Diagnostics 0x0004 /* diagnostics */ 65 #define WNO_Statistics 0x0006 /* statistics */ 66 67 /* Register offsets - Window 1 (WNO_Operating) */ 68 #define REG_CmdStatus 0x000E /* command/status */ 69 #define REG_TxFree 0x000C /* free transmit bytes */ 70 #define REG_TxStatus 0x000B /* transmit status (byte) */ 71 #define REG_RxStatus 0x0008 /* receive status */ 72 #define REG_RxFIFO 0x0000 /* RxFIFO read */ 73 #define REG_TxFIFO 0x0000 /* TxFIFO write */ 74 75 /* Register offsets - Window 0 (WNO_Setup) */ 76 #define REG_CfgControl 0x0004 /* configuration control */ 77 78 /* Register offsets - Window 2 (WNO_StationAddress) */ 79 #define REG_SA0_1 0x0000 /* station address bytes 0,1 */ 80 81 /* Register offsets - Window 3 (WNO_FIFO) */ 82 83 /* Register offsets - Window 4 (WNO_Diagnostics) */ 84 #define REG_MediaStatus 0x000A /* media type/status */ 85 86 /* Register offsets - Window 5 (WNO_Readable) */ 87 88 /* Register offsets - Window 6 (WNO_Statistics) */ 89 #define REG_TxBytes 0x000C /* tx bytes ok */ 90 #define REG_RxBytes 0x000A /* rx bytes ok */ 91 #define REG_TxDefer 0x0008 /* tx frames deferred (byte) */ 92 #define REG_RxFrames 0x0007 /* rx frames ok (byte) */ 93 #define REG_TxFrames 0x0006 /* tx frames ok (byte) */ 94 #define REG_RxDiscarded 0x0005 /* rx frames discarded (byte) */ 95 #define REG_TxLate 0x0004 /* tx frames late coll. (byte) */ 96 #define REG_TxSingleColl 0x0003 /* tx frames one coll. (byte) */ 97 #define REG_TxMultColl 0x0002 /* tx frames mult. coll. (byte) */ 98 #define REG_TxNoCD 0x0001 /* tx frames no CDheartbt (byte) */ 99 #define REG_TxCarrierLost 0x0000 /* tx frames carrier lost (byte) */ 100 101 /* Various command arguments */ 102 103 #define FilterIndividual 0x0001 /* individual address */ 104 #define FilterMulticast 0x0002 /* multicast/group addresses */ 105 #define FilterBroadcast 0x0004 /* broadcast address */ 106 #define FilterPromiscuous 0x0008 /* promiscuous mode */ 107 108 /* Resource Configuration Register bits */ 109 #define EL3_CONFIG_IRQ_MASK 0xF000 110 111 /* Address Configuration Register bits */ 112 #define EL3_CONFIG_XCVR_MASK 0xC000 113 #define EL3_CONFIG_IOBASE_MASK 0x001F 114 115 #define TP_XCVR 0x0000 116 #define BNC_XCVR 0xC000 117 #define AUI_XCVR 0x4000 118 119 #define EL3_IO_BASE_ADDR 0x200 120 121 /* Transmit Preamble */ 122 123 /* Bits in various diagnostics registers */ 124 #define MediaLBeatEnable 0x0080 /* link beat enable (TP) */ 125 #define MediaJabberEnable 0x0040 /* jabber enable (TP) */ 126 127 /* Board identification codes, byte swapped in Rev 0 */ 128 #define EL3_3COM_CODE 0x6D50 /* EISA manufacturer code */ 129 #define EL3_PRODUCT_ID 0x9050 /* Product ID for ISA board */ 130 131 /* EEProm access */ 132 #define EE_3COM_NODE_ADDR 0x00 133 #define EE_PROD_ID 0x03 134 #define EE_MANUFACTURING_DATA 0x04 135 #define EE_3COM_CODE 0x07 136 #define EE_ADDR_CFG 0x08 137 #define EE_RESOURCE_CFG 0x09 138 #define EE_SW_CONFIG_INFO 0x0D 139 #define EE_PROD_ID_MASK 0xF0FF /* Mask off revision nibble */ 140 141 /* Contention logic */ 142 #define EL3_READ_EEPROM 0x80 143 #define EL3_ID_GLOBAL_RESET 0xC0 144 #define EL3_SET_TAG_REGISTER 0xD0 145 #define EL3_ACTIVATE_AND_SET_IO 0xE0 146 #define EL3_ACTIVATE 0xFF 147 148 /* Software Configuration Register bits */ 149 150 /* Configuration Control Register bits */ 151 #define EL3_EnableAdapter 0x01 152 153 /* EL3 access macros */ 154 #define inb_el3(dep,reg) (inb((dep)->de_base_port+(reg))) 155 #define inw_el3(dep,reg) (inw((dep)->de_base_port+(reg))) 156 #define outb_el3(dep,reg,data) (outb((dep)->de_base_port+(reg),(data))) 157 #define outw_el3(dep,reg,data) (outw((dep)->de_base_port+(reg),(data))) 158 159 #define SetWindow(win) \ 160 outw(dep->de_base_port+REG_CmdStatus,CMD_SelectWindow|(win)) 161 162 /** 3c509.h **/ 163