1 /** 2 * @file e1000.c 3 * 4 * @brief This file contains a device driver for Intel Pro/1000 5 * Gigabit Ethernet Controllers. 6 */ 7 8 #include <minix/drivers.h> 9 #include <minix/netdriver.h> 10 #include <stdlib.h> 11 #include <net/gen/ether.h> 12 #include <net/gen/eth_io.h> 13 #include <machine/pci.h> 14 #include <minix/ds.h> 15 #include <minix/vm.h> 16 #include <minix/timers.h> 17 #include <sys/mman.h> 18 #include "assert.h" 19 #include "e1000.h" 20 #include "e1000_hw.h" 21 #include "e1000_reg.h" 22 #include "e1000_pci.h" 23 24 static int e1000_instance; 25 static e1000_t e1000_state; 26 27 static void e1000_init(message *mp); 28 static void e1000_init_pci(void); 29 static int e1000_probe(e1000_t *e, int skip); 30 static int e1000_init_hw(e1000_t *e); 31 static void e1000_init_addr(e1000_t *e); 32 static void e1000_init_buf(e1000_t *e); 33 static void e1000_reset_hw(e1000_t *e); 34 static void e1000_writev_s(message *mp, int from_int); 35 static void e1000_readv_s(message *mp, int from_int); 36 static void e1000_getstat_s(message *mp); 37 static void e1000_interrupt(message *mp); 38 static int e1000_link_changed(e1000_t *e); 39 static void e1000_stop(e1000_t *e); 40 static uint32_t e1000_reg_read(e1000_t *e, uint32_t reg); 41 static void e1000_reg_write(e1000_t *e, uint32_t reg, uint32_t value); 42 static void e1000_reg_set(e1000_t *e, uint32_t reg, uint32_t value); 43 static void e1000_reg_unset(e1000_t *e, uint32_t reg, uint32_t value); 44 static u16_t eeprom_eerd(void *e, int reg); 45 static u16_t eeprom_ich(void *e, int reg); 46 static int eeprom_ich_init(e1000_t *e); 47 static int eeprom_ich_cycle(const e1000_t *e, u32_t timeout); 48 static void reply(e1000_t *e); 49 static void mess_reply(message *req, message *reply); 50 51 /* SEF functions and variables. */ 52 static void sef_local_startup(void); 53 static int sef_cb_init_fresh(int type, sef_init_info_t *info); 54 static void sef_cb_signal_handler(int signo); 55 56 /*===========================================================================* 57 * main * 58 *===========================================================================*/ 59 int main(int argc, char *argv[]) 60 { 61 message m; 62 int ipc_status; 63 int r; 64 65 /* SEF local startup. */ 66 env_setargs(argc, argv); 67 sef_local_startup(); 68 69 /* 70 * Enter the main driver loop. 71 */ 72 while (TRUE) 73 { 74 if ((r= netdriver_receive(ANY, &m, &ipc_status)) != OK) 75 { 76 panic("netdriver_receive failed: %d", r); 77 } 78 79 if (is_ipc_notify(ipc_status)) 80 { 81 switch (_ENDPOINT_P(m.m_source)) 82 { 83 case HARDWARE: 84 e1000_interrupt(&m); 85 break; 86 87 case CLOCK: 88 break; 89 } 90 continue; 91 } 92 switch (m.m_type) 93 { 94 case DL_WRITEV_S: e1000_writev_s(&m, FALSE); break; 95 case DL_READV_S: e1000_readv_s(&m, FALSE); break; 96 case DL_CONF: e1000_init(&m); break; 97 case DL_GETSTAT_S: e1000_getstat_s(&m); break; 98 default: 99 panic("illegal message: %d", m.m_type); 100 } 101 } 102 } 103 104 /*===========================================================================* 105 * sef_local_startup * 106 *===========================================================================*/ 107 static void sef_local_startup() 108 { 109 /* Register init callbacks. */ 110 sef_setcb_init_fresh(sef_cb_init_fresh); 111 sef_setcb_init_lu(sef_cb_init_fresh); 112 sef_setcb_init_restart(sef_cb_init_fresh); 113 114 /* Register live update callbacks. */ 115 sef_setcb_lu_prepare(sef_cb_lu_prepare_always_ready); 116 sef_setcb_lu_state_isvalid(sef_cb_lu_state_isvalid_workfree); 117 118 /* Register signal callbacks. */ 119 sef_setcb_signal_handler(sef_cb_signal_handler); 120 121 /* Let SEF perform startup. */ 122 sef_startup(); 123 } 124 125 /*===========================================================================* 126 * sef_cb_init_fresh * 127 *===========================================================================*/ 128 static int sef_cb_init_fresh(int UNUSED(type), sef_init_info_t *UNUSED(info)) 129 { 130 /* Initialize the e1000 driver. */ 131 long v; 132 int r; 133 134 v = 0; 135 (void) env_parse("instance", "d", 0, &v, 0, 255); 136 e1000_instance = (int) v; 137 138 /* Clear state. */ 139 memset(&e1000_state, 0, sizeof(e1000_state)); 140 141 /* Perform calibration. */ 142 if((r = tsc_calibrate()) != OK) 143 { 144 panic("tsc_calibrate failed: %d", r); 145 } 146 147 /* Announce we are up! */ 148 netdriver_announce(); 149 150 return(OK); 151 } 152 153 /*===========================================================================* 154 * sef_cb_signal_handler * 155 *===========================================================================*/ 156 static void sef_cb_signal_handler(int signo) 157 { 158 e1000_t *e; 159 e = &e1000_state; 160 161 E1000_DEBUG(3, ("%s: got signal\n", e->name)); 162 163 /* Only check for termination signal, ignore anything else. */ 164 if (signo != SIGTERM) return; 165 166 e1000_stop(e); 167 } 168 169 /*===========================================================================* 170 * e1000_init * 171 *===========================================================================*/ 172 static void e1000_init(message *mp) 173 { 174 static int first_time = 1; 175 message reply_mess; 176 e1000_t *e; 177 178 E1000_DEBUG(3, ("e1000: init()\n")); 179 180 /* Configure PCI devices, if needed. */ 181 if (first_time) 182 { 183 first_time = 0; 184 e1000_init_pci(); 185 } 186 e = &e1000_state; 187 188 /* Initialize hardware, if needed. */ 189 if (!(e->status & E1000_ENABLED) && !(e1000_init_hw(e))) 190 { 191 reply_mess.m_type = DL_CONF_REPLY; 192 reply_mess.m_netdrv_net_dl_conf.stat = ENXIO; 193 mess_reply(mp, &reply_mess); 194 return; 195 } 196 /* Reply back to INET. */ 197 reply_mess.m_type = DL_CONF_REPLY; 198 reply_mess.m_netdrv_net_dl_conf.stat = OK; 199 memcpy(reply_mess.m_netdrv_net_dl_conf.hw_addr, e->address.ea_addr, 200 sizeof(reply_mess.m_netdrv_net_dl_conf.hw_addr)); 201 mess_reply(mp, &reply_mess); 202 } 203 204 /*===========================================================================* 205 * e1000_int_pci * 206 *===========================================================================*/ 207 static void e1000_init_pci() 208 { 209 e1000_t *e; 210 211 /* Initialize the PCI bus. */ 212 pci_init(); 213 214 /* Try to detect e1000's. */ 215 e = &e1000_state; 216 strlcpy(e->name, "e1000#0", sizeof(e->name)); 217 e->name[6] += e1000_instance; 218 e1000_probe(e, e1000_instance); 219 } 220 221 /*===========================================================================* 222 * e1000_probe * 223 *===========================================================================*/ 224 static int e1000_probe(e1000_t *e, int skip) 225 { 226 int r, devind, ioflag; 227 u16_t vid, did, cr; 228 u32_t status[2]; 229 u32_t base, size; 230 u32_t gfpreg, sector_base_addr; 231 char *dname; 232 233 E1000_DEBUG(3, ("%s: probe()\n", e->name)); 234 235 /* 236 * Attempt to iterate the PCI bus. Start at the beginning. 237 */ 238 if ((r = pci_first_dev(&devind, &vid, &did)) == 0) 239 { 240 return FALSE; 241 } 242 /* Loop devices on the PCI bus. */ 243 while (skip--) 244 { 245 E1000_DEBUG(3, ("%s: probe() devind %d vid 0x%x did 0x%x\n", 246 e->name, devind, vid, did)); 247 248 if (!(r = pci_next_dev(&devind, &vid, &did))) 249 { 250 return FALSE; 251 } 252 } 253 /* 254 * Successfully detected an Intel Pro/1000 on the PCI bus. 255 */ 256 e->status |= E1000_DETECTED; 257 e->eeprom_read = eeprom_eerd; 258 259 /* 260 * Set card specific properties. 261 */ 262 switch (did) 263 { 264 case E1000_DEV_ID_ICH10_D_BM_LM: 265 case E1000_DEV_ID_ICH10_R_BM_LF: 266 e->eeprom_read = eeprom_ich; 267 break; 268 269 case E1000_DEV_ID_82540EM: 270 case E1000_DEV_ID_82545EM: 271 e->eeprom_done_bit = (1 << 4); 272 e->eeprom_addr_off = 8; 273 break; 274 275 default: 276 e->eeprom_done_bit = (1 << 1); 277 e->eeprom_addr_off = 2; 278 break; 279 } 280 281 /* Inform the user about the new card. */ 282 if (!(dname = pci_dev_name(vid, did))) 283 { 284 dname = "Intel Pro/1000 Gigabit Ethernet Card"; 285 } 286 E1000_DEBUG(1, ("%s: %s (%04x/%04x/%02x) at %s\n", 287 e->name, dname, vid, did, e->revision, 288 pci_slot_name(devind))); 289 290 /* Reserve PCI resources found. */ 291 if ((r = pci_reserve_ok(devind)) != OK) 292 { 293 panic("failed to reserve PCI device: %d", r); 294 } 295 /* Read PCI configuration. */ 296 e->irq = pci_attr_r8(devind, PCI_ILR); 297 298 if ((r = pci_get_bar(devind, PCI_BAR, &base, &size, &ioflag)) != OK) 299 panic("failed to get PCI BAR (%d)", r); 300 if (ioflag) panic("PCI BAR is not for memory"); 301 302 e->regs = vm_map_phys(SELF, (void *) base, size); 303 if (e->regs == (u8_t *) -1) { 304 panic("failed to map hardware registers from PCI"); 305 } 306 307 /* FIXME: enable DMA bus mastering if necessary. This is disabled by 308 * default on VMware. Eventually, the PCI driver should deal with this. 309 */ 310 cr = pci_attr_r16(devind, PCI_CR); 311 if (!(cr & PCI_CR_MAST_EN)) 312 pci_attr_w16(devind, PCI_CR, cr | PCI_CR_MAST_EN); 313 314 /* Optionally map flash memory. */ 315 if (did != E1000_DEV_ID_82540EM && 316 did != E1000_DEV_ID_82545EM && 317 did != E1000_DEV_ID_82540EP && 318 pci_attr_r32(devind, PCI_BAR_2)) 319 { 320 size_t flash_size; 321 322 /* 82566/82567/82562V series support mapping 4kB of flash memory */ 323 switch(did) 324 { 325 case E1000_DEV_ID_ICH10_D_BM_LM: 326 case E1000_DEV_ID_ICH10_R_BM_LF: 327 flash_size = 0x1000; 328 break; 329 default: 330 flash_size = 0x10000; 331 } 332 333 if ((e->flash = vm_map_phys(SELF, 334 (void *) pci_attr_r32(devind, PCI_BAR_2), 335 flash_size)) == MAP_FAILED) { 336 panic("e1000: couldn't map in flash."); 337 } 338 339 gfpreg = E1000_READ_FLASH_REG(e, ICH_FLASH_GFPREG); 340 /* 341 * sector_base_addr is a "sector"-aligned address (4096 bytes) 342 */ 343 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 344 345 /* flash_base_addr is byte-aligned */ 346 e->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 347 } 348 /* 349 * Output debug information. 350 */ 351 status[0] = e1000_reg_read(e, E1000_REG_STATUS); 352 E1000_DEBUG(3, ("%s: MEM at %p, IRQ %d\n", 353 e->name, e->regs, e->irq)); 354 E1000_DEBUG(3, ("%s: link %s, %s duplex\n", 355 e->name, status[0] & 3 ? "up" : "down", 356 status[0] & 1 ? "full" : "half")); 357 return TRUE; 358 } 359 360 /*===========================================================================* 361 * e1000_init_hw * 362 *===========================================================================*/ 363 static int e1000_init_hw(e) 364 e1000_t *e; 365 { 366 int r, i; 367 368 e->status |= E1000_ENABLED; 369 e->irq_hook = e->irq; 370 371 /* 372 * Set the interrupt handler and policy. Do not automatically 373 * re-enable interrupts. Return the IRQ line number on interrupts. 374 */ 375 if ((r = sys_irqsetpolicy(e->irq, 0, &e->irq_hook)) != OK) 376 { 377 panic("sys_irqsetpolicy failed: %d", r); 378 } 379 if ((r = sys_irqenable(&e->irq_hook)) != OK) 380 { 381 panic("sys_irqenable failed: %d", r); 382 } 383 /* Reset hardware. */ 384 e1000_reset_hw(e); 385 386 /* 387 * Initialize appropriately, according to section 14.3 General Configuration 388 * of Intel's Gigabit Ethernet Controllers Software Developer's Manual. 389 */ 390 e1000_reg_set(e, E1000_REG_CTRL, E1000_REG_CTRL_ASDE | E1000_REG_CTRL_SLU); 391 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_LRST); 392 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_PHY_RST); 393 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_ILOS); 394 e1000_reg_write(e, E1000_REG_FCAL, 0); 395 e1000_reg_write(e, E1000_REG_FCAH, 0); 396 e1000_reg_write(e, E1000_REG_FCT, 0); 397 e1000_reg_write(e, E1000_REG_FCTTV, 0); 398 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_VME); 399 400 /* Clear Multicast Table Array (MTA). */ 401 for (i = 0; i < 128; i++) 402 { 403 e1000_reg_write(e, E1000_REG_MTA + i, 0); 404 } 405 /* Initialize statistics registers. */ 406 for (i = 0; i < 64; i++) 407 { 408 e1000_reg_write(e, E1000_REG_CRCERRS + (i * 4), 0); 409 } 410 /* 411 * Aquire MAC address and setup RX/TX buffers. 412 */ 413 e1000_init_addr(e); 414 e1000_init_buf(e); 415 416 /* Enable interrupts. */ 417 e1000_reg_set(e, E1000_REG_IMS, E1000_REG_IMS_LSC | 418 E1000_REG_IMS_RXO | 419 E1000_REG_IMS_RXT | 420 E1000_REG_IMS_TXQE | 421 E1000_REG_IMS_TXDW); 422 return TRUE; 423 } 424 425 /*===========================================================================* 426 * e1000_init_addr * 427 *===========================================================================*/ 428 static void e1000_init_addr(e) 429 e1000_t *e; 430 { 431 static char eakey[]= E1000_ENVVAR "#_EA"; 432 static char eafmt[]= "x:x:x:x:x:x"; 433 u16_t word; 434 int i; 435 long v; 436 437 /* 438 * Do we have a user defined ethernet address? 439 */ 440 eakey[sizeof(E1000_ENVVAR)-1] = '0' + e1000_instance; 441 442 for (i= 0; i < 6; i++) 443 { 444 if (env_parse(eakey, eafmt, i, &v, 0x00L, 0xFFL) != EP_SET) 445 break; 446 else 447 e->address.ea_addr[i]= v; 448 } 449 /* 450 * If that fails, read Ethernet Address from EEPROM. 451 */ 452 if (i != 6) 453 { 454 for (i = 0; i < 3; i++) 455 { 456 word = e->eeprom_read(e, i); 457 e->address.ea_addr[(i * 2)] = (word & 0xff); 458 e->address.ea_addr[(i * 2) + 1] = (word & 0xff00) >> 8; 459 } 460 } 461 /* 462 * Set Receive Address. 463 */ 464 e1000_reg_write(e, E1000_REG_RAL, *(u32_t *)(&e->address.ea_addr[0])); 465 e1000_reg_write(e, E1000_REG_RAH, *(u16_t *)(&e->address.ea_addr[4])); 466 e1000_reg_set(e, E1000_REG_RAH, E1000_REG_RAH_AV); 467 e1000_reg_set(e, E1000_REG_RCTL, E1000_REG_RCTL_MPE); 468 469 E1000_DEBUG(3, ("%s: Ethernet Address %x:%x:%x:%x:%x:%x\n", e->name, 470 e->address.ea_addr[0], e->address.ea_addr[1], 471 e->address.ea_addr[2], e->address.ea_addr[3], 472 e->address.ea_addr[4], e->address.ea_addr[5])); 473 } 474 475 /*===========================================================================* 476 * e1000_init_buf * 477 *===========================================================================*/ 478 static void e1000_init_buf(e) 479 e1000_t *e; 480 { 481 phys_bytes rx_buff_p; 482 phys_bytes tx_buff_p; 483 int i; 484 485 /* Number of descriptors. */ 486 e->rx_desc_count = E1000_RXDESC_NR; 487 e->tx_desc_count = E1000_TXDESC_NR; 488 489 /* 490 * First, allocate the receive descriptors. 491 */ 492 if (!e->rx_desc) 493 { 494 if ((e->rx_desc = alloc_contig(sizeof(e1000_rx_desc_t) * 495 e->rx_desc_count, AC_ALIGN4K, 496 &e->rx_desc_p)) == NULL) { 497 panic("failed to allocate RX descriptors"); 498 } 499 memset(e->rx_desc, 0, sizeof(e1000_rx_desc_t) * e->rx_desc_count); 500 501 /* 502 * Allocate 2048-byte buffers. 503 */ 504 e->rx_buffer_size = E1000_RXDESC_NR * E1000_IOBUF_SIZE; 505 506 /* Attempt to allocate. */ 507 if ((e->rx_buffer = alloc_contig(e->rx_buffer_size, 508 AC_ALIGN4K, &rx_buff_p)) == NULL) 509 { 510 panic("failed to allocate RX buffers"); 511 } 512 /* Setup receive descriptors. */ 513 for (i = 0; i < E1000_RXDESC_NR; i++) 514 { 515 e->rx_desc[i].buffer = rx_buff_p + (i * E1000_IOBUF_SIZE); 516 } 517 } 518 /* 519 * Then, allocate transmit descriptors. 520 */ 521 if (!e->tx_desc) 522 { 523 if ((e->tx_desc = alloc_contig(sizeof(e1000_tx_desc_t) * 524 e->tx_desc_count, AC_ALIGN4K, 525 &e->tx_desc_p)) == NULL) { 526 panic("failed to allocate TX descriptors"); 527 } 528 memset(e->tx_desc, 0, sizeof(e1000_tx_desc_t) * e->tx_desc_count); 529 530 /* 531 * Allocate 2048-byte buffers. 532 */ 533 e->tx_buffer_size = E1000_TXDESC_NR * E1000_IOBUF_SIZE; 534 535 /* Attempt to allocate. */ 536 if ((e->tx_buffer = alloc_contig(e->tx_buffer_size, 537 AC_ALIGN4K, &tx_buff_p)) == NULL) 538 { 539 panic("failed to allocate TX buffers"); 540 } 541 /* Setup transmit descriptors. */ 542 for (i = 0; i < E1000_TXDESC_NR; i++) 543 { 544 e->tx_desc[i].buffer = tx_buff_p + (i * E1000_IOBUF_SIZE); 545 } 546 } 547 /* 548 * Setup the receive ring registers. 549 */ 550 e1000_reg_write(e, E1000_REG_RDBAL, e->rx_desc_p); 551 e1000_reg_write(e, E1000_REG_RDBAH, 0); 552 e1000_reg_write(e, E1000_REG_RDLEN, e->rx_desc_count * 553 sizeof(e1000_rx_desc_t)); 554 e1000_reg_write(e, E1000_REG_RDH, 0); 555 e1000_reg_write(e, E1000_REG_RDT, e->rx_desc_count - 1); 556 e1000_reg_unset(e, E1000_REG_RCTL, E1000_REG_RCTL_BSIZE); 557 e1000_reg_set(e, E1000_REG_RCTL, E1000_REG_RCTL_EN); 558 559 /* 560 * Setup the transmit ring registers. 561 */ 562 e1000_reg_write(e, E1000_REG_TDBAL, e->tx_desc_p); 563 e1000_reg_write(e, E1000_REG_TDBAH, 0); 564 e1000_reg_write(e, E1000_REG_TDLEN, e->tx_desc_count * 565 sizeof(e1000_tx_desc_t)); 566 e1000_reg_write(e, E1000_REG_TDH, 0); 567 e1000_reg_write(e, E1000_REG_TDT, 0); 568 e1000_reg_set( e, E1000_REG_TCTL, E1000_REG_TCTL_EN | E1000_REG_TCTL_PSP); 569 } 570 571 /*===========================================================================* 572 * e1000_reset_hw * 573 *===========================================================================*/ 574 static void e1000_reset_hw(e) 575 e1000_t *e; 576 { 577 /* Assert a Device Reset signal. */ 578 e1000_reg_set(e, E1000_REG_CTRL, E1000_REG_CTRL_RST); 579 580 /* Wait one microsecond. */ 581 tickdelay(1); 582 } 583 584 /*===========================================================================* 585 * e1000_writev_s * 586 *===========================================================================*/ 587 static void e1000_writev_s(mp, from_int) 588 message *mp; 589 int from_int; 590 { 591 e1000_t *e = &e1000_state; 592 e1000_tx_desc_t *desc; 593 iovec_s_t iovec[E1000_IOVEC_NR]; 594 int r, head, tail, i, bytes = 0, size; 595 596 E1000_DEBUG(3, ("e1000: writev_s(%p,%d)\n", mp, from_int)); 597 598 /* Are we called from the interrupt handler? */ 599 if (!from_int) 600 { 601 /* We cannot write twice simultaneously. 602 assert(!(e->status & E1000_WRITING)); */ 603 604 /* Copy write message. */ 605 e->tx_message = *mp; 606 e->client = mp->m_source; 607 e->status |= E1000_WRITING; 608 609 /* Must be a sane vector count. */ 610 assert(e->tx_message.m_net_netdrv_dl_writev_s.count > 0); 611 assert(e->tx_message.m_net_netdrv_dl_writev_s.count < E1000_IOVEC_NR); 612 613 /* 614 * Copy the I/O vector table. 615 */ 616 if ((r = sys_safecopyfrom(e->tx_message.m_source, 617 e->tx_message.m_net_netdrv_dl_writev_s.grant, 0, 618 (vir_bytes) iovec, 619 e->tx_message.m_net_netdrv_dl_writev_s.count * 620 sizeof(iovec_s_t))) != OK) 621 { 622 panic("sys_safecopyfrom() failed: %d", r); 623 } 624 /* Find the head, tail and current descriptors. */ 625 head = e1000_reg_read(e, E1000_REG_TDH); 626 tail = e1000_reg_read(e, E1000_REG_TDT); 627 desc = &e->tx_desc[tail]; 628 629 E1000_DEBUG(4, ("%s: head=%d, tail=%d\n", 630 e->name, head, tail)); 631 632 /* Loop vector elements. */ 633 for (i = 0; i < e->tx_message.m_net_netdrv_dl_writev_s.count; i++) 634 { 635 size = iovec[i].iov_size < (E1000_IOBUF_SIZE - bytes) ? 636 iovec[i].iov_size : (E1000_IOBUF_SIZE - bytes); 637 638 E1000_DEBUG(4, ("iovec[%d] = %d\n", i, size)); 639 640 /* Copy bytes to TX queue buffers. */ 641 if ((r = sys_safecopyfrom(e->tx_message.m_source, 642 iovec[i].iov_grant, 0, 643 (vir_bytes) e->tx_buffer + 644 (tail * E1000_IOBUF_SIZE), 645 size)) != OK) 646 { 647 panic("sys_safecopyfrom() failed: %d", r); 648 } 649 /* Mark this descriptor ready. */ 650 desc->status = 0; 651 desc->command = 0; 652 desc->length = size; 653 654 /* Marks End-of-Packet. */ 655 if (i == e->tx_message.m_net_netdrv_dl_writev_s.count - 1) 656 { 657 desc->command = E1000_TX_CMD_EOP | 658 E1000_TX_CMD_FCS | 659 E1000_TX_CMD_RS; 660 } 661 /* Move to next descriptor. */ 662 tail = (tail + 1) % e->tx_desc_count; 663 bytes += size; 664 desc = &e->tx_desc[tail]; 665 } 666 /* Increment tail. Start transmission. */ 667 e1000_reg_write(e, E1000_REG_TDT, tail); 668 669 E1000_DEBUG(2, ("e1000: wrote %d byte packet\n", bytes)); 670 } 671 else 672 { 673 e->status |= E1000_TRANSMIT; 674 } 675 reply(e); 676 } 677 678 /*===========================================================================* 679 * e1000_readv_s * 680 *===========================================================================*/ 681 static void e1000_readv_s(mp, from_int) 682 message *mp; 683 int from_int; 684 { 685 e1000_t *e = &e1000_state; 686 e1000_rx_desc_t *desc; 687 iovec_s_t iovec[E1000_IOVEC_NR]; 688 int i, r, head, tail, cur, bytes = 0, size; 689 690 E1000_DEBUG(3, ("e1000: readv_s(%p,%d)\n", mp, from_int)); 691 692 /* Are we called from the interrupt handler? */ 693 if (!from_int) 694 { 695 e->rx_message = *mp; 696 e->client = mp->m_source; 697 e->status |= E1000_READING; 698 e->rx_size = 0; 699 700 assert(e->rx_message.m_net_netdrv_dl_readv_s.count > 0); 701 assert(e->rx_message.m_net_netdrv_dl_readv_s.count < E1000_IOVEC_NR); 702 } 703 if (e->status & E1000_READING) 704 { 705 /* 706 * Copy the I/O vector table first. 707 */ 708 if ((r = sys_safecopyfrom(e->rx_message.m_source, 709 e->rx_message.m_net_netdrv_dl_readv_s.grant, 0, 710 (vir_bytes) iovec, 711 e->rx_message.m_net_netdrv_dl_readv_s.count * 712 sizeof(iovec_s_t))) != OK) 713 { 714 panic("sys_safecopyfrom() failed: %d", r); 715 } 716 /* Find the head, tail and current descriptors. */ 717 head = e1000_reg_read(e, E1000_REG_RDH); 718 tail = e1000_reg_read(e, E1000_REG_RDT); 719 cur = (tail + 1) % e->rx_desc_count; 720 desc = &e->rx_desc[cur]; 721 722 /* 723 * Only handle one packet at a time. 724 */ 725 if (!(desc->status & E1000_RX_STATUS_EOP)) 726 { 727 reply(e); 728 return; 729 } 730 E1000_DEBUG(4, ("%s: head=%x, tail=%d\n", 731 e->name, head, tail)); 732 733 /* 734 * Copy to vector elements. 735 */ 736 for (i = 0; i < e->rx_message.m_net_netdrv_dl_readv_s.count && 737 bytes < desc->length; i++) 738 { 739 size = iovec[i].iov_size < (desc->length - bytes) ? 740 iovec[i].iov_size : (desc->length - bytes); 741 742 E1000_DEBUG(4, ("iovec[%d] = %lu[%d]\n", 743 i, iovec[i].iov_size, size)); 744 745 if ((r = sys_safecopyto(e->rx_message.m_source, iovec[i].iov_grant, 746 0, (vir_bytes) e->rx_buffer + bytes + 747 (cur * E1000_IOBUF_SIZE), 748 size)) != OK) 749 { 750 panic("sys_safecopyto() failed: %d", r); 751 } 752 bytes += size; 753 } 754 desc->status = 0; 755 756 /* 757 * Update state. 758 */ 759 e->rx_size = bytes; 760 e->status |= E1000_RECEIVED; 761 E1000_DEBUG(2, ("e1000: got %d byte packet\n", e->rx_size)); 762 763 /* Increment tail. */ 764 e1000_reg_write(e, E1000_REG_RDT, (tail + 1) % e->rx_desc_count); 765 } 766 reply(e); 767 } 768 769 /*===========================================================================* 770 * e1000_getstat_s * 771 *===========================================================================*/ 772 static void e1000_getstat_s(mp) 773 message *mp; 774 { 775 int r; 776 eth_stat_t stats; 777 e1000_t *e = &e1000_state; 778 779 E1000_DEBUG(3, ("e1000: getstat_s()\n")); 780 781 stats.ets_recvErr = e1000_reg_read(e, E1000_REG_RXERRC); 782 stats.ets_sendErr = 0; 783 stats.ets_OVW = 0; 784 stats.ets_CRCerr = e1000_reg_read(e, E1000_REG_CRCERRS); 785 stats.ets_frameAll = 0; 786 stats.ets_missedP = e1000_reg_read(e, E1000_REG_MPC); 787 stats.ets_packetR = e1000_reg_read(e, E1000_REG_TPR); 788 stats.ets_packetT = e1000_reg_read(e, E1000_REG_TPT); 789 stats.ets_collision = e1000_reg_read(e, E1000_REG_COLC); 790 stats.ets_transAb = 0; 791 stats.ets_carrSense = 0; 792 stats.ets_fifoUnder = 0; 793 stats.ets_fifoOver = 0; 794 stats.ets_CDheartbeat = 0; 795 stats.ets_OWC = 0; 796 797 sys_safecopyto(mp->m_source, mp->m_net_netdrv_dl_getstat_s.grant, 0, 798 (vir_bytes)&stats, sizeof(stats)); 799 mp->m_type = DL_STAT_REPLY; 800 if((r=ipc_send(mp->m_source, mp)) != OK) 801 panic("e1000_getstat: ipc_send() failed: %d", r); 802 } 803 804 /*===========================================================================* 805 * e1000_interrupt * 806 *===========================================================================*/ 807 static void e1000_interrupt(mp) 808 message *mp; 809 { 810 e1000_t *e; 811 u32_t cause; 812 813 E1000_DEBUG(3, ("e1000: interrupt\n")); 814 815 /* 816 * Check the card for interrupt reason(s). 817 */ 818 e = &e1000_state; 819 820 /* Re-enable interrupts. */ 821 if (sys_irqenable(&e->irq_hook) != OK) 822 { 823 panic("failed to re-enable IRQ"); 824 } 825 826 /* Read the Interrupt Cause Read register. */ 827 if ((cause = e1000_reg_read(e, E1000_REG_ICR))) 828 { 829 if (cause & E1000_REG_ICR_LSC) 830 e1000_link_changed(e); 831 832 if (cause & (E1000_REG_ICR_RXO | E1000_REG_ICR_RXT)) 833 e1000_readv_s(&e->rx_message, TRUE); 834 835 if ((cause & E1000_REG_ICR_TXQE) || 836 (cause & E1000_REG_ICR_TXDW)) 837 e1000_writev_s(&e->tx_message, TRUE); 838 } 839 } 840 841 /*===========================================================================* 842 * e1000_link_changed * 843 *===========================================================================*/ 844 static int e1000_link_changed(e) 845 e1000_t *e; 846 { 847 E1000_DEBUG(4, ("%s: link_changed()\n", e->name)); 848 return FALSE; 849 } 850 851 /*===========================================================================* 852 * e1000_stop * 853 *===========================================================================*/ 854 static void e1000_stop(e) 855 e1000_t *e; 856 { 857 E1000_DEBUG(3, ("%s: stop()\n", e->name)); 858 859 e1000_reset_hw(e); 860 861 exit(EXIT_SUCCESS); 862 } 863 864 /*===========================================================================* 865 * e1000_reg_read * 866 *===========================================================================*/ 867 static uint32_t e1000_reg_read(e, reg) 868 e1000_t *e; 869 uint32_t reg; 870 { 871 uint32_t value; 872 873 /* Assume a sane register. */ 874 assert(reg < 0x1ffff); 875 876 /* Read from memory mapped register. */ 877 value = *(volatile u32_t *)(e->regs + reg); 878 879 /* Return the result. */ 880 return value; 881 } 882 883 /*===========================================================================* 884 * e1000_reg_write * 885 *===========================================================================*/ 886 static void e1000_reg_write(e, reg, value) 887 e1000_t *e; 888 uint32_t reg; 889 uint32_t value; 890 { 891 /* Assume a sane register. */ 892 assert(reg < 0x1ffff); 893 894 /* Write to memory mapped register. */ 895 *(volatile u32_t *)(e->regs + reg) = value; 896 } 897 898 /*===========================================================================* 899 * e1000_reg_set * 900 *===========================================================================*/ 901 static void e1000_reg_set(e, reg, value) 902 e1000_t *e; 903 uint32_t reg; 904 uint32_t value; 905 { 906 uint32_t data; 907 908 /* First read the current value. */ 909 data = e1000_reg_read(e, reg); 910 911 /* Set value, and write back. */ 912 e1000_reg_write(e, reg, data | value); 913 } 914 915 /*===========================================================================* 916 * e1000_reg_unset * 917 *===========================================================================*/ 918 static void e1000_reg_unset(e, reg, value) 919 e1000_t *e; 920 uint32_t reg; 921 uint32_t value; 922 { 923 uint32_t data; 924 925 /* First read the current value. */ 926 data = e1000_reg_read(e, reg); 927 928 /* Unset value, and write back. */ 929 e1000_reg_write(e, reg, data & ~value); 930 } 931 932 933 /*===========================================================================* 934 * eeprom_eerd * 935 *===========================================================================*/ 936 static u16_t eeprom_eerd(v, reg) 937 void *v; 938 int reg; 939 { 940 e1000_t *e = (e1000_t *) v; 941 u32_t data; 942 943 /* Request EEPROM read. */ 944 e1000_reg_write(e, E1000_REG_EERD, 945 (reg << e->eeprom_addr_off) | (E1000_REG_EERD_START)); 946 947 /* Wait until ready. */ 948 while (!((data = (e1000_reg_read(e, E1000_REG_EERD))) & e->eeprom_done_bit)); 949 950 return data >> 16; 951 } 952 953 /*===========================================================================* 954 * eeprom_ich_init * 955 *===========================================================================*/ 956 static int eeprom_ich_init(e) 957 e1000_t *e; 958 { 959 union ich8_hws_flash_status hsfsts; 960 int ret_val = -1; 961 int i = 0; 962 963 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS); 964 965 /* Check if the flash descriptor is valid */ 966 if (hsfsts.hsf_status.fldesvalid == 0) 967 { 968 E1000_DEBUG(3, ("Flash descriptor invalid. " 969 "SW Sequencing must be used.")); 970 goto out; 971 } 972 /* Clear FCERR and DAEL in hw status by writing 1 */ 973 hsfsts.hsf_status.flcerr = 1; 974 hsfsts.hsf_status.dael = 1; 975 976 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, hsfsts.regval); 977 978 /* 979 * Either we should have a hardware SPI cycle in progress 980 * bit to check against, in order to start a new cycle or 981 * FDONE bit should be changed in the hardware so that it 982 * is 1 after hardware reset, which can then be used as an 983 * indication whether a cycle is in progress or has been 984 * completed. 985 */ 986 if (hsfsts.hsf_status.flcinprog == 0) 987 { 988 /* 989 * There is no cycle running at present, 990 * so we can start a cycle. 991 * Begin by setting Flash Cycle Done. 992 */ 993 hsfsts.hsf_status.flcdone = 1; 994 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, hsfsts.regval); 995 ret_val = 0; 996 } 997 else 998 { 999 /* 1000 * Otherwise poll for sometime so the current 1001 * cycle has a chance to end before giving up. 1002 */ 1003 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) 1004 { 1005 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS); 1006 1007 if (hsfsts.hsf_status.flcinprog == 0) 1008 { 1009 ret_val = 0; 1010 break; 1011 } 1012 tickdelay(1); 1013 } 1014 if (ret_val == 0) 1015 { 1016 /* 1017 * Successful in waiting for previous cycle to timeout, 1018 * now set the Flash Cycle Done. 1019 */ 1020 hsfsts.hsf_status.flcdone = 1; 1021 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, 1022 hsfsts.regval); 1023 } 1024 else 1025 { 1026 E1000_DEBUG(3, ("Flash controller busy, cannot get access")); 1027 } 1028 } 1029 out: 1030 return ret_val; 1031 } 1032 1033 /*===========================================================================* 1034 * eeprom_ich_cycle * 1035 *===========================================================================*/ 1036 static int eeprom_ich_cycle(const e1000_t *e, u32_t timeout) 1037 { 1038 union ich8_hws_flash_ctrl hsflctl; 1039 union ich8_hws_flash_status hsfsts; 1040 int ret_val = -1; 1041 u32_t i = 0; 1042 1043 E1000_DEBUG(3, ("e1000_flash_cycle_ich8lan")); 1044 1045 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1046 hsflctl.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFCTL); 1047 hsflctl.hsf_ctrl.flcgo = 1; 1048 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFCTL, hsflctl.regval); 1049 1050 /* wait till FDONE bit is set to 1 */ 1051 do 1052 { 1053 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS); 1054 if (hsfsts.hsf_status.flcdone == 1) 1055 break; 1056 tickdelay(1); 1057 } 1058 while (i++ < timeout); 1059 1060 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1061 ret_val = 0; 1062 1063 return ret_val; 1064 } 1065 1066 /*===========================================================================* 1067 * eeprom_ich * 1068 *===========================================================================*/ 1069 static u16_t eeprom_ich(v, reg) 1070 void *v; 1071 int reg; 1072 { 1073 union ich8_hws_flash_status hsfsts; 1074 union ich8_hws_flash_ctrl hsflctl; 1075 u32_t flash_linear_addr; 1076 u32_t flash_data = 0; 1077 int ret_val = -1; 1078 u8_t count = 0; 1079 e1000_t *e = (e1000_t *) v; 1080 u16_t data = 0; 1081 1082 E1000_DEBUG(3, ("e1000_read_flash_data_ich8lan")); 1083 1084 if (reg > ICH_FLASH_LINEAR_ADDR_MASK) 1085 goto out; 1086 1087 reg *= sizeof(u16_t); 1088 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & reg) + 1089 e->flash_base_addr; 1090 1091 do { 1092 tickdelay(1); 1093 1094 /* Steps */ 1095 ret_val = eeprom_ich_init(e); 1096 if (ret_val != 0) 1097 break; 1098 1099 hsflctl.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFCTL); 1100 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1101 hsflctl.hsf_ctrl.fldbcount = 1; 1102 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1103 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFCTL, hsflctl.regval); 1104 E1000_WRITE_FLASH_REG(e, ICH_FLASH_FADDR, flash_linear_addr); 1105 1106 ret_val = eeprom_ich_cycle(v, ICH_FLASH_READ_COMMAND_TIMEOUT); 1107 1108 /* 1109 * Check if FCERR is set to 1, if set to 1, clear it 1110 * and try the whole sequence a few more times, else 1111 * read in (shift in) the Flash Data0, the order is 1112 * least significant byte first msb to lsb 1113 */ 1114 if (ret_val == 0) 1115 { 1116 flash_data = E1000_READ_FLASH_REG(e, ICH_FLASH_FDATA0); 1117 data = (u16_t)(flash_data & 0x0000FFFF); 1118 break; 1119 } 1120 else 1121 { 1122 /* 1123 * If we've gotten here, then things are probably 1124 * completely hosed, but if the error condition is 1125 * detected, it won't hurt to give it another try... 1126 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1127 */ 1128 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS); 1129 1130 if (hsfsts.hsf_status.flcerr == 1) 1131 { 1132 /* Repeat for some time before giving up. */ 1133 continue; 1134 } 1135 else if (hsfsts.hsf_status.flcdone == 0) 1136 { 1137 E1000_DEBUG(3, ("Timeout error - flash cycle " 1138 "did not complete.")); 1139 break; 1140 } 1141 } 1142 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1143 1144 out: 1145 return data; 1146 } 1147 1148 /*===========================================================================* 1149 * reply * 1150 *===========================================================================*/ 1151 static void reply(e) 1152 e1000_t *e; 1153 { 1154 message msg; 1155 int r; 1156 1157 /* Only reply to client for read/write request. */ 1158 if (!(e->status & E1000_READING || 1159 e->status & E1000_WRITING)) 1160 { 1161 return; 1162 } 1163 /* Construct reply message. */ 1164 msg.m_type = DL_TASK_REPLY; 1165 msg.m_netdrv_net_dl_task.flags = DL_NOFLAGS; 1166 msg.m_netdrv_net_dl_task.count = 0; 1167 1168 /* Did we successfully receive packet(s)? */ 1169 if (e->status & E1000_READING && 1170 e->status & E1000_RECEIVED) 1171 { 1172 msg.m_netdrv_net_dl_task.flags |= DL_PACK_RECV; 1173 msg.m_netdrv_net_dl_task.count = 1174 e->rx_size >= ETH_MIN_PACK_SIZE ? 1175 e->rx_size : ETH_MIN_PACK_SIZE; 1176 1177 /* Clear flags. */ 1178 e->status &= ~(E1000_READING | E1000_RECEIVED); 1179 } 1180 /* Did we successfully transmit packet(s)? */ 1181 if (e->status & E1000_TRANSMIT && 1182 e->status & E1000_WRITING) 1183 { 1184 msg.m_netdrv_net_dl_task.flags |= DL_PACK_SEND; 1185 1186 /* Clear flags. */ 1187 e->status &= ~(E1000_WRITING | E1000_TRANSMIT); 1188 } 1189 1190 /* Acknowledge to INET. */ 1191 if ((r = ipc_send(e->client, &msg)) != OK) 1192 { 1193 panic("ipc_send() failed: %d", r); 1194 } 1195 } 1196 1197 /*===========================================================================* 1198 * mess_reply * 1199 *===========================================================================*/ 1200 static void mess_reply(req, reply_mess) 1201 message *req; 1202 message *reply_mess; 1203 { 1204 if (ipc_send(req->m_source, reply_mess) != OK) 1205 { 1206 panic("unable to send reply message"); 1207 } 1208 } 1209