1 /** 2 * @file e1000_reg.h 3 * 4 * @brief Hardware specific registers and flags of the Intel 5 * Pro/1000 Gigabit Ethernet card(s). 6 * 7 * Parts of this code is based on the DragonflyBSD (FreeBSD) 8 * implementation, and the fxp driver for Minix 3. 9 * 10 * @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/ 11 * @see fxp.c 12 * 13 * @author Niek Linnenbank <nieklinnenbank@gmail.com> 14 * @date September 2009 15 * 16 */ 17 18 #ifndef __E1000_REG_H 19 #define __E1000_REG_H 20 21 /** 22 * @name Controller Registers. 23 * @{ 24 */ 25 26 /** Device Control. */ 27 #define E1000_REG_CTRL 0x00000 28 29 /** Device Status. */ 30 #define E1000_REG_STATUS 0x00008 31 32 /** EEPROM Read. */ 33 #define E1000_REG_EERD 0x00014 34 35 /** Flow Control Address Low. */ 36 #define E1000_REG_FCAL 0x00028 37 38 /** Flow Control Address High. */ 39 #define E1000_REG_FCAH 0x0002c 40 41 /** Flow Control Type. */ 42 #define E1000_REG_FCT 0x00030 43 44 /** Interrupt Cause Read. */ 45 #define E1000_REG_ICR 0x000c0 46 47 /** Interrupt Mask Set/Read Register. */ 48 #define E1000_REG_IMS 0x000d0 49 50 /** Receive Control Register. */ 51 #define E1000_REG_RCTL 0x00100 52 53 /** Transmit Control Register. */ 54 #define E1000_REG_TCTL 0x00400 55 56 /** Flow Control Transmit Timer Value. */ 57 #define E1000_REG_FCTTV 0x00170 58 59 /** Receive Descriptor Base Address Low. */ 60 #define E1000_REG_RDBAL 0x02800 61 62 /** Receive Descriptor Base Address High. */ 63 #define E1000_REG_RDBAH 0x02804 64 65 /** Receive Descriptor Length. */ 66 #define E1000_REG_RDLEN 0x02808 67 68 /** Receive Descriptor Head. */ 69 #define E1000_REG_RDH 0x02810 70 71 /** Receive Descriptor Tail. */ 72 #define E1000_REG_RDT 0x02818 73 74 /** Transmit Descriptor Base Address Low. */ 75 #define E1000_REG_TDBAL 0x03800 76 77 /** Transmit Descriptor Base Address High. */ 78 #define E1000_REG_TDBAH 0x03804 79 80 /** Transmit Descriptor Length. */ 81 #define E1000_REG_TDLEN 0x03808 82 83 /** Transmit Descriptor Head. */ 84 #define E1000_REG_TDH 0x03810 85 86 /** Transmit Descriptor Tail. */ 87 #define E1000_REG_TDT 0x03818 88 89 /** CRC Error Count. */ 90 #define E1000_REG_CRCERRS 0x04000 91 92 /** RX Error Count. */ 93 #define E1000_REG_RXERRC 0x0400c 94 95 /** Missed Packets Count. */ 96 #define E1000_REG_MPC 0x04010 97 98 /** Collision Count. */ 99 #define E1000_REG_COLC 0x04028 100 101 /** Total Packets Received. */ 102 #define E1000_REG_TPR 0x040D0 103 104 /** Total Packets Transmitted. */ 105 #define E1000_REG_TPT 0x040D4 106 107 /** Receive Address Low. */ 108 #define E1000_REG_RAL 0x05400 109 110 /** Receive Address High. */ 111 #define E1000_REG_RAH 0x05404 112 113 /** Multicast Table Array. */ 114 #define E1000_REG_MTA 0x05200 115 116 /** 117 * @} 118 */ 119 120 /** 121 * @name Control Register Bits. 122 * @{ 123 */ 124 125 /** Auto-Speed Detection Enable. */ 126 #define E1000_REG_CTRL_ASDE (1 << 5) 127 128 /** Link Reset. */ 129 #define E1000_REG_CTRL_LRST (1 << 3) 130 131 /** Set Link Up. */ 132 #define E1000_REG_CTRL_SLU (1 << 6) 133 134 /** Invert Los Of Signal. */ 135 #define E1000_REG_CTRL_ILOS (1 << 7) 136 137 /** Device Reset. */ 138 #define E1000_REG_CTRL_RST (1 << 26) 139 140 /** VLAN Mode Enable. */ 141 #define E1000_REG_CTRL_VME (1 << 30) 142 143 /** PHY Reset. */ 144 #define E1000_REG_CTRL_PHY_RST (1 << 31) 145 146 /** 147 * @} 148 */ 149 150 /** 151 * @name Status Register Bits. 152 * @{ 153 */ 154 155 /** Link Full Duplex Configuration Indication. */ 156 #define E1000_REG_STATUS_FD (1 << 0) 157 158 /** Link Up Indication. */ 159 #define E1000_REG_STATUS_LU (1 << 1) 160 161 /** Transmission Paused. */ 162 #define E1000_REG_STATUS_TXOFF (1 << 4) 163 164 /** Link Speed Setting. */ 165 #define E1000_REG_STATUS_SPEED ((1 << 6) | (1 << 7)) 166 167 /** 168 * @} 169 */ 170 171 /** 172 * @name EEPROM Read Register Bits. 173 * @{ 174 */ 175 176 /** Start Read. */ 177 #define E1000_REG_EERD_START (1 << 0) 178 179 /** Read Done. */ 180 #define E1000_REG_EERD_DONE (1 << 4) 181 182 /** Read Address Bit Mask. */ 183 #define E1000_REG_EERD_ADDR (0xff << 8) 184 185 /** Read Data Bit Mask. */ 186 #define E1000_REG_EERD_DATA (0xffff << 16) 187 188 /** 189 * @} 190 */ 191 192 /** 193 * @name Interrupt Cause Read. 194 * @{ 195 */ 196 197 /** Transmit Descripts Written Back. */ 198 #define E1000_REG_ICR_TXDW (1 << 0) 199 200 /** Transmit Queue Empty. */ 201 #define E1000_REG_ICR_TXQE (1 << 1) 202 203 /** Link Status Change. */ 204 #define E1000_REG_ICR_LSC (1 << 2) 205 206 /** Receiver Overrun. */ 207 #define E1000_REG_ICR_RXO (1 << 6) 208 209 /** Receiver Timer Interrupt. */ 210 #define E1000_REG_ICR_RXT (1 << 7) 211 212 /** 213 * @} 214 */ 215 216 /** 217 * @name Interrupt Mask Set/Read Register Bits. 218 * @{ 219 */ 220 221 /** Transmit Descripts Written Back. */ 222 #define E1000_REG_IMS_TXDW (1 << 0) 223 224 /** Transmit Queue Empty. */ 225 #define E1000_REG_IMS_TXQE (1 << 1) 226 227 /** Link Status Change. */ 228 #define E1000_REG_IMS_LSC (1 << 2) 229 230 /** Receiver FIFO Overrun. */ 231 #define E1000_REG_IMS_RXO (1 << 6) 232 233 /** Receiver Timer Interrupt. */ 234 #define E1000_REG_IMS_RXT (1 << 7) 235 236 /** 237 * @} 238 */ 239 240 /** 241 * @name Receive Control Register Bits. 242 * @{ 243 */ 244 245 /** Receive Enable. */ 246 #define E1000_REG_RCTL_EN (1 << 1) 247 248 /** Multicast Promiscious Enable. */ 249 #define E1000_REG_RCTL_MPE (1 << 4) 250 251 /** Broadcast Accept Mode. */ 252 #define E1000_REG_RCTL_BAM (1 << 15) 253 254 /** Receive Buffer Size. */ 255 #define E1000_REG_RCTL_BSIZE ((1 << 16) | (1 << 17)) 256 257 /** 258 * @} 259 */ 260 261 /** 262 * @name Transmit Control Register Bits. 263 * @{ 264 */ 265 266 /** Transmit Enable. */ 267 #define E1000_REG_TCTL_EN (1 << 1) 268 269 /** Pad Short Packets. */ 270 #define E1000_REG_TCTL_PSP (1 << 3) 271 272 /** 273 * @} 274 */ 275 276 /** 277 * @name Receive Address High Register Bits. 278 * @{ 279 */ 280 281 /** Receive Address Valid. */ 282 #define E1000_REG_RAH_AV (1 << 31) 283 284 /** 285 * @} 286 */ 287 288 /** 289 * @name ICH Flash Registers. 290 * @see http://gitweb.dragonflybsd.org 291 * @{ 292 */ 293 294 #define ICH_FLASH_GFPREG 0x0000 295 #define ICH_FLASH_HSFSTS 0x0004 296 #define ICH_FLASH_HSFCTL 0x0006 297 #define ICH_FLASH_FADDR 0x0008 298 #define ICH_FLASH_FDATA0 0x0010 299 #define FLASH_GFPREG_BASE_MASK 0x1FFF 300 #define FLASH_SECTOR_ADDR_SHIFT 12 301 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 302 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 303 #define ICH_CYCLE_READ 0 304 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 305 306 /** 307 * @} 308 */ 309 310 #endif /* __E1000_REG_H */ 311