1 #include <minix/drivers.h> 2 #include <minix/netdriver.h> 3 #include <machine/pci.h> 4 #include "ip1000.h" 5 #include "io.h" 6 7 /* global value */ 8 static ic_driver g_driver; 9 static int g_instance; 10 11 /* driver interface */ 12 static int ic_init(unsigned int instance, ether_addr_t *addr); 13 static void ic_stop(void); 14 static void ic_mode(unsigned int mode); 15 static ssize_t ic_recv(struct netdriver_data *data, size_t max); 16 static int ic_send(struct netdriver_data *data, size_t size); 17 static void ic_intr(unsigned int mask); 18 static void ic_stat(eth_stat_t *stat); 19 20 /* internal function */ 21 static int ic_probe(ic_driver *pdev, int instance); 22 static int ic_init_buf(ic_driver *pdev); 23 static int ic_init_hw(ic_driver *pdev, ether_addr_t *addr); 24 static int ic_reset_hw(ic_driver *pdev); 25 static void ic_conf_addr(ic_driver *pdev, ether_addr_t *addr); 26 static void ic_handler(ic_driver *pdev); 27 static void ic_check_ints(ic_driver *pdev); 28 29 /* developer interface */ 30 static void ic_init_rx_desc(ic_desc *desc, size_t size, phys_bytes dma); 31 static void ic_init_tx_desc(ic_desc *desc, size_t size, phys_bytes dma); 32 static int ic_real_reset(u32_t base); 33 static int ic_init_power(u32_t base); 34 static int ic_init_mii(u32_t base); 35 static int ic_init_io(u32_t base); 36 static void ic_start_rx_tx(u32_t base); 37 static void ic_get_addr(u32_t base, u8_t *pa); 38 static int ic_check_link(u32_t base); 39 static void ic_stop_rx_tx(u32_t base); 40 static int ic_rx_status_ok(ic_desc *desc); 41 static int ic_get_rx_len(ic_desc *desc); 42 static void ic_tx_desc_start(ic_desc *desc, size_t size); 43 static void ic_wakeup_tx(u32_t base); 44 static int ic_tx_status_ok(ic_desc *desc); 45 46 /* ======= Developer-defined function ======= */ 47 /* ====== Self-defined function ======*/ 48 49 static u16_t read_eeprom(u32_t base, int addr) { 50 u16_t ret, data, val; 51 int i; 52 53 val = EC_READ | (addr & 0xff); 54 ic_out16(base, REG_EEPROM_CTRL, val); 55 for (i = 0; i < 100; i++) { 56 micro_delay(10000); 57 data = ic_in16(base, REG_EEPROM_CTRL); 58 if (!(data & EC_BUSY)) { 59 ret = ic_in16(base, REG_EEPROM_DATA); 60 break; 61 } 62 } 63 if (i == 100) 64 printf("IP1000: Fail to read EEPROM\n"); 65 return ret; 66 } 67 68 static u16_t read_phy_reg(u32_t base, int phy_addr, int phy_reg) { 69 int i, j, fieldlen[8]; 70 u32_t field[8]; 71 u8_t data, polar; 72 73 field[0] = 0xffffffff; fieldlen[0] = 32; 74 field[1] = 0x0001; fieldlen[1] = 2; 75 field[2] = 0x0002; fieldlen[2] = 2; 76 field[3] = phy_addr; fieldlen[3] = 5; 77 field[4] = phy_reg; fieldlen[4] = 5; 78 field[5] = 0x0000; fieldlen[5] = 2; 79 field[6] = 0x0000; fieldlen[6] = 16; 80 field[7] = 0x0000; fieldlen[7] = 1; 81 82 polar = ic_in8(base, REG_PHY_CTRL) & 0x28; 83 for (i = 0; i < 5; i++) { 84 for (j = 0; j < fieldlen[i]; j++) { 85 data = (field[i] >> (fieldlen[i] - j - 1)) << 1; 86 data = (0x02 & data) | (0x04 | polar); 87 ic_out8(base, REG_PHY_CTRL, data); 88 micro_delay(10); 89 ic_out8(base, REG_PHY_CTRL, (data | 0x01)); 90 micro_delay(10); 91 } 92 } 93 ic_out8(base, REG_PHY_CTRL, (polar | 0x04)); 94 micro_delay(10); 95 ic_out8(base, REG_PHY_CTRL, (polar | 0x05)); 96 micro_delay(10); 97 ic_out8(base, REG_PHY_CTRL, polar); 98 micro_delay(10); 99 data = ic_in8(base, REG_PHY_CTRL); 100 ic_out8(base, REG_PHY_CTRL, (polar | 0x01)); 101 micro_delay(10); 102 for (i = 0; i < fieldlen[6]; i++) { 103 ic_out8(base, REG_PHY_CTRL, polar); 104 micro_delay(10); 105 data = ((ic_in8(base, REG_PHY_CTRL) & 0x02) >> 1) & 0x01; 106 ic_out8(base, REG_PHY_CTRL, (polar | 0x01)); 107 micro_delay(10); 108 field[6] |= (data << (fieldlen[6] - i - 1)); 109 } 110 111 for (i = 0; i < 3; i++) { 112 ic_out8(base, REG_PHY_CTRL, (polar | 0x04)); 113 micro_delay(10); 114 ic_out8(base, REG_PHY_CTRL, (polar | 0x05)); 115 micro_delay(10); 116 } 117 ic_out8(base, REG_PHY_CTRL, (polar | 0x04)); 118 return field[6]; 119 } 120 121 static void write_phy_reg(u32_t base, int phy_addr, int phy_reg, u16_t val) { 122 int i, j, fieldlen[8]; 123 u32_t field[8]; 124 u8_t data, polar; 125 126 field[0] = 0xffffffff; fieldlen[0] = 32; 127 field[1] = 0x0001; fieldlen[1] = 2; 128 field[2] = 0x0001; fieldlen[2] = 2; 129 field[3] = phy_addr; fieldlen[3] = 5; 130 field[4] = phy_reg; fieldlen[4] = 5; 131 field[5] = 0x0002; fieldlen[5] = 2; 132 field[6] = val; fieldlen[6] = 16; 133 field[7] = 0x0000; fieldlen[7] = 1; 134 135 polar = ic_in8(base, REG_PHY_CTRL) & 0x28; 136 for (i = 0; i < 7; i++) { 137 for (j = 0; j < fieldlen[i]; j++) { 138 data = (field[i] >> (field[j] - j - 1)) << 1; 139 data = (0x02 & data) | (0x04 | polar); 140 ic_out8(base, REG_PHY_CTRL, data); 141 micro_delay(10); 142 ic_out8(base, REG_PHY_CTRL, (data | 0x01)); 143 micro_delay(10); 144 } 145 } 146 for (i = 0; i < fieldlen[7]; i ++) { 147 ic_out8(base, REG_PHY_CTRL, polar); 148 micro_delay(10); 149 field[7] |= ((ic_in8(base, REG_PHY_CTRL) & 0x02) >> 1) 150 << (fieldlen[7] - i -1); 151 ic_out8(base, REG_PHY_CTRL, (data | 0x01)); 152 micro_delay(10); 153 } 154 } 155 156 /* ====== Developer interface ======*/ 157 158 /* Intialize Rx descriptor (### RX_DESC_INIT ###) */ 159 static void ic_init_rx_desc(ic_desc *desc, size_t size, phys_bytes dma) { 160 desc->status = 0x0000000000000000ULL; 161 desc->frag_info = (u64_t)dma; 162 desc->frag_info |= ((u64_t)size << 48) & RFI_FRAG_LEN; 163 } 164 165 /* Intialize Tx descriptor (### TX_DESC_INIT ###) */ 166 static void ic_init_tx_desc(ic_desc *desc, size_t size, phys_bytes dma) { 167 desc->status = TFS_TFD_DONE; 168 desc->frag_info = (u64_t)dma; 169 } 170 171 /* Real hardware reset (### RESET_HARDWARE_CAN_FAIL ###) 172 * -- Return OK means success, Others means failure */ 173 static int ic_real_reset(u32_t base) { 174 u32_t data; 175 data = ic_in32(base, REG_ASIC_CTRL); 176 data |= AC_RESET_ALL; 177 ic_out32(base, REG_ASIC_CTRL, data); 178 micro_delay(10000); 179 if (ic_in32(base, REG_ASIC_CTRL) & AC_RESET_BUSY) 180 return -EIO; 181 return OK; 182 } 183 184 /* Intialize power (### POWER_INIT_CAN_FAIL ###) 185 * -- Return OK means success, Others means failure */ 186 static int ic_init_power(u32_t base) { 187 u8_t physet; 188 u32_t mode0, mode1; 189 190 mode0 = read_eeprom(base, 6); 191 mode1 = ic_in16(base, REG_ASIC_CTRL); 192 mode1 &= ~(AC_LED_MODE_B1 | AC_LED_MODE | AC_LED_SPEED); 193 if ((mode0 & 0x03) > 1) 194 mode1 |= AC_LED_MODE_B1; 195 if ((mode0 & 0x01) == 1) 196 mode1 |= AC_LED_MODE; 197 if ((mode0 & 0x08) == 8) 198 mode1 |= AC_LED_SPEED; 199 ic_out32(base, REG_ASIC_CTRL, mode1); 200 201 physet = ic_in8(base, REG_PHY_SET); 202 physet &= ~(0x07); 203 physet |= (mode0 & 0x70) >> 4; 204 ic_out8(base, REG_PHY_SET, physet); 205 206 return OK; 207 } 208 209 /* Intialize MII interface (### MII_INIT_CAN_FAIL ###) 210 * -- Return OK means success, Others means failure */ 211 static int ic_init_mii(u32_t base) { 212 int i, phyaddr; 213 u8_t revision; 214 u16_t phyctrl, cr1000, length, address, value; 215 u16_t *param; 216 u32_t status; 217 218 for (i = 0; i < 32; i++) { 219 phyaddr = (i + 0x01) % 32; 220 status = read_phy_reg(base, phyaddr, 0x01); 221 if ((status != 0xffff) && (status != 0)) 222 break; 223 } 224 if (i == 32) 225 return -EIO; 226 if (phyaddr != -1) { 227 cr1000 = read_phy_reg(base, phyaddr, 0x09); 228 cr1000 |= 0x0700; 229 write_phy_reg(base, phyaddr, 0x09, cr1000); 230 phyctrl = read_phy_reg(base, phyaddr, 0x00); 231 } 232 233 param = &PhyParam[0]; 234 length = (*param) & 0x00ff; 235 revision = (u8_t)((*param) >> 8); 236 param++; 237 while (length != 0) { 238 if (g_driver.revision == revision) { 239 while (length > 1) { 240 address = *param; 241 value = *(param + 1); 242 param += 2; 243 write_phy_reg(base, phyaddr, address, value); 244 length -= 4; 245 } 246 break; 247 } 248 else { 249 param += length / 2; 250 length = *param & 0x00ff; 251 revision = (u8_t)((*param) >> 8); 252 param++; 253 } 254 } 255 256 phyctrl |= 0x8200; 257 write_phy_reg(base, phyaddr, 0x00, phyctrl); 258 259 return OK; 260 } 261 262 /* Intialize other hardware I/O registers (### INIT_HARDWARE_IO_CAN_FAIL ###) 263 * -- Return OK means success, Others means failure */ 264 static int ic_init_io(u32_t base) { 265 u32_t mac_ctrl; 266 267 mac_ctrl = ic_in32(base, REG_MAC_CTRL); 268 mac_ctrl |= (MC_STAT_DISABLE | MC_TX_FC_ENA | MC_RX_FC_ENA); 269 ic_out32(base, REG_MAC_CTRL, 0x00000000); 270 ic_out16(base, REG_MAX_FRAME, RX_BUF_SIZE); 271 ic_out8(base, REG_RX_DMA_PERIOD, 0x01); 272 ic_out8(base, REG_RX_DMA_UTH, 0x30); 273 ic_out8(base, REG_RX_DMA_BTH, 0x30); 274 ic_out8(base, REG_TX_DMA_PERIOD, 0x26); 275 ic_out8(base, REG_TX_DMA_UTH, 0x04); 276 ic_out8(base, REG_TX_DMA_BTH, 0x30); 277 ic_out16(base, REG_FLOW_ON_TH, 0x0740); 278 ic_out16(base, REG_FLOW_OFF_TH, 0x00bf); 279 ic_out32(base, REG_MAC_CTRL, mac_ctrl); 280 return OK; 281 } 282 283 /* Start Rx/Tx (### START_RX_TX ###) */ 284 static void ic_start_rx_tx(u32_t base) { 285 u32_t mac_ctrl; 286 287 mac_ctrl = ic_in32(base, REG_MAC_CTRL); 288 mac_ctrl |= (MC_RX_ENABLE | MC_TX_ENABLE); 289 ic_out32(base, REG_MAC_CTRL, mac_ctrl); 290 } 291 292 /* Get MAC address to the array 'pa' (### GET_MAC_ADDR ###) */ 293 static void ic_get_addr(u32_t base, u8_t *pa) { 294 int i, sta_addr[3]; 295 for (i = 0; i < 3; i++) { 296 sta_addr[i] = read_eeprom(base, 16 + i); 297 ic_out16(base, (REG_STA_ADDR0 + i * 2), sta_addr[i]); 298 } 299 pa[0] = (u8_t)(ic_in16(base, REG_STA_ADDR0) & 0x00ff); 300 pa[1] = (u8_t)((ic_in16(base, REG_STA_ADDR0) & 0xff00) >> 8); 301 pa[2] = (u8_t)(ic_in16(base, REG_STA_ADDR1) & 0x00ff); 302 pa[3] = (u8_t)((ic_in16(base, REG_STA_ADDR1) & 0xff00) >> 8); 303 pa[4] = (u8_t)(ic_in16(base, REG_STA_ADDR2) & 0x00ff); 304 pa[5] = (u8_t)((ic_in16(base, REG_STA_ADDR2) & 0xff00) >> 8); 305 } 306 307 /* Check link status (### CHECK_LINK ###) 308 * -- Return LINK_UP or LINK_DOWN */ 309 static int ic_check_link(u32_t base) { 310 u8_t phy_ctrl; 311 u32_t mac_ctrl; 312 int ret; 313 char speed[20], duplex[20]; 314 315 phy_ctrl = ic_in8(base, REG_PHY_CTRL); 316 mac_ctrl = ic_in8(base, REG_MAC_CTRL); 317 switch (phy_ctrl & PC_LINK_SPEED) { 318 case PC_LINK_SPEED10: 319 strcpy(speed, "10Mbps"); 320 ret = LINK_UP; 321 break; 322 case PC_LINK_SPEED100: 323 strcpy(speed, "100Mbps"); 324 ret = LINK_UP; 325 break; 326 case PC_LINK_SPEED1000: 327 strcpy(speed, "1000Mbps"); 328 ret = LINK_UP; 329 break; 330 default: 331 strcpy(speed, "unknown"); 332 ret = LINK_DOWN; 333 break; 334 } 335 if (phy_ctrl & PC_DUPLEX_STS) { 336 strcpy(duplex, "full"); 337 mac_ctrl |= (MC_DUPLEX_SEL | MC_TX_FC_ENA | MC_RX_FC_ENA); 338 } 339 else 340 strcpy(duplex, "half"); 341 ic_out32(base, REG_MAC_CTRL, mac_ctrl); 342 #ifdef MY_DEBUG 343 printf("ip1000: Link speed is %s, %s duplex\n", speed, duplex); 344 #endif 345 return ret; 346 } 347 348 /* Stop Rx/Tx (### STOP_RX_TX ###) */ 349 static void ic_stop_rx_tx(u32_t base) { 350 ic_out32(base, REG_ASIC_CTRL, AC_RESET_ALL); 351 } 352 353 /* Check whether Rx status OK (### CHECK_RX_STATUS_OK ###) 354 * -- Return TRUE or FALSE */ 355 static int ic_rx_status_ok(ic_desc *desc) { 356 if ((desc->status & RFS_NORMAL) == RFS_NORMAL) 357 return TRUE; 358 return FALSE; 359 } 360 361 /* Get Rx data length from descriptor (### GET_RX_LEN ###) 362 * --- Return the length */ 363 static int ic_get_rx_len(ic_desc *desc) { 364 int totlen; 365 totlen = (u32_t)(desc->status & RFS_FRAME_LEN); 366 return totlen; 367 } 368 369 /* Set Tx descriptor in send (### TX_DESC_START ###) */ 370 static void ic_tx_desc_start(ic_desc *desc, size_t size) { 371 desc->status = TFS_TFD_DONE; 372 desc->status |= (u64_t)(TFS_WORD_ALIGN | (TFS_FRAMEID & (g_driver.tx_head)) 373 | (TFS_FRAG_COUNT & (1 << 24))); 374 desc->status |= TFS_TX_DMA_INDICATE; 375 desc->frag_info |= TFI_FRAG_LEN & ((u64_t)((size >= 60 ? size : 60) & 376 0xffff) << 48); 377 desc->status &= (u64_t)(~(TFS_TFD_DONE)); 378 } 379 380 /* Wake up Tx channel (### WAKE_UP_TX ###) */ 381 static void ic_wakeup_tx(u32_t base) { 382 ic_out32(base, REG_DMA_CTRL, 0x00001000); 383 } 384 385 /* Check whether Tx status OK (### CHECK_TX_STATUS_OK ###) 386 * -- Return TRUE or FALSE */ 387 static int ic_tx_status_ok(ic_desc *desc) { 388 if (desc->status & TFS_TFD_DONE) 389 return TRUE; 390 return FALSE; 391 } 392 393 /* Driver interface table */ 394 static const struct netdriver ic_table = { 395 .ndr_init = ic_init, 396 .ndr_stop = ic_stop, 397 .ndr_mode = ic_mode, 398 .ndr_recv = ic_recv, 399 .ndr_send = ic_send, 400 .ndr_stat = ic_stat, 401 .ndr_intr = ic_intr, 402 }; 403 404 int main(int argc, char *argv[]) { 405 env_setargs(argc, argv); 406 netdriver_task(&ic_table); 407 } 408 409 /* Initialize the driver */ 410 static int ic_init(unsigned int instance, ether_addr_t *addr) { 411 int ret = 0; 412 413 /* Intialize driver data structure */ 414 memset(&g_driver, 0, sizeof(g_driver)); 415 g_driver.link = LINK_UNKNOWN; 416 strcpy(g_driver.name, "netdriver#0"); 417 g_driver.name[10] += instance; 418 g_instance = instance; 419 420 /* Probe the device */ 421 if (ic_probe(&g_driver, instance)) { 422 printf("ip1000: Device is not found\n"); 423 ret = -ENODEV; 424 goto err_probe; 425 } 426 427 /* Allocate and initialize buffer */ 428 if (ic_init_buf(&g_driver)) { 429 printf("ip1000: Fail to initialize buffer\n"); 430 ret = -ENODEV; 431 goto err_init_buf; 432 } 433 434 /* Intialize hardware */ 435 if (ic_init_hw(&g_driver, addr)) { 436 printf("ip1000: Fail to initialize hardware\n"); 437 ret = -EIO; 438 goto err_init_hw; 439 } 440 441 /* Use a synchronous alarm instead of a watchdog timer */ 442 sys_setalarm(sys_hz(), 0); 443 444 /* Clear send and recv flag */ 445 g_driver.send_flag = FALSE; 446 g_driver.recv_flag = FALSE; 447 448 return 0; 449 450 err_init_hw: 451 free_contig(g_driver.buf, g_driver.buf_size); 452 err_init_buf: 453 err_probe: 454 return ret; 455 } 456 457 /* Match the device and get base address */ 458 static int ic_probe(ic_driver *pdev, int instance) { 459 int devind, ioflag; 460 u16_t cr, vid, did; 461 u32_t bar, size; 462 u8_t irq, rev; 463 u8_t *reg; 464 465 /* Find pci device */ 466 pci_init(); 467 if (!pci_first_dev(&devind, &vid, &did)) 468 return -EIO; 469 while (instance--) { 470 if (!pci_next_dev(&devind, &vid, &did)) 471 return -EIO; 472 } 473 pci_reserve(devind); 474 475 /* Enable bus mastering */ 476 cr = pci_attr_r16(devind, PCI_CR); 477 if (!(cr & PCI_CR_MAST_EN)) 478 pci_attr_w16(devind, PCI_CR, cr | PCI_CR_MAST_EN); 479 480 /* Get base address */ 481 #ifdef DMA_REG_MODE 482 if (pci_get_bar(devind, PCI_BAR, &base, &size, &ioflag)) { 483 printf("ip1000: Fail to get PCI BAR\n"); 484 return -EIO; 485 } 486 if (ioflag) { 487 printf("ip1000: PCI BAR is not for memory\n"); 488 return -EIO; 489 } 490 if ((reg = vm_map_phys(SELF, (void *)base, size)) == MAP_FAILED) { 491 printf("ip1000: Fail to map hardware registers from PCI\n"); 492 return -EIO; 493 } 494 pdev->base_addr = (u32_t)reg; 495 #else 496 bar = pci_attr_r32(devind, PCI_BAR) & 0xffffffe0; 497 if (bar < 0x400) { 498 printf("ip1000: Base address is not properly configured\n"); 499 return -EIO; 500 } 501 pdev->base_addr = bar; 502 #endif 503 504 /* Get irq number */ 505 irq = pci_attr_r8(devind, PCI_ILR); 506 pdev->irq = irq; 507 508 /* Get revision ID */ 509 rev = pci_attr_r8(devind, PCI_REV); 510 pdev->revision = rev; 511 512 #ifdef MY_DEBUG 513 printf("ip1000: Base address is 0x%08x\n", pdev->base_addr); 514 printf("ip1000: IRQ number is 0x%02x\n", pdev->irq); 515 printf("ip1000: Revision ID is 0x%02x\n", pdev->revision); 516 #endif 517 518 return 0; 519 } 520 521 /* Allocate and initialize buffer */ 522 static int ic_init_buf(ic_driver *pdev) { 523 size_t rx_desc_size, tx_desc_size, rx_buf_size, tx_buf_size, tot_buf_size; 524 ic_desc *desc; 525 phys_bytes buf_dma, next; 526 char *buf; 527 int i; 528 529 /* Build Rx and Tx descriptor buffer */ 530 rx_desc_size = RX_DESC_NUM * sizeof(ic_desc); 531 tx_desc_size = TX_DESC_NUM * sizeof(ic_desc); 532 533 /* Allocate Rx and Tx buffer */ 534 tx_buf_size = TX_BUF_SIZE; 535 if (tx_buf_size % 4) 536 tx_buf_size += 4 - (tx_buf_size % 4); 537 rx_buf_size = RX_BUF_SIZE; 538 tot_buf_size = rx_desc_size + tx_desc_size; 539 tot_buf_size += TX_DESC_NUM * tx_buf_size + RX_DESC_NUM * rx_buf_size; 540 if (tot_buf_size % 4096) 541 tot_buf_size += 4096 - (tot_buf_size % 4096); 542 543 if (!(buf = alloc_contig(tot_buf_size, 0, &buf_dma))) { 544 printf("ip1000: Fail to allocate memory\n"); 545 return -ENOMEM; 546 } 547 pdev->buf_size = tot_buf_size; 548 pdev->buf = buf; 549 550 /* Rx descriptor */ 551 pdev->rx_desc = (ic_desc *)buf; 552 pdev->rx_desc_dma = buf_dma; 553 memset(buf, 0, rx_desc_size); 554 buf += rx_desc_size; 555 buf_dma += rx_desc_size; 556 557 /* Tx descriptor */ 558 pdev->tx_desc = (ic_desc *)buf; 559 pdev->tx_desc_dma = buf_dma; 560 memset(buf, 0, tx_desc_size); 561 buf += tx_desc_size; 562 buf_dma += tx_desc_size; 563 564 /* Rx buffer assignment */ 565 desc = pdev->rx_desc; 566 next = pdev->rx_desc_dma; 567 for (i = 0; i < RX_DESC_NUM; i++) { 568 /* Set Rx buffer */ 569 pdev->rx[i].buf_dma = buf_dma; 570 pdev->rx[i].buf = buf; 571 buf_dma += rx_buf_size; 572 buf += rx_buf_size; 573 574 /* Set Rx descriptor */ 575 /* ### RX_DESC_INIT ### */ 576 ic_init_rx_desc(desc, rx_buf_size, pdev->rx[i].buf_dma); 577 if (i == (RX_DESC_NUM - 1)) 578 desc->next = pdev->rx_desc_dma; 579 else { 580 next += sizeof(ic_desc); 581 desc->next = next; 582 desc++; 583 } 584 } 585 586 /* Tx buffer assignment */ 587 desc = pdev->tx_desc; 588 next = pdev->tx_desc_dma; 589 for (i = 0; i < TX_DESC_NUM; i++) { 590 /* Set Tx buffer */ 591 pdev->tx[i].busy = 0; 592 pdev->tx[i].buf_dma = buf_dma; 593 pdev->tx[i].buf = buf; 594 buf_dma += tx_buf_size; 595 buf += tx_buf_size; 596 597 /* Set Rx descriptor */ 598 /* ### TX_DESC_INIT ### */ 599 ic_init_tx_desc(desc, tx_buf_size, pdev->tx[i].buf_dma); 600 if (i == (TX_DESC_NUM - 1)) 601 desc->next = pdev->tx_desc_dma; 602 else { 603 next += sizeof(ic_desc); 604 desc->next = next; 605 desc++; 606 } 607 } 608 pdev->tx_busy_num = 0; 609 pdev->tx_head = 0; 610 pdev->tx_tail = 0; 611 pdev->rx_head = 0; 612 613 return 0; 614 } 615 616 /* Intialize hardware */ 617 static int ic_init_hw(ic_driver *pdev, ether_addr_t *addr) { 618 int r, ret; 619 620 /* Set the OS interrupt handler */ 621 pdev->hook = pdev->irq; 622 if ((r = sys_irqsetpolicy(pdev->irq, 0, &pdev->hook)) != OK) { 623 printf("ip1000: Fail to set OS IRQ policy: %d\n", r); 624 ret = -EFAULT; 625 goto err_irq_policy; 626 } 627 628 /* Reset hardware */ 629 if (ic_reset_hw(pdev)) { 630 printf("ip1000: Fail to reset the device\n"); 631 ret = -EIO; 632 goto err_reset_hw; 633 } 634 635 /* Enable OS IRQ */ 636 if ((r = sys_irqenable(&pdev->hook)) != OK) { 637 printf("ip1000: Fail to enable OS IRQ: %d\n", r); 638 ret = -EFAULT; 639 goto err_irq_enable; 640 } 641 642 /* Configure MAC address */ 643 ic_conf_addr(pdev, addr); 644 645 /* Detect link status */ 646 pdev->link = ic_check_link(pdev->base_addr); 647 #ifdef MY_DEBUG 648 if (pdev->link) 649 printf("ip1000: Link up\n"); 650 else 651 printf("ip1000: Link down\n"); 652 #endif 653 654 return 0; 655 656 err_reset_hw: 657 err_irq_enable: 658 err_irq_policy: 659 return ret; 660 } 661 662 /* Reset hardware */ 663 static int ic_reset_hw(ic_driver *pdev) { 664 u32_t base = pdev->base_addr; 665 int ret; 666 667 /* Reset the chip */ 668 /* ### RESET_HARDWARE_CAN_FAIL ### */ 669 if (ic_real_reset(base)) { 670 printf("ip1000: Fail to reset the hardware\n"); 671 ret = -EIO; 672 goto err_real_reset; 673 } 674 675 /* Initialize power */ 676 /* ### POWER_INIT_CAN_FAIL ### */ 677 if (ic_init_power(base)) { 678 printf("ip1000: Fail to initialize power\n"); 679 ret = -EIO; 680 goto err_init_power; 681 } 682 683 /* Initialize MII interface */ 684 /* ### MII_INIT_CAN_FAIL ### */ 685 if (ic_init_mii(base)) { 686 printf("ip1000: Fail to initialize MII interface\n"); 687 ret = -EIO; 688 goto err_init_mii; 689 } 690 691 /* Initialize hardware I/O registers */ 692 /* ### SET_RX_DESC_REG ### */ 693 if (ic_init_io(base)) { 694 printf("ip1000: Fail to initialize I/O registers\n"); 695 ret = -EIO; 696 goto err_init_io; 697 } 698 699 /* Set Rx/Tx descriptor into register */ 700 /* ### SET_RX_DESC_REG ### */ 701 ic_out32(base, REG_RX_DESC_BASEL, pdev->rx_desc_dma); 702 #ifdef DESC_BASE_DMA64 703 ic_out32(base, REG_RX_DESC_BASEU, 0x00000000); 704 #endif 705 /* ### SET_TX_DESC_REG ### */ 706 ic_out32(base, REG_TX_DESC_BASEL, pdev->tx_desc_dma); 707 #ifdef DESC_BASE_DMA64 708 ic_out32(base, REG_TX_DESC_BASEU, 0x00000000); 709 #endif 710 711 /* Enable interrupts */ 712 /* ### ENABLE_INTR ### */ 713 ic_out16(base, REG_IMR, INTR_IMR_ENABLE); 714 715 /* Start the device, Rx and Tx */ 716 /* ### START_RX_TX ### */ 717 ic_start_rx_tx(base); 718 719 return 0; 720 721 err_init_io: 722 err_init_mii: 723 err_init_power: 724 err_real_reset: 725 return ret; 726 } 727 728 /* Configure MAC address */ 729 static void ic_conf_addr(ic_driver *pdev, ether_addr_t *addr) { 730 u8_t pa[6]; 731 u32_t base = pdev->base_addr; 732 733 /* Get MAC address */ 734 /* ### GET_MAC_ADDR ### */ 735 ic_get_addr(base, pa); 736 addr->ea_addr[0] = pa[0]; 737 addr->ea_addr[1] = pa[1]; 738 addr->ea_addr[2] = pa[2]; 739 addr->ea_addr[3] = pa[3]; 740 addr->ea_addr[4] = pa[4]; 741 addr->ea_addr[5] = pa[5]; 742 #ifdef MY_DEBUG 743 printf("ip1000: Ethernet address is %02x:%02x:%02x:%02x:%02x:%02x\n", 744 addr->ea_addr[0], addr->ea_addr[1], addr->ea_addr[2], 745 addr->ea_addr[3], addr->ea_addr[4], addr->ea_addr[5]); 746 #endif 747 } 748 749 /* Stop the driver */ 750 static void ic_stop(void) { 751 u32_t base = g_driver.base_addr; 752 753 /* Free Rx and Tx buffer*/ 754 free_contig(g_driver.buf, g_driver.buf_size); 755 756 /* Stop interrupt */ 757 /* ### DISABLE_INTR ### */ 758 ic_out16(base, REG_IMR, INTR_IMR_DISABLE); 759 760 /* Stop Rx/Tx */ 761 /* ### STOP_RX_TX ### */ 762 ic_stop_rx_tx(base); 763 } 764 765 /* Set driver mode */ 766 static void ic_mode(unsigned int mode) { 767 ic_driver *pdev = &g_driver; 768 u32_t base = pdev->base_addr; 769 u8_t rcr; 770 771 pdev->mode = mode; 772 773 /* ### READ_RCR ### */ 774 rcr = ic_in8(base, REG_RCR); 775 rcr &= ~(RCR_UNICAST | RCR_MULTICAST | RCR_BROADCAST); 776 if (pdev->mode & NDEV_PROMISC) 777 rcr |= RCR_UNICAST | RCR_MULTICAST; 778 if (pdev->mode & NDEV_BROAD) 779 rcr |= RCR_BROADCAST; 780 if (pdev->mode & NDEV_MULTI) 781 rcr |= RCR_MULTICAST; 782 rcr |= RCR_UNICAST; 783 /* ### WRITE_RCR ### */ 784 ic_out8(base, REG_RCR, rcr); 785 } 786 787 /* Receive data */ 788 static ssize_t ic_recv(struct netdriver_data *data, size_t max) { 789 ic_driver *pdev = &g_driver; 790 u32_t totlen, packlen; 791 ic_desc *desc; 792 int index, i; 793 794 index = pdev->rx_head; 795 desc = pdev->rx_desc; 796 desc += index; 797 798 /* Check whether the receiving is OK */ 799 /* ### CHECK_RX_STATUS_OK ### */ 800 if (ic_rx_status_ok(desc) != TRUE) 801 return SUSPEND; 802 803 /* Check Rx status error */ 804 /* ### CHECK_RX_STATUS_ERROR ### */ 805 if (desc->status & DESC_STATUS_RX_RECV_ERR) 806 printf("ip1000: Rx error\n"); 807 808 /* Get data length */ 809 /* ### Get Rx data length ### */ 810 totlen = ic_get_rx_len(desc); 811 if (totlen < 8 || totlen > 2 * ETH_MAX_PACK_SIZE) { 812 printf("ip1000: Bad data length: %d\n", totlen); 813 panic(NULL); 814 } 815 816 packlen = totlen; 817 if (packlen > max) 818 packlen = max; 819 820 /* Copy data to user */ 821 netdriver_copyout(data, 0, pdev->rx[index].buf, packlen); 822 pdev->stat.ets_packetR++; 823 824 /* Set Rx descriptor status */ 825 /* ### SET_RX_STATUS_INTR ### */ 826 desc->status = DESC_STATUS_RX_RECV_CLEAR; 827 if (index == RX_DESC_NUM - 1) 828 index = 0; 829 else 830 index++; 831 pdev->rx_head = index; 832 833 #ifdef MY_DEBUG 834 printf("ip1000: Successfully receive a packet, length = %d\n", packlen); 835 #endif 836 837 return packlen; 838 } 839 840 /* Transmit data */ 841 static int ic_send(struct netdriver_data *data, size_t size) { 842 ic_driver *pdev = &g_driver; 843 ic_desc *desc; 844 int tx_head, i; 845 u32_t base = pdev->base_addr; 846 847 tx_head = pdev->tx_head; 848 desc = pdev->tx_desc; 849 desc += tx_head; 850 851 if (pdev->tx[tx_head].busy) 852 return SUSPEND; 853 854 /* Copy data from user */ 855 netdriver_copyin(data, 0, pdev->tx[tx_head].buf, size); 856 857 /* Set busy */ 858 pdev->tx[tx_head].busy = TRUE; 859 pdev->tx_busy_num++; 860 861 /* Set Tx descriptor status */ 862 /* ### TX_DESC_START ### */ 863 ic_tx_desc_start(desc, size); 864 if (tx_head == TX_DESC_NUM - 1) 865 tx_head = 0; 866 else 867 tx_head++; 868 pdev->tx_head = tx_head; 869 870 /* Wake up transmit channel */ 871 /* ### WAKE_UP_TX ### */ 872 ic_wakeup_tx(base); 873 874 return 0; 875 } 876 877 /* Handle Interrupt */ 878 static void ic_intr(unsigned int mask) { 879 int s; 880 881 /* Run interrupt handler at driver level */ 882 ic_handler(&g_driver); 883 884 /* Reenable interrupts for this hook */ 885 if ((s = sys_irqenable(&g_driver.hook)) != OK) 886 printf("ip1000: Cannot enable OS interrupts: %d\n", s); 887 888 /* Perform tasks based on the flagged conditions */ 889 ic_check_ints(&g_driver); 890 } 891 892 /* Real handler interrupt */ 893 static void ic_handler(ic_driver *pdev) { 894 u32_t base = pdev->base_addr; 895 u16_t intr_status; 896 int flag = 0, tx_head, tx_tail; 897 ic_desc *desc; 898 899 /* Get interrupt status */ 900 /* ### GET_INTR_STATUS ### */ 901 intr_status = ic_in16(base, REG_ISR); 902 903 /* Clear interrupt */ 904 /* ### CLEAR_INTR ### */ 905 ic_out16(base, REG_ISR, intr_status & INTR_ISR_CLEAR); 906 907 /* Enable interrupt */ 908 /* ### ENABLE_INTR ### */ 909 ic_out16(base, REG_IMR, INTR_IMR_ENABLE); 910 911 /* Check interrupt error */ 912 /* ### CHECK_INTR_ERROR ### */ 913 if (intr_status & INTR_ISR_ERR) { 914 printf("ip1000: interrupt error\n"); 915 return; 916 } 917 918 /* Check link status */ 919 /* ### CHECK_LINK_INTR ### */ 920 if (intr_status & INTR_ISR_LINK_EVENT) { 921 pdev->link = ic_check_link(base); 922 #ifdef MY_DEBUG 923 printf("ip1000: Link state change\n"); 924 #endif 925 flag++; 926 } 927 928 /* Check Rx request status */ 929 /* ### CHECK_RX_INTR ### */ 930 if (intr_status & INTR_ISR_RX_DONE) { 931 pdev->recv_flag = TRUE; 932 flag++; 933 } 934 935 /* Check Tx request status */ 936 /* ### CHECK_TX_INTR ### */ 937 if (intr_status & INTR_ISR_TX_DONE) { 938 pdev->send_flag = TRUE; 939 flag++; 940 941 /* Manage Tx Buffer */ 942 tx_head = pdev->tx_head; 943 tx_tail = pdev->tx_tail; 944 while (tx_tail != tx_head) { 945 desc = pdev->tx_desc; 946 desc += tx_tail; 947 if (!pdev->tx[tx_tail].busy) 948 printf("ip1000: Strange, buffer not busy?\n"); 949 950 /* Check whether the transmiting is OK */ 951 /* ### CHECK_TX_STATUS_OK ### */ 952 if (ic_tx_status_ok(desc) != TRUE) 953 break; 954 955 /* Check Tx status error */ 956 /* ### CHECK_TX_STATUS_ERROR ### */ 957 if (desc->status & DESC_STATUS_TX_SEND_ERR) 958 printf("ip1000: Tx error\n"); 959 960 pdev->stat.ets_packetT++; 961 pdev->tx[tx_tail].busy = FALSE; 962 pdev->tx_busy_num--; 963 964 if (++tx_tail >= TX_DESC_NUM) 965 tx_tail = 0; 966 967 pdev->send_flag = TRUE; 968 pdev->recv_flag = TRUE; 969 970 /* Set Tx descriptor status in interrupt */ 971 /* ### SET_TX_STATUS_INTR ### */ 972 desc->status = DESC_STATUS_TX_SEND_CLEAR; 973 974 #ifdef MY_DEBUG 975 printf("ip1000: Successfully send a packet\n"); 976 #endif 977 } 978 pdev->tx_tail = tx_tail; 979 } 980 #ifdef MY_DEBUG 981 if (!flag) { 982 printf("ip1000: Unknown error in interrupt\n"); 983 return; 984 } 985 #endif 986 } 987 988 /* Check interrupt and perform */ 989 static void ic_check_ints(ic_driver *pdev) { 990 if (!pdev->recv_flag) 991 return; 992 pdev->recv_flag = FALSE; 993 994 /* Handle data receive */ 995 netdriver_recv(); 996 997 /* Handle data transmit */ 998 if (pdev->send_flag) { 999 pdev->send_flag = FALSE; 1000 netdriver_send(); 1001 } 1002 } 1003 1004 static void ic_stat(eth_stat_t *stat) { 1005 memcpy(stat, &g_driver.stat, sizeof(*stat)); 1006 } 1007