1 #ifndef _NDR_H 2 #define _NDR_H 3 4 /* ======= General Parameter ======= */ 5 /* Global configure */ 6 7 #include <minix/drivers.h> 8 9 #define DRIVER_NAME "IP1000" 10 11 /* Rx/Tx buffer parameter */ 12 #define RX_BUF_SIZE 1536 13 #define TX_BUF_SIZE 1536 14 #define RX_BUFFER_NUM 64 15 #define TX_BUFFER_NUM 64 16 17 /* Interrupt status */ 18 #define INTR_STS_LINK 0x0100 19 #define INTR_STS_RX 0x0400 20 #define INTR_STS_TX 0x0200 21 22 /* Link status */ 23 #define LINK_UP 1 24 #define LINK_DOWN 0 25 #define LINK_UNKNOWN -1 26 27 /* Interrupt control */ 28 #define INTR_ENABLE 1 29 #define INTR_DISABLE 0 30 31 /* Rx status */ 32 #define RX_ERROR 1 33 #define RX_OK 0 34 #define RX_SUSPEND -1 35 36 /* Tx status */ 37 #define TX_ERROR 1 38 #define TX_OK 0 39 #define TX_SUSPEND -1 40 41 /* Rx/Tx control */ 42 #define RX_TX_ENABLE 1 43 #define RX_TX_DISABLE 0 44 45 /* ======= Self-defined Parameter ======= */ 46 #define RFI_FRAG_LEN 0xffff000000000000ULL 47 #define RFS_FRAME_LEN 0x000000000000ffffULL 48 #define RFS_FRAME_START 0x0000000020000000ULL 49 #define RFS_FRAME_END 0x0000000040000000ULL 50 #define RFS_RFD_DONE 0x0000000080000000ULL 51 #define RFS_ERROR 0x00000000003f0000ULL 52 #define RFS_NORMAL (RFS_RFD_DONE | RFS_FRAME_START | RFS_FRAME_END) 53 54 #define TFI_FRAG_LEN 0xffff000000000000ULL 55 #define TFS_FRAMEID 0x000000000000ffffULL 56 #define TFS_WORD_ALIGN 0x0000000000030000ULL 57 #define TFS_TX_DMA_INDICATE 0x0000000000800000ULL 58 #define TFS_FRAG_COUNT 0x000000000f000000ULL 59 #define TFS_TFD_DONE 0x0000000080000000ULL 60 61 #define REG_DMA_CTRL 0x00 62 #define REG_TX_DESC_BASEL 0x10 63 #define REG_TX_DESC_BASEU 0x14 64 #define REG_TX_DMA_BTH 0x18 65 #define REG_TX_DMA_UTH 0x19 66 #define REG_TX_DMA_PERIOD 0x1a 67 #define REG_RX_DESC_BASEL 0x1c 68 #define REG_RX_DESC_BASEU 0x20 69 #define REG_RX_DMA_BTH 0x24 70 #define REG_RX_DMA_UTH 0x25 71 #define REG_RX_DMA_PERIOD 0x26 72 #define REG_ASIC_CTRL 0x30 73 #define REG_FLOW_OFF_TH 0x3c 74 #define REG_FLOW_ON_TH 0x3e 75 #define REG_EEPROM_DATA 0x48 76 #define REG_EEPROM_CTRL 0x4a 77 #define REG_ISR 0x5a 78 #define REG_IMR 0x5c 79 #define REG_MAC_CTRL 0x6c 80 #define REG_PHY_SET 0x75 81 #define REG_PHY_CTRL 0x76 82 #define REG_STA_ADDR0 0x78 83 #define REG_STA_ADDR1 0x7a 84 #define REG_STA_ADDR2 0x7c 85 #define REG_MAX_FRAME 0x86 86 #define REG_RCR 0x88 87 88 #define AC_LED_MODE 0x00004000 89 #define AC_GB_RESET 0x00010000 90 #define AC_RX_RESET 0x00020000 91 #define AC_TX_RESET 0x00040000 92 #define AC_DMA 0x00080000 93 #define AC_FIFO 0x00100000 94 #define AC_NETWORK 0x00200000 95 #define AC_HOST 0x00400000 96 #define AC_AUTO_INIT 0x00800000 97 #define AC_RESET_BUSY 0x04000000 98 #define AC_LED_SPEED 0x08000000 99 #define AC_LED_MODE_B1 0x20000000 100 #define AC_RESET_ALL (AC_GB_RESET | AC_RX_RESET | AC_TX_RESET | AC_DMA | \ 101 AC_FIFO | AC_NETWORK | AC_HOST | AC_AUTO_INIT) 102 103 #define MC_DUPLEX_SEL 0x00000020 104 #define MC_TX_FC_ENA 0x00000080 105 #define MC_RX_FC_ENA 0x00000100 106 #define MC_STAT_DISABLE 0x00400000 107 #define MC_TX_ENABLE 0x01000000 108 #define MC_TX_DISABLE 0x02000000 109 #define MC_RX_ENABLE 0x08000000 110 #define MC_RX_DISABLE 0x10000000 111 #define MC_PAUSED 0x40000000 112 113 #define PC_DUPLEX_STS 0x10 114 #define PC_LINK_SPEED 0xc0 115 #define PC_LINK_SPEED10 0x40 116 #define PC_LINK_SPEED100 0x80 117 #define PC_LINK_SPEED1000 0xc0 118 119 #define CMD_INTR_ENABLE 0x17e6 120 #define CMD_RCR_UNICAST 0x01 121 #define CMD_RCR_MULTICAST 0x02 122 #define CMD_RCR_BROADCAST 0x04 123 #define CMD_TX_START 0x1000 124 125 #define EC_READ 0x0200 126 #define EC_BUSY 0x8000 127 128 static u16_t PhyParam[] = { 129 (0x4000|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000, 130 30, 0x005e, 9, 0x0700, 131 (0x4100|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000, 132 30, 0x005e, 9, 0x0700, 133 (0x4200|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000, 134 30, 0x005e, 9, 0x0700, 135 (0x4300|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000, 136 30, 0x005e, 9, 0x0700, 0x0000 137 }; 138 139 /* ======= Data Descriptor ======= */ 140 typedef struct NDR_desc { 141 u64_t next; 142 u64_t status; 143 u64_t frag_info; 144 } NDR_desc; 145 146 /* Driver Data Structure */ 147 typedef struct NDR_driver { 148 char *dev_name; /* Device name */ 149 u16_t vid, did; /* Vendor and device ID */ 150 u32_t devind; /* Device index */ 151 u32_t base[6]; /* Base address */ 152 char irq; /* IRQ number */ 153 char revision; /* Revision ID */ 154 155 int mode; 156 int link; /* Whether link-up */ 157 int recv_flag; /* Receive flag */ 158 int send_flag; /* Send flag */ 159 int tx_busy; /* Whether Tx is busy */ 160 161 /* Buffer */ 162 size_t buf_size; 163 char *buf; 164 165 /* Rx data */ 166 int rx_head; 167 struct { 168 phys_bytes buf_dma; 169 char *buf; 170 } rx[RX_BUFFER_NUM]; 171 172 /* Tx data */ 173 int tx_head; 174 int tx_tail; 175 struct { 176 int busy; 177 phys_bytes buf_dma; 178 char *buf; 179 } tx[TX_BUFFER_NUM]; 180 int tx_busy_num; /* Number of busy Tx buffer */ 181 182 NDR_desc *rx_desc; /* Rx descriptor buffer */ 183 phys_bytes rx_desc_dma; /* Rx descriptor DMA buffer */ 184 NDR_desc *tx_desc; /* Tx descriptor buffer */ 185 phys_bytes tx_desc_dma; /* Tx descriptor DMA buffer */ 186 187 int hook; /* IRQ hook id at kernel */ 188 eth_stat_t stat; /* Ethernet status */ 189 char name[50]; /* Driver name */ 190 } NDR_driver; 191 192 #endif 193