1 #include <minix/blockdriver.h> 2 #include <minix/board.h> 3 #include <minix/log.h> 4 #include <minix/mmio.h> 5 #include <minix/spin.h> 6 #include <minix/syslib.h> 7 8 #include <sys/mman.h> 9 10 #include "omap_mmc.h" 11 #include "mmchost.h" 12 #include "sdmmcreg.h" 13 14 /* MINIX IRQ timeout. Twice the host controller data/busy timeout @ 48MHz. */ 15 #define IRQ_TIMEOUT 5600000 /* 5,600,000 us */ 16 17 #define MMCHS_TIMEOUT 500000 /* 500,000 us */ 18 19 /* Reference clock frequency divisors: */ 20 #define MMCHS_SD_SYSCTL_CLKD_400KHZ 240 /* 96MHz/400kHz */ 21 #define MMCHS_SD_SYSCTL_CLKD_26MHZ 4 /* ceiling 96MHz/26MHz */ 22 #define MMCHS_SD_SYSCTL_CLKD_52MHZ 2 /* ceiling 96MHz/52MHz */ 23 24 /* The host SD_DATA register is 128 words (512B). */ 25 #define SD_DATA_WLEN 128 26 27 /* 28 * Card initialization timeout, twice the standard: 29 * "The device must complete its initialization within 1 second of the first 30 * CMD1 issued with a valid OCR range." (MMCA, 4.41) 31 */ 32 #define CARD_INI_TIMEOUT 2000000 /* 2,000,000 us */ 33 34 /* Card EXT_CSD register fields. */ 35 #define MMC_EXT_CSD_SEC_COUNT (*(uint32_t *)&card_ext_csd[212]) 36 #define MMC_EXT_CSD_CARD_TYPE (card_ext_csd[196]) 37 #define MMC_EXT_CSD_CARD_TYPE_HS_MMC_52MHZ (0x1 << 1) 38 39 /* Card intended operating voltage range: 2.7V to 3.6V */ 40 #define MMC_OCR_VDD_RANGE 0x00FF8000 41 42 /* Error bits in the card status (R1) response. */ 43 #define R1_ERROR_MASK 0xFDFFA080 44 45 /* Relative Card Address. Must be greater than 1. */ 46 #define RCA 0x2 47 48 /* The card sector size is 512B. */ 49 #define SEC_SIZE 512 50 51 /* 52 * AM335x Control Module registers CONF_GPMC_ADn. 53 * Configuration do multiplex CONF_GPMC_ADn to signals MMC1_DATn (Mode 1). 54 */ 55 #define CONF_GPMC_AD(N) (0x800 + 4*(N)) 56 #define CONF_GPMC_AD_MASK 0x7F 57 #define CONF_GPMC_AD_VAL 0x31 58 59 /* AM335x MMC1 memory map (physical start address and size). */ 60 #define AM335X_MMC1_BASE_ADDR 0x481D8000 61 #define AM335X_MMC1_SIZE (4 << 10) 62 /* AM335x MMC1 interrupt number. */ 63 #define AM335X_MMCSD1INT 28 64 65 static uint32_t bus_width; 66 67 /* AM335x MMCHS registers virtual addresses: virtual base + offset. */ 68 static struct omap_mmchs_registers *reg; 69 70 /* Card registers. */ 71 static uint32_t card_csd[4]; 72 static uint8_t card_ext_csd[512]; 73 74 static uint32_t card_write_protect; 75 static uint64_t card_size; 76 77 /* IRQ_HOOK_ID for SYS_IRQCTL kernel call. */ 78 static int hook_id = 1; 79 80 /* Initialize the log system. */ 81 static struct log log = { 82 .name = "emmc", 83 .log_level = LEVEL_INFO, 84 .log_func = default_log, 85 }; 86 87 88 /* 89 * Spin until a register flag is set, or the time runs out. 90 * Return the flag value. 91 */ 92 static uint32_t 93 spin_until_set(uint32_t address, uint32_t flag) 94 { 95 spin_t s; 96 int spin; 97 uint32_t v; 98 99 spin_init(&s, MMCHS_TIMEOUT); 100 do { 101 spin = spin_check(&s); 102 v = (read32(address) & flag); 103 } while ((v == 0) && (spin == TRUE)); 104 105 return v; 106 } 107 108 /* 109 * Spin until a register flag is clear, or the time runs out. 110 * Return the flag value. 111 */ 112 static uint32_t 113 spin_until_clear(uint32_t address, uint32_t flag) 114 { 115 spin_t s; 116 int spin; 117 uint32_t v; 118 119 spin_init(&s, MMCHS_TIMEOUT); 120 do { 121 spin = spin_check(&s); 122 v = (read32(address) & flag); 123 } while ((v != 0) && (spin == TRUE)); 124 125 return v; 126 } 127 128 /* 129 * Change the bus clock frequency (divisor). 130 * Return 0 on success, a negative integer on error. 131 */ 132 static int 133 set_bus_clkd(uint32_t clkd) 134 { 135 /* 136 * Disable the bus clock, set the clock divider, wait until the 137 * internal clock is stable, enable the bus clock. 138 */ 139 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_CEN, MMCHS_SD_SYSCTL_CEN_DIS); 140 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_CLKD, clkd << 6); 141 if (spin_until_set(reg->SYSCTL, MMCHS_SD_SYSCTL_ICS) 142 == MMCHS_SD_SYSCTL_ICS_UNSTABLE) 143 return -1; 144 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_CEN, MMCHS_SD_SYSCTL_CEN_EN); 145 146 return 0; 147 } 148 149 /* 150 * Receive an interrupt request. 151 * Return 0 on success, a negative integer on error. 152 */ 153 static int 154 irq_receive(void) 155 { 156 message m; 157 int ipc_status; 158 159 while (1) { 160 if (driver_receive(ANY, &m, &ipc_status) != OK) 161 return -1; 162 if (is_ipc_notify(ipc_status) 163 && (_ENDPOINT_P(m.m_source) == CLOCK)) 164 return -1; 165 if (is_ipc_notify(ipc_status) 166 && (_ENDPOINT_P(m.m_source) == HARDWARE)) 167 return 0; 168 /* 169 * m will be discarded if the driver is out of memory. 170 */ 171 blockdriver_mq_queue(&m, ipc_status); 172 } 173 } 174 175 /* 176 * Wait for an interrupt request. 177 * Return 0 on interrupt, a negative integer on error. 178 */ 179 static int 180 irq_wait(void) 181 { 182 int r; 183 184 if (sys_irqenable(&hook_id) != OK) 185 return -1; 186 sys_setalarm(micros_to_ticks(IRQ_TIMEOUT), 0); 187 r = irq_receive(); 188 sys_setalarm(0, 0); 189 if (r < 0) 190 sys_irqdisable(&hook_id); 191 192 return r; 193 } 194 195 /* 196 * Software reset for mmc_cmd or mmc_dat line. 197 */ 198 static void 199 reset_mmchs_fsm(uint32_t line) 200 { 201 /* 202 * "The proper procedure is: (a) Set to 1 to start reset, 203 * (b) Poll for 1 to identify start of reset, and 204 * (c) Poll for 0 to identify reset is complete." (AM335x TRM) 205 */ 206 set32(reg->SYSCTL, line, line); 207 spin_until_set(reg->SYSCTL, line); 208 spin_until_clear(reg->SYSCTL, line); 209 } 210 211 /* 212 * Send a command to the card. 213 * Return 0 on success, a negative integer on error. 214 */ 215 static int 216 send_cmd(uint32_t arg, uint32_t cmd) 217 { 218 uint32_t stat; 219 220 if (read32(reg->PSTATE) 221 & (MMCHS_SD_PSTATE_DATI | MMCHS_SD_PSTATE_CMDI)) 222 return -1; /* Issuing of commands is not allowed. */ 223 write32(reg->ARG, arg); 224 write32(reg->CMD, cmd); 225 /* Wait for the command completion. */ 226 if (irq_wait() < 0) 227 return -1; 228 stat = read32(reg->SD_STAT); 229 /* 230 * Clear only the command status/error bits. The transfer status/error 231 * bits (including ERRI) must be preserved. 232 */ 233 write32(reg->SD_STAT, MMCHS_SD_STAT_CIE 234 | MMCHS_SD_STAT_CEB 235 | MMCHS_SD_STAT_CCRC 236 | MMCHS_SD_STAT_CTO 237 | MMCHS_SD_STAT_CC); 238 if (stat & MMCHS_SD_STAT_CTO) { 239 reset_mmchs_fsm(MMCHS_SD_SYSCTL_SRC); 240 return -1; 241 } 242 243 return 0; 244 } 245 246 /* 247 * Send a command to the card, and check for errors in the response (R1). 248 * Return 0 on success, a negative integer on error. 249 */ 250 static int 251 send_cmd_check_r1(uint32_t arg, uint32_t cmd) 252 { 253 if (send_cmd(arg, cmd) < 0) 254 return -1; 255 /* Check for card errors in the card response (R1). */ 256 if (read32(reg->RSP10) & R1_ERROR_MASK) 257 return -1; 258 259 return 0; 260 } 261 262 /* Send CMD0 (GO_IDLE_STATE) command to the card. */ 263 static int 264 go_idle_state(void) 265 { 266 return send_cmd(MMC_GO_IDLE_STATE, MMC_GO_IDLE_STATE); 267 } 268 269 /* Send CMD1 (SEND_OP_COND) command to the card. */ 270 static int 271 send_op_cond(void) 272 { 273 uint32_t cmd; 274 275 /* The driver is capable of handling sector type of addressing. */ 276 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SEND_OP_COND) 277 | MMCHS_SD_CMD_RSP_TYPE_48B; 278 return send_cmd((MMC_OCR_HCS | MMC_OCR_VDD_RANGE), cmd); 279 } 280 281 /* Send CMD2 (ALL_SEND_CID) command to the card. */ 282 static int 283 all_send_cid(void) 284 { 285 uint32_t cmd; 286 287 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_ALL_SEND_CID) 288 | MMCHS_SD_CMD_CCCE_ENABLE 289 | MMCHS_SD_CMD_RSP_TYPE_136B; 290 return send_cmd(0, cmd); 291 } 292 293 /* Send CMD3 (SET_RELATIVE_ADDR) command to the card. */ 294 static int 295 set_relative_addr(void) 296 { 297 uint32_t cmd; 298 299 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SET_RELATIVE_ADDR) 300 | MMCHS_SD_CMD_CICE_ENABLE 301 | MMCHS_SD_CMD_CCCE_ENABLE 302 | MMCHS_SD_CMD_RSP_TYPE_48B; 303 return send_cmd_check_r1(MMC_ARG_RCA(RCA), cmd); 304 } 305 306 /* Send CMD6 (SWITCH) command to the card. */ 307 static int 308 mmc_switch(uint32_t access, uint32_t index, uint32_t value) 309 { 310 uint32_t arg, cmd; 311 312 /* SWITCH argument: [25:24] Access, [23:16] Index, [15:8] Value. */ 313 arg = (access << 24) | (index << 16) | (value << 8); 314 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SWITCH) 315 | MMCHS_SD_CMD_CICE_ENABLE 316 | MMCHS_SD_CMD_CCCE_ENABLE 317 | MMCHS_SD_CMD_RSP_TYPE_48B_BUSY; 318 return send_cmd_check_r1(arg, cmd); 319 } 320 321 /* Send CMD7 (SELECT_CARD) command to the card. */ 322 static int 323 select_card(void) 324 { 325 uint32_t cmd; 326 327 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SELECT_CARD) 328 | MMCHS_SD_CMD_CICE_ENABLE 329 | MMCHS_SD_CMD_CCCE_ENABLE 330 | MMCHS_SD_CMD_RSP_TYPE_48B; 331 return send_cmd_check_r1(MMC_ARG_RCA(RCA), cmd); 332 } 333 334 /* Send CMD8 (SEND_EXT_CSD) command to the card. */ 335 static int 336 send_ext_csd(void) 337 { 338 uint32_t cmd; 339 340 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SEND_EXT_CSD) 341 | MMCHS_SD_CMD_DP_DATA 342 | MMCHS_SD_CMD_CICE_ENABLE 343 | MMCHS_SD_CMD_CCCE_ENABLE 344 | MMCHS_SD_CMD_RSP_TYPE_48B 345 | MMCHS_SD_CMD_DDIR_READ; 346 return send_cmd_check_r1(0, cmd); 347 } 348 349 /* Send CMD9 (SEND_CSD) command to the card. */ 350 static int 351 send_csd(void) 352 { 353 uint32_t cmd; 354 355 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SEND_CSD) 356 | MMCHS_SD_CMD_CCCE_ENABLE 357 | MMCHS_SD_CMD_RSP_TYPE_136B; 358 return send_cmd(MMC_ARG_RCA(RCA), cmd); 359 } 360 361 /* Send CMD13 (SEND_STATUS) command to the card. */ 362 static int 363 send_status(void) 364 { 365 uint32_t cmd; 366 367 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SEND_STATUS) 368 | MMCHS_SD_CMD_CICE_ENABLE 369 | MMCHS_SD_CMD_CCCE_ENABLE 370 | MMCHS_SD_CMD_RSP_TYPE_48B; 371 return send_cmd_check_r1(MMC_ARG_RCA(RCA), cmd); 372 } 373 374 /* Send CMD16 (SET_BLOCKLEN) command to the card. */ 375 static int 376 set_blocklen(void) 377 { 378 uint32_t cmd; 379 380 /* Set block length to sector size (512B). */ 381 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_SET_BLOCKLEN) 382 | MMCHS_SD_CMD_CICE_ENABLE 383 | MMCHS_SD_CMD_CCCE_ENABLE 384 | MMCHS_SD_CMD_RSP_TYPE_48B; 385 return send_cmd_check_r1(SEC_SIZE, cmd); 386 } 387 388 /* Send CMD17 (READ_SINGLE_BLOCK) to the card. */ 389 static int 390 read_single_block(uint32_t addr) 391 { 392 uint32_t cmd; 393 394 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_READ_BLOCK_SINGLE) 395 | MMCHS_SD_CMD_DP_DATA 396 | MMCHS_SD_CMD_CICE_ENABLE 397 | MMCHS_SD_CMD_CCCE_ENABLE 398 | MMCHS_SD_CMD_RSP_TYPE_48B 399 | MMCHS_SD_CMD_DDIR_READ; 400 return send_cmd_check_r1(addr, cmd); 401 } 402 403 /* Send CMD24 (WRITE_BLOCK) to the card. */ 404 static int 405 write_block(uint32_t addr) 406 { 407 uint32_t cmd; 408 409 cmd = MMCHS_SD_CMD_INDX_CMD(MMC_WRITE_BLOCK_SINGLE) 410 | MMCHS_SD_CMD_DP_DATA 411 | MMCHS_SD_CMD_CICE_ENABLE 412 | MMCHS_SD_CMD_CCCE_ENABLE 413 | MMCHS_SD_CMD_RSP_TYPE_48B 414 | MMCHS_SD_CMD_DDIR_WRITE; 415 return send_cmd_check_r1(addr, cmd); 416 } 417 418 /* 419 * Repeat CMD1 until the card is ready, or the time runs out. 420 * Return 0 on ready, a negative integer on error. 421 */ 422 static int 423 repeat_send_op_cond(void) 424 { 425 spin_t s; 426 int spin; 427 uint32_t card_ocr; 428 429 spin_init(&s, CARD_INI_TIMEOUT); 430 do { 431 spin = spin_check(&s); 432 if (send_op_cond() < 0) 433 return -1; 434 card_ocr = read32(reg->RSP10); 435 } while (((card_ocr & MMC_OCR_MEM_READY) == 0) && (spin == TRUE)); 436 437 if ((card_ocr & MMC_OCR_MEM_READY) == 0) 438 return -1; /* Card is still busy. */ 439 440 return 0; 441 } 442 443 /* 444 * Read (receive) the busy signal from the card. 445 * Return 0 on success, a negative integer on error. 446 */ 447 static int 448 read_busy(void) 449 { 450 uint32_t stat; 451 /* 452 * The busy signal is optional, but the host controller will assert 453 * SD_STAT[1] TC even if the card does not send it. 454 */ 455 if (irq_wait() < 0) 456 return -1; 457 stat = read32(reg->SD_STAT); 458 write32(reg->SD_STAT, MMCHS_SD_STAT_DCRC 459 | MMCHS_SD_STAT_DTO 460 | MMCHS_SD_STAT_TC); 461 if (stat & MMCHS_SD_STAT_ERRI) { 462 reset_mmchs_fsm(MMCHS_SD_SYSCTL_SRD); 463 return -1; 464 } 465 466 return 0; 467 } 468 469 /* 470 * Read (receive) data from the card. 471 * Return 0 on success, a negative integer on error. 472 */ 473 static int 474 read_data(uint32_t *data) 475 { 476 uint32_t stat, i; 477 478 /* Wait for BRR interrupt. */ 479 if (irq_wait() < 0) 480 return -1; 481 if (read32(reg->SD_STAT) & MMCHS_SD_STAT_BRR) { 482 write32(reg->SD_STAT, MMCHS_SD_STAT_BRR); 483 for (i=SD_DATA_WLEN; i>0; i--) 484 *data++ = read32(reg->DATA); 485 } 486 487 /* Wait for TC or ERRI interrupt. */ 488 if (irq_wait() < 0) 489 return -1; 490 stat = read32(reg->SD_STAT); 491 write32(reg->SD_STAT, MMCHS_SD_STAT_DEB 492 | MMCHS_SD_STAT_DCRC 493 | MMCHS_SD_STAT_DTO 494 | MMCHS_SD_STAT_TC); 495 if (stat & MMCHS_SD_STAT_ERRI) { 496 reset_mmchs_fsm(MMCHS_SD_SYSCTL_SRD); 497 return -1; 498 } 499 500 return 0; 501 } 502 503 /* 504 * Write (send) data to the card. 505 * Return 0 on success, a negative integer on error. 506 */ 507 static int 508 write_data(uint32_t *data) 509 { 510 uint32_t stat, i; 511 512 /* Wait for BWR interrupt. */ 513 if (irq_wait() < 0) 514 return -1; 515 if (read32(reg->SD_STAT) & MMCHS_SD_STAT_BWR) { 516 write32(reg->SD_STAT, MMCHS_SD_STAT_BWR); 517 for (i=SD_DATA_WLEN; i>0; i--) 518 write32(reg->DATA, *data++); 519 } 520 521 /* Wait for TC or ERRI interrupt. */ 522 if (irq_wait() < 0) 523 return -1; 524 stat = read32(reg->SD_STAT); 525 write32(reg->SD_STAT, MMCHS_SD_STAT_DEB 526 | MMCHS_SD_STAT_DCRC 527 | MMCHS_SD_STAT_DTO 528 | MMCHS_SD_STAT_TC); 529 if (stat & MMCHS_SD_STAT_ERRI) { 530 reset_mmchs_fsm(MMCHS_SD_SYSCTL_SRD); 531 return -1; 532 } 533 534 return 0; 535 } 536 537 /* 538 * Read a block from the card. 539 * Return 0 on success, a negative integer on error. 540 */ 541 static int 542 cim_read_block(uint32_t addr, uint32_t *data) 543 { 544 /* Send CMD17. */ 545 if (read_single_block(addr) < 0) 546 return -1; 547 /* Read from the host buffer. */ 548 return read_data(data); 549 } 550 551 /* 552 * Write a block to the card. 553 * Return 0 on success, a negative integer on error. 554 */ 555 static int 556 cim_write_block(uint32_t addr, uint32_t *data) 557 { 558 /* Send CMD24. */ 559 if (write_block(addr) < 0) 560 return -1; 561 /* Write into the host buffer. */ 562 if (write_data(data) < 0) 563 return -1; 564 /* CMD13. Check the result of the write operation. */ 565 return send_status(); 566 } 567 568 569 /* 570 * Interface to the MINIX block device driver. 571 */ 572 static int 573 emmc_host_set_instance(struct mmc_host *host, int instance) 574 { 575 if (instance != 0) 576 return EIO; 577 return 0; 578 } 579 580 /* 581 * Initialize the driver and kernel structures. 582 * Return 0 on success, a negative integer on error. 583 */ 584 static int 585 minix_init(void) 586 { 587 struct minix_mem_range mr; 588 uint32_t v_base; 589 590 /* 591 * On the BeagleBone Black, the eMMC device is connected to MMC1. 592 * Add the MMC1 memory address range to the process' resources. 593 */ 594 mr.mr_base = AM335X_MMC1_BASE_ADDR; 595 mr.mr_limit = AM335X_MMC1_BASE_ADDR + AM335X_MMC1_SIZE - 1; 596 if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != OK) 597 return -1; 598 599 /* Map the MMC1 physical base address to a virtual address. */ 600 v_base = (uint32_t)vm_map_phys(SELF, (void *)mr.mr_base, 601 AM335X_MMC1_SIZE); 602 if (v_base == (uint32_t)MAP_FAILED) 603 return -1; 604 605 /* Set the registers virtual addresses. */ 606 reg = ®s_v1; 607 reg->SYSCONFIG += v_base; 608 reg->SYSSTATUS += v_base; 609 reg->CON += v_base; 610 reg->BLK += v_base; 611 reg->ARG += v_base; 612 reg->CMD += v_base; 613 reg->RSP10 += v_base; 614 reg->RSP32 += v_base; 615 reg->RSP54 += v_base; 616 reg->RSP76 += v_base; 617 reg->DATA += v_base; 618 reg->PSTATE += v_base; 619 reg->HCTL += v_base; 620 reg->SYSCTL += v_base; 621 reg->SD_STAT += v_base; 622 reg->IE += v_base; 623 reg->ISE += v_base; 624 625 /* Register the MMC1 interrupt number. */ 626 if (sys_irqsetpolicy(AM335X_MMCSD1INT, 0, &hook_id) != OK) 627 return -1; 628 629 return 0; 630 } 631 632 /* 633 * Configure the Control Module registers CONF_GPMC_AD4-7. 634 * Multiplex pins GPMC_AD4-7 to signals MMC1_DAT4-7 (Mode 1). 635 * Return 0 on success, a negative integer on error. 636 */ 637 static int 638 conf_gpmc_ad(void) 639 { 640 uint32_t i; 641 642 for (i=4; i<8; i++) { 643 if (sys_padconf(CONF_GPMC_AD(i), CONF_GPMC_AD_MASK, 644 CONF_GPMC_AD_VAL) != OK) 645 return -1; 646 } 647 return 0; 648 } 649 650 /* 651 * Interface to the MINIX block device driver. 652 * Host controller initialization. 653 * Return 0 on success, a negative integer on error. 654 */ 655 static int 656 emmc_host_init(struct mmc_host *host) 657 { 658 struct machine machine; 659 660 /* The eMMC is present on the BBB only. */ 661 sys_getmachine(&machine); 662 if (!BOARD_IS_BBB(machine.board_id)) 663 return -1; 664 665 /* Initialize the driver and kernel structures. */ 666 if (minix_init() < 0) 667 return -1; 668 669 /* 670 * Multiplex pins GPMC_AD4-7 to signals MMC1_DAT4-7 (Mode 1), in order 671 * to allow the use of 8-bit mode. 672 * U-Boot multiplexes only pins GPMC_AD0-3 to signals MMC1_DAT0-3. 673 */ 674 if (conf_gpmc_ad() < 0) 675 bus_width = EXT_CSD_BUS_WIDTH_4; 676 else 677 bus_width = EXT_CSD_BUS_WIDTH_8; 678 679 /* Reset the host controller. */ 680 set32(reg->SYSCONFIG, MMCHS_SD_SYSCONFIG_SOFTRESET, 681 MMCHS_SD_SYSCONFIG_SOFTRESET); 682 if (spin_until_set(reg->SYSSTATUS, MMCHS_SD_SYSSTATUS_RESETDONE) 683 != MMCHS_SD_SYSSTATUS_RESETDONE) 684 return -1; 685 686 /* 687 * SD_CAPA: "The host driver shall not modify this register after the 688 * initialization." (AM335x TRM) 689 */ 690 691 /* 692 * Set the bus voltage to 3V, and turn the bus power on. 693 * On the BeagleBone Black, the bus voltage is pulled up to 3.3V, but 694 * the MMCHS supports only 1.8V or 3V. 695 */ 696 set32(reg->HCTL, MMCHS_SD_HCTL_SDVS, MMCHS_SD_HCTL_SDVS_VS30); 697 set32(reg->HCTL, MMCHS_SD_HCTL_SDBP, MMCHS_SD_HCTL_SDBP_ON); 698 if (spin_until_set(reg->HCTL, MMCHS_SD_HCTL_SDBP) 699 == MMCHS_SD_HCTL_SDBP_OFF) 700 return -1; 701 702 /* Set the bus clock frequency to FOD (400kHz). */ 703 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_CLKD, 704 MMCHS_SD_SYSCTL_CLKD_400KHZ << 6); 705 706 /* Set data and busy time-out: ~2,6s @ 400kHz.*/ 707 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_DTO, MMCHS_SD_SYSCTL_DTO_2POW20); 708 709 /* Enable the internal clock. */ 710 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_ICE, MMCHS_SD_SYSCTL_ICE_EN); 711 if (spin_until_set(reg->SYSCTL, MMCHS_SD_SYSCTL_ICS) 712 == MMCHS_SD_SYSCTL_ICS_UNSTABLE) 713 return -1; 714 715 /* Enable the bus clock. */ 716 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_CEN, MMCHS_SD_SYSCTL_CEN_EN); 717 718 /* 719 * Set the internal clock gating strategy to automatic, and enable 720 * Smart Idle mode. The host controller does not implement wake-up 721 * request (SWAKEUP pin is not connected). 722 */ 723 set32(reg->SYSCONFIG, MMCHS_SD_SYSCONFIG_AUTOIDLE, 724 MMCHS_SD_SYSCONFIG_AUTOIDLE_EN); 725 set32(reg->SYSCONFIG, MMCHS_SD_SYSCONFIG_SIDLEMODE, 726 MMCHS_SD_SYSCONFIG_SIDLEMODE_IDLE); 727 728 /* The driver reads and writes single 512B blocks. */ 729 set32(reg->BLK, MMCHS_SD_BLK_BLEN, SEC_SIZE); 730 731 /* Enable interrupt status and requests. */ 732 write32(reg->IE, MMCHS_SD_IE_ERROR_MASK 733 | MMCHS_SD_IE_BRR_ENABLE_ENABLE 734 | MMCHS_SD_IE_BWR_ENABLE_ENABLE 735 | MMCHS_SD_IE_TC_ENABLE_ENABLE 736 | MMCHS_SD_IE_CC_ENABLE_ENABLE); 737 write32(reg->ISE, MMCHS_SD_IE_ERROR_MASK 738 | MMCHS_SD_IE_BRR_ENABLE_ENABLE 739 | MMCHS_SD_IE_BWR_ENABLE_ENABLE 740 | MMCHS_SD_IE_TC_ENABLE_ENABLE 741 | MMCHS_SD_IE_CC_ENABLE_ENABLE); 742 743 return 0; 744 } 745 746 /* 747 * Interface to the MINIX block device driver. 748 * Set the log level. 749 */ 750 static void 751 emmc_set_log_level(int level) 752 { 753 log.log_level = level; 754 } 755 756 757 /* 758 * Interface to the MINIX block device driver. 759 * Unused, but declared in mmchost.h. 760 */ 761 #if 0 762 static int 763 emmc_host_reset(struct mmc_host *host) 764 { 765 return 0; 766 } 767 #endif 768 769 /* 770 * Interface to the MINIX block device driver. 771 * Card detection. 772 */ 773 static int 774 emmc_card_detect(struct sd_slot *slot) 775 { 776 /* The card is detected during card initialization. */ 777 return 1; 778 } 779 780 /* 781 * Interface to the MINIX block device driver. 782 * Card initialization. Also, finish the MMCHS initialization. 783 * Return NULL on error. 784 */ 785 static struct sd_card * 786 emmc_card_initialize(struct sd_slot *slot) 787 { 788 uint32_t clkd; 789 790 /* CMD0 */ 791 if (go_idle_state() < 0) 792 return NULL; 793 794 /* 795 * Set the MMC_CMD line to open drain. 796 * "The host starts the card identification process in open-drain mode 797 * with the identification clock rate FOD." (MMCA, 4.41) 798 */ 799 set32(reg->CON, MMCHS_SD_CON_OD, MMCHS_SD_CON_OD_OD); 800 801 /* CMD1 */ 802 if (repeat_send_op_cond() < 0) 803 return NULL; 804 805 /* CMD2. The driver has no use for the CID. */ 806 if (all_send_cid() < 0) 807 return NULL; 808 809 /* CMD3 */ 810 if (set_relative_addr() < 0) 811 return NULL; 812 813 /* 814 * Set the MMC_CMD line to push-pull. 815 * "When the card is in Stand-by State, communication over the CMD and 816 * DAT lines will be performed in push-pull mode." (MMCA, 4.41) 817 */ 818 set32(reg->CON, MMCHS_SD_CON_OD, MMCHS_SD_CON_OD_PP); 819 820 /* CMD9 */ 821 if (send_csd() < 0) 822 return NULL; 823 card_csd[0] = read32(reg->RSP10); 824 card_csd[1] = read32(reg->RSP32); 825 card_csd[2] = read32(reg->RSP54); 826 card_csd[3] = read32(reg->RSP76); 827 828 /* Card capacity for cards up to 2GB of density. */ 829 card_size = (uint64_t)MMC_CSD_CAPACITY(card_csd) 830 << MMC_CSD_READ_BL_LEN(card_csd); 831 832 card_write_protect = (SD_CSD_PERM_WRITE_PROTECT(card_csd) 833 | SD_CSD_TMP_WRITE_PROTECT(card_csd)); 834 if (card_write_protect) 835 log_info(&log, "the eMMC is write protected\n"); 836 837 /* CMD7 */ 838 if (select_card() < 0) 839 return NULL; 840 841 /* CMD8 */ 842 if (send_ext_csd() < 0) 843 return NULL; 844 /* Receive the Extended CSD register. */ 845 if (read_data((uint32_t *)card_ext_csd) < 0) 846 return NULL; 847 848 /* Card capacity for densities greater than 2GB. */ 849 if (MMC_EXT_CSD_SEC_COUNT > 0) 850 card_size = (uint64_t)MMC_EXT_CSD_SEC_COUNT * SEC_SIZE; 851 852 /* CMD6. Switch to high-speed mode: EXT_CSD[185] HS_TIMING = 1. */ 853 if (mmc_switch(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_HS_TIMING, 1) < 0) 854 return NULL; 855 /* Wait for the (optional) busy signal. */ 856 if (read_busy() < 0) 857 return NULL; 858 /* CMD13. Check the result of the SWITCH operation. */ 859 if (send_status() < 0) 860 return NULL; 861 862 /* Change the bus clock frequency. */ 863 if (MMC_EXT_CSD_CARD_TYPE & MMC_EXT_CSD_CARD_TYPE_HS_MMC_52MHZ) 864 clkd = MMCHS_SD_SYSCTL_CLKD_52MHZ; /* 48 MHz */ 865 else 866 clkd = MMCHS_SD_SYSCTL_CLKD_26MHZ; /* 24 MHz */ 867 if (set_bus_clkd(clkd) < 0) 868 return NULL; 869 870 /* Set data and busy time-out: ~ 2,8s @ 48MHz.*/ 871 set32(reg->SYSCTL, MMCHS_SD_SYSCTL_DTO, MMCHS_SD_SYSCTL_DTO_2POW27); 872 873 /* CMD6. Set data bus width. */ 874 if (mmc_switch(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_BUS_WIDTH, 875 bus_width) < 0) 876 return NULL; 877 /* Wait for the (optional) busy signal. */ 878 if (read_busy() < 0) 879 return NULL; 880 /* CMD13. Check the result of the SWITCH operation. */ 881 if (send_status() < 0) 882 return NULL; 883 884 /* Host controller: set data bus width. */ 885 if (bus_width == EXT_CSD_BUS_WIDTH_4) 886 set32(reg->HCTL, MMCHS_SD_HCTL_DTW, MMCHS_SD_HCTL_DTW_4BIT); 887 else 888 set32(reg->CON, MMCHS_SD_CON_DW8, MMCHS_SD_CON_DW8_8BITS); 889 890 /* CMD16. Set block length to sector size (512B). */ 891 if (set_blocklen() < 0) 892 return NULL; 893 894 /* Initialize the block device driver structures. */ 895 slot->card.blk_size = SEC_SIZE; 896 slot->card.blk_count = card_size / SEC_SIZE; 897 slot->card.state = SD_MODE_DATA_TRANSFER_MODE; 898 slot->card.open_ct = 0; 899 memset(slot->card.part, 0, sizeof(slot->card.part)); 900 memset(slot->card.subpart, 0, sizeof(slot->card.subpart)); 901 slot->card.part[0].dv_size = card_size; 902 903 return &(slot->card); 904 } 905 906 /* 907 * Interface to the MINIX block device driver. 908 * Card release. 909 */ 910 static int 911 emmc_card_release(struct sd_card *card) 912 { 913 /* Decrements the "in-use count." */ 914 card->open_ct--; 915 916 /* 917 * The block special file is closed, but the driver does not need to 918 * "release" the eMMC, even if the driver is unloaded. 919 */ 920 921 return 0; 922 } 923 924 /* 925 * Interface to the MINIX block device driver. 926 * Handle unexpected interrupts. 927 */ 928 static void 929 emmc_hw_intr(unsigned int irqs) 930 { 931 log_warn(&log, "register SD_STAT == 0x%08x\n", reg->SD_STAT); 932 } 933 934 /* 935 * Interface to the MINIX block device driver. 936 * Read/write blocks. 937 * Return the number of blocks read/written, or a negative integer on error. 938 */ 939 static int 940 emmc_read_write(int (*cim_read_write)(uint32_t, uint32_t *), 941 uint32_t blknr, uint32_t count, unsigned char *buf) 942 { 943 int blocks, r; 944 uint32_t addr; 945 946 blocks = 0; /* count of blocks read/written. */ 947 r = 0; 948 while ((count > 0) && (r == 0)) { 949 /* 950 * Data address for media =< 2GB is byte address, and data 951 * address for media > 2GB is sector address. 952 */ 953 if (card_size <= (2U << 30)) 954 addr = blknr * SEC_SIZE; 955 else 956 addr = blknr; 957 958 r = (*cim_read_write)(addr, (uint32_t *)buf); 959 if (r == 0) { 960 blknr++; 961 count--; 962 buf += SEC_SIZE; 963 blocks++; 964 } 965 else if (blocks == 0) 966 blocks = r; 967 } 968 969 return blocks; 970 } 971 972 /* 973 * Interface to the MINIX block device driver. 974 * Read blocks. 975 */ 976 static int 977 emmc_read(struct sd_card *card, 978 uint32_t blknr, uint32_t count, unsigned char *buf) 979 { 980 return emmc_read_write(&cim_read_block, blknr, count, buf); 981 } 982 983 /* 984 * Interface to the MINIX block device driver. 985 * Write blocks. 986 */ 987 static int 988 emmc_write(struct sd_card *card, 989 uint32_t blknr, uint32_t count, unsigned char *buf) 990 { 991 if (card_write_protect) 992 return -1; /* The card is write protected. */ 993 return emmc_read_write(&cim_write_block, blknr, count, buf); 994 } 995 996 /* 997 * Interface to the MINIX block device driver. 998 * Driver interface registration. 999 */ 1000 void 1001 host_initialize_host_structure_mmchs(struct mmc_host *host) 1002 { 1003 uint32_t i; 1004 1005 /* Register the driver interface at the block device driver. */ 1006 host->host_set_instance = &emmc_host_set_instance; 1007 host->host_init = &emmc_host_init; 1008 host->set_log_level = &emmc_set_log_level; 1009 host->host_reset = NULL; 1010 host->card_detect = &emmc_card_detect; 1011 host->card_initialize = &emmc_card_initialize; 1012 host->card_release = &emmc_card_release; 1013 host->hw_intr = &emmc_hw_intr; 1014 host->read = &emmc_read; 1015 host->write = &emmc_write; 1016 for (i=0; i<MAX_SD_SLOTS; i++) { 1017 host->slot[i].host = host; 1018 host->slot[i].card.state = SD_MODE_UNINITIALIZED; 1019 host->slot[i].card.slot = &host->slot[i]; 1020 } 1021 } 1022 1023 /* 1024 * Interface to the MINIX block device driver. 1025 * Unused, but declared in mmchost.h. 1026 */ 1027 void 1028 host_initialize_host_structure_dummy(struct mmc_host *host) 1029 { 1030 } 1031