1 struct omap_mmchs_registers; 2 3 struct omap_mmchs { 4 vir_bytes io_base; 5 vir_bytes io_size; 6 phys_bytes hw_base;/* HW address */ 7 int irq_nr; 8 struct omap_mmchs_registers * regs; 9 }; 10 11 struct omap_mmchs_registers { 12 /* SD system configuration */ 13 vir_bytes SYSCONFIG; 14 /* SD system status */ 15 vir_bytes SYSSTATUS; 16 /* Configuration (functional mode,card initialization etc) */ 17 vir_bytes CON; 18 /* Transfer length configuration */ 19 vir_bytes BLK; 20 /* Command argument bit 38-8 of command format*/ 21 vir_bytes ARG; 22 /* Command and transfer mode */ 23 vir_bytes CMD; 24 /* SDMA System address */ 25 vir_bytes SDMASA; 26 /* Command response 0 and 1 */ 27 vir_bytes RSP10; 28 /* Command response 2 and 3 */ 29 vir_bytes RSP32; 30 /* Command response 4 and 5 */ 31 vir_bytes RSP54; 32 /* Command response 6 and 7 */ 33 vir_bytes RSP76; 34 /* Data register */ 35 vir_bytes DATA; 36 /* Present state */ 37 vir_bytes PSTATE; 38 /* Host control(power ,wake-up and transfer) */ 39 vir_bytes HCTL; 40 /* SD System control (reset,clocks and timeout) */ 41 vir_bytes SYSCTL; 42 /* SD Interrupt status */ 43 vir_bytes SD_STAT; 44 /* SD Interrupt Enable register */ 45 vir_bytes IE; 46 /* SD Interrupt Signal Enable register */ 47 vir_bytes ISE; 48 /* Capabilities of the host controller */ 49 vir_bytes CAPA; 50 /* Current capabilities of the host controller */ 51 vir_bytes CUR_CAPA; 52 }; 53 54 /* version used on the AM335x */ 55 static struct omap_mmchs_registers regs_v1 = { 56 .SYSCONFIG = 0x110, 57 .SYSSTATUS = 0x114, 58 .CON = 0x12c, 59 .BLK = 0x204, 60 .ARG = 0x208, 61 .CMD = 0x20c, 62 .SDMASA = 0x200, 63 .RSP10 = 0x210, 64 .RSP32 = 0x214, 65 .RSP54 = 0x218, 66 .RSP76 = 0x21c, 67 .DATA = 0x220, 68 .PSTATE = 0x224, 69 .HCTL = 0x228, 70 .SYSCTL = 0x22c, 71 .SD_STAT = 0x230, 72 .IE = 0x234, 73 .ISE = 0x238, 74 .CAPA = 0x240, 75 .CUR_CAPA = 0x248, 76 }; 77 78 /* version used on the DM37xx */ 79 /* DM and AM have the same register but shifted by 0x100. */ 80 static struct omap_mmchs_registers regs_v0 = { 81 .SYSCONFIG = 0x010, 82 .SYSSTATUS = 0x014, 83 .CON = 0x02c, 84 .BLK = 0x104, 85 .ARG = 0x108, 86 .CMD = 0x10c, 87 .SDMASA = 0x100, 88 .RSP10 = 0x110, 89 .RSP32 = 0x114, 90 .RSP54 = 0x118, 91 .RSP76 = 0x11c, 92 .DATA = 0x120, 93 .PSTATE = 0x124, 94 .HCTL = 0x128, 95 .SYSCTL = 0x12c, 96 .SD_STAT = 0x130, 97 .IE = 0x134, 98 .ISE = 0x138, 99 .CAPA = 0x140, 100 .CUR_CAPA = 0x148, 101 }; 102 103 104 #define MMCHS_SD_SYSCONFIG_AUTOIDLE (0x1 << 0) /* Internal clock gating strategy */ 105 #define MMCHS_SD_SYSCONFIG_AUTOIDLE_DIS (0x0 << 0) /* Clocks are free running */ 106 #define MMCHS_SD_SYSCONFIG_AUTOIDLE_EN (0x1 << 0) /* Automatic clock gating strategy */ 107 #define MMCHS_SD_SYSCONFIG_SOFTRESET (0x1 << 1) /* Software reset bit writing */ 108 #define MMCHS_SD_SYSCONFIG_ENAWAKEUP (0x1 << 2) /* Wake-up feature control */ 109 #define MMCHS_SD_SYSCONFIG_ENAWAKEUP_DIS (0x0 << 2) /* Disable wake-up capability */ 110 #define MMCHS_SD_SYSCONFIG_ENAWAKEUP_EN (0x1 << 2) /* Enable wake-up capability */ 111 #define MMCHS_SD_SYSCONFIG_SIDLEMODE (0x3 << 3) /* Power management */ 112 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_UNCONDITIONAL (0x0 << 3) /* Go into idle mode unconditionally upon request */ 113 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_IGNORE (0x1 << 3) /* Ignore ILDE requests */ 114 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_IDLE (0x2 << 3) /* Acknowledge IDLE request switch to wake-up mode */ 115 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_SMART_IDLE (0x3 << 3) /* Smart-idle */ 116 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY (0x3 << 8) /* Clock activity during wake-up */ 117 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_OFF (0x0 << 8) /* Interface and functional clock can be switched off */ 118 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_IF (0x1 << 8) /* Only Interface clock (functional can be switched off*/ 119 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_FUNC (0x2 << 8) /* Only Functional clock (interface clock can be switched off) */ 120 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_BOOTH (0x3 << 8) /* Booth the interface and functional clock are maintained */ 121 #define MMCHS_SD_SYSCONFIG_STANDBYMODE (0x3 << 12) /* Configuration for standby */ 122 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_FORCE_STANDBY (0x0 << 12) /* Force standby mode upon idle request*/ 123 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_NO_STANDBY (0x1 << 12) /* Never go into standby mode */ 124 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_INTERNAL (0x2 << 12) /* Go into wake-up mode based on internal knowledge */ 125 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_SMART (0x3 << 12) /* Go info wake-up mode when possible */ 126 127 #define MMCHS_SD_SYSSTATUS_RESETDONE 0x01 128 129 #define MMCHS_SD_CON_DW8 (0x1 << 5) /* 8-bit mode MMC select , For SD clear this bit */ 130 #define MMCHS_SD_CON_DW8_1BIT (0x0 << 5) /* 1 or 4 bits data width configuration(also set SD_HCTL) */ 131 #define MMCHS_SD_CON_DW8_8BITS (0x1 << 5) /* 8 bits data width configuration */ 132 #define MMCHS_SD_CON_INIT (0x1 << 1) /* Send initialization stream (all cards) */ 133 #define MMCHS_SD_CON_INIT_NOINIT (0x0 << 1) /* Do nothing */ 134 #define MMCHS_SD_CON_INIT_INIT (0x1 << 1) /* Send initialization stream */ 135 136 #define MMCHS_SD_BLK_NBLK (0xffffu << 16) /* Block count for the current transfer */ 137 #define MMCHS_SD_BLK_BLEN (0xfff << 0) /* Transfer block size */ 138 #define MMCHS_SD_BLK_BLEN_NOTRANSFER (0x0 << 0) /* No transfer */ 139 140 #define MMCHS_SD_CMD_INDX (0x3f << 24) /* Command index */ 141 #define MMCHS_SD_CMD_INDX_CMD(x) (x << 24) /* MMC command index binary encoded values from 0 to 63 */ 142 143 #define MMCHS_SD_ARG_MASK (0xffffffffu) /* Mask everything */ 144 #define MMCHS_SD_ARG_CMD8_VHS (0x1 << (16 - 8)) /* Voltage between 2.7 and 3.6 v*/ 145 #define MMCHS_SD_ARG_CMD8_CHECK_PATTERN (0xaa <<(8 - 8)) /* 10101010b pattern */ 146 147 #define MMCHS_SD_CMD_TYPE (0x3 << 22) /* Command type. */ 148 #define MMCHS_SD_CMD_TYPE_OTHER (0x0 << 22) /* Other type of commands (like go idle) */ 149 #define MMCHS_SD_CMD_TYPE_BUS_SUSPEND (0x1 << 22) /* Upon CMD52 "Bus Suspend" operation */ 150 #define MMCHS_SD_CMD_TYPE_FUNCTION_SELECT (0x2 << 22) /* Upon CMD52 "Function Select" operation */ 151 #define MMCHS_SD_CMD_TYPE_IOABORT (0x3 << 22) /* Upon CMD12 and CMD21 "I/O Abort */ 152 #define MMCHS_SD_CMD_DP (0x1 << 21) /* Data present select */ 153 #define MMCHS_SD_CMD_DP_DATA (0x1 << 21) /* Additional data is present on the data lines */ 154 #define MMCHS_SD_CMD_DP_NODATA (0x0 << 21) /* No additional data is present on the data lines */ 155 #define MMCHS_SD_CMD_CICE (0x1 << 20) /* Command index response check enable */ 156 #define MMCHS_SD_CMD_CICE_ENABLE (0x1 << 20) /* Enable index check response */ 157 #define MMCHS_SD_CMD_CICE_DISABLE (0x0 << 20) /* Disable index check response */ 158 #define MMCHS_SD_CMD_CCCE (0x1 << 19) /* Command CRC7 Check enable on responses*/ 159 #define MMCHS_SD_CMD_CCCE_ENABLE (0x1 << 19) /* Enable CRC7 Check on response */ 160 #define MMCHS_SD_CMD_CCCE_DISABLE (0x0 << 19) /* Disable CRC7 Check on response */ 161 #define MMCHS_SD_CMD_RSP_TYPE (0x3 << 16) /* Response type */ 162 #define MMCHS_SD_CMD_RSP_TYPE_NO_RESP (0x0 << 16) /* No response */ 163 #define MMCHS_SD_CMD_RSP_TYPE_136B (0x1 << 16) /* Response length 136 bits */ 164 #define MMCHS_SD_CMD_RSP_TYPE_48B (0x2 << 16) /* Response length 48 bits */ 165 #define MMCHS_SD_CMD_RSP_TYPE_48B_BUSY (0x3 << 16) /* Response length 48 bits with busy after response */ 166 #define MMCHS_SD_CMD_MSBS (0x1 << 5) /* Multi/Single block select */ 167 #define MMCHS_SD_CMD_MSBS_SINGLE (0x0 << 5) /* Single block mode */ 168 #define MMCHS_SD_CMD_MSBS_MULTI (0x0 << 5) /* Multi block mode */ 169 #define MMCHS_SD_CMD_DDIR (0x1 << 4) /* Data transfer direction */ 170 #define MMCHS_SD_CMD_DDIR_READ (0x1 << 4) /* Data read (card to host) */ 171 #define MMCHS_SD_CMD_DDIR_WRITE (0x0 << 4) /* Data write (host to card) */ 172 #define MMCHS_SD_CMD_ACEN (0x1 << 2) /* Auto CMD12 Enable */ 173 #define MMCHS_SD_CMD_ACEN_DIS (0x0 << 2) /* Auto CMD12 Disable */ 174 #define MMCHS_SD_CMD_ACEN_EN (0x1 << 2) /* Auto CMD12 Enable */ 175 #define MMCHS_SD_CMD_BCE (0x1 << 1) /* Block Count Enable(for multi block transfer) */ 176 #define MMCHS_SD_CMD_BCE_DIS (0x0 << 1) /* Disabled block count for infinite transfer*/ 177 #define MMCHS_SD_CMD_BCE_EN (0x1 << 1) /* Enabled for multi block transfer with know amount of blocks */ 178 #define MMCHS_SD_CMD_DE (0x1 << 0) /* DMA enable */ 179 #define MMCHS_SD_CMD_DE_DIS (0x0 << 0) /* Disable DMA */ 180 #define MMCHS_SD_CMD_DE_EN (0x1 << 0) /* Enable DMA */ 181 #define MMCHS_SD_CMD_MASK ~(0x1 << 30 | 0x1 << 31 | 0x1 << 18 | 0x1 <<3) /* bits 30 , 31 and 18 are reserved */ 182 183 #define MMCHS_SD_PSTATE_CI (0x1 << 16) /* Card Inserted */ 184 #define MMCHS_SD_PSTATE_CI_INSERTED (0x1 << 16) /* Card Inserted is inserted*/ 185 #define MMCHS_SD_PSTATE_BRE (0x0 << 11) /* Buffer read enable */ 186 #define MMCHS_SD_PSTATE_BRE_DIS (0x0 << 11) /* Read BLEN bytes disabled*/ 187 #define MMCHS_SD_PSTATE_BRE_EN (0x1 << 11) /* Read BLEN bytes enabled*/ 188 #define MMCHS_SD_PSTATE_BWE (0x0 << 10) /* Buffer Write enable */ 189 #define MMCHS_SD_PSTATE_BWE_DIS (0x0 << 10) /* There is no room left in the buffer to write BLEN bytes of data */ 190 #define MMCHS_SD_PSTATE_BWE_EN (0x1 << 10) /* There is enough space in the buffer to write BLEN bytes of data*/ 191 192 #define MMCHS_SD_HCTL_DTW (0x1 << 1) /*Data transfer width.(must be set after a successful ACMD6) */ 193 #define MMCHS_SD_HCTL_DTW_1BIT (0x0 << 1) /*1 bit transfer with */ 194 #define MMCHS_SD_HCTL_DTW_4BIT (0x1 << 1) /*4 bit transfer with */ 195 #define MMCHS_SD_HCTL_SDBP (0x1 << 8) /*SD bus power */ 196 #define MMCHS_SD_HCTL_SDBP_OFF (0x0 << 8) /*SD Power off (start card detect?) */ 197 #define MMCHS_SD_HCTL_SDBP_ON (0x1 << 8) /*SD Power on (start card detect?) */ 198 #define MMCHS_SD_HCTL_SDVS (0x7 << 9) /*SD bus voltage select */ 199 #define MMCHS_SD_HCTL_SDVS_VS18 (0x5 << 9) /*1.8 V */ 200 #define MMCHS_SD_HCTL_SDVS_VS30 (0x6 << 9) /*3.0 V */ 201 #define MMCHS_SD_HCTL_SDVS_VS33 (0x7 << 9) /*3.3 V */ 202 #define MMCHS_SD_HCTL_IWE (0x1 << 24)/* wake-up event on SD interrupt */ 203 #define MMCHS_SD_HCTL_IWE_DIS (0x0 << 24)/* Disable wake-up on SD interrupt */ 204 #define MMCHS_SD_HCTL_IWE_EN (0x1 << 24)/* Enable wake-up on SD interrupt */ 205 206 #define MMCHS_SD_SYSCTL_CLKD (0x3ff << 6) /* 10 bits clock frequency select */ 207 #define MMCHS_SD_SYSCTL_SRD (0x1 << 26) /* Soft reset for mmc_dat line */ 208 #define MMCHS_SD_SYSCTL_SRC (0x1 << 25) /* Soft reset for mmc_cmd line */ 209 #define MMCHS_SD_SYSCTL_SRA (0x1 << 24) /* Soft reset all (host controller) */ 210 211 #define MMCHS_SD_SYSCTL_ICE (0x1 << 0) /* Internal clock enable register */ 212 #define MMCHS_SD_SYSCTL_ICE_DIS (0x0 << 0) /* Disable internal clock */ 213 #define MMCHS_SD_SYSCTL_ICE_EN (0x1 << 0) /* Enable internal clock */ 214 #define MMCHS_SD_SYSCTL_ICS (0x1 << 1) /* Internal clock stable register */ 215 #define MMCHS_SD_SYSCTL_ICS_UNSTABLE (0x0 << 1) /* Internal clock is unstable */ 216 #define MMCHS_SD_SYSCTL_ICS_STABLE (0x1 << 1) /* Internal clock is stable */ 217 #define MMCHS_SD_SYSCTL_CEN (0x1 << 2) /* Card lock enable provide clock to the card */ 218 #define MMCHS_SD_SYSCTL_CEN_DIS (0x0 << 2) /* Internal clock is unstable */ 219 #define MMCHS_SD_SYSCTL_CEN_EN (0x1 << 2) /* Internal clock is stable */ 220 221 #define MMCHS_SD_SYSCTL_DTO (0xf << 16) /* Data timeout counter */ 222 #define MMCHS_SD_SYSCTL_DTO_2POW13 (0x0 << 16) /* TCF x 2^13 */ 223 #define MMCHS_SD_SYSCTL_DTO_2POW14 (0x1 << 16) /* TCF x 2^14 */ 224 #define MMCHS_SD_SYSCTL_DTO_2POW27 (0xe << 16) /* TCF x 2^27 */ 225 226 #define MMCHS_SD_STAT_ERRI (0x01 << 15) /* Error interrupt */ 227 #define MMCHS_SD_STAT_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28) 228 #define MMCHS_SD_STAT_CC (0x1 << 0) /* Command complete status */ 229 #define MMCHS_SD_STAT_CC_UNRAISED (0x0 << 0) /* Command not completed */ 230 #define MMCHS_SD_STAT_CC_RAISED (0x1 << 0) /* Command completed */ 231 #define MMCHS_SD_STAT_TC (0x1 << 1) /* Transfer complete status */ 232 #define MMCHS_SD_STAT_TC_UNRAISED (0x0 << 1) /* Transfer not completed */ 233 #define MMCHS_SD_STAT_TC_RAISED (0x1 << 1) /* Transfer completed */ 234 235 #define MMCHS_SD_IE_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28) 236 237 #define MMCHS_SD_IE_CC_ENABLE (0x1 << 0) /* Command complete interrupt enable */ 238 #define MMCHS_SD_IE_CC_ENABLE_ENABLE (0x1 << 0) /* Command complete Interrupts are enabled */ 239 #define MMCHS_SD_IE_CC_ENABLE_CLEAR (0x1 << 0) /* Clearing is done by writing a 0x1 */ 240 241 #define MMCHS_SD_IE_TC_ENABLE (0x1 << 1) /* Transfer complete interrupt enable */ 242 #define MMCHS_SD_IE_TC_ENABLE_ENABLE (0x1 << 1) /* Transfer complete Interrupts are enabled */ 243 #define MMCHS_SD_IE_TC_ENABLE_CLEAR (0x1 << 1) /* Clearing TC is done by writing a 0x1 */ 244 245 #define MMCHS_SD_IE_BRR_ENABLE (0x1 << 5) /* Buffer read ready interrupt */ 246 #define MMCHS_SD_IE_BRR_ENABLE_DISABLE (0x0 << 5) /* Buffer read ready interrupt disable */ 247 #define MMCHS_SD_IE_BRR_ENABLE_ENABLE (0x1 << 5) /* Buffer read ready interrupt enable */ 248 #define MMCHS_SD_IE_BRR_ENABLE_CLEAR (0x1 << 5) /* Buffer read ready interrupt clear */ 249 250 #define MMCHS_SD_IE_BWR_ENABLE (0x1 << 4) /* Buffer write ready interrupt */ 251 #define MMCHS_SD_IE_BWR_ENABLE_DISABLE (0x0 << 4) /* Buffer write ready interrupt disable */ 252 #define MMCHS_SD_IE_BWR_ENABLE_ENABLE (0x1 << 4) /* Buffer write ready interrupt enable */ 253 #define MMCHS_SD_IE_BWR_ENABLE_CLEAR (0x1 << 4) /* Buffer write ready interrupt clear */ 254 255 #define MMCHS_SD_CAPA_VS_MASK (0x7 << 24 ) /* voltage mask */ 256 #define MMCHS_SD_CAPA_VS18 (0x01 << 26 ) /* 1.8 volt */ 257 #define MMCHS_SD_CAPA_VS30 (0x01 << 25 ) /* 3.0 volt */ 258 #define MMCHS_SD_CAPA_VS33 (0x01 << 24 ) /* 3.3 volt */ 259 260