1 /* 2 * Common MUSB core registers definitions 3 */ 4 5 #ifndef _MUSB_REGS_H_ 6 #define _MUSB_REGS_H_ 7 8 #include <usbd/hcd_common.h> 9 10 11 /*===========================================================================* 12 * MUSB core register offsets * 13 *===========================================================================*/ 14 #define MUSB_REG_FADDR 0x00u 15 #define MUSB_REG_POWER 0x01u 16 #define MUSB_REG_INTRTX 0x02u 17 #define MUSB_REG_INTRRX 0x04u 18 #define MUSB_REG_INTRTXE 0x06u 19 #define MUSB_REG_INTRRXE 0x08u 20 #define MUSB_REG_INTRUSB 0x0Au 21 #define MUSB_REG_INTRUSBE 0x0Bu 22 #define MUSB_REG_FRAME 0x0Cu 23 #define MUSB_REG_INDEX 0x0Eu 24 #define MUSB_REG_TESTMODE 0x0Fu 25 26 /* Proxy registers for endpoint configuration, 27 * that correspond to specific endpoint's register space 28 * selected with MUSB_REG_INDEX */ 29 #define MUSB_REG_TXMAXP 0x10u 30 #define MUSB_REG_PERI_CSR0 0x12u 31 #define MUSB_REG_HOST_CSR0 MUSB_REG_PERI_CSR0 32 #define MUSB_REG_PERI_TXCSR MUSB_REG_PERI_CSR0 33 #define MUSB_REG_HOST_TXCSR MUSB_REG_PERI_CSR0 34 #define MUSB_REG_RXMAXP 0x14u 35 #define MUSB_REG_PERI_RXCSR 0x16u 36 #define MUSB_REG_HOST_RXCSR MUSB_REG_PERI_RXCSR 37 #define MUSB_REG_COUNT0 0x18u 38 #define MUSB_REG_RXCOUNT MUSB_REG_COUNT0 39 #define MUSB_REG_HOST_TYPE0 0x1Au 40 #define MUSB_REG_HOST_TXTYPE MUSB_REG_HOST_TYPE0 41 #define MUSB_REG_HOST_NAKLIMIT0 0x1Bu 42 #define MUSB_REG_HOST_TXINTERVAL MUSB_REG_HOST_NAKLIMIT0 43 #define MUSB_REG_HOST_RXTYPE 0x1Cu 44 #define MUSB_REG_HOST_RXINTERVAL 0x1Du 45 46 #define MUSB_REG_FIFO0 0x20u 47 #define MUSB_REG_FIFO1 0x24u 48 #define MUSB_REG_FIFO2 0x28u 49 #define MUSB_REG_FIFO3 0x2Cu 50 #define MUSB_REG_FIFO4 0x30u 51 #define MUSB_REG_FIFO_LEN 0x04u 52 53 #define MUSB_REG_DEVCTL 0x60u 54 #define MUSB_REG_TXFIFOSZ 0x62u 55 #define MUSB_REG_RXFIFOSZ 0x63u 56 #define MUSB_REG_TXFIFOADDR 0x64u 57 #define MUSB_REG_RXFIFOADDR 0x66u 58 59 #define MUSB_REG_EP_CONFIG_BASE 0x80u 60 #define MUSB_REG_TXFUNCADDR 0x00u 61 #define MUSB_REG_TXHUBADDR 0x02u 62 #define MUSB_REG_TXHUBPORT 0x03u 63 #define MUSB_REG_RXFUNCADDR 0x04u 64 #define MUSB_REG_RXHUBADDR 0x06u 65 #define MUSB_REG_RXHUBPORT 0x07u 66 #define MUSB_REG_EP_CONFIG_LEN 0x08u 67 #define MUSB_REG_CONFIG(ep,reg) \ 68 (MUSB_REG_EP_CONFIG_BASE + (MUSB_REG_EP_CONFIG_LEN * (ep)) + (reg)) 69 70 71 /*===========================================================================* 72 * MUSB core register values * 73 *===========================================================================*/ 74 /* POWER */ 75 #define MUSB_VAL_POWER_ENSUSPM HCD_BIT(0) 76 #define MUSB_VAL_POWER_SUSPENDM HCD_BIT(1) 77 #define MUSB_VAL_POWER_RESUME HCD_BIT(2) 78 #define MUSB_VAL_POWER_RESET HCD_BIT(3) 79 #define MUSB_VAL_POWER_HSMODE HCD_BIT(4) 80 #define MUSB_VAL_POWER_HSEN HCD_BIT(5) 81 #define MUSB_VAL_POWER_SOFTCONN HCD_BIT(6) 82 #define MUSB_VAL_POWER_ISOUPDATE HCD_BIT(7) 83 84 /* DEVCTL */ 85 #define MUSB_VAL_DEVCTL_SESSION HCD_BIT(0) 86 #define MUSB_VAL_DEVCTL_HOSTREQ HCD_BIT(1) 87 #define MUSB_VAL_DEVCTL_HOSTMODE HCD_BIT(2) 88 #define MUSB_VAL_DEVCTL_VBUS_1 HCD_BIT(3) 89 #define MUSB_VAL_DEVCTL_VBUS_2 HCD_BIT(4) 90 #define MUSB_VAL_DEVCTL_VBUS_3 (HCD_BIT(3) | HCD_BIT(4)) 91 #define MUSB_VAL_DEVCTL_LSDEV HCD_BIT(5) 92 #define MUSB_VAL_DEVCTL_FSDEV HCD_BIT(6) 93 #define MUSB_VAL_DEVCTL_BDEVICE HCD_BIT(7) 94 95 /* INTRUSBE */ 96 #define MUSB_VAL_INTRUSBE_SUSPEND HCD_BIT(0) 97 #define MUSB_VAL_INTRUSBE_RESUME HCD_BIT(1) 98 #define MUSB_VAL_INTRUSBE_RESET_BABBLE HCD_BIT(2) 99 #define MUSB_VAL_INTRUSBE_SOF HCD_BIT(3) 100 #define MUSB_VAL_INTRUSBE_CONN HCD_BIT(4) 101 #define MUSB_VAL_INTRUSBE_DISCON HCD_BIT(5) 102 #define MUSB_VAL_INTRUSBE_SESSREQ HCD_BIT(6) 103 #define MUSB_VAL_INTRUSBE_VBUSERR HCD_BIT(7) 104 #define MUSB_VAL_INTRUSBE_NONE 0x00u 105 106 /* HOST_TYPE0 */ 107 #define MUSB_VAL_HOST_TYPE0_MASK (HCD_BIT(6) | HCD_BIT(7)) 108 #define MUSB_VAL_HOST_TYPE0_HIGH_SPEED HCD_BIT(6) 109 #define MUSB_VAL_HOST_TYPE0_FULL_SPEED HCD_BIT(7) 110 #define MUSB_VAL_HOST_TYPE0_LOW_SPEED (HCD_BIT(6) | HCD_BIT(7)) 111 112 /* INTRTXE */ 113 #define MUSB_VAL_INTRTXE_EP0 HCD_BIT(0) 114 #define MUSB_VAL_INTRTXE_EP1TX HCD_BIT(1) 115 #define MUSB_VAL_INTRTXE_EP2TX HCD_BIT(2) 116 #define MUSB_VAL_INTRTXE_EP3TX HCD_BIT(3) 117 #define MUSB_VAL_INTRTXE_EP4TX HCD_BIT(4) 118 119 /* HOST_CSR0 */ 120 #define MUSB_VAL_HOST_CSR0_RXPKTRDY HCD_BIT(0) 121 #define MUSB_VAL_HOST_CSR0_TXPKTRDY HCD_BIT(1) 122 #define MUSB_VAL_HOST_CSR0_RXSTALL HCD_BIT(2) 123 #define MUSB_VAL_HOST_CSR0_SETUPPKT HCD_BIT(3) 124 #define MUSB_VAL_HOST_CSR0_ERROR HCD_BIT(4) 125 #define MUSB_VAL_HOST_CSR0_REQPKT HCD_BIT(5) 126 #define MUSB_VAL_HOST_CSR0_STATUSPKT HCD_BIT(6) 127 #define MUSB_VAL_HOST_CSR0_NAK_TIMEOUT HCD_BIT(7) 128 #define MUSB_VAL_HOST_CSR0_FLUSHFIFO HCD_BIT(8) 129 130 /* HOST_RXTYPE/HOST_TXTYPE */ 131 #define MUSB_VAL_HOST_XXTYPE_SPEED_MASK (HCD_BIT(6) | HCD_BIT(7)) 132 #define MUSB_VAL_HOST_XXTYPE_HIGH_SPEED HCD_BIT(6) 133 #define MUSB_VAL_HOST_XXTYPE_FULL_SPEED HCD_BIT(7) 134 #define MUSB_VAL_HOST_XXTYPE_LOW_SPEED (HCD_BIT(6) | HCD_BIT(7)) 135 #define MUSB_VAL_HOST_XXTYPE_PROT_MASK (HCD_BIT(4) | HCD_BIT(5)) 136 #define MUSB_VAL_HOST_XXTYPE_ISOCHRONOUS HCD_BIT(4) 137 #define MUSB_VAL_HOST_XXTYPE_BULK HCD_BIT(5) 138 #define MUSB_VAL_HOST_XXTYPE_INTERRUPT (HCD_BIT(4) | HCD_BIT(5)) 139 #define MUSB_VAL_HOST_XXTYPE_RENDPN_MASK (HCD_BIT(0) | \ 140 HCD_BIT(1) | \ 141 HCD_BIT(2) | \ 142 HCD_BIT(3)) 143 144 /* HOST_RXCSR */ 145 #define MUSB_VAL_HOST_RXCSR_RXPKTRDY HCD_BIT(0) 146 #define MUSB_VAL_HOST_RXCSR_FIFOFULL HCD_BIT(1) 147 #define MUSB_VAL_HOST_RXCSR_ERROR HCD_BIT(2) 148 #define MUSB_VAL_HOST_RXCSR_NAKTIMEOUT HCD_BIT(3) 149 #define MUSB_VAL_HOST_RXCSR_FLUSHFIFO HCD_BIT(4) 150 #define MUSB_VAL_HOST_RXCSR_REQPKT HCD_BIT(5) 151 #define MUSB_VAL_HOST_RXCSR_RXSTALL HCD_BIT(6) 152 #define MUSB_VAL_HOST_RXCSR_CLRDATATOG HCD_BIT(7) 153 #define MUSB_VAL_HOST_RXCSR_DATATOG HCD_BIT(9) 154 #define MUSB_VAL_HOST_RXCSR_DATATOGWREN HCD_BIT(10) 155 #define MUSB_VAL_HOST_RXCSR_DISNYET HCD_BIT(12) 156 #define MUSB_VAL_HOST_RXCSR_DMAEN HCD_BIT(13) 157 158 /* HOST_TXCSR */ 159 #define MUSB_VAL_HOST_TXCSR_TXPKTRDY HCD_BIT(0) 160 #define MUSB_VAL_HOST_TXCSR_FIFONOTEMPTY HCD_BIT(1) 161 #define MUSB_VAL_HOST_TXCSR_ERROR HCD_BIT(2) 162 #define MUSB_VAL_HOST_TXCSR_FLUSHFIFO HCD_BIT(3) 163 #define MUSB_VAL_HOST_TXCSR_SETUPPKT HCD_BIT(4) 164 #define MUSB_VAL_HOST_TXCSR_RXSTALL HCD_BIT(5) 165 #define MUSB_VAL_HOST_TXCSR_CLRDATATOG HCD_BIT(6) 166 #define MUSB_VAL_HOST_TXCSR_NAK_TIMEOUT HCD_BIT(7) 167 #define MUSB_VAL_HOST_TXCSR_DATATOG HCD_BIT(8) 168 #define MUSB_VAL_HOST_TXCSR_DATATOGWREN HCD_BIT(9) 169 #define MUSB_VAL_HOST_TXCSR_DMAMODE HCD_BIT(10) 170 #define MUSB_VAL_HOST_TXCSR_FRCDATATOG HCD_BIT(11) 171 #define MUSB_VAL_HOST_TXCSR_DMAEN HCD_BIT(12) 172 #define MUSB_VAL_HOST_TXCSR_MODE HCD_BIT(13) 173 #define MUSB_VAL_HOST_TXCSR_ISO HCD_BIT(14) 174 #define MUSB_VAL_HOST_TXCSR_AUTOSET HCD_BIT(15) 175 176 /* RXFIFOADDR/TXFIFOADDR */ 177 #define MUSB_VAL_XXFIFOADDR_EP0_END 0x08u 178 179 /* RXFIFOSZ/TXFIFOSZ */ 180 #define MUSB_VAL_XXFIFOSZ_16 0x01u 181 #define MUSB_VAL_XXFIFOSZ_32 0x02u 182 #define MUSB_VAL_XXFIFOSZ_64 0x03u 183 #define MUSB_VAL_XXFIFOSZ_128 0x04u 184 #define MUSB_VAL_XXFIFOSZ_256 0x05u 185 #define MUSB_VAL_XXFIFOSZ_512 0x06u 186 #define MUSB_VAL_XXFIFOSZ_1024 0x07u 187 #define MUSB_VAL_XXFIFOSZ_2048 0x08u 188 #define MUSB_VAL_XXFIFOSZ_4096 0x09u 189 190 #endif /* !_MUSB_REGS_H_ */ 191