1 #ifndef _OMAP_TIMER_REGISTERS_H 2 #define _OMAP_TIMER_REGISTERS_H 3 4 5 /* General-purpose timer register map */ 6 #define OMAP3_GPTIMER1_BASE 0x48318000 /* GPTIMER1 physical address */ 7 #define OMAP3_GPTIMER2_BASE 0x49032000 /* GPTIMER2 physical address */ 8 #define OMAP3_GPTIMER3_BASE 0x49034000 /* GPTIMER3 physical address */ 9 #define OMAP3_GPTIMER4_BASE 0x49036000 /* GPTIMER4 physical address */ 10 #define OMAP3_GPTIMER5_BASE 0x49038000 /* GPTIMER5 physical address */ 11 #define OMAP3_GPTIMER6_BASE 0x4903A000 /* GPTIMER6 physical address */ 12 #define OMAP3_GPTIMER7_BASE 0x4903C000 /* GPTIMER7 physical address */ 13 #define OMAP3_GPTIMER8_BASE 0x4903E000 /* GPTIMER8 physical address */ 14 #define OMAP3_GPTIMER9_BASE 0x49040000 /* GPTIMER9 physical address */ 15 #define OMAP3_GPTIMER10_BASE 0x48086000 /* GPTIMER10 physical address */ 16 #define OMAP3_GPTIMER11_BASE 0x48088000 /* GPTIMER11 physical address */ 17 18 19 /* General-purpose timer registers */ 20 #define OMAP3_TIMER_TIDR 0x000 /* IP revision code */ 21 #define OMAP3_TIMER_TIOCP_CFG 0x010 /* Controls params for GP timer L4 interface */ 22 #define OMAP3_TIMER_TISTAT 0x014 /* Status (excl. interrupt status) */ 23 #define OMAP3_TIMER_TISR 0x018 /* Pending interrupt status */ 24 #define OMAP3_TIMER_TIER 0x01C /* Interrupt enable */ 25 #define OMAP3_TIMER_TWER 0x020 /* Wakeup enable */ 26 #define OMAP3_TIMER_TCLR 0x024 /* Controls optional features */ 27 #define OMAP3_TIMER_TCRR 0x028 /* Internal counter value */ 28 #define OMAP3_TIMER_TLDR 0x02C /* Timer load value */ 29 #define OMAP3_TIMER_TTGR 0x030 /* Triggers counter reload */ 30 #define OMAP3_TIMER_TWPS 0x034 /* Indicates if Write-Posted pending */ 31 #define OMAP3_TIMER_TMAR 0x038 /* Value to be compared with counter */ 32 #define OMAP3_TIMER_TCAR1 0x03C /* First captured value of counter register */ 33 #define OMAP3_TIMER_TSICR 0x040 /* Control posted mode and functional SW reset */ 34 #define OMAP3_TIMER_TCAR2 0x044 /* Second captured value of counter register */ 35 #define OMAP3_TIMER_TPIR 0x048 /* Positive increment (1 ms tick) */ 36 #define OMAP3_TIMER_TNIR 0x04C /* Negative increment (1 ms tick) */ 37 #define OMAP3_TIMER_TCVR 0x050 /* Defines TCRR is sub/over-period (1 ms tick) */ 38 #define OMAP3_TIMER_TOCR 0x054 /* Masks tick interrupt */ 39 #define OMAP3_TIMER_TOWR 0x058 /* Number of masked overflow interrupts */ 40 41 #define AM335X_DMTIMER0_BASE 0x44E05000 /* DMTimer0 Registers */ 42 #define AM335X_DMTIMER1_1MS_BASE 0x44E31000 /* DMTimer1 1ms Registers (Accurate 1ms timer) */ 43 #define AM335X_DMTIMER2_BASE 0x48040000 /* DMTimer2 Registers */ 44 #define AM335X_DMTIMER3_BASE 0x48042000 /* DMTimer3 Registers */ 45 #define AM335X_DMTIMER4_BASE 0x48044000 /* DMTimer4 Registers */ 46 #define AM335X_DMTIMER5_BASE 0x48046000 /* DMTimer5 Registers */ 47 #define AM335X_DMTIMER6_BASE 0x48048000 /* DMTimer6 Registers */ 48 #define AM335X_DMTIMER7_BASE 0x4804A000 /* DMTimer7 Registers */ 49 50 /* General-purpose timer registers AM335x non 1MS timers have different offsets */ 51 #define AM335X_TIMER_TIDR 0x000 /* IP revision code */ 52 #define AM335X_TIMER_TIOCP_CFG 0x010 /* Controls params for GP timer L4 interface */ 53 #define AM335X_TIMER_IRQSTATUS_RAW 0x024 /* Timer IRQSTATUS Raw Register */ 54 #define AM335X_TIMER_IRQSTATUS 0x028 /* Timer IRQSTATUS Register */ 55 #define AM335X_TIMER_IRQENABLE_SET 0x02C /* Timer IRQENABLE Set Register */ 56 #define AM335X_TIMER_IRQENABLE_CLR 0x030 /* Timer IRQENABLE Clear Register */ 57 #define AM335X_TIMER_IRQWAKEEN 0x034 /* Timer IRQ Wakeup Enable Register */ 58 #define AM335X_TIMER_TCLR 0x038 /* Controls optional features */ 59 #define AM335X_TIMER_TCRR 0x03C /* Internal counter value */ 60 #define AM335X_TIMER_TLDR 0x040 /* Timer load value */ 61 #define AM335X_TIMER_TTGR 0x044 /* Triggers counter reload */ 62 #define AM335X_TIMER_TWPS 0x048 /* Indicates if Write-Posted pending */ 63 #define AM335X_TIMER_TMAR 0x04C /* Value to be compared with counter */ 64 #define AM335X_TIMER_TCAR1 0x050 /* First captured value of counter register */ 65 #define AM335X_TIMER_TSICR 0x054 /* Control posted mode and functional SW reset */ 66 #define AM335X_TIMER_TCAR2 0x058 /* Second captured value of counter register */ 67 68 69 70 /* Interrupt status register fields */ 71 #define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */ 72 #define OMAP3_TISR_OVF_IT_FLAG (1 << 1) /* Pending overflow interrupt status */ 73 #define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */ 74 75 /* Interrupt enable register fields */ 76 #define OMAP3_TIER_MAT_IT_ENA (1 << 0) /* Enable match interrupt */ 77 #define OMAP3_TIER_OVF_IT_ENA (1 << 1) /* Enable overflow interrupt */ 78 #define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */ 79 80 /* Timer control fields */ 81 #define OMAP3_TCLR_ST (1 << 0) /* Start/stop timer */ 82 #define OMAP3_TCLR_AR (1 << 1) /* Autoreload or one-shot mode */ 83 #define OMAP3_TCLR_PRE (1 << 5) /* Prescaler on */ 84 #define OMAP3_TCLR_PTV 2 85 #define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */ 86 87 88 #define OMAP3_CM_CLKSEL_GFX 0x48004b40 89 #define OMAP3_CM_CLKEN_PLL 0x48004d00 90 #define OMAP3_CM_FCLKEN1_CORE 0x48004A00 91 #define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */ 92 #define OMAP3_CM_FCLKEN_PER 0x48005000 93 #define OMAP3_CM_CLKSEL_PER 0x48005040 94 #define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */ 95 96 97 #define CM_MODULEMODE_MASK (0x3 << 0) 98 #define CM_MODULEMODE_ENABLE (0x2 << 0) 99 #define CM_MODULEMODE_DISABLED (0x0 << 0) 100 101 #define CM_CLKCTRL_IDLEST (0x3 << 16) 102 #define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16) 103 #define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16) 104 #define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16) 105 #define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16) 106 107 #define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */ 108 109 #define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4) /* This register manages the TIMER1 clocks. [Memory Mapped] */ 110 111 112 #define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */ 113 #define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C) /* This register manages the TIMER7 clocks. [Memory Mapped] */ 114 115 116 117 /* CM_DPLL registers */ 118 119 120 #define CM_DPLL_BASE 0x44E00500 /* Clock Module PLL Registers */ 121 122 #define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28) 123 124 125 #define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0) 126 #define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) /* Select CLK_M_OSC clock */ 127 #define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_32KHZ clock */ 128 #define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) /* Select TCLKIN clock */ 129 #define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) /* Select CLK_RC32K clock */ 130 #define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) /* Selects the CLK_32768 from 32KHz Crystal Osc */ 131 132 #define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04) 133 #define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0) 134 #define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */ 135 #define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */ 136 #define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */ 137 #define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */ 138 139 140 141 142 #define OMAP3_CLKSEL_GPT1 (1 << 0) /* Selects GPTIMER 1 source 143 * clock: 144 * 145 * 0: use 32KHz clock 146 * 1: sys clock) 147 */ 148 #define OMAP3_CLKSEL_GPT10 (1 << 6) 149 #define OMAP3_CLKSEL_GPT11 (1 << 7) 150 151 152 #define TIMER_FREQ 1000 /* clock frequency for OMAP timer (1ms) */ 153 #define TIMER_COUNT(freq) (TIMER_FREQ/(freq)) /* initial value for counter*/ 154 155 #endif /* _OMAP_TIMER_REGISTERS_H */ 156