1 /* $NetBSD: armreg.h,v 1.83 2013/09/07 00:32:33 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_ARMREG_H 40 #define _ARM_ARMREG_H 41 42 /* 43 * ARM Process Status Register 44 * 45 * The picture in the ARM manuals looks like this: 46 * 3 3 2 2 2 2 47 * 1 0 9 8 7 6 8 7 6 5 4 0 48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 50 * | | | | | | | | | |4 3 2 1 0| 51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 52 */ 53 54 #define PSR_FLAGS 0xf0000000 /* flags */ 55 #define PSR_N_bit (1 << 31) /* negative */ 56 #define PSR_Z_bit (1 << 30) /* zero */ 57 #define PSR_C_bit (1 << 29) /* carry */ 58 #define PSR_V_bit (1 << 28) /* overflow */ 59 60 #define PSR_Q_bit (1 << 27) /* saturation */ 61 62 #define I32_bit (1 << 7) /* IRQ disable */ 63 #define F32_bit (1 << 6) /* FIQ disable */ 64 #define IF32_bits (3 << 6) /* IRQ/FIQ disable */ 65 66 #define PSR_T_bit (1 << 5) /* Thumb state */ 67 #define PSR_J_bit (1 << 24) /* Java mode */ 68 69 #ifdef __minix 70 /* Minix uses these aliases */ 71 #define PSR_F F32_bit 72 #define PSR_I I32_bit 73 #endif 74 75 #define PSR_MODE 0x0000001f /* mode mask */ 76 #define PSR_USR26_MODE 0x00000000 77 #define PSR_FIQ26_MODE 0x00000001 78 #define PSR_IRQ26_MODE 0x00000002 79 #define PSR_SVC26_MODE 0x00000003 80 #define PSR_USR32_MODE 0x00000010 81 #define PSR_FIQ32_MODE 0x00000011 82 #define PSR_IRQ32_MODE 0x00000012 83 #define PSR_SVC32_MODE 0x00000013 84 #define PSR_MON32_MODE 0x00000016 85 #define PSR_ABT32_MODE 0x00000017 86 #define PSR_HYP32_MODE 0x0000001a 87 #define PSR_UND32_MODE 0x0000001b 88 #define PSR_SYS32_MODE 0x0000001f 89 #define PSR_32_MODE 0x00000010 90 91 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 92 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 93 94 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ 95 96 #define R15_MODE 0x00000003 97 #define R15_MODE_USR 0x00000000 98 #define R15_MODE_FIQ 0x00000001 99 #define R15_MODE_IRQ 0x00000002 100 #define R15_MODE_SVC 0x00000003 101 102 #define R15_PC 0x03fffffc 103 104 #define R15_FIQ_DISABLE 0x04000000 105 #define R15_IRQ_DISABLE 0x08000000 106 107 #define R15_FLAGS 0xf0000000 108 #define R15_FLAG_N 0x80000000 109 #define R15_FLAG_Z 0x40000000 110 #define R15_FLAG_C 0x20000000 111 #define R15_FLAG_V 0x10000000 112 113 /* 114 * Co-processor 15: The system control co-processor. 115 */ 116 117 #define ARM_CP15_CPU_ID 0 118 119 /* 120 * The CPU ID register is theoretically structured, but the definitions of 121 * the fields keep changing. 122 */ 123 124 /* The high-order byte is always the implementor */ 125 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 126 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 127 #define CPU_ID_DEC 0x44000000 /* 'D' */ 128 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 129 #define CPU_ID_TI 0x54000000 /* 'T' */ 130 #define CPU_ID_MARVELL 0x56000000 /* 'V' */ 131 #define CPU_ID_FARADAY 0x66000000 /* 'f' */ 132 133 /* How to decide what format the CPUID is in. */ 134 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 135 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 136 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 137 138 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 139 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 140 #define CPU_ID_FOUNDRY_VLSI 0x00560000 141 142 /* On ARM7 it holds the architecture and variant (sub-model) */ 143 #define CPU_ID_7ARCH_MASK 0x00800000 144 #define CPU_ID_7ARCH_V3 0x00000000 145 #define CPU_ID_7ARCH_V4T 0x00800000 146 #define CPU_ID_7VARIANT_MASK 0x007f0000 147 148 /* On more recent ARMs, it does the same, but in a different format */ 149 #define CPU_ID_ARCH_MASK 0x000f0000 150 #define CPU_ID_ARCH_V3 0x00000000 151 #define CPU_ID_ARCH_V4 0x00010000 152 #define CPU_ID_ARCH_V4T 0x00020000 153 #define CPU_ID_ARCH_V5 0x00030000 154 #define CPU_ID_ARCH_V5T 0x00040000 155 #define CPU_ID_ARCH_V5TE 0x00050000 156 #define CPU_ID_ARCH_V5TEJ 0x00060000 157 #define CPU_ID_ARCH_V6 0x00070000 158 #define CPU_ID_VARIANT_MASK 0x00f00000 159 160 /* Next three nybbles are part number */ 161 #define CPU_ID_PARTNO_MASK 0x0000fff0 162 163 /* Intel XScale has sub fields in part number */ 164 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 165 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 166 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 167 168 /* And finally, the revision number. */ 169 #define CPU_ID_REVISION_MASK 0x0000000f 170 171 /* Individual CPUs are probably best IDed by everything but the revision. */ 172 #define CPU_ID_CPU_MASK 0xfffffff0 173 174 /* Fake CPU IDs for ARMs without CP15 */ 175 #define CPU_ID_ARM2 0x41560200 176 #define CPU_ID_ARM250 0x41560250 177 178 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 179 #define CPU_ID_ARM3 0x41560300 180 #define CPU_ID_ARM600 0x41560600 181 #define CPU_ID_ARM610 0x41560610 182 #define CPU_ID_ARM620 0x41560620 183 184 /* ARM7 CPUs -- [15:12] == 7 */ 185 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 186 #define CPU_ID_ARM710 0x41007100 187 #define CPU_ID_ARM7500 0x41027100 188 #define CPU_ID_ARM710A 0x41067100 189 #define CPU_ID_ARM7500FE 0x41077100 190 #define CPU_ID_ARM710T 0x41807100 191 #define CPU_ID_ARM720T 0x41807200 192 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 193 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 194 195 /* Post-ARM7 CPUs */ 196 #define CPU_ID_ARM810 0x41018100 197 #define CPU_ID_ARM920T 0x41129200 198 #define CPU_ID_ARM922T 0x41029220 199 #define CPU_ID_ARM926EJS 0x41069260 200 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 201 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 202 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 203 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 204 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 205 #define CPU_ID_ARM1022ES 0x4105a220 206 #define CPU_ID_ARM1026EJS 0x4106a260 207 #define CPU_ID_ARM11MPCORE 0x410fb020 208 #define CPU_ID_ARM1136JS 0x4107b360 209 #define CPU_ID_ARM1136JSR1 0x4117b360 210 #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ 211 #define CPU_ID_ARM1176JZS 0x410fb760 212 #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) 213 #define CPU_ID_CORTEXA5R0 0x410fc050 214 #define CPU_ID_CORTEXA7R0 0x410fc070 215 #define CPU_ID_CORTEXA8R1 0x411fc080 216 #define CPU_ID_CORTEXA8R2 0x412fc080 217 #define CPU_ID_CORTEXA8R3 0x413fc080 218 #define CPU_ID_CORTEXA9R2 0x411fc090 219 #define CPU_ID_CORTEXA9R3 0x412fc090 220 #define CPU_ID_CORTEXA9R4 0x413fc090 221 #define CPU_ID_CORTEXA15R2 0x412fc0f0 222 #define CPU_ID_CORTEXA15R3 0x413fc0f0 223 #define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000) 224 #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) 225 #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) 226 #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) 227 #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) 228 #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) 229 #define CPU_ID_SA110 0x4401a100 230 #define CPU_ID_SA1100 0x4401a110 231 #define CPU_ID_TI925T 0x54029250 232 #define CPU_ID_MV88FR571_VD 0x56155710 233 #define CPU_ID_MV88SV131 0x56251310 234 #define CPU_ID_FA526 0x66015260 235 #define CPU_ID_SA1110 0x6901b110 236 #define CPU_ID_IXP1200 0x6901c120 237 #define CPU_ID_80200 0x69052000 238 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 239 #define CPU_ID_PXA210 0x69052120 240 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 241 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 242 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 243 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 244 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 245 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 246 #define CPU_ID_PXA27X 0x69054110 247 #define CPU_ID_80321_400 0x69052420 248 #define CPU_ID_80321_600 0x69052430 249 #define CPU_ID_80321_400_B0 0x69052c20 250 #define CPU_ID_80321_600_B0 0x69052c30 251 #define CPU_ID_80219_400 0x69052e20 252 #define CPU_ID_80219_600 0x69052e30 253 #define CPU_ID_IXP425_533 0x690541c0 254 #define CPU_ID_IXP425_400 0x690541d0 255 #define CPU_ID_IXP425_266 0x690541f0 256 #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) 257 #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ 258 #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ 259 #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ 260 #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ 261 /* Marvell's CPUIDs with ARM ID in implementor field */ 262 #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 263 #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ 264 #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ 265 266 /* CPUID registers */ 267 #define ARM_PFR0_THUMBEE_MASK 0x0000f000 268 #define ARM_PFR1_GTIMER_MASK 0x000f0000 269 #define ARM_PFR1_VIRT_MASK 0x0000f000 270 #define ARM_PFR1_SEC_MASK 0x000000f0 271 272 /* Media and VFP Feature registers */ 273 #define ARM_MVFR0_ROUNDING_MASK 0xf0000000 274 #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000 275 #define ARM_MVFR0_SQRT_MASK 0x00f00000 276 #define ARM_MVFR0_DIVIDE_MASK 0x000f0000 277 #define ARM_MVFR0_EXCEPT_MASK 0x0000f000 278 #define ARM_MVFR0_DFLOAT_MASK 0x00000f00 279 #define ARM_MVFR0_SFLOAT_MASK 0x000000f0 280 #define ARM_MVFR0_ASIMD_MASK 0x0000000f 281 #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000 282 #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000 283 #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000 284 #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000 285 #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000 286 #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00 287 #define ARM_MVFR1_D_NAN_MASK 0x000000f0 288 #define ARM_MVFR1_FTZ_MASK 0x0000000f 289 290 /* ARM3-specific coprocessor 15 registers */ 291 #define ARM3_CP15_FLUSH 1 292 #define ARM3_CP15_CONTROL 2 293 #define ARM3_CP15_CACHEABLE 3 294 #define ARM3_CP15_UPDATEABLE 4 295 #define ARM3_CP15_DISRUPTIVE 5 296 297 /* ARM3 Control register bits */ 298 #define ARM3_CTL_CACHE_ON 0x00000001 299 #define ARM3_CTL_SHARED 0x00000002 300 #define ARM3_CTL_MONITOR 0x00000004 301 302 /* 303 * Post-ARM3 CP15 registers: 304 * 305 * 1 Control register 306 * 307 * 2 Translation Table Base 308 * 309 * 3 Domain Access Control 310 * 311 * 4 Reserved 312 * 313 * 5 Fault Status 314 * 315 * 6 Fault Address 316 * 317 * 7 Cache/write-buffer Control 318 * 319 * 8 TLB Control 320 * 321 * 9 Cache Lockdown 322 * 323 * 10 TLB Lockdown 324 * 325 * 11 Reserved 326 * 327 * 12 Reserved 328 * 329 * 13 Process ID (for FCSE) 330 * 331 * 14 Reserved 332 * 333 * 15 Implementation Dependent 334 */ 335 336 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 337 338 /* CPU control register (CP15 register 1) */ 339 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 340 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 341 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 342 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 343 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 344 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 345 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 346 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 347 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 348 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 349 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 350 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ 351 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 352 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 353 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 354 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 355 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 356 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 357 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 358 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ 359 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 360 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 361 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 362 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ 363 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ 364 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 365 366 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 367 368 /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */ 369 #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ 370 #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ 371 #define CPACR_CPn(n) (3 << (2*n)) 372 #define CPACR_NOACCESS 0 /* reset value */ 373 #define CPACR_PRIVED 1 /* Privileged mode access */ 374 #define CPACR_RESERVED 2 375 #define CPACR_ALL 3 /* Privileged and User mode access */ 376 377 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 378 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 379 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 380 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 381 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 382 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 383 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 384 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 385 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 386 387 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 388 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 389 /* This is an undocumented flag 390 * used to work around a cache bug 391 * in r0 steppings. See errata 392 * 364296. 393 */ 394 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 395 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 396 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 397 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 398 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 399 400 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 401 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Enable parity */ 402 #define CORTEXA9_AUXCTL_1WAY 0x00000100 /* Alloc in one way only */ 403 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache */ 404 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* CPU is in SMP mode */ 405 #define CORTEXA9_AUXCTL_WRZERO 0x00000008 /* Write full line of zeroes */ 406 #define CORTEXA9_AUXCTL_L1PLD 0x00000004 /* L1 Dside prefetch */ 407 #define CORTEXA9_AUXCTL_L2PLD 0x00000002 /* L2 Dside prefetch */ 408 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Forward Cache/TLB ops */ 409 410 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */ 411 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 412 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 413 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 414 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 415 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 416 #define XSCALE_AUXCTL_MD_MASK 0x00000030 417 418 /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */ 419 #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ 420 #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 421 #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ 422 #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ 423 #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 424 #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ 425 426 /* Marvell PJ4B Auxillary Control Register */ 427 #define PJ4B_AUXCTL_SMPNAMP 0x00000040 /* SMP/AMP */ 428 429 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ 430 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ 431 #define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */ 432 #define CORTEXA9_AUXCTL_L1_PLD 0x00000004 /* Data prefetch hint enable */ 433 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ 434 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ 435 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ 436 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ 437 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ 438 439 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 440 #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 441 #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 442 #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 443 #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 444 #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 445 #define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 446 #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 447 #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 448 #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 449 #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 450 451 /* Cache type register definitions 0 */ 452 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ 453 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 454 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 455 #define CPU_CT_S (1U << 24) /* split cache */ 456 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 457 458 #define CPU_CT_CTYPE_WT 0 /* write-through */ 459 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 460 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 461 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 462 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 463 #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ 464 465 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 466 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 467 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 468 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 469 #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ 470 471 /* format 4 definitions */ 472 #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ 473 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ 474 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ 475 #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ 476 #define CPU_CT4_L1_VIPT 2 /* VIPT */ 477 #define CPU_CT4_L1_PIPT 3 /* PIPT */ 478 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ 479 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ 480 481 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ 482 #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ 483 #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ 484 #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ 485 #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ 486 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) 487 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) 488 #define CPU_CSID_LEN(x) ((x) & 0x07) 489 490 /* Cache size selection register definitions 2, Rd, c0, c0, 0 */ 491 #define CPU_CSSR_L2 0x00000002 492 #define CPU_CSSR_L1 0x00000000 493 #define CPU_CSSR_InD 0x00000001 494 495 /* ARMv7A CP15 Global Timer definitions */ 496 #define CNTKCTL_PL0PTEN 0x00000200 /* PL0 Physical Timer Enable */ 497 #define CNTKCTL_PL0VTEN 0x00000100 /* PL0 Virtual Timer Enable */ 498 #define CNTKCTL_EVNTI 0x000000f0 /* CNTVCT Event Bit Select */ 499 #define CNTKCTL_EVNTDIR 0x00000008 /* CNTVCT Event Dir (1->0) */ 500 #define CNTKCTL_EVNTEN 0x00000004 /* CNTVCT Event Enable */ 501 #define CNTKCTL_PL0PCTEN 0x00000200 /* PL0 Physical Counter Enable */ 502 #define CNTKCTL_PL0VCTEN 0x00000100 /* PL0 Virtual Counter Enable */ 503 504 #define CNT_CTL_ISTATUS 0x00000004 /* Timer is asserted */ 505 #define CNT_CTL_IMASK 0x00000002 /* Timer output is masked */ 506 #define CNT_CTL_ENABLE 0x00000001 /* Timer is enabled */ 507 508 /* Fault status register definitions */ 509 510 #define FAULT_TYPE_MASK 0x0f 511 #define FAULT_USER 0x10 512 513 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 514 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 515 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 516 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 517 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 518 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 519 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 520 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 521 #define FAULT_ALIGN_0 0x01 /* Alignment */ 522 #define FAULT_ALIGN_1 0x03 /* Alignment */ 523 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 524 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 525 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 526 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 527 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 528 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 529 530 #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 531 532 /* 533 * Address of the vector page, low and high versions. 534 */ 535 #define ARM_VECTORS_LOW 0x00000000U 536 #define ARM_VECTORS_HIGH 0xffff0000U 537 538 /* 539 * ARM Instructions 540 * 541 * 3 3 2 2 2 542 * 1 0 9 8 7 0 543 * +-------+-------------------------------------------------------+ 544 * | cond | instruction dependent | 545 * |c c c c| | 546 * +-------+-------------------------------------------------------+ 547 */ 548 549 #define INSN_SIZE 4 /* Always 4 bytes */ 550 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 551 #define INSN_COND_AL 0xe0000000 /* Always condition */ 552 553 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 554 555 /* 556 * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) 557 */ 558 #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ 559 #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ 560 #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ 561 #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ 562 #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ 563 #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ 564 #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ 565 #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ 566 #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ 567 #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ 568 #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ 569 #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ 570 #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ 571 #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ 572 #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ 573 #define ARM11_PMCCTL_SBZ \ 574 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) 575 576 #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ 577 #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ 578 #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ 579 #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ 580 #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ 581 #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ 582 #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ 583 #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ 584 #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ 585 #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ 586 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ 587 #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ 588 #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ 589 #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ 590 #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ 591 #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ 592 #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ 593 #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ 594 #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ 595 #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ 596 #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ 597 #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ 598 #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ 599 #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ 600 601 /* Defines for ARM CORTEX performance counters */ 602 #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ 603 #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ 604 #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ 605 606 /* Translate Table Base Control Register */ 607 #define TTBCR_S_EAE __BIT(31) // Extended Address Extension 608 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1 609 #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0 610 #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0 611 612 #define TTBCR_L_EAE __BIT(31) // Extended Address Extension 613 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability 614 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability 615 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability 616 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1 617 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1 618 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset 619 #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability 620 #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability 621 #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability 622 #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0 623 #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset 624 625 /* Defines for ARM Generic Timer */ 626 #define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled 627 #define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt 628 #define ARM_CNTCTL_ISTATUS __BIT(2) // Interrupt is pending 629 630 #define ARM_CNTKCTL_PL0PTEN __BIT(9) 631 #define ARM_CNTKCTL_PL0VTEN __BIT(8) 632 #define ARM_CNTKCTL_EVNTI __BITS(7,4) 633 #define ARM_CNTKCTL_EVNTDIR __BIT(3) 634 #define ARM_CNTKCTL_EVNTEN __BIT(2) 635 #define ARM_CNTKCTL_PL0PCTEN __BIT(1) 636 #define ARM_CNTKCTL_PL0VCTEN __BIT(0) 637 638 #define ARM_CNTHCTL_EVNTI __BITS(7,4) 639 #define ARM_CNTHCTL_EVNTDIR __BIT(3) 640 #define ARM_CNTHCTL_EVNTEN __BIT(2) 641 #define ARM_CNTHCTL_PL1PCTEN __BIT(1) 642 #define ARM_CNTHCTL_PL1VCTEN __BIT(0) 643 644 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL) 645 #define ARMREG_READ_INLINE(name, __insnstring) \ 646 static inline uint32_t armreg_##name##_read(void) \ 647 { \ 648 uint32_t __rv; \ 649 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ 650 return __rv; \ 651 } 652 653 #define ARMREG_WRITE_INLINE(name, __insnstring) \ 654 static inline void armreg_##name##_write(uint32_t __val) \ 655 { \ 656 __asm __volatile("mcr " __insnstring :: "r"(__val)); \ 657 } 658 659 #define ARMREG_READ64_INLINE(name, __insnstring) \ 660 static inline uint64_t armreg_##name##_read(void) \ 661 { \ 662 uint64_t __rv; \ 663 __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \ 664 return __rv; \ 665 } 666 667 #define ARMREG_WRITE64_INLINE(name, __insnstring) \ 668 static inline void armreg_##name##_write(uint64_t __val) \ 669 { \ 670 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \ 671 } 672 673 /* cp10 registers */ 674 ARMREG_READ_INLINE(fpsid, "p10,7,%0,c0,c0,0") /* VFP System ID */ 675 ARMREG_READ_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */ 676 ARMREG_WRITE_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */ 677 ARMREG_READ_INLINE(mvfr1, "p10,7,%0,c6,c0,0") /* Media and VFP Feature Register 1 */ 678 ARMREG_READ_INLINE(mvfr0, "p10,7,%0,c7,c0,0") /* Media and VFP Feature Register 0 */ 679 ARMREG_READ_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */ 680 ARMREG_WRITE_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */ 681 ARMREG_READ_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */ 682 ARMREG_WRITE_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */ 683 ARMREG_READ_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */ 684 ARMREG_WRITE_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */ 685 686 /* cp15 c0 registers */ 687 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ 688 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ 689 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ 690 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ 691 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ 692 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ 693 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ 694 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ 695 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ 696 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ 697 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ 698 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ 699 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ 700 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ 701 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ 702 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ 703 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ 704 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 705 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 706 /* cp15 c1 registers */ 707 ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ 708 ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ 709 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 710 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 711 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 712 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 713 /* cp15 c2 registers */ 714 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 715 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 716 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 717 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 718 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 719 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 720 /* cp15 c5 registers */ 721 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ 722 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ 723 /* cp15 c6 registers */ 724 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ 725 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ 726 /* cp15 c7 registers */ 727 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ 728 ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */ 729 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ 730 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ 731 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ 732 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ 733 ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */ 734 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ 735 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ 736 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ 737 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ 738 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ 739 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ 740 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ 741 ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */ 742 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ 743 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ 744 /* cp15 c8 registers */ 745 ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */ 746 ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */ 747 ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */ 748 ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */ 749 ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */ 750 ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */ 751 ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */ 752 ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */ 753 ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */ 754 ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */ 755 ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */ 756 ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */ 757 ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */ 758 ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */ 759 /* cp15 c9 registers */ 760 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 761 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 762 ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 763 ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 764 ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 765 ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 766 ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 767 ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 768 ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 769 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 770 ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 771 ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 772 /* cp15 c13 registers */ 773 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 774 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 775 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 776 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 777 /* cp14 c12 registers */ 778 ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 779 ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 780 /* cp15 c14 registers */ 781 /* cp15 Global Timer Registers */ 782 ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 783 ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 784 ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 785 ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 786 ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 787 ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 788 ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 789 ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 790 ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 791 ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 792 ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 793 ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 794 ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 795 ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 796 ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 797 ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 798 ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 799 ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 800 ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 801 ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 802 /* cp15 c15 registers */ 803 ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ 804 ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 805 ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 806 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 807 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 808 809 #endif /* !__ASSEMBLER__ */ 810 811 812 #define MPIDR_31 0x80000000 813 #define MPIDR_U 0x40000000 // 1 = Uniprocessor 814 #define MPIDR_MT 0x01000000 // AFF0 for SMT 815 #define MPIDR_AFF2 0x00ff0000 816 #define MPIDR_AFF1 0x0000ff00 817 #define MPIDR_AFF0 0x000000ff 818 819 #endif /* _ARM_ARMREG_H */ 820