1 /* $NetBSD: cpu.h,v 1.58 2013/12/01 01:05:16 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_STANDALONE) 41 #include <sys/types.h> 42 #else 43 #include <stdbool.h> 44 #endif /* _KERNEL || _STANDALONE */ 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_xen.h" 49 #ifdef i386 50 #include "opt_user_ldt.h" 51 #include "opt_vm86.h" 52 #endif 53 #endif 54 55 /* 56 * Definitions unique to x86 cpu support. 57 */ 58 #include <machine/frame.h> 59 #include <machine/pte.h> 60 #include <machine/segments.h> 61 #include <machine/tss.h> 62 #include <machine/intrdefs.h> 63 64 #include <x86/cacheinfo.h> 65 66 #include <sys/cpu_data.h> 67 #include <sys/evcnt.h> 68 #include <sys/device_if.h> /* for device_t */ 69 70 #ifdef XEN 71 #include <xen/xen-public/xen.h> 72 #include <xen/xen-public/event_channel.h> 73 #include <sys/mutex.h> 74 #endif /* XEN */ 75 76 struct intrsource; 77 struct pmap; 78 79 #ifdef __x86_64__ 80 #define i386tss x86_64_tss 81 #endif 82 83 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 84 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 85 86 /* 87 * a bunch of this belongs in cpuvar.h; move it later.. 88 */ 89 90 struct cpu_info { 91 struct cpu_data ci_data; /* MI per-cpu data */ 92 device_t ci_dev; /* pointer to our device */ 93 struct cpu_info *ci_self; /* self-pointer */ 94 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 95 void *ci_tlog_base; /* Trap log base */ 96 int32_t ci_tlog_offset; /* Trap log current offset */ 97 98 /* 99 * Will be accessed by other CPUs. 100 */ 101 struct cpu_info *ci_next; /* next cpu */ 102 struct lwp *ci_curlwp; /* current owner of the processor */ 103 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 104 int ci_fpsaving; /* save in progress */ 105 int ci_fpused; /* XEN: FPU was used by curlwp */ 106 cpuid_t ci_cpuid; /* our CPU ID */ 107 int _unused; 108 uint32_t ci_acpiid; /* our ACPI/MADT ID */ 109 uint32_t ci_initapicid; /* our intitial APIC ID */ 110 111 /* 112 * Private members. 113 */ 114 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 115 struct pmap *ci_pmap; /* current pmap */ 116 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 117 int ci_want_pmapload; /* pmap_load() is needed */ 118 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 119 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 120 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 121 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 122 int ci_curldt; /* current LDT descriptor */ 123 int ci_nintrhand; /* number of H/W interrupt handlers */ 124 uint64_t ci_scratch; 125 uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)]; 126 127 #ifdef XEN 128 struct iplsource *ci_isources[NIPL]; 129 u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */ 130 #else 131 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 132 #endif 133 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 134 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 135 136 /* The following must be aligned for cmpxchg8b. */ 137 struct { 138 uint32_t ipending; 139 int ilevel; 140 } ci_istate __aligned(8); 141 #define ci_ipending ci_istate.ipending 142 #define ci_ilevel ci_istate.ilevel 143 144 int ci_idepth; 145 void * ci_intrstack; 146 uint32_t ci_imask[NIPL]; 147 uint32_t ci_iunmask[NIPL]; 148 149 uint32_t ci_flags; /* flags; see below */ 150 uint32_t ci_ipis; /* interprocessor interrupts pending */ 151 uint32_t sc_apic_version; /* local APIC version */ 152 153 uint32_t ci_signature; /* X86 cpuid type */ 154 uint32_t ci_vendor[4]; /* vendor string */ 155 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 156 volatile uint32_t ci_lapic_counter; 157 158 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 159 * [0] basic features %edx 160 * [1] basic features %ecx 161 * [2] extended features %edx 162 * [3] extended features %ecx 163 * [4] VIA padlock features 164 */ 165 166 const struct cpu_functions *ci_func; /* start/stop functions */ 167 struct trapframe *ci_ddb_regs; 168 169 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 170 struct x86_cache_info ci_cinfo[CAI_COUNT]; 171 172 union descriptor *ci_gdt; 173 174 #ifdef i386 175 struct i386tss ci_doubleflt_tss; 176 struct i386tss ci_ddbipi_tss; 177 #endif 178 179 #ifdef PAE 180 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 181 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 182 #endif 183 184 #if defined(XEN) && (defined(PAE) || defined(__x86_64__)) 185 /* Currently active user PGD (can't use rcr3() with Xen) */ 186 pd_entry_t * ci_kpm_pdir; /* per-cpu PMD (va) */ 187 paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */ 188 kmutex_t ci_kpm_mtx; 189 #if defined(__x86_64__) 190 /* per-cpu version of normal_pdes */ 191 pd_entry_t * ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XEN */ 192 paddr_t ci_xen_current_user_pgd; 193 #endif /* __x86_64__ */ 194 #endif /* XEN et.al */ 195 196 char *ci_doubleflt_stack; 197 char *ci_ddbipi_stack; 198 199 #ifndef XEN 200 struct evcnt ci_ipi_events[X86_NIPI]; 201 #else /* XEN */ 202 struct evcnt ci_ipi_events[XEN_NIPIS]; 203 evtchn_port_t ci_ipi_evtchn; 204 #endif /* XEN */ 205 206 device_t ci_frequency; /* Frequency scaling technology */ 207 device_t ci_padlock; /* VIA PadLock private storage */ 208 device_t ci_temperature; /* Intel coretemp(4) or equivalent */ 209 device_t ci_vm; /* Virtual machine guest driver */ 210 211 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 212 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 213 int ci_tss_sel; /* TSS selector of this cpu */ 214 215 /* 216 * The following two are actually region_descriptors, 217 * but that would pollute the namespace. 218 */ 219 uintptr_t ci_suspend_gdt; 220 uint16_t ci_suspend_gdt_padding; 221 uintptr_t ci_suspend_idt; 222 uint16_t ci_suspend_idt_padding; 223 224 uint16_t ci_suspend_tr; 225 uint16_t ci_suspend_ldt; 226 uintptr_t ci_suspend_fs; 227 uintptr_t ci_suspend_gs; 228 uintptr_t ci_suspend_kgs; 229 uintptr_t ci_suspend_efer; 230 uintptr_t ci_suspend_reg[12]; 231 uintptr_t ci_suspend_cr0; 232 uintptr_t ci_suspend_cr2; 233 uintptr_t ci_suspend_cr3; 234 uintptr_t ci_suspend_cr4; 235 uintptr_t ci_suspend_cr8; 236 237 /* The following must be in a single cache line. */ 238 int ci_want_resched __aligned(64); 239 int ci_padout __aligned(64); 240 }; 241 242 /* 243 * Macros to handle (some) trapframe registers for common x86 code. 244 */ 245 #ifdef __x86_64__ 246 #define X86_TF_RAX(tf) tf->tf_rax 247 #define X86_TF_RDX(tf) tf->tf_rdx 248 #define X86_TF_RSP(tf) tf->tf_rsp 249 #define X86_TF_RIP(tf) tf->tf_rip 250 #define X86_TF_RFLAGS(tf) tf->tf_rflags 251 #else 252 #define X86_TF_RAX(tf) tf->tf_eax 253 #define X86_TF_RDX(tf) tf->tf_edx 254 #define X86_TF_RSP(tf) tf->tf_esp 255 #define X86_TF_RIP(tf) tf->tf_eip 256 #define X86_TF_RFLAGS(tf) tf->tf_eflags 257 #endif 258 259 /* 260 * Processor flag notes: The "primary" CPU has certain MI-defined 261 * roles (mostly relating to hardclock handling); we distinguish 262 * betwen the processor which booted us, and the processor currently 263 * holding the "primary" role just to give us the flexibility later to 264 * change primaries should we be sufficiently twisted. 265 */ 266 267 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 268 #define CPUF_AP 0x0002 /* CPU is an AP */ 269 #define CPUF_SP 0x0004 /* CPU is only processor */ 270 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 271 272 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 273 #define CPUF_PRESENT 0x1000 /* CPU is present */ 274 #define CPUF_RUNNING 0x2000 /* CPU is running */ 275 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 276 #define CPUF_GO 0x8000 /* CPU should start running */ 277 278 #endif /* _KERNEL || __KMEMUSER */ 279 280 #ifdef _KERNEL 281 /* 282 * We statically allocate the CPU info for the primary CPU (or, 283 * the only CPU on uniprocessors), and the primary CPU is the 284 * first CPU on the CPU info list. 285 */ 286 extern struct cpu_info cpu_info_primary; 287 extern struct cpu_info *cpu_info_list; 288 289 #define CPU_INFO_ITERATOR int __unused 290 #define CPU_INFO_FOREACH(cii, ci) ci = cpu_info_list; \ 291 ci != NULL; ci = ci->ci_next 292 293 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 294 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 295 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 296 297 #if !defined(__GNUC__) || defined(_MODULE) 298 /* For non-GCC and modules */ 299 struct cpu_info *x86_curcpu(void); 300 void cpu_set_curpri(int); 301 # ifdef __GNUC__ 302 lwp_t *x86_curlwp(void) __attribute__ ((const)); 303 # else 304 lwp_t *x86_curlwp(void); 305 # endif 306 #endif 307 308 #define cpu_number() (cpu_index(curcpu())) 309 310 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 311 312 #define X86_AST_GENERIC 0x01 313 #define X86_AST_PREEMPT 0x02 314 315 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 316 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 317 318 void cpu_boot_secondary_processors(void); 319 void cpu_init_idle_lwps(void); 320 void cpu_init_msrs(struct cpu_info *, bool); 321 void cpu_load_pmap(struct pmap *, struct pmap *); 322 void cpu_broadcast_halt(void); 323 void cpu_kick(struct cpu_info *); 324 325 #define curcpu() x86_curcpu() 326 #define curlwp x86_curlwp() 327 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 328 329 /* 330 * Arguments to hardclock, softclock and statclock 331 * encapsulate the previous machine state in an opaque 332 * clockframe; for now, use generic intrframe. 333 */ 334 struct clockframe { 335 struct intrframe cf_if; 336 }; 337 338 /* 339 * Give a profiling tick to the current process when the user profiling 340 * buffer pages are invalid. On the i386, request an ast to send us 341 * through trap(), marking the proc as needing a profiling tick. 342 */ 343 extern void cpu_need_proftick(struct lwp *l); 344 345 /* 346 * Notify the LWP l that it has a signal pending, process as soon as 347 * possible. 348 */ 349 extern void cpu_signotify(struct lwp *); 350 351 /* 352 * We need a machine-independent name for this. 353 */ 354 extern void (*delay_func)(unsigned int); 355 struct timeval; 356 357 #define DELAY(x) (*delay_func)(x) 358 #define delay(x) (*delay_func)(x) 359 360 extern int biosbasemem; 361 extern int biosextmem; 362 extern int cputype; 363 extern int cpuid_level; 364 extern int cpu_class; 365 extern char cpu_brand_string[]; 366 extern int use_pae; 367 368 extern int i386_use_fxsave; 369 extern int i386_has_sse; 370 extern int i386_has_sse2; 371 372 extern void (*x86_cpu_idle)(void); 373 #define cpu_idle() (*x86_cpu_idle)() 374 375 /* machdep.c */ 376 void dumpconf(void); 377 void cpu_reset(void); 378 void i386_proc0_tss_ldt_init(void); 379 void dumpconf(void); 380 void cpu_reset(void); 381 void x86_64_proc0_tss_ldt_init(void); 382 void x86_64_init_pcb_tss_ldt(struct cpu_info *); 383 384 /* longrun.c */ 385 u_int tmx86_get_longrun_mode(void); 386 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 387 void tmx86_init_longrun(void); 388 389 /* identcpu.c */ 390 void cpu_probe(struct cpu_info *); 391 void cpu_identify(struct cpu_info *); 392 393 /* cpu_topology.c */ 394 void x86_cpu_topology(struct cpu_info *); 395 396 /* vm_machdep.c */ 397 void cpu_proc_fork(struct proc *, struct proc *); 398 399 /* locore.s */ 400 struct region_descriptor; 401 void lgdt(struct region_descriptor *); 402 #ifdef XEN 403 void lgdt_finish(void); 404 #endif 405 406 struct pcb; 407 void savectx(struct pcb *); 408 void lwp_trampoline(void); 409 #ifdef XEN 410 void startrtclock(void); 411 void xen_delay(unsigned int); 412 void xen_initclocks(void); 413 void xen_suspendclocks(struct cpu_info *); 414 void xen_resumeclocks(struct cpu_info *); 415 #else 416 /* clock.c */ 417 void initrtclock(u_long); 418 void startrtclock(void); 419 void i8254_delay(unsigned int); 420 void i8254_microtime(struct timeval *); 421 void i8254_initclocks(void); 422 #endif 423 424 /* cpu.c */ 425 426 void cpu_probe_features(struct cpu_info *); 427 428 /* npx.c */ 429 void npxsave_lwp(struct lwp *, bool); 430 void npxsave_cpu(bool); 431 432 /* vm_machdep.c */ 433 paddr_t kvtop(void *); 434 435 #ifdef USER_LDT 436 /* sys_machdep.h */ 437 int x86_get_ldt(struct lwp *, void *, register_t *); 438 int x86_set_ldt(struct lwp *, void *, register_t *); 439 #endif 440 441 /* isa_machdep.c */ 442 void isa_defaultirq(void); 443 int isa_nmi(void); 444 445 #ifdef VM86 446 /* vm86.c */ 447 void vm86_gpfault(struct lwp *, int); 448 #endif /* VM86 */ 449 450 /* consinit.c */ 451 void kgdb_port_init(void); 452 453 /* bus_machdep.c */ 454 void x86_bus_space_init(void); 455 void x86_bus_space_mallocok(void); 456 457 #endif /* _KERNEL */ 458 459 #if defined(_KERNEL) || defined(_KMEMUSER) 460 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 461 #endif /* _KERNEL || __KMEMUSER */ 462 463 /* 464 * CTL_MACHDEP definitions. 465 */ 466 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 467 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 468 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 469 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 470 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 471 #define CPU_DISKINFO 6 /* struct disklist *: 472 * disk geometry information */ 473 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 474 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 475 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 476 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 477 #define CPU_TMLR_MODE 11 /* int: longrun mode 478 * 0: minimum frequency 479 * 1: economy 480 * 2: performance 481 * 3: maximum frequency 482 */ 483 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 484 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 485 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 486 #define CPU_MAXID 15 /* number of valid machdep ids */ 487 488 /* 489 * Structure for CPU_DISKINFO sysctl call. 490 * XXX this should be somewhere else. 491 */ 492 #define MAX_BIOSDISKS 16 493 494 struct disklist { 495 int dl_nbiosdisks; /* number of bios disks */ 496 struct biosdisk_info { 497 int bi_dev; /* BIOS device # (0x80 ..) */ 498 int bi_cyl; /* cylinders on disk */ 499 int bi_head; /* heads per track */ 500 int bi_sec; /* sectors per track */ 501 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 502 #define BIFLAG_INVALID 0x01 503 #define BIFLAG_EXTINT13 0x02 504 int bi_flags; 505 } dl_biosdisks[MAX_BIOSDISKS]; 506 507 int dl_nnativedisks; /* number of native disks */ 508 struct nativedisk_info { 509 char ni_devname[16]; /* native device name */ 510 int ni_nmatches; /* # of matches w/ BIOS */ 511 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 512 } dl_nativedisks[1]; /* actually longer */ 513 }; 514 #endif /* !_X86_CPU_H_ */ 515