xref: /minix/sys/arch/x86/include/i82489reg.h (revision 0a6a1f1d)
1 /*	$NetBSD: i82489reg.h,v 1.13 2015/07/17 05:16:09 msaitoh Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Frank van der Linden.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 
33 /*
34  * Registers and constants for the 82489DX and Pentium (and up) integrated
35  * "local" APIC.
36  */
37 
38 #define	LAPIC_ID		0x020	/* ID. RW */
39 #	define LAPIC_ID_MASK		0xff000000
40 #	define LAPIC_ID_SHIFT		24
41 
42 #define LAPIC_VERS		0x030	/* Version. R */
43 #	define LAPIC_VERSION_MASK	0x000000ff
44 #	define LAPIC_VERSION_LVT_MASK	0x00ff0000
45 #	define LAPIC_VERSION_LVT_SHIFT	16
46 
47 #define LAPIC_TPRI		0x080	/* Task Prio. RW */
48 #	define LAPIC_TPRI_MASK		0x000000ff
49 #	define LAPIC_TPRI_INT_MASK	0x000000f0
50 #	define LAPIC_TPRI_SUB_MASK	0x0000000f
51 
52 #define LAPIC_APRI		0x090	/* Arbitration prio R */
53 #	define LAPIC_APRI_MASK		0x000000ff
54 
55 #define LAPIC_PPRI		0x0a0	/* Processor prio. R */
56 #define LAPIC_EOI		0x0b0	/* End Int. W */
57 #define LAPIC_RRR		0x0c0	/* Remote read R */
58 #define LAPIC_LDR		0x0d0	/* Logical dest. RW */
59 
60 #define LAPIC_DFR		0x0e0	/* Dest. format RW */
61 #	define LAPIC_DFR_MASK		0xf0000000
62 #	define LAPIC_DFR_FLAT		0xf0000000
63 #	define LAPIC_DFR_CLUSTER	0x00000000
64 
65 #define LAPIC_SVR		0x0f0	/* Spurious intvec RW */
66 #	define LAPIC_SVR_VECTOR_MASK	0x000000ff
67 #	define LAPIC_SVR_VEC_FIX	0x0000000f
68 #	define LAPIC_SVR_VEC_PROG	0x000000f0
69 #	define LAPIC_SVR_ENABLE		0x00000100
70 #	define LAPIC_SVR_SWEN		0x00000100
71 #	define LAPIC_SVR_FOCUS		0x00000200
72 #	define LAPIC_SVR_FDIS		0x00000200
73 
74 #define LAPIC_ISR	0x100		/* In-Service Status */
75 #define LAPIC_TMR	0x180		/* Trigger Mode */
76 #define LAPIC_IRR	0x200		/* Interrupt Req */
77 #define LAPIC_ESR	0x280		/* Err status. R */
78 
79 #define LAPIC_ICRLO	0x300		/* Int. cmd. RW */
80 #	define LAPIC_DLMODE_MASK	0x00000700
81 #	define LAPIC_DLMODE_FIXED	0x00000000
82 #	define LAPIC_DLMODE_LOW		0x00000100
83 #	define LAPIC_DLMODE_SMI		0x00000200
84 #	define LAPIC_DLMODE_NMI		0x00000400
85 #	define LAPIC_DLMODE_INIT	0x00000500
86 #	define LAPIC_DLMODE_STARTUP	0x00000600
87 #	define LAPIC_DLMODE_EXTINT	0x00000700
88 
89 #	define LAPIC_DSTMODE_PHYS	0x00000000
90 #	define LAPIC_DSTMODE_LOG	0x00000800
91 
92 #	define LAPIC_DLSTAT_BUSY	0x00001000
93 #	define LAPIC_DLSTAT_IDLE	0x00000000
94 
95 #	define LAPIC_LEVEL_MASK		0x00004000
96 #	define LAPIC_LEVEL_ASSERT	0x00004000
97 #	define LAPIC_LEVEL_DEASSERT	0x00000000
98 
99 #	define LAPIC_TRIGGER_MASK	0x00008000
100 #	define LAPIC_TRIGGER_EDGE	0x00000000
101 #	define LAPIC_TRIGGER_LEVEL	0x00008000
102 
103 #	define LAPIC_DEST_MASK		0x000c0000
104 #	define LAPIC_DEST_DEFAULT	0x00000000
105 #	define LAPIC_DEST_SELF		0x00040000
106 #	define LAPIC_DEST_ALLINCL	0x00080000
107 #	define LAPIC_DEST_ALLEXCL	0x000c0000
108 
109 
110 #define LAPIC_ICRHI	0x310		/* Int. cmd. RW */
111 
112 #define LAPIC_LVTT	0x320		/* Loc.vec.(timer) RW */
113 #	define LAPIC_LVTT_VEC_MASK	0x000000ff
114 #	define LAPIC_LVTT_DS		0x00001000
115 #	define LAPIC_LVTT_M		0x00010000
116 #	define LAPIC_LVTT_TM		0x00020000
117 
118 #define LAPIC_TMINT	0x330		/* Loc.vec (Thermal) */
119 #define LAPIC_PCINT	0x340		/* Loc.vec (Perf Mon) */
120 #define LAPIC_LVINT0	0x350		/* Loc.vec (LINT0) RW */
121 #	define LAPIC_LVT_MASKED		0x00010000
122 #	define LAPIC_LVT_LEVTRIG	0x00008000
123 #	define LAPIC_LVT_REMOTE_IRR	0x00004000
124 #	define LAPIC_INP_POL		0x00002000
125 #	define LAPIC_PEND_SEND		0x00001000
126 
127 #define LAPIC_LVINT1	0x360		/* Loc.vec (LINT1) RW */
128 #define LAPIC_LVERR	0x370		/* Loc.vec (ERROR) RW */
129 #define LAPIC_ICR_TIMER	0x380		/* Initial count RW */
130 #define LAPIC_CCR_TIMER	0x390		/* Current count RO */
131 
132 #define LAPIC_DCR_TIMER	0x3e0		/* Divisor config register */
133 #	define LAPIC_DCRT_DIV1		0x0b
134 #	define LAPIC_DCRT_DIV2		0x00
135 #	define LAPIC_DCRT_DIV4		0x01
136 #	define LAPIC_DCRT_DIV8		0x02
137 #	define LAPIC_DCRT_DIV16		0x03
138 #	define LAPIC_DCRT_DIV32		0x08
139 #	define LAPIC_DCRT_DIV64		0x09
140 #	define LAPIC_DCRT_DIV128	0x0a
141 
142 #define LAPIC_MSIADDR_BASE		0xfee00000
143 #define	LAPIC_MSIADDR_DSTID_MASK	__BITS(19, 12)
144 #define	LAPIC_MSIADDR_RSVD0_MASK	__BITS(11, 4)
145 #define	LAPIC_MSIADDR_RH		__BIT(3)
146 #define	LAPIC_MSIADDR_DM		__BIT(2)
147 #define	LAPIC_MSIADDR_RSVD1_MASK	__BITS(1, 0)
148 
149 #define	LAPIC_MSIDATA_VECTOR_MASK	__BITS(7, 0)
150 #define	LAPIC_MSIDATA_DM_MASK		__BITS(10, 8)
151 #define	LAPIC_MSIDATA_DM_FIXED		__SHIFTIN(0, LAPIC_MSIDATA_DM_MASK)
152 #define	LAPIC_MSIDATA_DM_LOPRI		__SHIFTIN(1, LAPIC_MSIDATA_DM_MASK)
153 #define	LAPIC_MSIDATA_DM_SMI		__SHIFTIN(2, LAPIC_MSIDATA_DM_MASK)
154 #define	LAPIC_MSIDATA_DM_RSVD0		__SHIFTIN(3, LAPIC_MSIDATA_DM_MASK)
155 #define	LAPIC_MSIDATA_DM_NMI		__SHIFTIN(4, LAPIC_MSIDATA_DM_MASK)
156 #define	LAPIC_MSIDATA_DM_INIT		__SHIFTIN(5, LAPIC_MSIDATA_DM_MASK)
157 #define	LAPIC_MSIDATA_DM_RSVD1		__SHIFTIN(6, LAPIC_MSIDATA_DM_MASK)
158 #define	LAPIC_MSIDATA_DM_EXTINT		__SHIFTIN(7, LAPIC_MSIDATA_DM_MASK)
159 #define	LAPIC_MSIDATA_RSVD0_MASK	__BITS(13, 11)
160 #define	LAPIC_MSIDATA_LEVEL_MASK	__BIT(14)
161 #define	LAPIC_MSIDATA_LEVEL_DEASSERT	__SHIFTIN(0, LAPIC_MSIDATA_LEVEL_MASK)
162 #define	LAPIC_MSIDATA_LEVEL_ASSERT	__SHIFTIN(1, LAPIC_MSIDATA_LEVEL_MASK)
163 #define	LAPIC_MSIDATA_TRGMODE_MASK	__BIT(15)
164 #define	LAPIC_MSIDATA_TRGMODE_EDGE	__SHIFTIN(0,LAPIC_MSIDATA_TRGMODE_MASK)
165 #define	LAPIC_MSIDATA_TRGMODE_LEVEL	__SHIFTIN(1,LAPIC_MSIDATA_TRGMODE_MASK)
166 #define	LAPIC_MSIDATA_RSVD1_MASK	__BITS(31, 16)
167 
168 #define LAPIC_BASE		0xfee00000
169 
170 #define LAPIC_IRQ_MASK(i)	(1 << ((i) + 1))
171 
172 /* Extended APIC registers, valid when CPUID features4 EAPIC is present */
173 #define LEAPIC_FR	0x400	/* Feature register */
174 #	define LEAPIC_FR_ELC		__BITS(23,16) /* Ext. Lvt Count RO */
175 #	define LEAPIC_FR_EIDCAP		__BIT(2)     /* Ext. Apic ID Cap. RO */
176 #	define LEAPIC_FR_SEIOCAP	__BIT(1)     /* Specific EOI Cap. RO */
177 #	define LEAPIC_FR_IERCAP		__BIT(0)     /* Intr. Enable Reg. RO */
178 
179 #define LEAPIC_CR	0x410	/* Control Register */
180 #	define LEAPIC_CR_EID_ENABLE	__BIT(2)     /* Ext. Apic ID enable */
181 #	define LEAPIC_CR_SEOI_ENABLE	__BIT(1)     /* Specific EOI enable */
182 #	define LEAPIC_CR_IER_ENABLE	__BIT(0)     /* Enable writes to IER */
183 
184 #define LEAPIC_SEOIR	0x420	/* Specific EOI Register */
185 #	define LEAPIC_SEOI_VEC	__BITS(7,0)
186 
187 #define LEAPIC_IER_480	0x480	/* Interrupts 0-31 */
188 #define LEAPIC_IER_490	0x490	/* Interrupts 32-63 */
189 #define LEAPIC_IER_4B0	0x4B0	/* Interrupts 64-95 */
190 #define LEAPIC_IER_4C0	0x4C0	/* Interrupts 96-127 */
191 #define LEAPIC_IER_4D0	0x4D0	/* Interrupts 128-159 */
192 #define LEAPIC_IER_4E0	0x4E0	/* Interrupts 160-191 */
193 #define LEAPIC_IER_4F0	0x4F0	/* Interrupts 192-255 */
194 
195 /* Extended Local Vector Table Entries */
196 #define LEAPIC_LVTR_500	0x500
197 #define LEAPIC_LVTR_504	0x504
198 #define LEAPIC_LVTR_508	0x508
199 #define LEAPIC_LVTR_50C	0x50C
200 #define LEAPIC_LVTR_510	0x510
201 #define LEAPIC_LVTR_514	0x514
202 #define LEAPIC_LVTR_518	0x518
203 #define LEAPIC_LVTR_51C	0x51C
204 #define LEAPIC_LVTR_520	0x520
205 #define LEAPIC_LVTR_524	0x524
206 #define LEAPIC_LVTR_528	0x528
207 #define LEAPIC_LVTR_52C	0x52C
208 #define LEAPIC_LVTR_530	0x530
209 #	define LEAPIC_LVTR_MASK		__BIT(16)     /* interrupt masked RW */
210 #	define LEAPIC_LVTR_DSTAT	__BIT(12)	/* delivery state RO */
211 #	define LEAPIC_LVTR_MSGTYPE	__BITS(10,8)	/* Message type */
212 #	define LEAPIC_LVTR_VEC		__BITS(7,0)	/* the intr. vector */
213 
214 /*
215  * Model specific registers
216  */
217 
218 #define	LAPIC_MSR	0x001b
219 #	define	LAPIC_MSR_BSP		0x00000100	/* boot processor */
220 #	define	LAPIC_MSR_ENABLE_x2	0x00000400	/* x2APIC mode */
221 #	define	LAPIC_MSR_ENABLE	0x00000800	/* software enable */
222 #	define	LAPIC_MSR_ADDR		0xfffff000	/* physical address */
223 
224