1 /* $NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #if defined(__minix) && defined(_PCI_SERVER) 36 /* This is a quick hack, simple copy of the file, until we can use it as is. */ 37 #include <sys/types.h> 38 39 #include <stdint.h> 40 #include <stdbool.h> 41 #include <stdio.h> 42 43 #include <pci.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pci_verbose.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/pcidevs_data.h> 48 49 const char *pci_baseclass_name(pcireg_t reg); 50 const char *pci_subclass_name(pcireg_t reg); 51 #else 52 /* 53 * PCI autoconfiguration support functions. 54 * 55 * Note: This file is also built into a userland library (libpci). 56 * Pay attention to this when you make modifications. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $"); 61 62 #ifdef _KERNEL_OPT 63 #include "opt_pci.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #ifdef _KERNEL 69 #include <sys/systm.h> 70 #include <sys/intr.h> 71 #include <sys/module.h> 72 #else 73 #include <pci.h> 74 #include <stdbool.h> 75 #include <stdio.h> 76 #include <stdlib.h> 77 #include <string.h> 78 #endif 79 80 #include <dev/pci/pcireg.h> 81 #ifdef _KERNEL 82 #include <dev/pci/pcivar.h> 83 #else 84 #include <dev/pci/pci_verbose.h> 85 #include <dev/pci/pcidevs.h> 86 #include <dev/pci/pcidevs_data.h> 87 #endif 88 #endif /* defined(__minix) && defined(_PCI_SERVER) */ 89 90 /* 91 * Descriptions of known PCI classes and subclasses. 92 * 93 * Subclasses are described in the same way as classes, but have a 94 * NULL subclass pointer. 95 */ 96 struct pci_class { 97 const char *name; 98 u_int val; /* as wide as pci_{,sub}class_t */ 99 const struct pci_class *subclasses; 100 }; 101 102 /* 103 * Class 0x00. 104 * Before rev. 2.0. 105 */ 106 static const struct pci_class pci_subclass_prehistoric[] = { 107 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 108 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 109 { NULL, 0, NULL, }, 110 }; 111 112 /* 113 * Class 0x01. 114 * Mass storage controller 115 */ 116 117 /* ATA programming interface */ 118 static const struct pci_class pci_interface_ata[] = { 119 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 120 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 121 { NULL, 0, NULL, }, 122 }; 123 124 /* SATA programming interface */ 125 static const struct pci_class pci_interface_sata[] = { 126 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 127 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 128 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 129 { NULL, 0, NULL, }, 130 }; 131 132 /* Flash programming interface */ 133 static const struct pci_class pci_interface_nvm[] = { 134 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 135 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 136 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* Subclasses */ 141 static const struct pci_class pci_subclass_mass_storage[] = { 142 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 143 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 144 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 145 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 146 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 147 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 148 pci_interface_ata, }, 149 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 150 pci_interface_sata, }, 151 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 152 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 153 pci_interface_nvm, }, 154 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 155 { NULL, 0, NULL, }, 156 }; 157 158 /* 159 * Class 0x02. 160 * Network controller. 161 */ 162 static const struct pci_class pci_subclass_network[] = { 163 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 164 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 165 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 166 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 167 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 168 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 169 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 170 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 171 { NULL, 0, NULL, }, 172 }; 173 174 /* 175 * Class 0x03. 176 * Display controller. 177 */ 178 179 /* VGA programming interface */ 180 static const struct pci_class pci_interface_vga[] = { 181 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 182 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 183 { NULL, 0, NULL, }, 184 }; 185 /* Subclasses */ 186 static const struct pci_class pci_subclass_display[] = { 187 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 188 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 189 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 190 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 191 { NULL, 0, NULL, }, 192 }; 193 194 /* 195 * Class 0x04. 196 * Multimedia device. 197 */ 198 static const struct pci_class pci_subclass_multimedia[] = { 199 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 200 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 201 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 202 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 203 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 204 { NULL, 0, NULL, }, 205 }; 206 207 /* 208 * Class 0x05. 209 * Memory controller. 210 */ 211 static const struct pci_class pci_subclass_memory[] = { 212 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 213 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 214 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 215 { NULL, 0, NULL, }, 216 }; 217 218 /* 219 * Class 0x06. 220 * Bridge device. 221 */ 222 223 /* PCI bridge programming interface */ 224 static const struct pci_class pci_interface_pcibridge[] = { 225 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 226 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 /* Semi-transparent PCI-to-PCI bridge programming interface */ 231 static const struct pci_class pci_interface_stpci[] = { 232 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 233 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 234 { NULL, 0, NULL, }, 235 }; 236 237 /* Advanced Switching programming interface */ 238 static const struct pci_class pci_interface_advsw[] = { 239 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 240 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 241 { NULL, 0, NULL, }, 242 }; 243 244 /* Subclasses */ 245 static const struct pci_class pci_subclass_bridge[] = { 246 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 247 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 248 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 249 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 250 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 251 pci_interface_pcibridge, }, 252 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 253 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 254 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 255 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 256 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 257 pci_interface_stpci, }, 258 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 259 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 260 pci_interface_advsw, }, 261 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 262 { NULL, 0, NULL, }, 263 }; 264 265 /* 266 * Class 0x07. 267 * Simple communications controller. 268 */ 269 270 /* Serial controller programming interface */ 271 static const struct pci_class pci_interface_serial[] = { 272 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 273 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 274 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 275 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 276 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 277 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 278 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 279 { NULL, 0, NULL, }, 280 }; 281 282 /* Parallel controller programming interface */ 283 static const struct pci_class pci_interface_parallel[] = { 284 { "", PCI_INTERFACE_PARALLEL, NULL,}, 285 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 286 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 287 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 288 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 289 { NULL, 0, NULL,}, 290 }; 291 292 /* Modem programming interface */ 293 static const struct pci_class pci_interface_modem[] = { 294 { "", PCI_INTERFACE_MODEM, NULL,}, 295 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 296 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 297 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 298 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 299 { NULL, 0, NULL,}, 300 }; 301 302 /* Subclasses */ 303 static const struct pci_class pci_subclass_communications[] = { 304 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 305 pci_interface_serial, }, 306 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 307 pci_interface_parallel, }, 308 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 309 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 310 pci_interface_modem, }, 311 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 312 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 313 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 314 { NULL, 0, NULL,}, 315 }; 316 317 /* 318 * Class 0x08. 319 * Base system peripheral. 320 */ 321 322 /* PIC programming interface */ 323 static const struct pci_class pci_interface_pic[] = { 324 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 325 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 326 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 327 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 328 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 329 { NULL, 0, NULL, }, 330 }; 331 332 /* DMA programming interface */ 333 static const struct pci_class pci_interface_dma[] = { 334 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 335 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 336 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 337 { NULL, 0, NULL, }, 338 }; 339 340 /* Timer programming interface */ 341 static const struct pci_class pci_interface_tmr[] = { 342 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 343 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 344 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 345 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 346 { NULL, 0, NULL, }, 347 }; 348 349 /* RTC programming interface */ 350 static const struct pci_class pci_interface_rtc[] = { 351 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 352 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 353 { NULL, 0, NULL, }, 354 }; 355 356 /* Subclasses */ 357 static const struct pci_class pci_subclass_system[] = { 358 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 359 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 360 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 361 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 362 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 363 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 364 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 365 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 366 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 367 { NULL, 0, NULL, }, 368 }; 369 370 /* 371 * Class 0x09. 372 * Input device. 373 */ 374 375 /* Gameport programming interface */ 376 static const struct pci_class pci_interface_game[] = { 377 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 378 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 379 { NULL, 0, NULL, }, 380 }; 381 382 /* Subclasses */ 383 static const struct pci_class pci_subclass_input[] = { 384 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 385 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 386 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 387 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 388 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 389 pci_interface_game, }, 390 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 391 { NULL, 0, NULL, }, 392 }; 393 394 /* 395 * Class 0x0a. 396 * Docking station. 397 */ 398 static const struct pci_class pci_subclass_dock[] = { 399 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 400 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 401 { NULL, 0, NULL, }, 402 }; 403 404 /* 405 * Class 0x0b. 406 * Processor. 407 */ 408 static const struct pci_class pci_subclass_processor[] = { 409 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 410 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 411 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 412 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 413 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 414 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 415 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 416 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 417 { NULL, 0, NULL, }, 418 }; 419 420 /* 421 * Class 0x0c. 422 * Serial bus controller. 423 */ 424 425 /* IEEE1394 programming interface */ 426 static const struct pci_class pci_interface_ieee1394[] = { 427 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 428 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 429 { NULL, 0, NULL,}, 430 }; 431 432 /* USB programming interface */ 433 static const struct pci_class pci_interface_usb[] = { 434 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 435 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 436 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 437 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 438 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 439 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 440 { NULL, 0, NULL, }, 441 }; 442 443 /* IPMI programming interface */ 444 static const struct pci_class pci_interface_ipmi[] = { 445 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 446 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 447 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 448 { NULL, 0, NULL,}, 449 }; 450 451 /* Subclasses */ 452 static const struct pci_class pci_subclass_serialbus[] = { 453 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 454 pci_interface_ieee1394, }, 455 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 456 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 457 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 458 pci_interface_usb, }, 459 /* XXX Fiber Channel/_FIBRECHANNEL */ 460 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 461 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 462 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 463 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 464 pci_interface_ipmi, }, 465 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 466 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 467 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 468 { NULL, 0, NULL, }, 469 }; 470 471 /* 472 * Class 0x0d. 473 * Wireless Controller. 474 */ 475 static const struct pci_class pci_subclass_wireless[] = { 476 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 477 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 478 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 479 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 480 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 481 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 482 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 483 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 484 { NULL, 0, NULL, }, 485 }; 486 487 /* 488 * Class 0x0e. 489 * Intelligent IO controller. 490 */ 491 492 /* Intelligent IO programming interface */ 493 static const struct pci_class pci_interface_i2o[] = { 494 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 495 { NULL, 0, NULL,}, 496 }; 497 498 /* Subclasses */ 499 static const struct pci_class pci_subclass_i2o[] = { 500 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 501 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 502 { NULL, 0, NULL, }, 503 }; 504 505 /* 506 * Class 0x0f. 507 * Satellite communication controller. 508 */ 509 static const struct pci_class pci_subclass_satcom[] = { 510 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 511 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 512 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 513 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 514 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 515 { NULL, 0, NULL, }, 516 }; 517 518 /* 519 * Class 0x10. 520 * Encryption/Decryption controller. 521 */ 522 static const struct pci_class pci_subclass_crypto[] = { 523 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 524 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 525 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 526 { NULL, 0, NULL, }, 527 }; 528 529 /* 530 * Class 0x11. 531 * Data aquuisition and signal processing controller. 532 */ 533 static const struct pci_class pci_subclass_dasp[] = { 534 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 535 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 536 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 537 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 538 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 539 { NULL, 0, NULL, }, 540 }; 541 542 /* List of classes */ 543 static const struct pci_class pci_class[] = { 544 { "prehistoric", PCI_CLASS_PREHISTORIC, 545 pci_subclass_prehistoric, }, 546 { "mass storage", PCI_CLASS_MASS_STORAGE, 547 pci_subclass_mass_storage, }, 548 { "network", PCI_CLASS_NETWORK, 549 pci_subclass_network, }, 550 { "display", PCI_CLASS_DISPLAY, 551 pci_subclass_display, }, 552 { "multimedia", PCI_CLASS_MULTIMEDIA, 553 pci_subclass_multimedia, }, 554 { "memory", PCI_CLASS_MEMORY, 555 pci_subclass_memory, }, 556 { "bridge", PCI_CLASS_BRIDGE, 557 pci_subclass_bridge, }, 558 { "communications", PCI_CLASS_COMMUNICATIONS, 559 pci_subclass_communications, }, 560 { "system", PCI_CLASS_SYSTEM, 561 pci_subclass_system, }, 562 { "input", PCI_CLASS_INPUT, 563 pci_subclass_input, }, 564 { "dock", PCI_CLASS_DOCK, 565 pci_subclass_dock, }, 566 { "processor", PCI_CLASS_PROCESSOR, 567 pci_subclass_processor, }, 568 { "serial bus", PCI_CLASS_SERIALBUS, 569 pci_subclass_serialbus, }, 570 { "wireless", PCI_CLASS_WIRELESS, 571 pci_subclass_wireless, }, 572 { "I2O", PCI_CLASS_I2O, 573 pci_subclass_i2o, }, 574 { "satellite comm", PCI_CLASS_SATCOM, 575 pci_subclass_satcom, }, 576 { "crypto", PCI_CLASS_CRYPTO, 577 pci_subclass_crypto, }, 578 { "DASP", PCI_CLASS_DASP, 579 pci_subclass_dasp, }, 580 { "undefined", PCI_CLASS_UNDEFINED, 581 NULL, }, 582 { NULL, 0, 583 NULL, }, 584 }; 585 586 #if defined(__minix) && defined(_PCI_SERVER) 587 const char * 588 pci_baseclass_name(pcireg_t reg) 589 { 590 const struct pci_class *classp = pci_class; 591 592 while (classp->name != NULL) { 593 if (PCI_CLASS(reg) == classp->val) 594 break; 595 classp++; 596 } 597 598 return classp->name; 599 } 600 601 const char * 602 pci_subclass_name(pcireg_t reg) 603 { 604 const struct pci_class *classp = pci_class; 605 const struct pci_class *subclassp; 606 607 while (classp->name != NULL) { 608 if (PCI_CLASS(reg) == classp->val) 609 break; 610 classp++; 611 } 612 613 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 614 while (subclassp && subclassp->name != NULL) { 615 if (PCI_SUBCLASS(reg) == subclassp->val) 616 break; 617 subclassp++; 618 } 619 620 return subclassp->name; 621 } 622 #endif /* defined(__minix) && defined(_PCI_SERVER) */ 623 624 DEV_VERBOSE_DEFINE(pci); 625 626 #if defined(__minix) && !defined(_PCI_SERVER) 627 628 void 629 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 630 size_t l) 631 { 632 pci_class_t pciclass; 633 pci_subclass_t subclass; 634 pci_interface_t interface; 635 pci_revision_t revision; 636 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 637 const struct pci_class *classp, *subclassp, *interfacep; 638 char *ep; 639 640 ep = cp + l; 641 642 pciclass = PCI_CLASS(class_reg); 643 subclass = PCI_SUBCLASS(class_reg); 644 interface = PCI_INTERFACE(class_reg); 645 revision = PCI_REVISION(class_reg); 646 647 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 648 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 649 PCI_PRODUCT(id_reg)); 650 651 classp = pci_class; 652 while (classp->name != NULL) { 653 if (pciclass == classp->val) 654 break; 655 classp++; 656 } 657 658 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 659 while (subclassp && subclassp->name != NULL) { 660 if (subclass == subclassp->val) 661 break; 662 subclassp++; 663 } 664 665 interfacep = (subclassp && subclassp->name != NULL) ? 666 subclassp->subclasses : NULL; 667 while (interfacep && interfacep->name != NULL) { 668 if (interface == interfacep->val) 669 break; 670 interfacep++; 671 } 672 673 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 674 if (showclass) { 675 cp += snprintf(cp, ep - cp, " ("); 676 if (classp->name == NULL) 677 cp += snprintf(cp, ep - cp, 678 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 679 else { 680 if (subclassp == NULL || subclassp->name == NULL) 681 cp += snprintf(cp, ep - cp, 682 "%s, subclass 0x%02x", 683 classp->name, subclass); 684 else 685 cp += snprintf(cp, ep - cp, "%s %s", 686 subclassp->name, classp->name); 687 } 688 if ((interfacep == NULL) || (interfacep->name == NULL)) { 689 if (interface != 0) 690 cp += snprintf(cp, ep - cp, 691 ", interface 0x%02x", interface); 692 } else if (strncmp(interfacep->name, "", 1) != 0) 693 cp += snprintf(cp, ep - cp, ", %s", 694 interfacep->name); 695 if (revision != 0) 696 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 697 revision); 698 cp += snprintf(cp, ep - cp, ")"); 699 } 700 } 701 702 #ifdef _KERNEL 703 void 704 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 705 const char *known, int addrev) 706 { 707 char devinfo[256]; 708 709 if (known) { 710 aprint_normal(": %s", known); 711 if (addrev) 712 aprint_normal(" (rev. 0x%02x)", 713 PCI_REVISION(pa->pa_class)); 714 aprint_normal("\n"); 715 } else { 716 pci_devinfo(pa->pa_id, pa->pa_class, 0, 717 devinfo, sizeof(devinfo)); 718 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 719 PCI_REVISION(pa->pa_class)); 720 } 721 if (naive) 722 aprint_naive(": %s\n", naive); 723 else 724 aprint_naive("\n"); 725 } 726 #endif 727 728 /* 729 * Print out most of the PCI configuration registers. Typically used 730 * in a device attach routine like this: 731 * 732 * #ifdef MYDEV_DEBUG 733 * printf("%s: ", device_xname(sc->sc_dev)); 734 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 735 * #endif 736 */ 737 738 #define i2o(i) ((i) * 4) 739 #define o2i(o) ((o) / 4) 740 #define onoff2(str, rval, bit, onstr, offstr) \ 741 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 742 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 743 744 static void 745 pci_conf_print_common( 746 #ifdef _KERNEL 747 pci_chipset_tag_t pc, pcitag_t tag, 748 #endif 749 const pcireg_t *regs) 750 { 751 const char *name; 752 const struct pci_class *classp, *subclassp; 753 char vendor[PCI_VENDORSTR_LEN]; 754 char product[PCI_PRODUCTSTR_LEN]; 755 pcireg_t rval; 756 unsigned int num; 757 758 rval = regs[o2i(PCI_ID_REG)]; 759 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 760 if (name) 761 printf(" Vendor Name: %s (0x%04x)\n", name, 762 PCI_VENDOR(rval)); 763 else 764 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 765 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 766 PCI_PRODUCT(rval)); 767 if (name) 768 printf(" Device Name: %s (0x%04x)\n", name, 769 PCI_PRODUCT(rval)); 770 else 771 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 772 773 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 774 775 printf(" Command register: 0x%04x\n", rval & 0xffff); 776 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 777 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 778 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 779 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 780 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 781 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 782 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 783 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 784 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 785 onoff("Fast back-to-back transactions", rval, 786 PCI_COMMAND_BACKTOBACK_ENABLE); 787 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 788 789 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 790 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 791 "inactive"); 792 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 793 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 794 onoff("User Definable Features (UDF) support", rval, 795 PCI_STATUS_UDF_SUPPORT); 796 onoff("Fast back-to-back capable", rval, 797 PCI_STATUS_BACKTOBACK_SUPPORT); 798 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 799 800 printf(" DEVSEL timing: "); 801 switch (rval & PCI_STATUS_DEVSEL_MASK) { 802 case PCI_STATUS_DEVSEL_FAST: 803 printf("fast"); 804 break; 805 case PCI_STATUS_DEVSEL_MEDIUM: 806 printf("medium"); 807 break; 808 case PCI_STATUS_DEVSEL_SLOW: 809 printf("slow"); 810 break; 811 default: 812 printf("unknown/reserved"); /* XXX */ 813 break; 814 } 815 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 816 817 onoff("Slave signaled Target Abort", rval, 818 PCI_STATUS_TARGET_TARGET_ABORT); 819 onoff("Master received Target Abort", rval, 820 PCI_STATUS_MASTER_TARGET_ABORT); 821 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 822 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 823 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 824 825 rval = regs[o2i(PCI_CLASS_REG)]; 826 for (classp = pci_class; classp->name != NULL; classp++) { 827 if (PCI_CLASS(rval) == classp->val) 828 break; 829 } 830 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 831 while (subclassp && subclassp->name != NULL) { 832 if (PCI_SUBCLASS(rval) == subclassp->val) 833 break; 834 subclassp++; 835 } 836 if (classp->name != NULL) { 837 printf(" Class Name: %s (0x%02x)\n", classp->name, 838 PCI_CLASS(rval)); 839 if (subclassp != NULL && subclassp->name != NULL) 840 printf(" Subclass Name: %s (0x%02x)\n", 841 subclassp->name, PCI_SUBCLASS(rval)); 842 else 843 printf(" Subclass ID: 0x%02x\n", 844 PCI_SUBCLASS(rval)); 845 } else { 846 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 847 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 848 } 849 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 850 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 851 852 rval = regs[o2i(PCI_BHLC_REG)]; 853 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 854 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 855 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 856 PCI_HDRTYPE(rval)); 857 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 858 num = PCI_CACHELINE(rval); 859 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 860 } 861 862 static int 863 pci_conf_print_bar( 864 #ifdef _KERNEL 865 pci_chipset_tag_t pc, pcitag_t tag, 866 #endif 867 const pcireg_t *regs, int reg, const char *name 868 #ifdef _KERNEL 869 , int sizebar 870 #endif 871 ) 872 { 873 int width; 874 pcireg_t rval, rval64h; 875 #ifdef _KERNEL 876 int s; 877 pcireg_t mask, mask64h; 878 #endif 879 880 width = 4; 881 882 /* 883 * Section 6.2.5.1, `Address Maps', tells us that: 884 * 885 * 1) The builtin software should have already mapped the 886 * device in a reasonable way. 887 * 888 * 2) A device which wants 2^n bytes of memory will hardwire 889 * the bottom n bits of the address to 0. As recommended, 890 * we write all 1s and see what we get back. 891 */ 892 893 rval = regs[o2i(reg)]; 894 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 895 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 896 rval64h = regs[o2i(reg + 4)]; 897 width = 8; 898 } else 899 rval64h = 0; 900 901 #ifdef _KERNEL 902 /* XXX don't size unknown memory type? */ 903 if (rval != 0 && sizebar) { 904 /* 905 * The following sequence seems to make some devices 906 * (e.g. host bus bridges, which don't normally 907 * have their space mapped) very unhappy, to 908 * the point of crashing the system. 909 * 910 * Therefore, if the mapping register is zero to 911 * start out with, don't bother trying. 912 */ 913 s = splhigh(); 914 pci_conf_write(pc, tag, reg, 0xffffffff); 915 mask = pci_conf_read(pc, tag, reg); 916 pci_conf_write(pc, tag, reg, rval); 917 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 918 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 919 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 920 mask64h = pci_conf_read(pc, tag, reg + 4); 921 pci_conf_write(pc, tag, reg + 4, rval64h); 922 } else 923 mask64h = 0; 924 splx(s); 925 } else 926 mask = mask64h = 0; 927 #endif /* _KERNEL */ 928 929 printf(" Base address register at 0x%02x", reg); 930 if (name) 931 printf(" (%s)", name); 932 printf("\n "); 933 if (rval == 0) { 934 printf("not implemented(?)\n"); 935 return width; 936 } 937 printf("type: "); 938 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 939 const char *type, *prefetch; 940 941 switch (PCI_MAPREG_MEM_TYPE(rval)) { 942 case PCI_MAPREG_MEM_TYPE_32BIT: 943 type = "32-bit"; 944 break; 945 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 946 type = "32-bit-1M"; 947 break; 948 case PCI_MAPREG_MEM_TYPE_64BIT: 949 type = "64-bit"; 950 break; 951 default: 952 type = "unknown (XXX)"; 953 break; 954 } 955 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 956 prefetch = ""; 957 else 958 prefetch = "non"; 959 printf("%s %sprefetchable memory\n", type, prefetch); 960 switch (PCI_MAPREG_MEM_TYPE(rval)) { 961 case PCI_MAPREG_MEM_TYPE_64BIT: 962 printf(" base: 0x%016llx, ", 963 PCI_MAPREG_MEM64_ADDR( 964 ((((long long) rval64h) << 32) | rval))); 965 #ifdef _KERNEL 966 if (sizebar) 967 printf("size: 0x%016llx", 968 PCI_MAPREG_MEM64_SIZE( 969 ((((long long) mask64h) << 32) | mask))); 970 else 971 #endif /* _KERNEL */ 972 printf("not sized"); 973 printf("\n"); 974 break; 975 case PCI_MAPREG_MEM_TYPE_32BIT: 976 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 977 default: 978 printf(" base: 0x%08x, ", 979 PCI_MAPREG_MEM_ADDR(rval)); 980 #ifdef _KERNEL 981 if (sizebar) 982 printf("size: 0x%08x", 983 PCI_MAPREG_MEM_SIZE(mask)); 984 else 985 #endif /* _KERNEL */ 986 printf("not sized"); 987 printf("\n"); 988 break; 989 } 990 } else { 991 #ifdef _KERNEL 992 if (sizebar) 993 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 994 #endif /* _KERNEL */ 995 printf("i/o\n"); 996 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 997 #ifdef _KERNEL 998 if (sizebar) 999 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 1000 else 1001 #endif /* _KERNEL */ 1002 printf("not sized"); 1003 printf("\n"); 1004 } 1005 1006 return width; 1007 } 1008 1009 static void 1010 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1011 { 1012 int off, needaddr, neednl; 1013 1014 needaddr = 1; 1015 neednl = 0; 1016 for (off = first; off < pastlast; off += 4) { 1017 if ((off % 16) == 0 || needaddr) { 1018 printf(" 0x%02x:", off); 1019 needaddr = 0; 1020 } 1021 printf(" 0x%08x", regs[o2i(off)]); 1022 neednl = 1; 1023 if ((off % 16) == 12) { 1024 printf("\n"); 1025 neednl = 0; 1026 } 1027 } 1028 if (neednl) 1029 printf("\n"); 1030 } 1031 1032 static void 1033 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1034 { 1035 pcireg_t rval; 1036 1037 printf("\n AGP Capabilities Register\n"); 1038 1039 rval = regs[o2i(capoff)]; 1040 printf(" Revision: %d.%d\n", 1041 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1042 1043 /* XXX need more */ 1044 } 1045 1046 static const char * 1047 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1048 { 1049 1050 switch ((caps >> 6) & 7) { 1051 case 0: return "self-powered"; 1052 case 1: return "55 mA"; 1053 case 2: return "100 mA"; 1054 case 3: return "160 mA"; 1055 case 4: return "220 mA"; 1056 case 5: return "270 mA"; 1057 case 6: return "320 mA"; 1058 case 7: 1059 default: return "375 mA"; 1060 } 1061 } 1062 1063 static const char * 1064 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1065 { 1066 static const char unk[] = "unknown"; 1067 static const char *pmrev[8] = { 1068 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1069 }; 1070 if (val > 7) 1071 return unk; 1072 return pmrev[val]; 1073 } 1074 1075 static void 1076 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1077 { 1078 uint16_t caps, pmcsr; 1079 pcireg_t reg; 1080 1081 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1082 reg = regs[o2i(capoff + PCI_PMCSR)]; 1083 pmcsr = reg & 0xffff; 1084 1085 printf("\n PCI Power Management Capabilities Register\n"); 1086 1087 printf(" Capabilities register: 0x%04x\n", caps); 1088 printf(" Version: %s\n", 1089 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1090 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1091 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1092 printf(" 3.3V auxiliary current: %s\n", 1093 pci_conf_print_pcipm_cap_aux(caps)); 1094 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1095 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1096 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1097 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1098 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1099 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1100 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1101 1102 printf(" Control/status register: 0x%04x\n", pmcsr); 1103 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1104 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1105 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1106 printf(" PME# assertion: %sabled\n", 1107 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1108 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1109 printf(" Bridge Support Extensions register: 0x%02x\n", 1110 (reg >> 16) & 0xff); 1111 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1112 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1113 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1114 1115 } 1116 1117 /* XXX pci_conf_print_vpd_cap */ 1118 /* XXX pci_conf_print_slotid_cap */ 1119 1120 static void 1121 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1122 { 1123 uint32_t ctl, mmc, mme; 1124 1125 regs += o2i(capoff); 1126 ctl = *regs++; 1127 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1128 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1129 1130 printf("\n PCI Message Signaled Interrupt\n"); 1131 1132 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1133 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1134 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1135 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1136 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1137 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1138 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1139 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1140 printf(" Message Address %sregister: 0x%08x\n", 1141 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1142 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1143 printf(" Message Address %sregister: 0x%08x\n", 1144 "(upper) ", *regs++); 1145 } 1146 printf(" Message Data register: 0x%08x\n", *regs++); 1147 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1148 printf(" Vector Mask register: 0x%08x\n", *regs++); 1149 printf(" Vector Pending register: 0x%08x\n", *regs++); 1150 } 1151 } 1152 1153 /* XXX pci_conf_print_cpci_hostwap_cap */ 1154 1155 /* 1156 * For both command register and status register. 1157 * The argument "idx" is index number (0 to 7). 1158 */ 1159 static int 1160 pcix_split_trans(unsigned int idx) 1161 { 1162 static int table[8] = { 1163 1, 2, 3, 4, 8, 12, 16, 32 1164 }; 1165 1166 if (idx >= __arraycount(table)) 1167 return -1; 1168 return table[idx]; 1169 } 1170 1171 static void 1172 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1173 { 1174 pcireg_t reg; 1175 int isbridge; 1176 int i; 1177 1178 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1179 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1180 printf("\n PCI-X %s Capabilities Register\n", 1181 isbridge ? "Bridge" : "Non-bridge"); 1182 1183 reg = regs[o2i(capoff)]; 1184 if (isbridge != 0) { 1185 printf(" Secondary status register: 0x%04x\n", 1186 (reg & 0xffff0000) >> 16); 1187 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1188 onoff("133MHz capable", reg, PCIX_STATUS_133); 1189 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1190 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1191 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1192 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1193 printf(" Secondary clock frequency: 0x%x\n", 1194 (reg & PCIX_BRIDGE_2NDST_CLKF) 1195 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1196 printf(" Version: 0x%x\n", 1197 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1198 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1199 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1200 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1201 } else { 1202 printf(" Command register: 0x%04x\n", 1203 (reg & 0xffff0000) >> 16); 1204 onoff("Data Parity Error Recovery", reg, 1205 PCIX_CMD_PERR_RECOVER); 1206 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1207 printf(" Maximum Burst Read Count: %u\n", 1208 PCIX_CMD_BYTECNT(reg)); 1209 printf(" Maximum Split Transactions: %d\n", 1210 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1211 >> PCIX_CMD_SPLTRANS_SHIFT)); 1212 } 1213 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1214 printf(" %sStatus register: 0x%08x\n", 1215 isbridge ? "Bridge " : "", reg); 1216 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1217 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1218 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1219 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1220 onoff("133MHz capable", reg, PCIX_STATUS_133); 1221 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1222 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1223 if (isbridge != 0) { 1224 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1225 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1226 } else { 1227 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1228 "bridge device", "simple device"); 1229 printf(" Designed max memory read byte count: %d\n", 1230 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1231 >> PCIX_STATUS_MAXB_SHIFT)); 1232 printf(" Designed max outstanding split transaction: %d\n", 1233 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1234 >> PCIX_STATUS_MAXST_SHIFT)); 1235 printf(" MAX cumulative Read Size: %u\n", 1236 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1237 onoff("Received split completion error", reg, 1238 PCIX_STATUS_SCERR); 1239 } 1240 onoff("266MHz capable", reg, PCIX_STATUS_266); 1241 onoff("533MHz capable", reg, PCIX_STATUS_533); 1242 1243 if (isbridge == 0) 1244 return; 1245 1246 /* Only for bridge */ 1247 for (i = 0; i < 2; i++) { 1248 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1249 printf(" %s split transaction control register: 0x%08x\n", 1250 (i == 0) ? "Upstream" : "Downstream", reg); 1251 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1252 printf(" Commitment Limit: %d\n", 1253 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1254 } 1255 } 1256 1257 /* XXX pci_conf_print_ldt_cap */ 1258 1259 static void 1260 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1261 { 1262 uint16_t caps; 1263 1264 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1265 1266 printf("\n PCI Vendor Specific Capabilities Register\n"); 1267 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1268 } 1269 1270 static void 1271 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1272 { 1273 pcireg_t val; 1274 1275 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1276 1277 printf("\n Debugport Capability Register\n"); 1278 printf(" Debug base Register: 0x%04x\n", 1279 val >> PCI_DEBUG_BASER_SHIFT); 1280 printf(" port offset: 0x%04x\n", 1281 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1282 printf(" BAR number: %u\n", 1283 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1284 } 1285 1286 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1287 /* XXX pci_conf_print_hotplug_cap */ 1288 1289 static void 1290 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1291 { 1292 pcireg_t reg; 1293 1294 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1295 1296 printf("\n Subsystem ID Capability Register\n"); 1297 printf(" Subsystem ID : 0x%08x\n", reg); 1298 } 1299 1300 /* XXX pci_conf_print_agp8_cap */ 1301 /* XXX pci_conf_print_secure_cap */ 1302 1303 static void 1304 pci_print_pcie_L0s_latency(uint32_t val) 1305 { 1306 1307 switch (val) { 1308 case 0x0: 1309 printf("Less than 64ns\n"); 1310 break; 1311 case 0x1: 1312 case 0x2: 1313 case 0x3: 1314 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1315 break; 1316 case 0x4: 1317 printf("512ns to less than 1us\n"); 1318 break; 1319 case 0x5: 1320 printf("1us to less than 2us\n"); 1321 break; 1322 case 0x6: 1323 printf("2us - 4us\n"); 1324 break; 1325 case 0x7: 1326 printf("More than 4us\n"); 1327 break; 1328 } 1329 } 1330 1331 static void 1332 pci_print_pcie_L1_latency(uint32_t val) 1333 { 1334 1335 switch (val) { 1336 case 0x0: 1337 printf("Less than 1us\n"); 1338 break; 1339 case 0x6: 1340 printf("32us - 64us\n"); 1341 break; 1342 case 0x7: 1343 printf("More than 64us\n"); 1344 break; 1345 default: 1346 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1347 break; 1348 } 1349 } 1350 1351 static void 1352 pci_print_pcie_compl_timeout(uint32_t val) 1353 { 1354 1355 switch (val) { 1356 case 0x0: 1357 printf("50us to 50ms\n"); 1358 break; 1359 case 0x5: 1360 printf("16ms to 55ms\n"); 1361 break; 1362 case 0x6: 1363 printf("65ms to 210ms\n"); 1364 break; 1365 case 0x9: 1366 printf("260ms to 900ms\n"); 1367 break; 1368 case 0xa: 1369 printf("1s to 3.5s\n"); 1370 break; 1371 default: 1372 printf("unknown %u value\n", val); 1373 break; 1374 } 1375 } 1376 1377 static void 1378 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1379 { 1380 pcireg_t reg; /* for each register */ 1381 pcireg_t val; /* for each bitfield */ 1382 bool check_link = false; 1383 bool check_slot = false; 1384 bool check_rootport = false; 1385 unsigned int pciever; 1386 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1387 int i; 1388 1389 printf("\n PCI Express Capabilities Register\n"); 1390 /* Capability Register */ 1391 reg = regs[o2i(capoff)]; 1392 printf(" Capability register: %04x\n", reg >> 16); 1393 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1394 printf(" Capability version: %u\n", pciever); 1395 printf(" Device type: "); 1396 switch ((reg & 0x00f00000) >> 20) { 1397 case 0x0: 1398 printf("PCI Express Endpoint device\n"); 1399 check_link = true; 1400 break; 1401 case 0x1: 1402 printf("Legacy PCI Express Endpoint device\n"); 1403 check_link = true; 1404 break; 1405 case 0x4: 1406 printf("Root Port of PCI Express Root Complex\n"); 1407 check_link = true; 1408 check_slot = true; 1409 check_rootport = true; 1410 break; 1411 case 0x5: 1412 printf("Upstream Port of PCI Express Switch\n"); 1413 break; 1414 case 0x6: 1415 printf("Downstream Port of PCI Express Switch\n"); 1416 check_slot = true; 1417 check_rootport = true; 1418 break; 1419 case 0x7: 1420 printf("PCI Express to PCI/PCI-X Bridge\n"); 1421 break; 1422 case 0x8: 1423 printf("PCI/PCI-X to PCI Express Bridge\n"); 1424 break; 1425 case 0x9: 1426 printf("Root Complex Integrated Endpoint\n"); 1427 break; 1428 case 0xa: 1429 check_rootport = true; 1430 printf("Root Complex Event Collector\n"); 1431 break; 1432 default: 1433 printf("unknown\n"); 1434 break; 1435 } 1436 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1437 printf(" Interrupt Message Number: %x\n", 1438 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1439 1440 /* Device Capability Register */ 1441 reg = regs[o2i(capoff + PCIE_DCAP)]; 1442 printf(" Device Capabilities Register: 0x%08x\n", reg); 1443 printf(" Max Payload Size Supported: %u bytes max\n", 1444 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1445 printf(" Phantom Functions Supported: "); 1446 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1447 case 0x0: 1448 printf("not available\n"); 1449 break; 1450 case 0x1: 1451 printf("MSB\n"); 1452 break; 1453 case 0x2: 1454 printf("two MSB\n"); 1455 break; 1456 case 0x3: 1457 printf("All three bits\n"); 1458 break; 1459 } 1460 printf(" Extended Tag Field Supported: %dbit\n", 1461 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1462 printf(" Endpoint L0 Acceptable Latency: "); 1463 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1464 printf(" Endpoint L1 Acceptable Latency: "); 1465 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1466 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1467 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1468 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1469 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1470 printf(" Captured Slot Power Limit Value: %d\n", 1471 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1472 printf(" Captured Slot Power Limit Scale: %d\n", 1473 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1474 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1475 1476 /* Device Control Register */ 1477 reg = regs[o2i(capoff + PCIE_DCSR)]; 1478 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1479 onoff("Correctable Error Reporting Enable", reg, 1480 PCIE_DCSR_ENA_COR_ERR); 1481 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1482 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1483 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1484 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1485 printf(" Max Payload Size: %d byte\n", 1486 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1487 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1488 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1489 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1490 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1491 printf(" Max Read Request Size: %d byte\n", 1492 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1493 1494 /* Device Status Register */ 1495 reg = regs[o2i(capoff + PCIE_DCSR)]; 1496 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1497 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1498 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1499 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1500 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1501 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1502 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1503 1504 if (check_link) { 1505 /* Link Capability Register */ 1506 reg = regs[o2i(capoff + PCIE_LCAP)]; 1507 printf(" Link Capabilities Register: 0x%08x\n", reg); 1508 printf(" Maximum Link Speed: "); 1509 val = reg & PCIE_LCAP_MAX_SPEED; 1510 if (val < 1 || val > 3) { 1511 printf("unknown %u value\n", val); 1512 } else { 1513 printf("%sGT/s\n", linkspeeds[val - 1]); 1514 } 1515 printf(" Maximum Link Width: x%u lanes\n", 1516 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1517 printf(" Active State PM Support: "); 1518 val = (reg & PCIE_LCAP_ASPM) >> 10; 1519 switch (val) { 1520 case 0x1: 1521 printf("L0s Entry supported\n"); 1522 break; 1523 case 0x3: 1524 printf("L0s and L1 supported\n"); 1525 break; 1526 default: 1527 printf("Reserved value\n"); 1528 break; 1529 } 1530 printf(" L0 Exit Latency: "); 1531 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1532 printf(" L1 Exit Latency: "); 1533 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1534 printf(" Port Number: %u\n", reg >> 24); 1535 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1536 onoff("Surprise Down Error Report", reg, 1537 PCIE_LCAP_SURPRISE_DOWN); 1538 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1539 onoff("Link BW Notification Capable", reg, 1540 PCIE_LCAP_LINK_BW_NOTIFY); 1541 onoff("ASPM Optionally Compliance", reg, 1542 PCIE_LCAP_ASPM_COMPLIANCE); 1543 1544 /* Link Control Register */ 1545 reg = regs[o2i(capoff + PCIE_LCSR)]; 1546 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1547 printf(" Active State PM Control: "); 1548 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1549 switch (val) { 1550 case 0: 1551 printf("disabled\n"); 1552 break; 1553 case 1: 1554 printf("L0s Entry Enabled\n"); 1555 break; 1556 case 2: 1557 printf("L1 Entry Enabled\n"); 1558 break; 1559 case 3: 1560 printf("L0s and L1 Entry Enabled\n"); 1561 break; 1562 } 1563 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1564 "128bytes", "64bytes"); 1565 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1566 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1567 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1568 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1569 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1570 onoff("Hardware Autonomous Width Disable", reg, 1571 PCIE_LCSR_HAWD); 1572 onoff("Link Bandwidth Management Interrupt Enable", reg, 1573 PCIE_LCSR_LBMIE); 1574 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1575 PCIE_LCSR_LABIE); 1576 1577 /* Link Status Register */ 1578 reg = regs[o2i(capoff + PCIE_LCSR)]; 1579 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1580 printf(" Negotiated Link Speed: "); 1581 if (((reg >> 16) & 0x000f) < 1 || 1582 ((reg >> 16) & 0x000f) > 3) { 1583 printf("unknown %u value\n", 1584 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1585 } else { 1586 printf("%sGT/s\n", 1587 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1588 } 1589 printf(" Negotiated Link Width: x%u lanes\n", 1590 (reg >> 20) & 0x003f); 1591 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1592 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1593 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1594 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1595 onoff("Link Bandwidth Management Status", reg, 1596 PCIE_LCSR_LINK_BW_MGMT); 1597 onoff("Link Autonomous Bandwidth Status", reg, 1598 PCIE_LCSR_LINK_AUTO_BW); 1599 } 1600 1601 if (check_slot == true) { 1602 /* Slot Capability Register */ 1603 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1604 printf(" Slot Capability Register: %08x\n", reg); 1605 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1606 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1607 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1608 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1609 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1610 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1611 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1612 printf(" Slot Power Limit Value: %d\n", 1613 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1614 printf(" Slot Power Limit Scale: %d\n", 1615 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1616 onoff("Electromechanical Interlock Present", reg, 1617 PCIE_SLCAP_EIP); 1618 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1619 printf(" Physical Slot Number: %d\n", 1620 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1621 1622 /* Slot Control Register */ 1623 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1624 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1625 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1626 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1627 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1628 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1629 onoff("Command Completed Interrupt Enabled", reg, 1630 PCIE_SLCSR_CCE); 1631 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1632 printf(" Attention Indicator Control: "); 1633 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1634 case 0x0: 1635 printf("reserved\n"); 1636 break; 1637 case 0x1: 1638 printf("on\n"); 1639 break; 1640 case 0x2: 1641 printf("blink\n"); 1642 break; 1643 case 0x3: 1644 printf("off\n"); 1645 break; 1646 } 1647 printf(" Power Indicator Control: "); 1648 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1649 case 0x0: 1650 printf("reserved\n"); 1651 break; 1652 case 0x1: 1653 printf("on\n"); 1654 break; 1655 case 0x2: 1656 printf("blink\n"); 1657 break; 1658 case 0x3: 1659 printf("off\n"); 1660 break; 1661 } 1662 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1663 onoff("Electromechanical Interlock Control", 1664 reg, PCIE_SLCSR_EIC); 1665 onoff("Data Link Layer State Changed Enable", reg, 1666 PCIE_SLCSR_DLLSCE); 1667 1668 /* Slot Status Register */ 1669 printf(" Slot Status Register: %04x\n", reg >> 16); 1670 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1671 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1672 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1673 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1674 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1675 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1676 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1677 onoff("Electromechanical Interlock engaged", reg, 1678 PCIE_SLCSR_EIS); 1679 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1680 } 1681 1682 if (check_rootport == true) { 1683 /* Root Control Register */ 1684 reg = regs[o2i(capoff + PCIE_RCR)]; 1685 printf(" Root Control Register: %04x\n", reg & 0xffff); 1686 onoff("SERR on Correctable Error Enable", reg, 1687 PCIE_RCR_SERR_CER); 1688 onoff("SERR on Non-Fatal Error Enable", reg, 1689 PCIE_RCR_SERR_NFER); 1690 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1691 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1692 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1693 1694 /* Root Capability Register */ 1695 printf(" Root Capability Register: %04x\n", 1696 reg >> 16); 1697 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1698 1699 /* Root Status Register */ 1700 reg = regs[o2i(capoff + PCIE_RSR)]; 1701 printf(" Root Status Register: %08x\n", reg); 1702 printf(" PME Requester ID: %04x\n", 1703 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1704 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1705 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1706 } 1707 1708 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1709 if (pciever < 2) 1710 return; 1711 1712 /* Device Capabilities 2 */ 1713 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1714 printf(" Device Capabilities 2: 0x%08x\n", reg); 1715 printf(" Completion Timeout Ranges Supported: %u \n", 1716 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1717 onoff("Completion Timeout Disable Supported", reg, 1718 PCIE_DCAP2_COMPT_DIS); 1719 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1720 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1721 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1722 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1723 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1724 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1725 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1726 printf(" TPH Completer Supported: %u\n", 1727 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1728 printf(" OBFF Supported: "); 1729 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1730 case 0x0: 1731 printf("Not supported\n"); 1732 break; 1733 case 0x1: 1734 printf("Message only\n"); 1735 break; 1736 case 0x2: 1737 printf("WAKE# only\n"); 1738 break; 1739 case 0x3: 1740 printf("Both\n"); 1741 break; 1742 } 1743 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1744 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1745 printf(" Max End-End TLP Prefixes: %u\n", 1746 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1747 1748 /* Device Control 2 */ 1749 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1750 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1751 printf(" Completion Timeout Value: "); 1752 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1753 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1754 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1755 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1756 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1757 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1758 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1759 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1760 printf(" OBFF: "); 1761 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1762 case 0x0: 1763 printf("Disabled\n"); 1764 break; 1765 case 0x1: 1766 printf("Enabled with Message Signaling Variation A\n"); 1767 break; 1768 case 0x2: 1769 printf("Enabled with Message Signaling Variation B\n"); 1770 break; 1771 case 0x3: 1772 printf("Enabled using WAKE# signaling\n"); 1773 break; 1774 } 1775 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1776 1777 if (check_link) { 1778 /* Link Capability 2 */ 1779 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1780 printf(" Link Capabilities 2: 0x%08x\n", reg); 1781 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1782 printf(" Supported Link Speed Vector:"); 1783 for (i = 0; i <= 2; i++) { 1784 if (((val >> i) & 0x01) != 0) 1785 printf(" %sGT/s", linkspeeds[i]); 1786 } 1787 printf("\n"); 1788 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1789 1790 /* Link Control 2 */ 1791 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1792 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1793 printf(" Target Link Speed: "); 1794 val = reg & PCIE_LCSR2_TGT_LSPEED; 1795 if (val < 1 || val > 3) 1796 printf("unknown %u value\n", val); 1797 else 1798 printf("%sGT/s\n", linkspeeds[val - 1]); 1799 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1800 onoff("HW Autonomous Speed Disabled", reg, 1801 PCIE_LCSR2_HW_AS_DIS); 1802 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1803 printf(" Transmit Margin: %u\n", 1804 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1805 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1806 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1807 printf(" Compliance Present/De-emphasis: %u\n", 1808 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1809 1810 /* Link Status 2 */ 1811 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1812 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1813 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1814 onoff("Equalization Phase 1 Successful", reg, 1815 PCIE_LCSR2_EQP1_SUC); 1816 onoff("Equalization Phase 2 Successful", reg, 1817 PCIE_LCSR2_EQP2_SUC); 1818 onoff("Equalization Phase 3 Successful", reg, 1819 PCIE_LCSR2_EQP3_SUC); 1820 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1821 } 1822 1823 /* Slot Capability 2 */ 1824 /* Slot Control 2 */ 1825 /* Slot Status 2 */ 1826 } 1827 1828 static void 1829 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1830 { 1831 pcireg_t reg; 1832 1833 printf("\n MSI-X Capability Register\n"); 1834 1835 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1836 printf(" Message Control register: 0x%04x\n", 1837 (reg >> 16) & 0xff); 1838 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1839 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1840 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1841 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1842 printf(" Table offset register: 0x%08x\n", reg); 1843 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1844 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1845 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1846 printf(" Pending bit array register: 0x%08x\n", reg); 1847 printf(" Pending bit array offset: %08x\n", 1848 reg & PCI_MSIX_PBAOFFSET_MASK); 1849 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1850 } 1851 1852 /* XXX pci_conf_print_sata_cap */ 1853 static void 1854 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1855 { 1856 pcireg_t reg; 1857 1858 printf("\n Advanced Features Capability Register\n"); 1859 1860 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1861 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1862 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1863 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1864 reg = regs[o2i(capoff + PCI_AFCSR)]; 1865 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1866 /* 1867 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1868 * and it's always 0 on read 1869 */ 1870 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1871 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1872 } 1873 1874 static struct { 1875 pcireg_t cap; 1876 const char *name; 1877 void (*printfunc)(const pcireg_t *, int); 1878 } pci_captab[] = { 1879 { PCI_CAP_RESERVED0, "reserved", NULL }, 1880 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 1881 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 1882 { PCI_CAP_VPD, "VPD", NULL }, 1883 { PCI_CAP_SLOTID, "SlotID", NULL }, 1884 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 1885 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 1886 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 1887 { PCI_CAP_LDT, "HyperTransport", NULL }, 1888 { PCI_CAP_VENDSPEC, "Vendor-specific", 1889 pci_conf_print_vendspec_cap }, 1890 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 1891 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 1892 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 1893 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 1894 pci_conf_print_subsystem_cap }, 1895 { PCI_CAP_AGP8, "AGP 8x", NULL }, 1896 { PCI_CAP_SECURE, "Secure Device", NULL }, 1897 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 1898 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 1899 { PCI_CAP_SATA, "SATA", NULL }, 1900 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap } 1901 }; 1902 1903 static int 1904 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 1905 int *offsetp) 1906 { 1907 pcireg_t rval; 1908 int off; 1909 1910 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1911 off != 0; 1912 off = PCI_CAPLIST_NEXT(rval)) { 1913 rval = regs[o2i(off)]; 1914 if (capid == PCI_CAPLIST_CAP(rval)) { 1915 if (offsetp != NULL) 1916 *offsetp = off; 1917 return 1; 1918 } 1919 } 1920 return 0; 1921 } 1922 1923 static void 1924 pci_conf_print_caplist( 1925 #ifdef _KERNEL 1926 pci_chipset_tag_t pc, pcitag_t tag, 1927 #endif 1928 const pcireg_t *regs, int capoff) 1929 { 1930 int off; 1931 pcireg_t foundcap; 1932 pcireg_t rval; 1933 bool foundtable[__arraycount(pci_captab)]; 1934 unsigned int i; 1935 1936 /* Clear table */ 1937 for (i = 0; i < __arraycount(pci_captab); i++) 1938 foundtable[i] = false; 1939 1940 /* Print capability register's offset and the type first */ 1941 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1942 off != 0; 1943 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1944 rval = regs[o2i(off)]; 1945 printf(" Capability register at 0x%02x\n", off); 1946 1947 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1948 foundcap = PCI_CAPLIST_CAP(rval); 1949 if (foundcap < __arraycount(pci_captab)) { 1950 printf("%s)\n", pci_captab[foundcap].name); 1951 /* Mark as found */ 1952 foundtable[foundcap] = true; 1953 } else 1954 printf("unknown)\n"); 1955 } 1956 1957 /* 1958 * And then, print the detail of each capability registers 1959 * in capability value's order. 1960 */ 1961 for (i = 0; i < __arraycount(pci_captab); i++) { 1962 if (foundtable[i] == false) 1963 continue; 1964 1965 /* 1966 * The type was found. Search capability list again and 1967 * print all capabilities that the capabiliy type is 1968 * the same. This is required because some capabilities 1969 * appear multiple times (e.g. HyperTransport capability). 1970 */ 1971 if (pci_conf_find_cap(regs, capoff, i, &off)) { 1972 rval = regs[o2i(off)]; 1973 if (pci_captab[i].printfunc != NULL) 1974 pci_captab[i].printfunc(regs, off); 1975 } 1976 } 1977 } 1978 1979 /* Extended Capability */ 1980 1981 static void 1982 pci_conf_print_aer_cap_uc(pcireg_t reg) 1983 { 1984 1985 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 1986 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 1987 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 1988 onoff("Poisoned TLP", reg, PCI_AER_UC_POISONED_TLP); 1989 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 1990 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 1991 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 1992 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 1993 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 1994 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 1995 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 1996 onoff("Unsupported Request Error", reg, 1997 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 1998 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 1999 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2000 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2001 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2002 onoff("TLP Prefix Blocked Error", reg, 2003 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2004 } 2005 2006 static void 2007 pci_conf_print_aer_cap_cor(pcireg_t reg) 2008 { 2009 2010 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2011 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2012 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2013 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2014 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2015 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2016 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2017 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2018 } 2019 2020 static void 2021 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2022 { 2023 2024 printf(" First Error Pointer: 0x%04x\n", 2025 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2026 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2027 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2028 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2029 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2030 onoff("Multiple Header Recording Capable", reg, 2031 PCI_AER_MULT_HDR_CAPABLE); 2032 onoff("Multiple Header Recording Enable", reg, PCI_AER_MULT_HDR_ENABLE); 2033 2034 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2035 if (!tlp_prefix_log) 2036 return; 2037 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2038 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2039 } 2040 2041 static void 2042 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2043 { 2044 2045 onoff("Correctable Error Reporting Enable", reg, 2046 PCI_AER_ROOTERR_COR_ENABLE); 2047 onoff("Non-Fatal Error Reporting Enable", reg, 2048 PCI_AER_ROOTERR_NF_ENABLE); 2049 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2050 } 2051 2052 static void 2053 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2054 { 2055 2056 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2057 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2058 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2059 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2060 PCI_AER_ROOTERR_MULTI_UC_ERR); 2061 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2062 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2063 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2064 printf(" Advanced Error Interrupt Message Number: 0x%u\n", 2065 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2066 } 2067 2068 static void 2069 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2070 { 2071 2072 printf(" Correctable Source ID: 0x%04x\n", 2073 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2074 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2075 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2076 } 2077 2078 static void 2079 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2080 { 2081 pcireg_t reg; 2082 int pcie_capoff; 2083 int pcie_devtype = -1; 2084 bool tlp_prefix_log = false; 2085 2086 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2087 reg = regs[o2i(pcie_capoff)]; 2088 pcie_devtype = reg & PCIE_XCAP_TYPE_MASK; 2089 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2090 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2091 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2092 /* End-End TLP Prefix Supported */ 2093 if (reg & PCIE_DCAP2_EETLP_PREF) { 2094 tlp_prefix_log = true; 2095 } 2096 } 2097 } 2098 2099 printf("\n Advanced Error Reporting Register\n"); 2100 2101 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2102 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2103 pci_conf_print_aer_cap_uc(reg); 2104 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2105 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2106 pci_conf_print_aer_cap_uc(reg); 2107 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2108 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2109 pci_conf_print_aer_cap_uc(reg); 2110 2111 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2112 printf(" Correctable Error Status register: 0x%08x\n", reg); 2113 pci_conf_print_aer_cap_cor(reg); 2114 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2115 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2116 pci_conf_print_aer_cap_cor(reg); 2117 2118 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2119 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2120 reg); 2121 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2122 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2123 printf(" Header Log register:\n"); 2124 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2125 extcapoff + PCI_AER_ROOTERR_CMD); 2126 2127 switch (pcie_devtype) { 2128 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2129 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2130 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2131 printf(" Root Error Command register: 0x%08x\n", reg); 2132 pci_conf_print_aer_cap_rooterr_cmd(reg); 2133 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2134 printf(" Root Error Status register: 0x%08x\n", reg); 2135 pci_conf_print_aer_cap_rooterr_status(reg); 2136 2137 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2138 printf(" Error Source Identification: 0x%04x\n", reg); 2139 pci_conf_print_aer_cap_errsrc_id(reg); 2140 break; 2141 } 2142 2143 if (tlp_prefix_log) { 2144 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2145 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2146 } 2147 } 2148 2149 static void 2150 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2151 pcireg_t parbsel, int parbsize) 2152 { 2153 pcireg_t reg; 2154 int num = 16 << parbsel; 2155 int num_per_reg = sizeof(pcireg_t) / parbsize; 2156 int i, j; 2157 2158 /* First, dump the table */ 2159 for (i = 0; i < num; i += num_per_reg) { 2160 reg = regs[o2i(off + i / num_per_reg)]; 2161 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2162 } 2163 /* And then, decode each entry */ 2164 for (i = 0; i < num; i += num_per_reg) { 2165 reg = regs[o2i(off + i / num_per_reg)]; 2166 for (j = 0; j < num_per_reg; j++) 2167 printf(" Phase[%d]: %d\n", j, reg); 2168 } 2169 } 2170 2171 static void 2172 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2173 { 2174 pcireg_t reg, n; 2175 int parbtab, parbsize; 2176 pcireg_t parbsel; 2177 int varbtab, varbsize; 2178 pcireg_t varbsel; 2179 int i, count; 2180 2181 printf("\n Virtual Channel Register\n"); 2182 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2183 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2184 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2185 printf(" Extended VC Count: %d\n", count); 2186 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2187 printf(" Low Priority Extended VC Count: %u\n", n); 2188 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2189 printf(" Reference Clock: %s\n", 2190 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100" : "unknown"); 2191 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2192 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2193 2194 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2195 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2196 onoff("Hardware fixed arbitration scheme", 2197 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2198 onoff("WRR arbitration with 32 phases", 2199 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2200 onoff("WRR arbitration with 64 phases", 2201 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2202 onoff("WRR arbitration with 128 phases", 2203 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2204 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2205 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2206 2207 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2208 printf(" Port VC Control register: 0x%04x\n", reg); 2209 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2210 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2211 2212 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2213 printf(" Port VC Status register: 0x%04x\n", reg); 2214 onoff("VC Arbitration Table Status", 2215 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2216 2217 for (i = 0; i < count + 1; i++) { 2218 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2219 printf(" VC number %d\n", i); 2220 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2221 onoff(" Non-configurable Hardware fixed arbitration scheme", 2222 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2223 onoff(" WRR arbitration with 32 phases", 2224 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2225 onoff(" WRR arbitration with 64 phases", 2226 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2227 onoff(" WRR arbitration with 128 phases", 2228 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2229 onoff(" Time-based WRR arbitration with 128 phases", 2230 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2231 onoff(" WRR arbitration with 256 phases", 2232 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2233 onoff(" Advanced Packet Switching", 2234 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2235 onoff(" Reject Snoop Transaction", 2236 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2237 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2238 printf(" Maximum Time Slots: %d\n", n); 2239 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2240 printf(" Port Arbitration Table offset: 0x%02x\n", 2241 parbtab); 2242 2243 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2244 printf(" VC Resource Control Register: 0x%08x\n", reg); 2245 printf(" TC/VC Map: %02x\n", 2246 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2247 /* 2248 * The load Port Arbitration Table bit is used to update 2249 * the Port Arbitration logic and it's always 0 on read, so 2250 * we don't print it. 2251 */ 2252 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2253 printf(" Port Arbitration Select: %x\n", parbsel); 2254 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2255 printf(" VC ID %d\n", n); 2256 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2257 2258 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2259 printf(" VC Resource Status Register: 0x%08x\n", reg); 2260 onoff(" Port Arbitration Table Status", 2261 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2262 onoff(" VC Negotiation Pending", 2263 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2264 2265 if ((parbtab != 0) && (parbsel != 0)) 2266 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2267 "Port", parbsel, parbsize); 2268 } 2269 2270 varbsize = 8; 2271 if ((varbtab != 0) && (varbsel != 0)) 2272 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2273 " VC", varbsel, varbsize); 2274 } 2275 2276 static const char * 2277 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2278 { 2279 2280 switch (reg) { 2281 case 0xf0: 2282 return "250W"; 2283 case 0xf1: 2284 return "275W"; 2285 case 0xf2: 2286 return "300W"; 2287 default: 2288 return "Unknown"; 2289 } 2290 } 2291 2292 static const char * 2293 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2294 { 2295 2296 switch (reg) { 2297 case 0x00: 2298 return "1.0x"; 2299 case 0x01: 2300 return "0.1x"; 2301 case 0x02: 2302 return "0.01x"; 2303 case 0x03: 2304 return "0.001x"; 2305 default: 2306 return "wrong value!"; 2307 } 2308 } 2309 2310 static const char * 2311 pci_conf_print_pwrbdgt_type(uint8_t reg) 2312 { 2313 2314 switch (reg) { 2315 case 0x00: 2316 return "PME Aux"; 2317 case 0x01: 2318 return "Auxilary"; 2319 case 0x02: 2320 return "Idle"; 2321 case 0x03: 2322 return "Sustained"; 2323 case 0x07: 2324 return "Maximun"; 2325 default: 2326 return "Unknown"; 2327 } 2328 } 2329 2330 static const char * 2331 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2332 { 2333 2334 switch (reg) { 2335 case 0x00: 2336 return "Power(12V)"; 2337 case 0x01: 2338 return "Power(3.3V)"; 2339 case 0x02: 2340 return "Power(1.5V or 1.8V)"; 2341 case 0x07: 2342 return "Thermal"; 2343 default: 2344 return "Unknown"; 2345 } 2346 } 2347 2348 static void 2349 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2350 { 2351 pcireg_t reg; 2352 2353 printf("\n Power Budget Register\n"); 2354 2355 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2356 printf(" Data Select register: 0x%08x\n", reg); 2357 2358 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2359 printf(" Data register: 0x%08x\n", reg); 2360 printf(" Base Power: %s\n", 2361 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2362 printf(" Data Scale: %s\n", 2363 pci_conf_print_pwrbdgt_data_scale( 2364 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2365 printf(" PM Sub State: 0x%hhx\n", 2366 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2367 printf(" PM State: D%u\n", 2368 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2369 printf(" Type: %s\n", 2370 pci_conf_print_pwrbdgt_type( 2371 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2372 printf(" Power Rail: %s\n", 2373 pci_conf_print_pwrbdgt_pwrrail( 2374 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2375 2376 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2377 printf(" Power Budget Capability register: 0x%08x\n", reg); 2378 onoff("System Allocated", 2379 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2380 } 2381 2382 static const char * 2383 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2384 { 2385 2386 switch (type) { 2387 case 0x00: 2388 return "Configuration Space Element"; 2389 case 0x01: 2390 return "System Egress Port or internal sink (memory)"; 2391 case 0x02: 2392 return "Internal Root Complex Link"; 2393 default: 2394 return "Unknown"; 2395 } 2396 } 2397 2398 static void 2399 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2400 { 2401 pcireg_t reg; 2402 unsigned char nent, linktype; 2403 int i; 2404 2405 printf("\n Root Complex Link Declaration\n"); 2406 2407 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2408 printf(" Element Self Description Register: 0x%08x\n", reg); 2409 printf(" Element Type: %s\n", 2410 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2411 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2412 printf(" Number of Link Entries: %hhu\n", nent); 2413 printf(" Component ID: %hhu\n", 2414 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2415 printf(" Port Number: %hhu\n", 2416 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2417 for (i = 0; i < nent; i++) { 2418 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2419 printf(" Link Description Register: 0x%08x\n", reg); 2420 onoff("Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2421 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2422 onoff2("Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2423 "Configuration Space", "Memory-Mapped Space"); 2424 onoff("Associated RCRB Header", reg, 2425 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2426 printf(" Target Component ID: %hhu\n", 2427 (unsigned char)__SHIFTOUT(reg, 2428 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2429 printf(" Target Port Number: %hhu\n", 2430 (unsigned char)__SHIFTOUT(reg, 2431 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2432 2433 if (linktype == 0) { 2434 /* Memory-Mapped Space */ 2435 reg = regs[o2i(extcapoff 2436 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2437 printf(" Link Address Low Register: 0x%08x\n", reg); 2438 reg = regs[o2i(extcapoff 2439 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2440 printf(" Link Address High Register: 0x%08x\n",reg); 2441 } else { 2442 unsigned int nb; 2443 pcireg_t lo, hi; 2444 2445 /* Configuration Space */ 2446 lo = regs[o2i(extcapoff 2447 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2448 printf(" Configuration Space Low Register: 0x%08x" 2449 "\n", lo); 2450 hi = regs[o2i(extcapoff 2451 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2452 printf(" Configuration Space High Register: 0x%08x" 2453 "\n", hi); 2454 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2455 printf(" N: %u\n", nb); 2456 printf(" Func: %hhu\n", 2457 (unsigned char)__SHIFTOUT(lo, 2458 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2459 printf(" Dev: %hhu\n", 2460 (unsigned char)__SHIFTOUT(lo, 2461 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2462 printf(" Bus: %hhu\n", 2463 (unsigned char)__SHIFTOUT(lo, 2464 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2465 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2466 printf(" Configuration Space Base Address: 0x%016" 2467 PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2468 } 2469 } 2470 } 2471 2472 /* XXX pci_conf_print_rclink_ctl_cap */ 2473 2474 static void 2475 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2476 { 2477 pcireg_t reg; 2478 2479 printf("\n Root Complex Event Collector Association\n"); 2480 2481 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2482 printf(" Association Bitmap for Root Complex Integrated Devices:" 2483 " 0x%08x\n", reg); 2484 } 2485 2486 /* XXX pci_conf_print_mfvc_cap */ 2487 /* XXX pci_conf_print_vc2_cap */ 2488 /* XXX pci_conf_print_rcrb_cap */ 2489 /* XXX pci_conf_print_vendor_cap */ 2490 /* XXX pci_conf_print_cac_cap */ 2491 2492 static void 2493 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2494 { 2495 pcireg_t reg, cap, ctl; 2496 unsigned int size, i; 2497 2498 printf("\n Access Control Services\n"); 2499 2500 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2501 cap = reg & 0xffff; 2502 ctl = reg >> 16; 2503 printf(" ACS Capability register: 0x%08x\n", cap); 2504 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2505 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2506 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2507 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2508 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2509 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2510 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2511 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2512 if (size == 0) 2513 size = 256; 2514 printf(" Egress Control Vector Size: %u\n", size); 2515 printf(" ACS Control register: 0x%08x\n", ctl); 2516 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2517 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2518 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2519 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2520 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2521 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2522 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2523 2524 /* 2525 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2526 * Control vector. 2527 */ 2528 if ((cap & PCI_ACS_CAP_E) == 0) 2529 return; 2530 for (i = 0; i < size; i += 32) 2531 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31, 2532 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2533 } 2534 2535 static void 2536 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2537 { 2538 pcireg_t reg, cap, ctl; 2539 2540 printf("\n Alternative Routing-ID Interpretation Register\n"); 2541 2542 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2543 cap = reg & 0xffff; 2544 ctl = reg >> 16; 2545 printf(" Capability register: 0x%08x\n", cap); 2546 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2547 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2548 printf(" Next Function Number: %u\n", 2549 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2550 printf(" Control register: 0x%08x\n", ctl); 2551 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2552 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2553 printf(" Function Group: %u\n", 2554 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2555 } 2556 2557 static void 2558 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2559 { 2560 pcireg_t reg, cap, ctl; 2561 unsigned int num; 2562 2563 printf("\n Address Translation Services\n"); 2564 2565 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2566 cap = reg & 0xffff; 2567 ctl = reg >> 16; 2568 printf(" Capability register: 0x%04x\n", cap); 2569 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2570 if (num == 0) 2571 num = 32; 2572 printf(" Invalidate Queue Depth: %u\n", num); 2573 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2574 2575 printf(" Control register: 0x%04x\n", ctl); 2576 printf(" Smallest Translation Unit: %u\n", 2577 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2578 onoff("Enable", reg, PCI_ATS_CTL_EN); 2579 } 2580 2581 static void 2582 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2583 { 2584 pcireg_t lo, hi; 2585 2586 printf("\n Device Serial Number Register\n"); 2587 2588 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2589 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2590 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2591 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2592 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2593 } 2594 2595 static void 2596 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2597 { 2598 char buf[sizeof("99999 MB")]; 2599 pcireg_t reg; 2600 pcireg_t total_vfs; 2601 int i; 2602 bool first; 2603 2604 printf("\n Single Root IO Virtualization Register\n"); 2605 2606 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2607 printf(" Capabilities register: 0x%08x\n", reg); 2608 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2609 onoff("ARI Capable Hierarchy Preserved", reg, 2610 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2611 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2612 printf(" VF Migration Interrupt Message Number: 0x%u\n", 2613 (pcireg_t)__SHIFTOUT(reg, 2614 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2615 } 2616 2617 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2618 printf(" Control register: 0x%04x\n", reg); 2619 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2620 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2621 onoff("VF Migration Interrupt Enable", reg, 2622 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2623 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2624 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2625 2626 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2627 printf(" Status register: 0x%04x\n", reg); 2628 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2629 2630 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2631 printf(" InitialVFs register: 0x%04x\n", reg); 2632 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2633 printf(" TotalVFs register: 0x%04x\n", reg); 2634 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2635 printf(" NumVFs register: 0x%04x\n", reg); 2636 2637 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2638 printf(" Function Dependency Link register: 0x%04x\n", reg); 2639 2640 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2641 printf(" First VF Offset register: 0x%04x\n", reg); 2642 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2643 printf(" VF Stride register: 0x%04x\n", reg); 2644 2645 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2646 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2647 printf(" Supported Page Size:"); 2648 for (i = 0, first = true; i < 32; i++) { 2649 if (reg & __BIT(i)) { 2650 #ifdef _KERNEL 2651 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2652 #else 2653 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2654 HN_AUTOSCALE, 0); 2655 #endif 2656 printf("%s %s", first ? "" : ",", buf); 2657 first = false; 2658 } 2659 } 2660 printf("\n"); 2661 2662 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2663 printf(" System Page Sizes register: 0x%08x\n", reg); 2664 printf(" Page Size: "); 2665 if (reg != 0) { 2666 #ifdef _KERNEL 2667 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2668 #else 2669 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2670 HN_AUTOSCALE, 0); 2671 #endif 2672 printf("%s", buf); 2673 } else { 2674 printf("unknown"); 2675 } 2676 printf("\n"); 2677 2678 for (i = 0; i < 6; i++) { 2679 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 2680 printf(" VF BAR%d register: 0x%08x\n", i, reg); 2681 } 2682 2683 if (total_vfs > 0) { 2684 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 2685 printf(" VF Migration State Array Offset register: 0x%08x\n", 2686 reg); 2687 printf(" VF Migration State Offset: 0x%08x\n", 2688 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 2689 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 2690 printf(" VF Migration State BIR: "); 2691 if (i >= 0 && i <= 5) { 2692 printf("BAR%d", i); 2693 } else { 2694 printf("unknown BAR (%d)", i); 2695 } 2696 printf("\n"); 2697 } 2698 } 2699 2700 /* XXX pci_conf_print_mriov_cap */ 2701 /* XXX pci_conf_print_multicast_cap */ 2702 2703 static void 2704 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2705 { 2706 pcireg_t reg, ctl, sta; 2707 2708 printf("\n Page Request\n"); 2709 2710 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 2711 ctl = reg & 0xffff; 2712 sta = reg >> 16; 2713 printf(" Control Register: 0x%04x\n", ctl); 2714 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 2715 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 2716 2717 printf(" Status Register: 0x%04x\n", sta); 2718 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 2719 onoff("Unexpected Page Request Group Index", reg, 2720 PCI_PAGE_REQ_STA_UPRGI); 2721 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 2722 2723 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 2724 printf(" Outstanding Page Request Capacity: %u\n", reg); 2725 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 2726 printf(" Outstanding Page Request Allocation: %u\n", reg); 2727 } 2728 2729 /* XXX pci_conf_print_amd_cap */ 2730 /* XXX pci_conf_print_resize_bar_cap */ 2731 /* XXX pci_conf_print_dpa_cap */ 2732 2733 static const char * 2734 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 2735 { 2736 2737 switch (val) { 2738 case 0x0: 2739 return "Not Present"; 2740 case 0x1: 2741 return "in the TPH Requester Capability Structure"; 2742 case 0x2: 2743 return "in the MSI-X Table"; 2744 default: 2745 return "Unknown"; 2746 } 2747 } 2748 2749 static void 2750 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2751 { 2752 pcireg_t reg; 2753 int size, i, j; 2754 2755 printf("\n TPH Requester Extended Capability\n"); 2756 2757 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 2758 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 2759 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 2760 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 2761 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 2762 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 2763 printf(" ST Table Location: %s\n", 2764 pci_conf_print_tph_req_cap_sttabloc( 2765 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 2766 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 2767 printf(" ST Table Size: %d\n", size); 2768 for (i = 0; i < size ; i += 2) { 2769 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 2770 for (j = 0; j < 2 ; j++) { 2771 uint32_t entry = reg; 2772 2773 if (j != 0) 2774 entry >>= 16; 2775 entry &= 0xffff; 2776 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 2777 i + j, entry); 2778 } 2779 } 2780 } 2781 2782 static void 2783 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 2784 { 2785 pcireg_t reg; 2786 2787 printf("\n Latency Tolerance Reporting\n"); 2788 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 2789 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 2790 printf(" Max Snoop LatencyValue: %u\n", 2791 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 2792 printf(" Max Snoop LatencyScale: %uns\n", 2793 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 2794 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 2795 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 2796 printf(" Max No-Snoop LatencyValue: %u\n", 2797 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 2798 printf(" Max No-Snoop LatencyScale: %uns\n", 2799 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 2800 } 2801 2802 static void 2803 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 2804 { 2805 int pcie_capoff; 2806 pcireg_t reg; 2807 int i, maxlinkwidth; 2808 2809 printf("\n Secondary PCI Express Register\n"); 2810 2811 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 2812 printf(" Link Control 3 register: 0x%08x\n", reg); 2813 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 2814 onoff("Link Equalization Request Interrupt Enable", 2815 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 2816 2817 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 2818 printf(" Lane Error Status register: 0x%08x\n", reg); 2819 2820 /* Get Max Link Width */ 2821 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 2822 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 2823 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 2824 } else { 2825 printf("error: falied to get PCIe capablity\n"); 2826 return; 2827 } 2828 for (i = 0; i < maxlinkwidth; i++) { 2829 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 2830 if (i % 2 != 0) 2831 reg >>= 16; 2832 else 2833 reg &= 0xffff; 2834 printf(" Equalization Control Register (Link %d): %04x\n", 2835 i, reg); 2836 printf(" Downstream Port Transmit Preset: 0x%x\n", 2837 (pcireg_t)__SHIFTOUT(reg, 2838 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 2839 printf(" Downstream Port Receive Hint: 0x%x\n", 2840 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 2841 printf(" Upstream Port Transmit Preset: 0x%x\n", 2842 (pcireg_t)__SHIFTOUT(reg, 2843 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 2844 printf(" Upstream Port Receive Hint: 0x%x\n", 2845 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 2846 } 2847 } 2848 2849 /* XXX pci_conf_print_pmux_cap */ 2850 2851 static void 2852 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 2853 { 2854 pcireg_t reg, cap, ctl; 2855 unsigned int num; 2856 2857 printf("\n Process Address Space ID\n"); 2858 2859 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 2860 cap = reg & 0xffff; 2861 ctl = reg >> 16; 2862 printf(" PASID Capability Register: 0x%04x\n", cap); 2863 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 2864 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 2865 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 2866 printf(" Max PASID Width: %u\n", num); 2867 2868 printf(" PASID Control Register: 0x%04x\n", ctl); 2869 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 2870 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 2871 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 2872 } 2873 2874 static void 2875 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 2876 { 2877 pcireg_t reg, cap, ctl; 2878 unsigned int num; 2879 2880 printf("\n LN Requester\n"); 2881 2882 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 2883 cap = reg & 0xffff; 2884 ctl = reg >> 16; 2885 printf(" LNR Capability register: 0x%04x\n", cap); 2886 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 2887 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 2888 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 2889 printf(" LNR Registration MAX: %u\n", num); 2890 2891 printf(" LNR Control register: 0x%04x\n", ctl); 2892 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 2893 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 2894 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 2895 printf(" LNR Registration Limit: %u\n", num); 2896 } 2897 2898 /* XXX pci_conf_print_dpc_cap */ 2899 2900 static int 2901 pci_conf_l1pm_cap_tposcale(unsigned char scale) 2902 { 2903 2904 /* Return scale in us */ 2905 switch (scale) { 2906 case 0x0: 2907 return 2; 2908 case 0x1: 2909 return 10; 2910 case 0x2: 2911 return 100; 2912 default: 2913 return -1; 2914 } 2915 } 2916 2917 static void 2918 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 2919 { 2920 pcireg_t reg; 2921 int scale, val; 2922 2923 printf("\n L1 PM Substates\n"); 2924 2925 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 2926 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 2927 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 2928 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 2929 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 2930 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 2931 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 2932 printf(" Port Common Mode Restore Time: %uus\n", 2933 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 2934 scale = pci_conf_l1pm_cap_tposcale( 2935 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 2936 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 2937 printf(" Port T_POWER_ON: "); 2938 if (scale == -1) 2939 printf("unknown\n"); 2940 else 2941 printf("%dus\n", val * scale); 2942 2943 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 2944 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 2945 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 2946 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 2947 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 2948 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 2949 printf(" Common Mode Restore Time: %uus\n", 2950 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 2951 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 2952 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 2953 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 2954 2955 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 2956 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 2957 scale = pci_conf_l1pm_cap_tposcale( 2958 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 2959 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 2960 printf(" T_POWER_ON: "); 2961 if (scale == -1) 2962 printf("unknown\n"); 2963 else 2964 printf("%dus\n", val * scale); 2965 } 2966 2967 /* XXX pci_conf_print_ptm_cap */ 2968 /* XXX pci_conf_print_mpcie_cap */ 2969 /* XXX pci_conf_print_frsq_cap */ 2970 /* XXX pci_conf_print_rtr_cap */ 2971 /* XXX pci_conf_print_desigvndsp_cap */ 2972 2973 #undef MS 2974 #undef SM 2975 #undef RW 2976 2977 static struct { 2978 pcireg_t cap; 2979 const char *name; 2980 void (*printfunc)(const pcireg_t *, int, int); 2981 } pci_extcaptab[] = { 2982 { 0, "reserved", 2983 NULL }, 2984 { PCI_EXTCAP_AER, "Advanced Error Reporting", 2985 pci_conf_print_aer_cap }, 2986 { PCI_EXTCAP_VC, "Virtual Channel", 2987 pci_conf_print_vc_cap }, 2988 { PCI_EXTCAP_SERNUM, "Device Serial Number", 2989 pci_conf_print_sernum_cap }, 2990 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 2991 pci_conf_print_pwrbdgt_cap }, 2992 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 2993 pci_conf_print_rclink_dcl_cap }, 2994 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 2995 NULL }, 2996 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 2997 pci_conf_print_rcec_assoc_cap }, 2998 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 2999 NULL }, 3000 { PCI_EXTCAP_VC2, "Virtual Channel", 3001 NULL }, 3002 { PCI_EXTCAP_RCRB, "RCRB Header", 3003 NULL }, 3004 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3005 NULL }, 3006 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3007 NULL }, 3008 { PCI_EXTCAP_ACS, "Access Control Services", 3009 pci_conf_print_acs_cap }, 3010 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3011 pci_conf_print_ari_cap }, 3012 { PCI_EXTCAP_ATS, "Address Translation Services", 3013 pci_conf_print_ats_cap }, 3014 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3015 pci_conf_print_sriov_cap }, 3016 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3017 NULL }, 3018 { PCI_EXTCAP_MULTICAST, "Multicast", 3019 NULL }, 3020 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3021 pci_conf_print_page_req_cap }, 3022 { PCI_EXTCAP_AMD, "Reserved for AMD", 3023 NULL }, 3024 { PCI_EXTCAP_RESIZE_BAR,"Resizable BAR", 3025 NULL }, 3026 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3027 NULL }, 3028 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3029 pci_conf_print_tph_req_cap }, 3030 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3031 pci_conf_print_ltr_cap }, 3032 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3033 pci_conf_print_sec_pcie_cap }, 3034 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3035 NULL }, 3036 { PCI_EXTCAP_PASID, "Process Address Space ID", 3037 pci_conf_print_pasid_cap }, 3038 { PCI_EXTCAP_LN_REQ, "LN Requester", 3039 pci_conf_print_lnr_cap }, 3040 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3041 NULL }, 3042 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3043 pci_conf_print_l1pm_cap }, 3044 { PCI_EXTCAP_PTM, "Precision Time Management", 3045 NULL }, 3046 { PCI_EXTCAP_MPCIE, "M-PCIe", 3047 NULL }, 3048 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3049 NULL }, 3050 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3051 NULL }, 3052 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3053 NULL }, 3054 }; 3055 3056 static int 3057 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3058 int *offsetp) 3059 { 3060 int off; 3061 pcireg_t rval; 3062 3063 for (off = PCI_EXTCAPLIST_BASE; 3064 off != 0; 3065 off = PCI_EXTCAPLIST_NEXT(rval)) { 3066 rval = regs[o2i(off)]; 3067 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3068 if (offsetp != NULL) 3069 *offsetp = off; 3070 return 1; 3071 } 3072 } 3073 return 0; 3074 } 3075 3076 static void 3077 pci_conf_print_extcaplist( 3078 #ifdef _KERNEL 3079 pci_chipset_tag_t pc, pcitag_t tag, 3080 #endif 3081 const pcireg_t *regs, int capoff) 3082 { 3083 int off; 3084 pcireg_t foundcap; 3085 pcireg_t rval; 3086 bool foundtable[__arraycount(pci_extcaptab)]; 3087 unsigned int i; 3088 3089 /* Check Extended capability structure */ 3090 off = PCI_EXTCAPLIST_BASE; 3091 rval = regs[o2i(off)]; 3092 if (rval == 0xffffffff || rval == 0) 3093 return; 3094 3095 /* Clear table */ 3096 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3097 foundtable[i] = false; 3098 3099 /* Print extended capability register's offset and the type first */ 3100 for (;;) { 3101 printf(" Extended Capability Register at 0x%02x\n", off); 3102 3103 foundcap = PCI_EXTCAPLIST_CAP(rval); 3104 printf(" type: 0x%04x (", foundcap); 3105 if (foundcap < __arraycount(pci_extcaptab)) { 3106 printf("%s)\n", pci_extcaptab[foundcap].name); 3107 /* Mark as found */ 3108 foundtable[foundcap] = true; 3109 } else 3110 printf("unknown)\n"); 3111 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3112 3113 off = PCI_EXTCAPLIST_NEXT(rval); 3114 if (off == 0) 3115 break; 3116 rval = regs[o2i(off)]; 3117 } 3118 3119 /* 3120 * And then, print the detail of each capability registers 3121 * in capability value's order. 3122 */ 3123 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3124 if (foundtable[i] == false) 3125 continue; 3126 3127 /* 3128 * The type was found. Search capability list again and 3129 * print all capabilities that the capabiliy type is 3130 * the same. 3131 */ 3132 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3133 continue; 3134 rval = regs[o2i(off)]; 3135 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3136 || (pci_extcaptab[i].printfunc == NULL)) 3137 continue; 3138 3139 pci_extcaptab[i].printfunc(regs, capoff, off); 3140 3141 } 3142 } 3143 3144 /* Print the Secondary Status Register. */ 3145 static void 3146 pci_conf_print_ssr(pcireg_t rval) 3147 { 3148 pcireg_t devsel; 3149 3150 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3151 onoff("66 MHz capable", rval, __BIT(5)); 3152 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3153 onoff("Fast back-to-back capable", rval, __BIT(7)); 3154 onoff("Data parity error detected", rval, __BIT(8)); 3155 3156 printf(" DEVSEL timing: "); 3157 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3158 switch (devsel) { 3159 case 0: 3160 printf("fast"); 3161 break; 3162 case 1: 3163 printf("medium"); 3164 break; 3165 case 2: 3166 printf("slow"); 3167 break; 3168 default: 3169 printf("unknown/reserved"); /* XXX */ 3170 break; 3171 } 3172 printf(" (0x%x)\n", devsel); 3173 3174 onoff("Signalled target abort", rval, __BIT(11)); 3175 onoff("Received target abort", rval, __BIT(12)); 3176 onoff("Received master abort", rval, __BIT(13)); 3177 onoff("Received system error", rval, __BIT(14)); 3178 onoff("Detected parity error", rval, __BIT(15)); 3179 } 3180 3181 static void 3182 pci_conf_print_type0( 3183 #ifdef _KERNEL 3184 pci_chipset_tag_t pc, pcitag_t tag, 3185 #endif 3186 const pcireg_t *regs 3187 #ifdef _KERNEL 3188 , int sizebars 3189 #endif 3190 ) 3191 { 3192 int off, width; 3193 pcireg_t rval; 3194 3195 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3196 #ifdef _KERNEL 3197 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3198 #else 3199 width = pci_conf_print_bar(regs, off, NULL); 3200 #endif 3201 } 3202 3203 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3204 3205 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3206 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3207 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3208 3209 /* XXX */ 3210 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3211 3212 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3213 printf(" Capability list pointer: 0x%02x\n", 3214 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3215 else 3216 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3217 3218 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3219 3220 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3221 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3222 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3223 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3224 switch (PCI_INTERRUPT_PIN(rval)) { 3225 case PCI_INTERRUPT_PIN_NONE: 3226 printf("(none)"); 3227 break; 3228 case PCI_INTERRUPT_PIN_A: 3229 printf("(pin A)"); 3230 break; 3231 case PCI_INTERRUPT_PIN_B: 3232 printf("(pin B)"); 3233 break; 3234 case PCI_INTERRUPT_PIN_C: 3235 printf("(pin C)"); 3236 break; 3237 case PCI_INTERRUPT_PIN_D: 3238 printf("(pin D)"); 3239 break; 3240 default: 3241 printf("(? ? ?)"); 3242 break; 3243 } 3244 printf("\n"); 3245 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3246 } 3247 3248 static void 3249 pci_conf_print_type1( 3250 #ifdef _KERNEL 3251 pci_chipset_tag_t pc, pcitag_t tag, 3252 #endif 3253 const pcireg_t *regs 3254 #ifdef _KERNEL 3255 , int sizebars 3256 #endif 3257 ) 3258 { 3259 int off, width; 3260 pcireg_t rval; 3261 uint32_t base, limit; 3262 uint32_t base_h, limit_h; 3263 uint64_t pbase, plimit; 3264 int use_upper; 3265 3266 /* 3267 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3268 * Bridge chip documentation, and may not be correct with 3269 * respect to various standards. (XXX) 3270 */ 3271 3272 for (off = 0x10; off < 0x18; off += width) { 3273 #ifdef _KERNEL 3274 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3275 #else 3276 width = pci_conf_print_bar(regs, off, NULL); 3277 #endif 3278 } 3279 3280 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3281 printf(" Primary bus number: 0x%02x\n", 3282 PCI_BRIDGE_BUS_PRIMARY(rval)); 3283 printf(" Secondary bus number: 0x%02x\n", 3284 PCI_BRIDGE_BUS_SECONDARY(rval)); 3285 printf(" Subordinate bus number: 0x%02x\n", 3286 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3287 printf(" Secondary bus latency timer: 0x%02x\n", 3288 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3289 3290 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3291 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3292 3293 /* I/O region */ 3294 printf(" I/O region:\n"); 3295 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3296 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3297 if (PCI_BRIDGE_IO_32BITS(rval)) 3298 use_upper = 1; 3299 else 3300 use_upper = 0; 3301 onoff("32bit I/O", rval, use_upper); 3302 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3303 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3304 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3305 limit |= 0x00000fff; 3306 3307 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3308 base_h = (rval >> 0) & 0xffff; 3309 limit_h = (rval >> 16) & 0xffff; 3310 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3311 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3312 3313 if (use_upper == 1) { 3314 base |= base_h << 16; 3315 limit |= limit_h << 16; 3316 } 3317 if (base < limit) { 3318 if (use_upper == 1) 3319 printf(" range: 0x%08x-0x%08x\n", base, limit); 3320 else 3321 printf(" range: 0x%04x-0x%04x\n", base, limit); 3322 } else 3323 printf(" range: not set\n"); 3324 3325 /* Non-prefetchable memory region */ 3326 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3327 printf(" Memory region:\n"); 3328 printf(" base register: 0x%04x\n", 3329 (rval >> 0) & 0xffff); 3330 printf(" limit register: 0x%04x\n", 3331 (rval >> 16) & 0xffff); 3332 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3333 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3334 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3335 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3336 if (base < limit) 3337 printf(" range: 0x%08x-0x%08x\n", base, limit); 3338 else 3339 printf(" range: not set\n"); 3340 3341 /* Prefetchable memory region */ 3342 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3343 printf(" Prefetchable memory region:\n"); 3344 printf(" base register: 0x%04x\n", 3345 (rval >> 0) & 0xffff); 3346 printf(" limit register: 0x%04x\n", 3347 (rval >> 16) & 0xffff); 3348 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3349 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3350 printf(" base upper 32 bits register: 0x%08x\n", 3351 base_h); 3352 printf(" limit upper 32 bits register: 0x%08x\n", 3353 limit_h); 3354 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3355 use_upper = 1; 3356 else 3357 use_upper = 0; 3358 onoff("64bit memory address", rval, use_upper); 3359 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3360 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3361 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3362 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3363 if (use_upper == 1) { 3364 pbase |= (uint64_t)base_h << 32; 3365 plimit |= (uint64_t)limit_h << 32; 3366 } 3367 if (pbase < plimit) { 3368 if (use_upper == 1) 3369 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3370 "\n", pbase, plimit); 3371 else 3372 printf(" range: 0x%08x-0x%08x\n", 3373 (uint32_t)pbase, (uint32_t)plimit); 3374 } else 3375 printf(" range: not set\n"); 3376 3377 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3378 printf(" Capability list pointer: 0x%02x\n", 3379 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3380 else 3381 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3382 3383 /* XXX */ 3384 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3385 3386 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3387 printf(" Interrupt line: 0x%02x\n", 3388 (rval >> 0) & 0xff); 3389 printf(" Interrupt pin: 0x%02x ", 3390 (rval >> 8) & 0xff); 3391 switch ((rval >> 8) & 0xff) { 3392 case PCI_INTERRUPT_PIN_NONE: 3393 printf("(none)"); 3394 break; 3395 case PCI_INTERRUPT_PIN_A: 3396 printf("(pin A)"); 3397 break; 3398 case PCI_INTERRUPT_PIN_B: 3399 printf("(pin B)"); 3400 break; 3401 case PCI_INTERRUPT_PIN_C: 3402 printf("(pin C)"); 3403 break; 3404 case PCI_INTERRUPT_PIN_D: 3405 printf("(pin D)"); 3406 break; 3407 default: 3408 printf("(? ? ?)"); 3409 break; 3410 } 3411 printf("\n"); 3412 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3413 & PCI_BRIDGE_CONTROL_MASK; 3414 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3415 onoff("Parity error response", rval, 0x0001); 3416 onoff("Secondary SERR forwarding", rval, 0x0002); 3417 onoff("ISA enable", rval, 0x0004); 3418 onoff("VGA enable", rval, 0x0008); 3419 onoff("Master abort reporting", rval, 0x0020); 3420 onoff("Secondary bus reset", rval, 0x0040); 3421 onoff("Fast back-to-back capable", rval, 0x0080); 3422 } 3423 3424 static void 3425 pci_conf_print_type2( 3426 #ifdef _KERNEL 3427 pci_chipset_tag_t pc, pcitag_t tag, 3428 #endif 3429 const pcireg_t *regs 3430 #ifdef _KERNEL 3431 , int sizebars 3432 #endif 3433 ) 3434 { 3435 pcireg_t rval; 3436 3437 /* 3438 * XXX these need to be printed in more detail, need to be 3439 * XXX checked against specs/docs, etc. 3440 * 3441 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 3442 * controller chip documentation, and may not be correct with 3443 * respect to various standards. (XXX) 3444 */ 3445 3446 #ifdef _KERNEL 3447 pci_conf_print_bar(pc, tag, regs, 0x10, 3448 "CardBus socket/ExCA registers", sizebars); 3449 #else 3450 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 3451 #endif 3452 3453 /* Capability list pointer and secondary status register */ 3454 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 3455 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3456 printf(" Capability list pointer: 0x%02x\n", 3457 PCI_CAPLIST_PTR(rval)); 3458 else 3459 printf(" Reserved @ 0x14: 0x%04x\n", 3460 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 3461 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3462 3463 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3464 printf(" PCI bus number: 0x%02x\n", 3465 (rval >> 0) & 0xff); 3466 printf(" CardBus bus number: 0x%02x\n", 3467 (rval >> 8) & 0xff); 3468 printf(" Subordinate bus number: 0x%02x\n", 3469 (rval >> 16) & 0xff); 3470 printf(" CardBus latency timer: 0x%02x\n", 3471 (rval >> 24) & 0xff); 3472 3473 /* XXX Print more prettily */ 3474 printf(" CardBus memory region 0:\n"); 3475 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 3476 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 3477 printf(" CardBus memory region 1:\n"); 3478 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 3479 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 3480 printf(" CardBus I/O region 0:\n"); 3481 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 3482 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 3483 printf(" CardBus I/O region 1:\n"); 3484 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 3485 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 3486 3487 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3488 printf(" Interrupt line: 0x%02x\n", 3489 (rval >> 0) & 0xff); 3490 printf(" Interrupt pin: 0x%02x ", 3491 (rval >> 8) & 0xff); 3492 switch ((rval >> 8) & 0xff) { 3493 case PCI_INTERRUPT_PIN_NONE: 3494 printf("(none)"); 3495 break; 3496 case PCI_INTERRUPT_PIN_A: 3497 printf("(pin A)"); 3498 break; 3499 case PCI_INTERRUPT_PIN_B: 3500 printf("(pin B)"); 3501 break; 3502 case PCI_INTERRUPT_PIN_C: 3503 printf("(pin C)"); 3504 break; 3505 case PCI_INTERRUPT_PIN_D: 3506 printf("(pin D)"); 3507 break; 3508 default: 3509 printf("(? ? ?)"); 3510 break; 3511 } 3512 printf("\n"); 3513 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 3514 printf(" Bridge control register: 0x%04x\n", rval); 3515 onoff("Parity error response", rval, __BIT(0)); 3516 onoff("SERR# enable", rval, __BIT(1)); 3517 onoff("ISA enable", rval, __BIT(2)); 3518 onoff("VGA enable", rval, __BIT(3)); 3519 onoff("Master abort mode", rval, __BIT(5)); 3520 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 3521 onoff("Functional interrupts routed by ExCA registers", rval, 3522 __BIT(7)); 3523 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 3524 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 3525 onoff("Write posting enable", rval, __BIT(10)); 3526 3527 rval = regs[o2i(0x40)]; 3528 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3529 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3530 3531 #ifdef _KERNEL 3532 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 3533 sizebars); 3534 #else 3535 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 3536 #endif 3537 } 3538 3539 void 3540 pci_conf_print( 3541 #ifdef _KERNEL 3542 pci_chipset_tag_t pc, pcitag_t tag, 3543 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 3544 #else 3545 int pcifd, u_int bus, u_int dev, u_int func 3546 #endif 3547 ) 3548 { 3549 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 3550 int off, capoff, endoff, hdrtype; 3551 const char *type_name; 3552 #ifdef _KERNEL 3553 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 3554 int); 3555 int sizebars; 3556 #else 3557 void (*type_printfn)(const pcireg_t *); 3558 #endif 3559 3560 printf("PCI configuration registers:\n"); 3561 3562 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 3563 #ifdef _KERNEL 3564 regs[o2i(off)] = pci_conf_read(pc, tag, off); 3565 #else 3566 if (pcibus_conf_read(pcifd, bus, dev, func, off, 3567 ®s[o2i(off)]) == -1) 3568 regs[o2i(off)] = 0; 3569 #endif 3570 } 3571 3572 #ifdef _KERNEL 3573 sizebars = 1; 3574 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 3575 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 3576 sizebars = 0; 3577 #endif 3578 3579 /* common header */ 3580 printf(" Common header:\n"); 3581 pci_conf_print_regs(regs, 0, 16); 3582 3583 printf("\n"); 3584 #ifdef _KERNEL 3585 pci_conf_print_common(pc, tag, regs); 3586 #else 3587 pci_conf_print_common(regs); 3588 #endif 3589 printf("\n"); 3590 3591 /* type-dependent header */ 3592 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 3593 switch (hdrtype) { /* XXX make a table, eventually */ 3594 case 0: 3595 /* Standard device header */ 3596 type_name = "\"normal\" device"; 3597 type_printfn = &pci_conf_print_type0; 3598 capoff = PCI_CAPLISTPTR_REG; 3599 endoff = 64; 3600 break; 3601 case 1: 3602 /* PCI-PCI bridge header */ 3603 type_name = "PCI-PCI bridge"; 3604 type_printfn = &pci_conf_print_type1; 3605 capoff = PCI_CAPLISTPTR_REG; 3606 endoff = 64; 3607 break; 3608 case 2: 3609 /* PCI-CardBus bridge header */ 3610 type_name = "PCI-CardBus bridge"; 3611 type_printfn = &pci_conf_print_type2; 3612 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 3613 endoff = 72; 3614 break; 3615 default: 3616 type_name = NULL; 3617 type_printfn = 0; 3618 capoff = -1; 3619 endoff = 64; 3620 break; 3621 } 3622 printf(" Type %d ", hdrtype); 3623 if (type_name != NULL) 3624 printf("(%s) ", type_name); 3625 printf("header:\n"); 3626 pci_conf_print_regs(regs, 16, endoff); 3627 printf("\n"); 3628 if (type_printfn) { 3629 #ifdef _KERNEL 3630 (*type_printfn)(pc, tag, regs, sizebars); 3631 #else 3632 (*type_printfn)(regs); 3633 #endif 3634 } else 3635 printf(" Don't know how to pretty-print type %d header.\n", 3636 hdrtype); 3637 printf("\n"); 3638 3639 /* capability list, if present */ 3640 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3641 && (capoff > 0)) { 3642 #ifdef _KERNEL 3643 pci_conf_print_caplist(pc, tag, regs, capoff); 3644 #else 3645 pci_conf_print_caplist(regs, capoff); 3646 #endif 3647 printf("\n"); 3648 } 3649 3650 /* device-dependent header */ 3651 printf(" Device-dependent header:\n"); 3652 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 3653 printf("\n"); 3654 #ifdef _KERNEL 3655 if (printfn) 3656 (*printfn)(pc, tag, regs); 3657 else 3658 printf(" Don't know how to pretty-print device-dependent header.\n"); 3659 printf("\n"); 3660 #endif /* _KERNEL */ 3661 3662 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 3663 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 3664 return; 3665 3666 #ifdef _KERNEL 3667 pci_conf_print_extcaplist(pc, tag, regs, capoff); 3668 #else 3669 pci_conf_print_extcaplist(regs, capoff); 3670 #endif 3671 printf("\n"); 3672 3673 /* Extended Configuration Space, if present */ 3674 printf(" Extended Configuration Space:\n"); 3675 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 3676 } 3677 #endif /* defined(__minix) && !defined(_PCI_SERVER) */ 3678