1 /* $NetBSD: pci_subr.c,v 1.106 2013/08/05 07:53:31 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #if defined(__minix) && defined(_PCI_SERVER) 36 /* This is a quick hack, simple copy of the file, until we can use it as is. */ 37 #include <sys/types.h> 38 39 #include <stdint.h> 40 #include <stdbool.h> 41 #include <stdio.h> 42 43 #include <pci.h> 44 #include <dev/pci/pcireg.h> 45 46 const char *pci_baseclass_name(pcireg_t reg); 47 const char *pci_subclass_name(pcireg_t reg); 48 #else 49 /* 50 * PCI autoconfiguration support functions. 51 * 52 * Note: This file is also built into a userland library (libpci). 53 * Pay attention to this when you make modifications. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.106 2013/08/05 07:53:31 msaitoh Exp $"); 58 59 #ifdef _KERNEL_OPT 60 #include "opt_pci.h" 61 #endif 62 63 #include <sys/param.h> 64 65 #ifdef _KERNEL 66 #include <sys/systm.h> 67 #include <sys/intr.h> 68 #include <sys/module.h> 69 #else 70 #include <pci.h> 71 #include <stdbool.h> 72 #include <stdio.h> 73 #endif 74 75 #include <dev/pci/pcireg.h> 76 #ifdef _KERNEL 77 #include <dev/pci/pcivar.h> 78 #endif 79 #endif /* defined(__minix) && defined(_PCI_SERVER) */ 80 81 /* 82 * Descriptions of known PCI classes and subclasses. 83 * 84 * Subclasses are described in the same way as classes, but have a 85 * NULL subclass pointer. 86 */ 87 struct pci_class { 88 const char *name; 89 u_int val; /* as wide as pci_{,sub}class_t */ 90 const struct pci_class *subclasses; 91 }; 92 93 static const struct pci_class pci_subclass_prehistoric[] = { 94 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 95 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 96 { NULL, 0, NULL, }, 97 }; 98 99 static const struct pci_class pci_subclass_mass_storage[] = { 100 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 101 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 102 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 103 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 104 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 105 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 106 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 107 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 108 { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, }, 109 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 110 { NULL, 0, NULL, }, 111 }; 112 113 static const struct pci_class pci_subclass_network[] = { 114 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 115 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 116 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 117 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 118 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 119 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 120 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 121 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 static const struct pci_class pci_subclass_display[] = { 126 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 127 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 128 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 129 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 130 { NULL, 0, NULL, }, 131 }; 132 133 static const struct pci_class pci_subclass_multimedia[] = { 134 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 135 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 136 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 137 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 138 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 139 { NULL, 0, NULL, }, 140 }; 141 142 static const struct pci_class pci_subclass_memory[] = { 143 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 144 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 145 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 146 { NULL, 0, NULL, }, 147 }; 148 149 static const struct pci_class pci_subclass_bridge[] = { 150 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 151 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 152 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 153 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 154 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 155 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 156 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 157 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 158 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 159 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 160 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 161 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 162 { NULL, 0, NULL, }, 163 }; 164 165 static const struct pci_class pci_subclass_communications[] = { 166 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 167 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 168 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 169 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 170 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 171 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 172 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 173 { NULL, 0, NULL, }, 174 }; 175 176 static const struct pci_class pci_subclass_system[] = { 177 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 178 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 179 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 180 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 181 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 182 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 183 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 184 { NULL, 0, NULL, }, 185 }; 186 187 static const struct pci_class pci_subclass_input[] = { 188 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 189 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 190 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 191 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 192 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 193 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 194 { NULL, 0, NULL, }, 195 }; 196 197 static const struct pci_class pci_subclass_dock[] = { 198 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 199 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 static const struct pci_class pci_subclass_processor[] = { 204 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 205 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 206 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 207 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 208 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 209 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 210 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_serialbus[] = { 215 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 216 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 217 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 218 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 219 /* XXX Fiber Channel/_FIBRECHANNEL */ 220 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 221 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 222 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 223 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 224 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 225 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 static const struct pci_class pci_subclass_wireless[] = { 230 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 231 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 232 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 233 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 234 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 235 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 236 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 237 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 238 { NULL, 0, NULL, }, 239 }; 240 241 static const struct pci_class pci_subclass_i2o[] = { 242 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 static const struct pci_class pci_subclass_satcom[] = { 247 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 248 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 249 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 250 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 251 { NULL, 0, NULL, }, 252 }; 253 254 static const struct pci_class pci_subclass_crypto[] = { 255 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 256 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 257 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 258 { NULL, 0, NULL, }, 259 }; 260 261 static const struct pci_class pci_subclass_dasp[] = { 262 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 263 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 264 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 265 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 266 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 267 { NULL, 0, NULL, }, 268 }; 269 270 static const struct pci_class pci_class[] = { 271 { "prehistoric", PCI_CLASS_PREHISTORIC, 272 pci_subclass_prehistoric, }, 273 { "mass storage", PCI_CLASS_MASS_STORAGE, 274 pci_subclass_mass_storage, }, 275 { "network", PCI_CLASS_NETWORK, 276 pci_subclass_network, }, 277 { "display", PCI_CLASS_DISPLAY, 278 pci_subclass_display, }, 279 { "multimedia", PCI_CLASS_MULTIMEDIA, 280 pci_subclass_multimedia, }, 281 { "memory", PCI_CLASS_MEMORY, 282 pci_subclass_memory, }, 283 { "bridge", PCI_CLASS_BRIDGE, 284 pci_subclass_bridge, }, 285 { "communications", PCI_CLASS_COMMUNICATIONS, 286 pci_subclass_communications, }, 287 { "system", PCI_CLASS_SYSTEM, 288 pci_subclass_system, }, 289 { "input", PCI_CLASS_INPUT, 290 pci_subclass_input, }, 291 { "dock", PCI_CLASS_DOCK, 292 pci_subclass_dock, }, 293 { "processor", PCI_CLASS_PROCESSOR, 294 pci_subclass_processor, }, 295 { "serial bus", PCI_CLASS_SERIALBUS, 296 pci_subclass_serialbus, }, 297 { "wireless", PCI_CLASS_WIRELESS, 298 pci_subclass_wireless, }, 299 { "I2O", PCI_CLASS_I2O, 300 pci_subclass_i2o, }, 301 { "satellite comm", PCI_CLASS_SATCOM, 302 pci_subclass_satcom, }, 303 { "crypto", PCI_CLASS_CRYPTO, 304 pci_subclass_crypto, }, 305 { "DASP", PCI_CLASS_DASP, 306 pci_subclass_dasp, }, 307 { "undefined", PCI_CLASS_UNDEFINED, 308 NULL, }, 309 { NULL, 0, 310 NULL, }, 311 }; 312 313 #if defined(__minix) && defined(_PCI_SERVER) 314 const char * 315 pci_baseclass_name(pcireg_t reg) 316 { 317 const struct pci_class *classp = pci_class; 318 319 while (classp->name != NULL) { 320 if (PCI_CLASS(reg) == classp->val) 321 break; 322 classp++; 323 } 324 325 return classp->name; 326 } 327 328 const char * 329 pci_subclass_name(pcireg_t reg) 330 { 331 const struct pci_class *classp = pci_class; 332 const struct pci_class *subclassp; 333 334 while (classp->name != NULL) { 335 if (PCI_CLASS(reg) == classp->val) 336 break; 337 classp++; 338 } 339 340 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 341 while (subclassp && subclassp->name != NULL) { 342 if (PCI_SUBCLASS(reg) == subclassp->val) 343 break; 344 subclassp++; 345 } 346 347 return subclassp->name; 348 } 349 350 #else 351 void pci_load_verbose(void); 352 353 #if defined(_KERNEL) 354 /* 355 * In kernel, these routines are provided and linked via the 356 * pciverbose module. 357 */ 358 const char *pci_findvendor_stub(pcireg_t); 359 const char *pci_findproduct_stub(pcireg_t); 360 361 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 362 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 363 const char *pci_unmatched = ""; 364 #else 365 /* 366 * For userland we just set the vectors here. 367 */ 368 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 369 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 370 const char *pci_unmatched = "unmatched "; 371 #endif 372 373 int pciverbose_loaded = 0; 374 375 #if defined(_KERNEL) 376 /* 377 * Routine to load the pciverbose kernel module as needed 378 */ 379 void pci_load_verbose(void) 380 { 381 if (pciverbose_loaded == 0) 382 module_autoload("pciverbose", MODULE_CLASS_MISC); 383 } 384 385 const char *pci_findvendor_stub(pcireg_t id_reg) 386 { 387 pci_load_verbose(); 388 if (pciverbose_loaded) 389 return pci_findvendor(id_reg); 390 else 391 return NULL; 392 } 393 394 const char *pci_findproduct_stub(pcireg_t id_reg) 395 { 396 pci_load_verbose(); 397 if (pciverbose_loaded) 398 return pci_findproduct(id_reg); 399 else 400 return NULL; 401 } 402 #endif 403 404 void 405 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 406 size_t l) 407 { 408 pci_vendor_id_t vendor; 409 pci_product_id_t product; 410 pci_class_t class; 411 pci_subclass_t subclass; 412 pci_interface_t interface; 413 pci_revision_t revision; 414 const char *unmatched = pci_unmatched; 415 const char *vendor_namep, *product_namep; 416 const struct pci_class *classp, *subclassp; 417 char *ep; 418 419 ep = cp + l; 420 421 vendor = PCI_VENDOR(id_reg); 422 product = PCI_PRODUCT(id_reg); 423 424 class = PCI_CLASS(class_reg); 425 subclass = PCI_SUBCLASS(class_reg); 426 interface = PCI_INTERFACE(class_reg); 427 revision = PCI_REVISION(class_reg); 428 429 vendor_namep = pci_findvendor(id_reg); 430 product_namep = pci_findproduct(id_reg); 431 432 classp = pci_class; 433 while (classp->name != NULL) { 434 if (class == classp->val) 435 break; 436 classp++; 437 } 438 439 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 440 while (subclassp && subclassp->name != NULL) { 441 if (subclass == subclassp->val) 442 break; 443 subclassp++; 444 } 445 446 if (vendor_namep == NULL) 447 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 448 unmatched, vendor, product); 449 else if (product_namep != NULL) 450 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 451 product_namep); 452 else 453 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 454 vendor_namep, product); 455 if (showclass) { 456 cp += snprintf(cp, ep - cp, " ("); 457 if (classp->name == NULL) 458 cp += snprintf(cp, ep - cp, 459 "class 0x%02x, subclass 0x%02x", class, subclass); 460 else { 461 if (subclassp == NULL || subclassp->name == NULL) 462 cp += snprintf(cp, ep - cp, 463 "%s, subclass 0x%02x", 464 classp->name, subclass); 465 else 466 cp += snprintf(cp, ep - cp, "%s %s", 467 subclassp->name, classp->name); 468 } 469 if (interface != 0) 470 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 471 interface); 472 if (revision != 0) 473 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 474 revision); 475 cp += snprintf(cp, ep - cp, ")"); 476 } 477 } 478 479 #ifdef _KERNEL 480 void 481 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 482 const char *known, int addrev) 483 { 484 char devinfo[256]; 485 486 if (known) { 487 aprint_normal(": %s", known); 488 if (addrev) 489 aprint_normal(" (rev. 0x%02x)", 490 PCI_REVISION(pa->pa_class)); 491 aprint_normal("\n"); 492 } else { 493 pci_devinfo(pa->pa_id, pa->pa_class, 0, 494 devinfo, sizeof(devinfo)); 495 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 496 PCI_REVISION(pa->pa_class)); 497 } 498 if (naive) 499 aprint_naive(": %s\n", naive); 500 else 501 aprint_naive("\n"); 502 } 503 #endif 504 505 /* 506 * Print out most of the PCI configuration registers. Typically used 507 * in a device attach routine like this: 508 * 509 * #ifdef MYDEV_DEBUG 510 * printf("%s: ", device_xname(sc->sc_dev)); 511 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 512 * #endif 513 */ 514 515 #define i2o(i) ((i) * 4) 516 #define o2i(o) ((o) / 4) 517 #define onoff2(str, bit, onstr, offstr) \ 518 printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr); 519 #define onoff(str, bit) onoff2(str, bit, "on", "off") 520 521 static void 522 pci_conf_print_common( 523 #ifdef _KERNEL 524 pci_chipset_tag_t pc, pcitag_t tag, 525 #endif 526 const pcireg_t *regs) 527 { 528 const char *name; 529 const struct pci_class *classp, *subclassp; 530 pcireg_t rval; 531 532 rval = regs[o2i(PCI_ID_REG)]; 533 name = pci_findvendor(rval); 534 if (name) 535 printf(" Vendor Name: %s (0x%04x)\n", name, 536 PCI_VENDOR(rval)); 537 else 538 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 539 name = pci_findproduct(rval); 540 if (name) 541 printf(" Device Name: %s (0x%04x)\n", name, 542 PCI_PRODUCT(rval)); 543 else 544 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 545 546 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 547 548 printf(" Command register: 0x%04x\n", rval & 0xffff); 549 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 550 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 551 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 552 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 553 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 554 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 555 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 556 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 557 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 558 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 559 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 560 561 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 562 onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive"); 563 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 564 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 565 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 566 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 567 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 568 569 printf(" DEVSEL timing: "); 570 switch (rval & PCI_STATUS_DEVSEL_MASK) { 571 case PCI_STATUS_DEVSEL_FAST: 572 printf("fast"); 573 break; 574 case PCI_STATUS_DEVSEL_MEDIUM: 575 printf("medium"); 576 break; 577 case PCI_STATUS_DEVSEL_SLOW: 578 printf("slow"); 579 break; 580 default: 581 printf("unknown/reserved"); /* XXX */ 582 break; 583 } 584 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 585 586 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 587 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 588 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 589 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 590 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 591 592 rval = regs[o2i(PCI_CLASS_REG)]; 593 for (classp = pci_class; classp->name != NULL; classp++) { 594 if (PCI_CLASS(rval) == classp->val) 595 break; 596 } 597 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 598 while (subclassp && subclassp->name != NULL) { 599 if (PCI_SUBCLASS(rval) == subclassp->val) 600 break; 601 subclassp++; 602 } 603 if (classp->name != NULL) { 604 printf(" Class Name: %s (0x%02x)\n", classp->name, 605 PCI_CLASS(rval)); 606 if (subclassp != NULL && subclassp->name != NULL) 607 printf(" Subclass Name: %s (0x%02x)\n", 608 subclassp->name, PCI_SUBCLASS(rval)); 609 else 610 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 611 } else { 612 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 613 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 614 } 615 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 616 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 617 618 rval = regs[o2i(PCI_BHLC_REG)]; 619 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 620 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 621 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 622 PCI_HDRTYPE(rval)); 623 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 624 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 625 } 626 627 static int 628 pci_conf_print_bar( 629 #ifdef _KERNEL 630 pci_chipset_tag_t pc, pcitag_t tag, 631 #endif 632 const pcireg_t *regs, int reg, const char *name 633 #ifdef _KERNEL 634 , int sizebar 635 #endif 636 ) 637 { 638 int width; 639 pcireg_t rval, rval64h; 640 #ifdef _KERNEL 641 int s; 642 pcireg_t mask, mask64h; 643 #endif 644 645 width = 4; 646 647 /* 648 * Section 6.2.5.1, `Address Maps', tells us that: 649 * 650 * 1) The builtin software should have already mapped the 651 * device in a reasonable way. 652 * 653 * 2) A device which wants 2^n bytes of memory will hardwire 654 * the bottom n bits of the address to 0. As recommended, 655 * we write all 1s and see what we get back. 656 */ 657 658 rval = regs[o2i(reg)]; 659 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 660 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 661 rval64h = regs[o2i(reg + 4)]; 662 width = 8; 663 } else 664 rval64h = 0; 665 666 #ifdef _KERNEL 667 /* XXX don't size unknown memory type? */ 668 if (rval != 0 && sizebar) { 669 /* 670 * The following sequence seems to make some devices 671 * (e.g. host bus bridges, which don't normally 672 * have their space mapped) very unhappy, to 673 * the point of crashing the system. 674 * 675 * Therefore, if the mapping register is zero to 676 * start out with, don't bother trying. 677 */ 678 s = splhigh(); 679 pci_conf_write(pc, tag, reg, 0xffffffff); 680 mask = pci_conf_read(pc, tag, reg); 681 pci_conf_write(pc, tag, reg, rval); 682 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 683 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 684 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 685 mask64h = pci_conf_read(pc, tag, reg + 4); 686 pci_conf_write(pc, tag, reg + 4, rval64h); 687 } else 688 mask64h = 0; 689 splx(s); 690 } else 691 mask = mask64h = 0; 692 #endif /* _KERNEL */ 693 694 printf(" Base address register at 0x%02x", reg); 695 if (name) 696 printf(" (%s)", name); 697 printf("\n "); 698 if (rval == 0) { 699 printf("not implemented(?)\n"); 700 return width; 701 } 702 printf("type: "); 703 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 704 const char *type, *prefetch; 705 706 switch (PCI_MAPREG_MEM_TYPE(rval)) { 707 case PCI_MAPREG_MEM_TYPE_32BIT: 708 type = "32-bit"; 709 break; 710 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 711 type = "32-bit-1M"; 712 break; 713 case PCI_MAPREG_MEM_TYPE_64BIT: 714 type = "64-bit"; 715 break; 716 default: 717 type = "unknown (XXX)"; 718 break; 719 } 720 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 721 prefetch = ""; 722 else 723 prefetch = "non"; 724 printf("%s %sprefetchable memory\n", type, prefetch); 725 switch (PCI_MAPREG_MEM_TYPE(rval)) { 726 case PCI_MAPREG_MEM_TYPE_64BIT: 727 printf(" base: 0x%016llx, ", 728 PCI_MAPREG_MEM64_ADDR( 729 ((((long long) rval64h) << 32) | rval))); 730 #ifdef _KERNEL 731 if (sizebar) 732 printf("size: 0x%016llx", 733 PCI_MAPREG_MEM64_SIZE( 734 ((((long long) mask64h) << 32) | mask))); 735 else 736 #endif /* _KERNEL */ 737 printf("not sized"); 738 printf("\n"); 739 break; 740 case PCI_MAPREG_MEM_TYPE_32BIT: 741 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 742 default: 743 printf(" base: 0x%08x, ", 744 PCI_MAPREG_MEM_ADDR(rval)); 745 #ifdef _KERNEL 746 if (sizebar) 747 printf("size: 0x%08x", 748 PCI_MAPREG_MEM_SIZE(mask)); 749 else 750 #endif /* _KERNEL */ 751 printf("not sized"); 752 printf("\n"); 753 break; 754 } 755 } else { 756 #ifdef _KERNEL 757 if (sizebar) 758 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 759 #endif /* _KERNEL */ 760 printf("i/o\n"); 761 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 762 #ifdef _KERNEL 763 if (sizebar) 764 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 765 else 766 #endif /* _KERNEL */ 767 printf("not sized"); 768 printf("\n"); 769 } 770 771 return width; 772 } 773 774 static void 775 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 776 { 777 int off, needaddr, neednl; 778 779 needaddr = 1; 780 neednl = 0; 781 for (off = first; off < pastlast; off += 4) { 782 if ((off % 16) == 0 || needaddr) { 783 printf(" 0x%02x:", off); 784 needaddr = 0; 785 } 786 printf(" 0x%08x", regs[o2i(off)]); 787 neednl = 1; 788 if ((off % 16) == 12) { 789 printf("\n"); 790 neednl = 0; 791 } 792 } 793 if (neednl) 794 printf("\n"); 795 } 796 797 static void 798 pci_conf_print_type0( 799 #ifdef _KERNEL 800 pci_chipset_tag_t pc, pcitag_t tag, 801 #endif 802 const pcireg_t *regs 803 #ifdef _KERNEL 804 , int sizebars 805 #endif 806 ) 807 { 808 int off, width; 809 pcireg_t rval; 810 811 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 812 #ifdef _KERNEL 813 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 814 #else 815 width = pci_conf_print_bar(regs, off, NULL); 816 #endif 817 } 818 819 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 820 821 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 822 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 823 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 824 825 /* XXX */ 826 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 827 828 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 829 printf(" Capability list pointer: 0x%02x\n", 830 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 831 else 832 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 833 834 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 835 836 rval = regs[o2i(PCI_INTERRUPT_REG)]; 837 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 838 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 839 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 840 switch (PCI_INTERRUPT_PIN(rval)) { 841 case PCI_INTERRUPT_PIN_NONE: 842 printf("(none)"); 843 break; 844 case PCI_INTERRUPT_PIN_A: 845 printf("(pin A)"); 846 break; 847 case PCI_INTERRUPT_PIN_B: 848 printf("(pin B)"); 849 break; 850 case PCI_INTERRUPT_PIN_C: 851 printf("(pin C)"); 852 break; 853 case PCI_INTERRUPT_PIN_D: 854 printf("(pin D)"); 855 break; 856 default: 857 printf("(? ? ?)"); 858 break; 859 } 860 printf("\n"); 861 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 862 } 863 864 static void 865 pci_print_pcie_L0s_latency(uint32_t val) 866 { 867 868 switch (val) { 869 case 0x0: 870 printf("Less than 64ns\n"); 871 break; 872 case 0x1: 873 case 0x2: 874 case 0x3: 875 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 876 break; 877 case 0x4: 878 printf("512ns to less than 1us\n"); 879 break; 880 case 0x5: 881 printf("1us to less than 2us\n"); 882 break; 883 case 0x6: 884 printf("2us - 4us\n"); 885 break; 886 case 0x7: 887 printf("More than 4us\n"); 888 break; 889 } 890 } 891 892 static void 893 pci_print_pcie_L1_latency(uint32_t val) 894 { 895 896 switch (val) { 897 case 0x0: 898 printf("Less than 1us\n"); 899 break; 900 case 0x6: 901 printf("32us - 64us\n"); 902 break; 903 case 0x7: 904 printf("More than 64us\n"); 905 break; 906 default: 907 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 908 break; 909 } 910 } 911 912 static void 913 pci_print_pcie_compl_timeout(uint32_t val) 914 { 915 916 switch (val) { 917 case 0x0: 918 printf("50us to 50ms\n"); 919 break; 920 case 0x5: 921 printf("16ms to 55ms\n"); 922 break; 923 case 0x6: 924 printf("65ms to 210ms\n"); 925 break; 926 case 0x9: 927 printf("260ms to 900ms\n"); 928 break; 929 case 0xa: 930 printf("1s to 3.5s\n"); 931 break; 932 default: 933 printf("unknown %u value\n", val); 934 break; 935 } 936 } 937 938 static void 939 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 940 { 941 pcireg_t reg; /* for each register */ 942 pcireg_t val; /* for each bitfield */ 943 bool check_link = false; 944 bool check_slot = false; 945 bool check_rootport = false; 946 unsigned int pciever; 947 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 948 int i; 949 950 printf("\n PCI Express Capabilities Register\n"); 951 /* Capability Register */ 952 reg = regs[o2i(capoff)]; 953 printf(" Capability register: %04x\n", reg >> 16); 954 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 955 printf(" Capability version: %u\n", pciever); 956 printf(" Device type: "); 957 switch ((reg & 0x00f00000) >> 20) { 958 case 0x0: 959 printf("PCI Express Endpoint device\n"); 960 check_link = true; 961 break; 962 case 0x1: 963 printf("Legacy PCI Express Endpoint device\n"); 964 check_link = true; 965 break; 966 case 0x4: 967 printf("Root Port of PCI Express Root Complex\n"); 968 check_link = true; 969 check_slot = true; 970 check_rootport = true; 971 break; 972 case 0x5: 973 printf("Upstream Port of PCI Express Switch\n"); 974 break; 975 case 0x6: 976 printf("Downstream Port of PCI Express Switch\n"); 977 check_slot = true; 978 check_rootport = true; 979 break; 980 case 0x7: 981 printf("PCI Express to PCI/PCI-X Bridge\n"); 982 break; 983 case 0x8: 984 printf("PCI/PCI-X to PCI Express Bridge\n"); 985 break; 986 case 0x9: 987 printf("Root Complex Integrated Endpoint\n"); 988 break; 989 case 0xa: 990 check_rootport = true; 991 printf("Root Complex Event Collector\n"); 992 break; 993 default: 994 printf("unknown\n"); 995 break; 996 } 997 if (check_slot && (reg & PCIE_XCAP_SI) != 0) 998 printf(" Slot implemented\n"); 999 printf(" Interrupt Message Number: %x\n", 1000 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1001 1002 /* Device Capability Register */ 1003 reg = regs[o2i(capoff + PCIE_DCAP)]; 1004 printf(" Device Capabilities Register: 0x%08x\n", reg); 1005 printf(" Max Payload Size Supported: %u bytes max\n", 1006 (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD) * 256); 1007 printf(" Phantom Functions Supported: "); 1008 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1009 case 0x0: 1010 printf("not available\n"); 1011 break; 1012 case 0x1: 1013 printf("MSB\n"); 1014 break; 1015 case 0x2: 1016 printf("two MSB\n"); 1017 break; 1018 case 0x3: 1019 printf("All three bits\n"); 1020 break; 1021 } 1022 printf(" Extended Tag Field Supported: %dbit\n", 1023 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1024 printf(" Endpoint L0 Acceptable Latency: "); 1025 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1026 printf(" Endpoint L1 Acceptable Latency: "); 1027 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1028 printf(" Attention Button Present: %s\n", 1029 (reg & PCIE_DCAP_ATTN_BUTTON) != 0 ? "yes" : "no"); 1030 printf(" Attention Indicator Present: %s\n", 1031 (reg & PCIE_DCAP_ATTN_IND) != 0 ? "yes" : "no"); 1032 printf(" Power Indicator Present: %s\n", 1033 (reg & PCIE_DCAP_PWR_IND) != 0 ? "yes" : "no"); 1034 printf(" Role-Based Error Report: %s\n", 1035 (reg & PCIE_DCAP_ROLE_ERR_RPT) != 0 ? "yes" : "no"); 1036 printf(" Captured Slot Power Limit Value: %d\n", 1037 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1038 printf(" Captured Slot Power Limit Scale: %d\n", 1039 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1040 printf(" Function-Level Reset Capability: %s\n", 1041 (reg & PCIE_DCAP_FLR) != 0 ? "yes" : "no"); 1042 1043 /* Device Control Register */ 1044 reg = regs[o2i(capoff + PCIE_DCSR)]; 1045 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1046 printf(" Correctable Error Reporting Enable: %s\n", 1047 (reg & PCIE_DCSR_ENA_COR_ERR) != 0 ? "on" : "off"); 1048 printf(" Non Fatal Error Reporting Enable: %s\n", 1049 (reg & PCIE_DCSR_ENA_NFER) != 0 ? "on" : "off"); 1050 printf(" Fatal Error Reporting Enable: %s\n", 1051 (reg & PCIE_DCSR_ENA_FER) != 0 ? "on" : "off"); 1052 printf(" Unsupported Request Reporting Enable: %s\n", 1053 (reg & PCIE_DCSR_ENA_URR) != 0 ? "on" : "off"); 1054 printf(" Enable Relaxed Ordering: %s\n", 1055 (reg & PCIE_DCSR_ENA_RELAX_ORD) != 0 ? "on" : "off"); 1056 printf(" Max Payload Size: %d byte\n", 1057 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1058 printf(" Extended Tag Field Enable: %s\n", 1059 (reg & PCIE_DCSR_EXT_TAG_FIELD) != 0 ? "on" : "off"); 1060 printf(" Phantom Functions Enable: %s\n", 1061 (reg & PCIE_DCSR_PHANTOM_FUNCS) != 0 ? "on" : "off"); 1062 printf(" Aux Power PM Enable: %s\n", 1063 (reg & PCIE_DCSR_AUX_POWER_PM) != 0 ? "on" : "off"); 1064 printf(" Enable No Snoop: %s\n", 1065 (reg & PCIE_DCSR_ENA_NO_SNOOP) != 0 ? "on" : "off"); 1066 printf(" Max Read Request Size: %d byte\n", 1067 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1068 1069 /* Device Status Register */ 1070 reg = regs[o2i(capoff + PCIE_DCSR)]; 1071 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1072 printf(" Correctable Error Detected: %s\n", 1073 (reg & PCIE_DCSR_CED) != 0 ? "on" : "off"); 1074 printf(" Non Fatal Error Detected: %s\n", 1075 (reg & PCIE_DCSR_NFED) != 0 ? "on" : "off"); 1076 printf(" Fatal Error Detected: %s\n", 1077 (reg & PCIE_DCSR_FED) != 0 ? "on" : "off"); 1078 printf(" Unsupported Request Detected: %s\n", 1079 (reg & PCIE_DCSR_URD) != 0 ? "on" : "off"); 1080 printf(" Aux Power Detected: %s\n", 1081 (reg & PCIE_DCSR_AUX_PWR) != 0 ? "on" : "off"); 1082 printf(" Transaction Pending: %s\n", 1083 (reg & PCIE_DCSR_TRANSACTION_PND) != 0 ? "on" : "off"); 1084 1085 if (check_link) { 1086 /* Link Capability Register */ 1087 reg = regs[o2i(capoff + PCIE_LCAP)]; 1088 printf(" Link Capabilities Register: 0x%08x\n", reg); 1089 printf(" Maximum Link Speed: "); 1090 val = reg & PCIE_LCAP_MAX_SPEED; 1091 if (val < 1 || val > 3) { 1092 printf("unknown %u value\n", val); 1093 } else { 1094 printf("%sGT/s\n", linkspeeds[val - 1]); 1095 } 1096 printf(" Maximum Link Width: x%u lanes\n", 1097 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1098 printf(" Active State PM Support: "); 1099 val = (reg & PCIE_LCAP_ASPM) >> 10; 1100 switch (val) { 1101 case 0x1: 1102 printf("L0s Entry supported\n"); 1103 break; 1104 case 0x3: 1105 printf("L0s and L1 supported\n"); 1106 break; 1107 default: 1108 printf("Reserved value\n"); 1109 break; 1110 } 1111 printf(" L0 Exit Latency: "); 1112 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1113 printf(" L1 Exit Latency: "); 1114 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1115 printf(" Port Number: %u\n", reg >> 24); 1116 1117 /* Link Control Register */ 1118 reg = regs[o2i(capoff + PCIE_LCSR)]; 1119 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1120 printf(" Active State PM Control: "); 1121 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1122 switch (val) { 1123 case 0: 1124 printf("disabled\n"); 1125 break; 1126 case 1: 1127 printf("L0s Entry Enabled\n"); 1128 break; 1129 case 2: 1130 printf("L1 Entry Enabled\n"); 1131 break; 1132 case 3: 1133 printf("L0s and L1 Entry Enabled\n"); 1134 break; 1135 } 1136 printf(" Read Completion Boundary Control: %dbyte\n", 1137 (reg & PCIE_LCSR_RCB) != 0 ? 128 : 64); 1138 printf(" Link Disable: %s\n", 1139 (reg & PCIE_LCSR_LINK_DIS) != 0 ? "on" : "off"); 1140 printf(" Retrain Link: %s\n", 1141 (reg & PCIE_LCSR_RETRAIN) != 0 ? "on" : "off"); 1142 printf(" Common Clock Configuration: %s\n", 1143 (reg & PCIE_LCSR_COMCLKCFG) != 0 ? "on" : "off"); 1144 printf(" Extended Synch: %s\n", 1145 (reg & PCIE_LCSR_EXTNDSYNC) != 0 ? "on" : "off"); 1146 printf(" Enable Clock Power Management: %s\n", 1147 (reg & PCIE_LCSR_ENCLKPM) != 0 ? "on" : "off"); 1148 printf(" Hardware Autonomous Width Disable: %s\n", 1149 (reg & PCIE_LCSR_HAWD) != 0 ? "on" : "off"); 1150 printf(" Link Bandwidth Management Interrupt Enable: %s\n", 1151 (reg & PCIE_LCSR_LBMIE) != 0 ? "on" : "off"); 1152 printf(" Link Autonomous Bandwidth Interrupt Enable: %s\n", 1153 (reg & PCIE_LCSR_LABIE) != 0 ? "on" : "off"); 1154 1155 /* Link Status Register */ 1156 reg = regs[o2i(capoff + PCIE_LCSR)]; 1157 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1158 printf(" Negotiated Link Speed: "); 1159 if (((reg >> 16) & 0x000f) < 1 || 1160 ((reg >> 16) & 0x000f) > 3) { 1161 printf("unknown %u value\n", 1162 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1163 } else { 1164 printf("%sGT/s\n", 1165 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16) - 1]); 1166 } 1167 printf(" Negotiated Link Width: x%u lanes\n", 1168 (reg >> 20) & 0x003f); 1169 printf(" Training Error: %s\n", 1170 (reg & PCIE_LCSR_LINKTRAIN_ERR) != 0 ? "on" : "off"); 1171 printf(" Link Training: %s\n", 1172 (reg & PCIE_LCSR_LINKTRAIN) != 0 ? "on" : "off"); 1173 printf(" Slot Clock Configuration: %s\n", 1174 (reg & PCIE_LCSR_SLOTCLKCFG) != 0 ? "on" : "off"); 1175 printf(" Data Link Layer Link Active: %s\n", 1176 (reg & PCIE_LCSR_DLACTIVE) != 0 ? "on" : "off"); 1177 printf(" Link Bandwidth Management Status: %s\n", 1178 (reg & PCIE_LCSR_LINK_BW_MGMT) != 0 ? "on" : "off"); 1179 printf(" Link Autonomous Bandwidth Status: %s\n", 1180 (reg & PCIE_LCSR_LINK_AUTO_BW) != 0 ? "on" : "off"); 1181 } 1182 1183 if (check_slot == true) { 1184 /* Slot Capability Register */ 1185 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1186 printf(" Slot Capability Register: %08x\n", reg); 1187 if ((reg & PCIE_SLCAP_ABP) != 0) 1188 printf(" Attention Button Present\n"); 1189 if ((reg & PCIE_SLCAP_PCP) != 0) 1190 printf(" Power Controller Present\n"); 1191 if ((reg & PCIE_SLCAP_MSP) != 0) 1192 printf(" MRL Sensor Present\n"); 1193 if ((reg & PCIE_SLCAP_AIP) != 0) 1194 printf(" Attention Indicator Present\n"); 1195 if ((reg & PCIE_SLCAP_PIP) != 0) 1196 printf(" Power Indicator Present\n"); 1197 if ((reg & PCIE_SLCAP_HPS) != 0) 1198 printf(" Hot-Plug Surprise\n"); 1199 if ((reg & PCIE_SLCAP_HPC) != 0) 1200 printf(" Hot-Plug Capable\n"); 1201 printf(" Slot Power Limit Value: %d\n", 1202 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1203 printf(" Slot Power Limit Scale: %d\n", 1204 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1205 if ((reg & PCIE_SLCAP_EIP) != 0) 1206 printf(" Electromechanical Interlock Present\n"); 1207 if ((reg & PCIE_SLCAP_NCCS) != 0) 1208 printf(" No Command Completed Support\n"); 1209 printf(" Physical Slot Number: %d\n", 1210 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1211 1212 /* Slot Control Register */ 1213 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1214 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1215 if ((reg & PCIE_SLCSR_ABE) != 0) 1216 printf(" Attention Button Pressed Enabled\n"); 1217 if ((reg & PCIE_SLCSR_PFE) != 0) 1218 printf(" Power Fault Detected Enabled\n"); 1219 if ((reg & PCIE_SLCSR_MSE) != 0) 1220 printf(" MRL Sensor Changed Enabled\n"); 1221 if ((reg & PCIE_SLCSR_PDE) != 0) 1222 printf(" Presense Detect Changed Enabled\n"); 1223 if ((reg & PCIE_SLCSR_CCE) != 0) 1224 printf(" Command Completed Interrupt Enabled\n"); 1225 if ((reg & PCIE_SLCSR_HPE) != 0) 1226 printf(" Hot-Plug Interrupt Enabled\n"); 1227 printf(" Attention Indicator Control: "); 1228 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1229 case 0x0: 1230 printf("reserved\n"); 1231 break; 1232 case 0x1: 1233 printf("on\n"); 1234 break; 1235 case 0x2: 1236 printf("blink\n"); 1237 break; 1238 case 0x3: 1239 printf("off\n"); 1240 break; 1241 } 1242 printf(" Power Indicator Control: "); 1243 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1244 case 0x0: 1245 printf("reserved\n"); 1246 break; 1247 case 0x1: 1248 printf("on\n"); 1249 break; 1250 case 0x2: 1251 printf("blink\n"); 1252 break; 1253 case 0x3: 1254 printf("off\n"); 1255 break; 1256 } 1257 printf(" Power Controller Control: "); 1258 if ((reg & PCIE_SLCSR_PCC) != 0) 1259 printf("off\n"); 1260 else 1261 printf("on\n"); 1262 if ((reg & PCIE_SLCSR_EIC) != 0) 1263 printf(" Electromechanical Interlock Control\n"); 1264 if ((reg & PCIE_SLCSR_LACS) != 0) 1265 printf(" Data Link Layer State Changed Enable\n"); 1266 1267 /* Slot Status Register */ 1268 printf(" Slot Status Register: %04x\n", reg >> 16); 1269 if ((reg & PCIE_SLCSR_ABP) != 0) 1270 printf(" Attention Button Pressed\n"); 1271 if ((reg & PCIE_SLCSR_PFD) != 0) 1272 printf(" Power Fault Detected\n"); 1273 if ((reg & PCIE_SLCSR_MSC) != 0) 1274 printf(" MRL Sensor Changed\n"); 1275 if ((reg & PCIE_SLCSR_PDC) != 0) 1276 printf(" Presense Detect Changed\n"); 1277 if ((reg & PCIE_SLCSR_CC) != 0) 1278 printf(" Command Completed\n"); 1279 if ((reg & PCIE_SLCSR_MS) != 0) 1280 printf(" MRL Open\n"); 1281 if ((reg & PCIE_SLCSR_PDS) != 0) 1282 printf(" Card Present in slot\n"); 1283 if ((reg & PCIE_SLCSR_EIS) != 0) 1284 printf(" Electromechanical Interlock engaged\n"); 1285 if ((reg & PCIE_SLCSR_LACS) != 0) 1286 printf(" Data Link Layer State Changed\n"); 1287 } 1288 1289 if (check_rootport == true) { 1290 /* Root Control Register */ 1291 reg = regs[o2i(capoff + PCIE_RCR)]; 1292 printf(" Root Control Register: %04x\n", reg & 0xffff); 1293 if ((reg & PCIE_RCR_SERR_CER) != 0) 1294 printf(" SERR on Correctable Error Enable\n"); 1295 if ((reg & PCIE_RCR_SERR_NFER) != 0) 1296 printf(" SERR on Non-Fatal Error Enable\n"); 1297 if ((reg & PCIE_RCR_SERR_FER) != 0) 1298 printf(" SERR on Fatal Error Enable\n"); 1299 if ((reg & PCIE_RCR_PME_IE) != 0) 1300 printf(" PME Interrupt Enable\n"); 1301 1302 /* Root Capability Register */ 1303 printf(" Root Capability Register: %04x\n", 1304 reg >> 16); 1305 1306 /* Root Status Register */ 1307 reg = regs[o2i(capoff + PCIE_RSR)]; 1308 printf(" Root Status Register: %08x\n", reg); 1309 printf(" PME Requester ID: %04x\n", 1310 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1311 if ((reg & PCIE_RSR_PME_STAT) != 0) 1312 printf(" PME was asserted\n"); 1313 if ((reg & PCIE_RSR_PME_PEND) != 0) 1314 printf(" another PME is pending\n"); 1315 } 1316 1317 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1318 if (pciever < 2) 1319 return; 1320 1321 /* Device Capabilities 2 */ 1322 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1323 printf(" Device Capabilities 2: 0x%08x\n", reg); 1324 printf(" Completion Timeout Ranges Supported: %u \n", 1325 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1326 printf(" Completion Timeout Disable Supported: %s\n", 1327 (reg & PCIE_DCAP2_COMPT_DIS) != 0 ? "yes" : "no"); 1328 printf(" ARI Forwarding Supported: %s\n", 1329 (reg & PCIE_DCAP2_ARI_FWD) != 0 ? "yes" : "no"); 1330 printf(" AtomicOp Routing Supported: %s\n", 1331 (reg & PCIE_DCAP2_ATOM_ROUT) != 0 ? "yes" : "no"); 1332 printf(" 32bit AtomicOp Completer Supported: %s\n", 1333 (reg & PCIE_DCAP2_32ATOM) != 0 ? "yes" : "no"); 1334 printf(" 64bit AtomicOp Completer Supported: %s\n", 1335 (reg & PCIE_DCAP2_64ATOM) != 0 ? "yes" : "no"); 1336 printf(" 128-bit CAS Completer Supported: %s\n", 1337 (reg & PCIE_DCAP2_128CAS) != 0 ? "yes" : "no"); 1338 printf(" No RO-enabled PR-PR passing: %s\n", 1339 (reg & PCIE_DCAP2_NO_ROPR_PASS) != 0 ? "yes" : "no"); 1340 printf(" LTR Mechanism Supported: %s\n", 1341 (reg & PCIE_DCAP2_LTR_MEC) != 0 ? "yes" : "no"); 1342 printf(" TPH Completer Supported: %u\n", 1343 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1344 printf(" OBFF Supported: "); 1345 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1346 case 0x0: 1347 printf("Not supported\n"); 1348 break; 1349 case 0x1: 1350 printf("Message only\n"); 1351 break; 1352 case 0x2: 1353 printf("WAKE# only\n"); 1354 break; 1355 case 0x3: 1356 printf("Both\n"); 1357 break; 1358 } 1359 printf(" Extended Fmt Field Supported: %s\n", 1360 (reg & PCIE_DCAP2_EXTFMT_FLD) != 0 ? "yes" : "no"); 1361 printf(" End-End TLP Prefix Supported: %s\n", 1362 (reg & PCIE_DCAP2_EETLP_PREF) != 0 ? "yes" : "no"); 1363 printf(" Max End-End TLP Prefixes: %u\n", 1364 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1365 1366 /* Device Control 2 */ 1367 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1368 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1369 printf(" Completion Timeout Value: "); 1370 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1371 if ((reg & PCIE_DCSR2_COMPT_DIS) != 0) 1372 printf(" Completion Timeout Disabled\n"); 1373 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 1374 printf(" ARI Forwarding Enabled\n"); 1375 if ((reg & PCIE_DCSR2_ATOM_REQ) != 0) 1376 printf(" AtomicOp Rquester Enabled\n"); 1377 if ((reg & PCIE_DCSR2_ATOM_EBLK) != 0) 1378 printf(" AtomicOp Egress Blocking on\n"); 1379 if ((reg & PCIE_DCSR2_IDO_REQ) != 0) 1380 printf(" IDO Request Enabled\n"); 1381 if ((reg & PCIE_DCSR2_IDO_COMP) != 0) 1382 printf(" IDO Completion Enabled\n"); 1383 if ((reg & PCIE_DCSR2_LTR_MEC) != 0) 1384 printf(" LTR Mechanism Enabled\n"); 1385 printf(" OBFF: "); 1386 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1387 case 0x0: 1388 printf("Disabled\n"); 1389 break; 1390 case 0x1: 1391 printf("Enabled with Message Signaling Variation A\n"); 1392 break; 1393 case 0x2: 1394 printf("Enabled with Message Signaling Variation B\n"); 1395 break; 1396 case 0x3: 1397 printf("Enabled using WAKE# signaling\n"); 1398 break; 1399 } 1400 if ((reg & PCIE_DCSR2_EETLP) != 0) 1401 printf(" End-End TLP Prefix Blocking on\n"); 1402 1403 if (check_link) { 1404 /* Link Capability 2 */ 1405 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1406 printf(" Link Capabilities 2: 0x%08x\n", reg); 1407 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1408 printf(" Supported Link Speed Vector:"); 1409 for (i = 0; i <= 2; i++) { 1410 if (((val >> i) & 0x01) != 0) 1411 printf(" %sGT/s", linkspeeds[i]); 1412 } 1413 printf("\n"); 1414 1415 /* Link Control 2 */ 1416 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1417 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1418 printf(" Target Link Speed: "); 1419 val = reg & PCIE_LCSR2_TGT_LSPEED; 1420 if (val < 1 || val > 3) { 1421 printf("unknown %u value\n", val); 1422 } else { 1423 printf("%sGT/s\n", linkspeeds[val - 1]); 1424 } 1425 if ((reg & PCIE_LCSR2_ENT_COMPL) != 0) 1426 printf(" Enter Compliance Enabled\n"); 1427 if ((reg & PCIE_LCSR2_HW_AS_DIS) != 0) 1428 printf(" HW Autonomous Speed Disabled\n"); 1429 if ((reg & PCIE_LCSR2_SEL_DEEMP) != 0) 1430 printf(" Selectable De-emphasis\n"); 1431 printf(" Transmit Margin: %u\n", 1432 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1433 if ((reg & PCIE_LCSR2_EN_MCOMP) != 0) 1434 printf(" Enter Modified Compliance\n"); 1435 if ((reg & PCIE_LCSR2_COMP_SOS) != 0) 1436 printf(" Compliance SOS\n"); 1437 printf(" Compliance Present/De-emphasis: %u\n", 1438 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1439 1440 /* Link Status 2 */ 1441 if ((reg & PCIE_LCSR2_DEEMP_LVL) != 0) 1442 printf(" Current De-emphasis Level\n"); 1443 if ((reg & PCIE_LCSR2_EQ_COMPL) != 0) 1444 printf(" Equalization Complete\n"); 1445 if ((reg & PCIE_LCSR2_EQP1_SUC) != 0) 1446 printf(" Equalization Phase 1 Successful\n"); 1447 if ((reg & PCIE_LCSR2_EQP2_SUC) != 0) 1448 printf(" Equalization Phase 2 Successful\n"); 1449 if ((reg & PCIE_LCSR2_EQP3_SUC) != 0) 1450 printf(" Equalization Phase 3 Successful\n"); 1451 if ((reg & PCIE_LCSR2_LNKEQ_REQ) != 0) 1452 printf(" Link Equalization Request\n"); 1453 } 1454 1455 /* Slot Capability 2 */ 1456 /* Slot Control 2 */ 1457 /* Slot Status 2 */ 1458 } 1459 1460 static const char * 1461 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1462 { 1463 switch ((caps >> 6) & 7) { 1464 case 0: return "self-powered"; 1465 case 1: return "55 mA"; 1466 case 2: return "100 mA"; 1467 case 3: return "160 mA"; 1468 case 4: return "220 mA"; 1469 case 5: return "270 mA"; 1470 case 6: return "320 mA"; 1471 case 7: 1472 default: return "375 mA"; 1473 } 1474 } 1475 1476 static const char * 1477 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1478 { 1479 static const char unk[] = "unknown"; 1480 static const char *pmrev[8] = { 1481 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1482 }; 1483 if (val > 7) 1484 return unk; 1485 return pmrev[val]; 1486 } 1487 1488 static void 1489 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1490 { 1491 uint16_t caps, pmcsr; 1492 1493 caps = regs[o2i(capoff)] >> 16; 1494 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 1495 1496 printf("\n PCI Power Management Capabilities Register\n"); 1497 1498 printf(" Capabilities register: 0x%04x\n", caps); 1499 printf(" Version: %s\n", 1500 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 1501 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 1502 printf(" Device specific initialization: %s\n", 1503 caps & 0x20 ? "on" : "off"); 1504 printf(" 3.3V auxiliary current: %s\n", 1505 pci_conf_print_pcipm_cap_aux(caps)); 1506 printf(" D1 power management state support: %s\n", 1507 (caps >> 9) & 1 ? "on" : "off"); 1508 printf(" D2 power management state support: %s\n", 1509 (caps >> 10) & 1 ? "on" : "off"); 1510 printf(" PME# support: 0x%02x\n", caps >> 11); 1511 1512 printf(" Control/status register: 0x%04x\n", pmcsr); 1513 printf(" Power state: D%d\n", pmcsr & 3); 1514 printf(" PCI Express reserved: %s\n", 1515 (pmcsr >> 2) & 1 ? "on" : "off"); 1516 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 1517 printf(" PME# assertion %sabled\n", 1518 (pmcsr >> 8) & 1 ? "en" : "dis"); 1519 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 1520 } 1521 1522 static void 1523 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1524 { 1525 uint32_t ctl, mmc, mme; 1526 1527 regs += o2i(capoff); 1528 ctl = *regs++; 1529 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1530 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1531 1532 printf("\n PCI Message Signaled Interrupt\n"); 1533 1534 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1535 printf(" MSI Enabled: %s\n", 1536 ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no"); 1537 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1538 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1539 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1540 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1541 printf(" 64 Bit Address Capable: %s\n", 1542 ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no"); 1543 printf(" Per-Vector Masking Capable: %s\n", 1544 ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no"); 1545 printf(" Message Address %sregister: 0x%08x\n", 1546 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1547 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1548 printf(" Message Address %sregister: 0x%08x\n", 1549 "(upper) ", *regs++); 1550 } 1551 printf(" Message Data register: 0x%08x\n", *regs++); 1552 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1553 printf(" Vector Mask register: 0x%08x\n", *regs++); 1554 printf(" Vector Pending register: 0x%08x\n", *regs++); 1555 } 1556 } 1557 static void 1558 pci_conf_print_caplist( 1559 #ifdef _KERNEL 1560 pci_chipset_tag_t pc, pcitag_t tag, 1561 #endif 1562 const pcireg_t *regs, int capoff) 1563 { 1564 int off; 1565 pcireg_t rval; 1566 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1567 1568 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1569 off != 0; 1570 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1571 rval = regs[o2i(off)]; 1572 printf(" Capability register at 0x%02x\n", off); 1573 1574 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1575 switch (PCI_CAPLIST_CAP(rval)) { 1576 case PCI_CAP_RESERVED0: 1577 printf("reserved"); 1578 break; 1579 case PCI_CAP_PWRMGMT: 1580 printf("Power Management, rev. %s", 1581 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1582 pcipm_off = off; 1583 break; 1584 case PCI_CAP_AGP: 1585 printf("AGP, rev. %d.%d", 1586 PCI_CAP_AGP_MAJOR(rval), 1587 PCI_CAP_AGP_MINOR(rval)); 1588 break; 1589 case PCI_CAP_VPD: 1590 printf("VPD"); 1591 break; 1592 case PCI_CAP_SLOTID: 1593 printf("SlotID"); 1594 break; 1595 case PCI_CAP_MSI: 1596 printf("MSI"); 1597 msi_off = off; 1598 break; 1599 case PCI_CAP_CPCI_HOTSWAP: 1600 printf("CompactPCI Hot-swapping"); 1601 break; 1602 case PCI_CAP_PCIX: 1603 printf("PCI-X"); 1604 break; 1605 case PCI_CAP_LDT: 1606 printf("LDT"); 1607 break; 1608 case PCI_CAP_VENDSPEC: 1609 printf("Vendor-specific"); 1610 break; 1611 case PCI_CAP_DEBUGPORT: 1612 printf("Debug Port"); 1613 break; 1614 case PCI_CAP_CPCI_RSRCCTL: 1615 printf("CompactPCI Resource Control"); 1616 break; 1617 case PCI_CAP_HOTPLUG: 1618 printf("Hot-Plug"); 1619 break; 1620 case PCI_CAP_SUBVENDOR: 1621 printf("Sub Vendor ID"); 1622 break; 1623 case PCI_CAP_AGP8: 1624 printf("AGP 8x"); 1625 break; 1626 case PCI_CAP_SECURE: 1627 printf("Secure Device"); 1628 break; 1629 case PCI_CAP_PCIEXPRESS: 1630 printf("PCI Express"); 1631 pcie_off = off; 1632 break; 1633 case PCI_CAP_MSIX: 1634 printf("MSI-X"); 1635 break; 1636 case PCI_CAP_SATA: 1637 printf("SATA"); 1638 break; 1639 case PCI_CAP_PCIAF: 1640 printf("Advanced Features"); 1641 break; 1642 default: 1643 printf("unknown"); 1644 } 1645 printf(")\n"); 1646 } 1647 if (msi_off != -1) 1648 pci_conf_print_msi_cap(regs, msi_off); 1649 if (pcipm_off != -1) 1650 pci_conf_print_pcipm_cap(regs, pcipm_off); 1651 if (pcie_off != -1) 1652 pci_conf_print_pcie_cap(regs, pcie_off); 1653 } 1654 1655 /* Print the Secondary Status Register. */ 1656 static void 1657 pci_conf_print_ssr(pcireg_t rval) 1658 { 1659 pcireg_t devsel; 1660 1661 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1662 onoff("66 MHz capable", __BIT(5)); 1663 onoff("User Definable Features (UDF) support", __BIT(6)); 1664 onoff("Fast back-to-back capable", __BIT(7)); 1665 onoff("Data parity error detected", __BIT(8)); 1666 1667 printf(" DEVSEL timing: "); 1668 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1669 switch (devsel) { 1670 case 0: 1671 printf("fast"); 1672 break; 1673 case 1: 1674 printf("medium"); 1675 break; 1676 case 2: 1677 printf("slow"); 1678 break; 1679 default: 1680 printf("unknown/reserved"); /* XXX */ 1681 break; 1682 } 1683 printf(" (0x%x)\n", devsel); 1684 1685 onoff("Signalled target abort", __BIT(11)); 1686 onoff("Received target abort", __BIT(12)); 1687 onoff("Received master abort", __BIT(13)); 1688 onoff("Received system error", __BIT(14)); 1689 onoff("Detected parity error", __BIT(15)); 1690 } 1691 1692 static void 1693 pci_conf_print_type1( 1694 #ifdef _KERNEL 1695 pci_chipset_tag_t pc, pcitag_t tag, 1696 #endif 1697 const pcireg_t *regs 1698 #ifdef _KERNEL 1699 , int sizebars 1700 #endif 1701 ) 1702 { 1703 int off, width; 1704 pcireg_t rval; 1705 1706 /* 1707 * XXX these need to be printed in more detail, need to be 1708 * XXX checked against specs/docs, etc. 1709 * 1710 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1711 * Bridge chip documentation, and may not be correct with 1712 * respect to various standards. (XXX) 1713 */ 1714 1715 for (off = 0x10; off < 0x18; off += width) { 1716 #ifdef _KERNEL 1717 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1718 #else 1719 width = pci_conf_print_bar(regs, off, NULL); 1720 #endif 1721 } 1722 1723 printf(" Primary bus number: 0x%02x\n", 1724 (regs[o2i(0x18)] >> 0) & 0xff); 1725 printf(" Secondary bus number: 0x%02x\n", 1726 (regs[o2i(0x18)] >> 8) & 0xff); 1727 printf(" Subordinate bus number: 0x%02x\n", 1728 (regs[o2i(0x18)] >> 16) & 0xff); 1729 printf(" Secondary bus latency timer: 0x%02x\n", 1730 (regs[o2i(0x18)] >> 24) & 0xff); 1731 1732 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1733 1734 /* XXX Print more prettily */ 1735 printf(" I/O region:\n"); 1736 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1737 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1738 printf(" base upper 16 bits register: 0x%04x\n", 1739 (regs[o2i(0x30)] >> 0) & 0xffff); 1740 printf(" limit upper 16 bits register: 0x%04x\n", 1741 (regs[o2i(0x30)] >> 16) & 0xffff); 1742 1743 /* XXX Print more prettily */ 1744 printf(" Memory region:\n"); 1745 printf(" base register: 0x%04x\n", 1746 (regs[o2i(0x20)] >> 0) & 0xffff); 1747 printf(" limit register: 0x%04x\n", 1748 (regs[o2i(0x20)] >> 16) & 0xffff); 1749 1750 /* XXX Print more prettily */ 1751 printf(" Prefetchable memory region:\n"); 1752 printf(" base register: 0x%04x\n", 1753 (regs[o2i(0x24)] >> 0) & 0xffff); 1754 printf(" limit register: 0x%04x\n", 1755 (regs[o2i(0x24)] >> 16) & 0xffff); 1756 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1757 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1758 1759 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1760 printf(" Capability list pointer: 0x%02x\n", 1761 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1762 else 1763 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1764 1765 /* XXX */ 1766 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1767 1768 printf(" Interrupt line: 0x%02x\n", 1769 (regs[o2i(0x3c)] >> 0) & 0xff); 1770 printf(" Interrupt pin: 0x%02x ", 1771 (regs[o2i(0x3c)] >> 8) & 0xff); 1772 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1773 case PCI_INTERRUPT_PIN_NONE: 1774 printf("(none)"); 1775 break; 1776 case PCI_INTERRUPT_PIN_A: 1777 printf("(pin A)"); 1778 break; 1779 case PCI_INTERRUPT_PIN_B: 1780 printf("(pin B)"); 1781 break; 1782 case PCI_INTERRUPT_PIN_C: 1783 printf("(pin C)"); 1784 break; 1785 case PCI_INTERRUPT_PIN_D: 1786 printf("(pin D)"); 1787 break; 1788 default: 1789 printf("(? ? ?)"); 1790 break; 1791 } 1792 printf("\n"); 1793 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1794 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1795 onoff("Parity error response", 0x0001); 1796 onoff("Secondary SERR forwarding", 0x0002); 1797 onoff("ISA enable", 0x0004); 1798 onoff("VGA enable", 0x0008); 1799 onoff("Master abort reporting", 0x0020); 1800 onoff("Secondary bus reset", 0x0040); 1801 onoff("Fast back-to-back capable", 0x0080); 1802 } 1803 1804 static void 1805 pci_conf_print_type2( 1806 #ifdef _KERNEL 1807 pci_chipset_tag_t pc, pcitag_t tag, 1808 #endif 1809 const pcireg_t *regs 1810 #ifdef _KERNEL 1811 , int sizebars 1812 #endif 1813 ) 1814 { 1815 pcireg_t rval; 1816 1817 /* 1818 * XXX these need to be printed in more detail, need to be 1819 * XXX checked against specs/docs, etc. 1820 * 1821 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1822 * controller chip documentation, and may not be correct with 1823 * respect to various standards. (XXX) 1824 */ 1825 1826 #ifdef _KERNEL 1827 pci_conf_print_bar(pc, tag, regs, 0x10, 1828 "CardBus socket/ExCA registers", sizebars); 1829 #else 1830 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1831 #endif 1832 1833 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1834 printf(" Capability list pointer: 0x%02x\n", 1835 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1836 else 1837 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1838 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1839 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1840 1841 printf(" PCI bus number: 0x%02x\n", 1842 (regs[o2i(0x18)] >> 0) & 0xff); 1843 printf(" CardBus bus number: 0x%02x\n", 1844 (regs[o2i(0x18)] >> 8) & 0xff); 1845 printf(" Subordinate bus number: 0x%02x\n", 1846 (regs[o2i(0x18)] >> 16) & 0xff); 1847 printf(" CardBus latency timer: 0x%02x\n", 1848 (regs[o2i(0x18)] >> 24) & 0xff); 1849 1850 /* XXX Print more prettily */ 1851 printf(" CardBus memory region 0:\n"); 1852 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1853 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1854 printf(" CardBus memory region 1:\n"); 1855 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1856 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1857 printf(" CardBus I/O region 0:\n"); 1858 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1859 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1860 printf(" CardBus I/O region 1:\n"); 1861 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1862 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1863 1864 printf(" Interrupt line: 0x%02x\n", 1865 (regs[o2i(0x3c)] >> 0) & 0xff); 1866 printf(" Interrupt pin: 0x%02x ", 1867 (regs[o2i(0x3c)] >> 8) & 0xff); 1868 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1869 case PCI_INTERRUPT_PIN_NONE: 1870 printf("(none)"); 1871 break; 1872 case PCI_INTERRUPT_PIN_A: 1873 printf("(pin A)"); 1874 break; 1875 case PCI_INTERRUPT_PIN_B: 1876 printf("(pin B)"); 1877 break; 1878 case PCI_INTERRUPT_PIN_C: 1879 printf("(pin C)"); 1880 break; 1881 case PCI_INTERRUPT_PIN_D: 1882 printf("(pin D)"); 1883 break; 1884 default: 1885 printf("(? ? ?)"); 1886 break; 1887 } 1888 printf("\n"); 1889 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1890 printf(" Bridge control register: 0x%04x\n", rval); 1891 onoff("Parity error response", __BIT(0)); 1892 onoff("SERR# enable", __BIT(1)); 1893 onoff("ISA enable", __BIT(2)); 1894 onoff("VGA enable", __BIT(3)); 1895 onoff("Master abort mode", __BIT(5)); 1896 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1897 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1898 onoff("Memory window 0 prefetchable", __BIT(8)); 1899 onoff("Memory window 1 prefetchable", __BIT(9)); 1900 onoff("Write posting enable", __BIT(10)); 1901 1902 rval = regs[o2i(0x40)]; 1903 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1904 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1905 1906 #ifdef _KERNEL 1907 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1908 sizebars); 1909 #else 1910 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1911 #endif 1912 } 1913 1914 void 1915 pci_conf_print( 1916 #ifdef _KERNEL 1917 pci_chipset_tag_t pc, pcitag_t tag, 1918 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1919 #else 1920 int pcifd, u_int bus, u_int dev, u_int func 1921 #endif 1922 ) 1923 { 1924 pcireg_t regs[o2i(256)]; 1925 int off, capoff, endoff, hdrtype; 1926 const char *typename; 1927 #ifdef _KERNEL 1928 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1929 int sizebars; 1930 #else 1931 void (*typeprintfn)(const pcireg_t *); 1932 #endif 1933 1934 printf("PCI configuration registers:\n"); 1935 1936 for (off = 0; off < 256; off += 4) { 1937 #ifdef _KERNEL 1938 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1939 #else 1940 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1941 ®s[o2i(off)]) == -1) 1942 regs[o2i(off)] = 0; 1943 #endif 1944 } 1945 1946 #ifdef _KERNEL 1947 sizebars = 1; 1948 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1949 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1950 sizebars = 0; 1951 #endif 1952 1953 /* common header */ 1954 printf(" Common header:\n"); 1955 pci_conf_print_regs(regs, 0, 16); 1956 1957 printf("\n"); 1958 #ifdef _KERNEL 1959 pci_conf_print_common(pc, tag, regs); 1960 #else 1961 pci_conf_print_common(regs); 1962 #endif 1963 printf("\n"); 1964 1965 /* type-dependent header */ 1966 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1967 switch (hdrtype) { /* XXX make a table, eventually */ 1968 case 0: 1969 /* Standard device header */ 1970 typename = "\"normal\" device"; 1971 typeprintfn = &pci_conf_print_type0; 1972 capoff = PCI_CAPLISTPTR_REG; 1973 endoff = 64; 1974 break; 1975 case 1: 1976 /* PCI-PCI bridge header */ 1977 typename = "PCI-PCI bridge"; 1978 typeprintfn = &pci_conf_print_type1; 1979 capoff = PCI_CAPLISTPTR_REG; 1980 endoff = 64; 1981 break; 1982 case 2: 1983 /* PCI-CardBus bridge header */ 1984 typename = "PCI-CardBus bridge"; 1985 typeprintfn = &pci_conf_print_type2; 1986 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1987 endoff = 72; 1988 break; 1989 default: 1990 typename = NULL; 1991 typeprintfn = 0; 1992 capoff = -1; 1993 endoff = 64; 1994 break; 1995 } 1996 printf(" Type %d ", hdrtype); 1997 if (typename != NULL) 1998 printf("(%s) ", typename); 1999 printf("header:\n"); 2000 pci_conf_print_regs(regs, 16, endoff); 2001 printf("\n"); 2002 if (typeprintfn) { 2003 #ifdef _KERNEL 2004 (*typeprintfn)(pc, tag, regs, sizebars); 2005 #else 2006 (*typeprintfn)(regs); 2007 #endif 2008 } else 2009 printf(" Don't know how to pretty-print type %d header.\n", 2010 hdrtype); 2011 printf("\n"); 2012 2013 /* capability list, if present */ 2014 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2015 && (capoff > 0)) { 2016 #ifdef _KERNEL 2017 pci_conf_print_caplist(pc, tag, regs, capoff); 2018 #else 2019 pci_conf_print_caplist(regs, capoff); 2020 #endif 2021 printf("\n"); 2022 } 2023 2024 /* device-dependent header */ 2025 printf(" Device-dependent header:\n"); 2026 pci_conf_print_regs(regs, endoff, 256); 2027 printf("\n"); 2028 #ifdef _KERNEL 2029 if (printfn) 2030 (*printfn)(pc, tag, regs); 2031 else 2032 printf(" Don't know how to pretty-print device-dependent header.\n"); 2033 printf("\n"); 2034 #endif /* _KERNEL */ 2035 } 2036 #endif /* defined(__minix) && defined(_PCI_SERVER) */ 2037