1 /* $NetBSD: pcireg.h,v 1.84 2013/04/21 23:46:06 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Size of each function's configuration space. 45 */ 46 47 #define PCI_CONF_SIZE 0x100 48 #define PCI_EXTCONF_SIZE 0x1000 49 50 /* 51 * Device identification register; contains a vendor ID and a device ID. 52 */ 53 #define PCI_ID_REG 0x00 54 55 typedef u_int16_t pci_vendor_id_t; 56 typedef u_int16_t pci_product_id_t; 57 58 #define PCI_VENDOR_SHIFT 0 59 #define PCI_VENDOR_MASK 0xffff 60 #define PCI_VENDOR(id) \ 61 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 62 63 #define PCI_PRODUCT_SHIFT 16 64 #define PCI_PRODUCT_MASK 0xffff 65 #define PCI_PRODUCT(id) \ 66 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 67 68 #define PCI_ID_CODE(vid,pid) \ 69 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 70 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 71 72 /* 73 * Command and status register. 74 */ 75 #define PCI_COMMAND_STATUS_REG 0x04 76 #define PCI_COMMAND_SHIFT 0 77 #define PCI_COMMAND_MASK 0xffff 78 #define PCI_STATUS_SHIFT 16 79 #define PCI_STATUS_MASK 0xffff 80 81 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 82 ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \ 83 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \ 84 85 #define PCI_COMMAND_IO_ENABLE 0x00000001 86 #define PCI_COMMAND_MEM_ENABLE 0x00000002 87 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 88 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 89 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 90 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 91 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 92 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 93 #define PCI_COMMAND_SERR_ENABLE 0x00000100 94 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 95 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 96 97 #define PCI_STATUS_INT_STATUS 0x00080000 98 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 99 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 100 #define PCI_STATUS_UDF_SUPPORT 0x00400000 101 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 102 #define PCI_STATUS_PARITY_ERROR 0x01000000 103 #define PCI_STATUS_DEVSEL_FAST 0x00000000 104 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 105 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 106 #define PCI_STATUS_DEVSEL_MASK 0x06000000 107 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 108 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 109 #define PCI_STATUS_MASTER_ABORT 0x20000000 110 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 111 #define PCI_STATUS_PARITY_DETECT 0x80000000 112 113 /* 114 * PCI Class and Revision Register; defines type and revision of device. 115 */ 116 #define PCI_CLASS_REG 0x08 117 118 typedef u_int8_t pci_class_t; 119 typedef u_int8_t pci_subclass_t; 120 typedef u_int8_t pci_interface_t; 121 typedef u_int8_t pci_revision_t; 122 123 #define PCI_CLASS_SHIFT 24 124 #define PCI_CLASS_MASK 0xff 125 #define PCI_CLASS(cr) \ 126 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 127 128 #define PCI_SUBCLASS_SHIFT 16 129 #define PCI_SUBCLASS_MASK 0xff 130 #define PCI_SUBCLASS(cr) \ 131 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 132 133 #define PCI_INTERFACE_SHIFT 8 134 #define PCI_INTERFACE_MASK 0xff 135 #define PCI_INTERFACE(cr) \ 136 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 137 138 #define PCI_REVISION_SHIFT 0 139 #define PCI_REVISION_MASK 0xff 140 #define PCI_REVISION(cr) \ 141 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 142 143 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 144 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 145 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 146 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 147 148 /* base classes */ 149 #define PCI_CLASS_PREHISTORIC 0x00 150 #define PCI_CLASS_MASS_STORAGE 0x01 151 #define PCI_CLASS_NETWORK 0x02 152 #define PCI_CLASS_DISPLAY 0x03 153 #define PCI_CLASS_MULTIMEDIA 0x04 154 #define PCI_CLASS_MEMORY 0x05 155 #define PCI_CLASS_BRIDGE 0x06 156 #define PCI_CLASS_COMMUNICATIONS 0x07 157 #define PCI_CLASS_SYSTEM 0x08 158 #define PCI_CLASS_INPUT 0x09 159 #define PCI_CLASS_DOCK 0x0a 160 #define PCI_CLASS_PROCESSOR 0x0b 161 #define PCI_CLASS_SERIALBUS 0x0c 162 #define PCI_CLASS_WIRELESS 0x0d 163 #define PCI_CLASS_I2O 0x0e 164 #define PCI_CLASS_SATCOM 0x0f 165 #define PCI_CLASS_CRYPTO 0x10 166 #define PCI_CLASS_DASP 0x11 167 #define PCI_CLASS_UNDEFINED 0xff 168 169 /* 0x00 prehistoric subclasses */ 170 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 171 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 172 173 /* 0x01 mass storage subclasses */ 174 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 175 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 176 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 177 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 178 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 179 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 180 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 181 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 182 #define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 183 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 184 185 /* 0x02 network subclasses */ 186 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 187 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 188 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 189 #define PCI_SUBCLASS_NETWORK_ATM 0x03 190 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 191 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 192 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 193 #define PCI_SUBCLASS_NETWORK_MISC 0x80 194 195 /* 0x03 display subclasses */ 196 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 197 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 198 #define PCI_SUBCLASS_DISPLAY_3D 0x02 199 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 200 201 /* 0x04 multimedia subclasses */ 202 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 203 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 204 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 205 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 206 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 207 208 /* 0x05 memory subclasses */ 209 #define PCI_SUBCLASS_MEMORY_RAM 0x00 210 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 211 #define PCI_SUBCLASS_MEMORY_MISC 0x80 212 213 /* 0x06 bridge subclasses */ 214 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 215 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 216 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 217 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ 218 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 219 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 220 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 221 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 222 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 223 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 224 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 225 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 226 227 /* 0x07 communications subclasses */ 228 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 229 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 230 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 231 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 232 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 233 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 234 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 235 236 /* 0x08 system subclasses */ 237 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 238 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 239 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 240 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 241 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 242 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 243 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 244 245 /* 0x09 input subclasses */ 246 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 247 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 248 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 249 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 250 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 251 #define PCI_SUBCLASS_INPUT_MISC 0x80 252 253 /* 0x0a dock subclasses */ 254 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 255 #define PCI_SUBCLASS_DOCK_MISC 0x80 256 257 /* 0x0b processor subclasses */ 258 #define PCI_SUBCLASS_PROCESSOR_386 0x00 259 #define PCI_SUBCLASS_PROCESSOR_486 0x01 260 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 261 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 262 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 263 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 264 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 265 266 /* 0x0c serial bus subclasses */ 267 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 268 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 269 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 270 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 271 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 272 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 273 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 274 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 275 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 276 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 277 278 /* 0x0d wireless subclasses */ 279 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 280 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 281 #define PCI_SUBCLASS_WIRELESS_RF 0x10 282 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 283 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 284 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 285 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 286 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 287 288 /* 0x0e I2O (Intelligent I/O) subclasses */ 289 #define PCI_SUBCLASS_I2O_STANDARD 0x00 290 291 /* 0x0f satellite communication subclasses */ 292 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 293 #define PCI_SUBCLASS_SATCOM_TV 0x01 294 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 295 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 296 #define PCI_SUBCLASS_SATCOM_DATA 0x04 297 298 /* 0x10 encryption/decryption subclasses */ 299 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 300 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 301 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 302 303 /* 0x11 data acquisition and signal processing subclasses */ 304 #define PCI_SUBCLASS_DASP_DPIO 0x00 305 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 306 #define PCI_SUBCLASS_DASP_SYNC 0x10 307 #define PCI_SUBCLASS_DASP_MGMT 0x20 308 #define PCI_SUBCLASS_DASP_MISC 0x80 309 310 /* 311 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 312 */ 313 #define PCI_BHLC_REG 0x0c 314 315 #define PCI_BIST_SHIFT 24 316 #define PCI_BIST_MASK 0xff 317 #define PCI_BIST(bhlcr) \ 318 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 319 320 #define PCI_HDRTYPE_SHIFT 16 321 #define PCI_HDRTYPE_MASK 0xff 322 #define PCI_HDRTYPE(bhlcr) \ 323 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 324 325 #define PCI_HDRTYPE_TYPE(bhlcr) \ 326 (PCI_HDRTYPE(bhlcr) & 0x7f) 327 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 328 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 329 330 #define PCI_LATTIMER_SHIFT 8 331 #define PCI_LATTIMER_MASK 0xff 332 #define PCI_LATTIMER(bhlcr) \ 333 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 334 335 #define PCI_CACHELINE_SHIFT 0 336 #define PCI_CACHELINE_MASK 0xff 337 #define PCI_CACHELINE(bhlcr) \ 338 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 339 340 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 341 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 342 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 343 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 344 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 345 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 346 347 /* 348 * PCI header type 349 */ 350 #define PCI_HDRTYPE_DEVICE 0 /* PCI/PCIX/Cardbus */ 351 #define PCI_HDRTYPE_PPB 1 /* PCI/PCIX/Cardbus */ 352 #define PCI_HDRTYPE_PCB 2 /* PCI/PCIX/Cardbus */ 353 #define PCI_HDRTYPE_EP 0 /* PCI Express */ 354 #define PCI_HDRTYPE_RC 1 /* PCI Express */ 355 356 357 /* 358 * Mapping registers 359 */ 360 #define PCI_MAPREG_START 0x10 361 #define PCI_MAPREG_END 0x28 362 #define PCI_MAPREG_ROM 0x30 363 #define PCI_MAPREG_PPB_END 0x18 364 #define PCI_MAPREG_PCB_END 0x14 365 366 #define PCI_BAR0 0x10 367 #define PCI_BAR1 0x14 368 #define PCI_BAR2 0x18 369 #define PCI_BAR3 0x1C 370 #define PCI_BAR4 0x20 371 #define PCI_BAR5 0x24 372 373 #define PCI_BAR(__n) (PCI_MAPREG_START + 4 * (__n)) 374 375 #define PCI_MAPREG_TYPE(mr) \ 376 ((mr) & PCI_MAPREG_TYPE_MASK) 377 #define PCI_MAPREG_TYPE_MASK 0x00000001 378 379 #define PCI_MAPREG_TYPE_MEM 0x00000000 380 #define PCI_MAPREG_TYPE_ROM 0x00000000 381 #define PCI_MAPREG_TYPE_IO 0x00000001 382 #define PCI_MAPREG_ROM_ENABLE 0x00000001 383 384 #define PCI_MAPREG_MEM_TYPE(mr) \ 385 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 386 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 387 388 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 389 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 390 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 391 392 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 393 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 394 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 395 396 #define PCI_MAPREG_MEM_ADDR(mr) \ 397 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 398 #define PCI_MAPREG_MEM_SIZE(mr) \ 399 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 400 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 401 402 #define PCI_MAPREG_MEM64_ADDR(mr) \ 403 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 404 #define PCI_MAPREG_MEM64_SIZE(mr) \ 405 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 406 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 407 408 #define PCI_MAPREG_IO_ADDR(mr) \ 409 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 410 #define PCI_MAPREG_IO_SIZE(mr) \ 411 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 412 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 413 414 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 415 (-(size)) 416 417 #define PCI_MAPREG_NUM(offset) \ 418 (((unsigned)(offset)-PCI_MAPREG_START)/4) 419 420 421 /* 422 * Cardbus CIS pointer (PCI rev. 2.1) 423 */ 424 #define PCI_CARDBUS_CIS_REG 0x28 425 426 /* 427 * Subsystem identification register; contains a vendor ID and a device ID. 428 * Types/macros for PCI_ID_REG apply. 429 * (PCI rev. 2.1) 430 */ 431 #define PCI_SUBSYS_ID_REG 0x2c 432 433 #define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0) 434 #define PCI_SUBSYS_ID_MASK __BITS(31, 16) 435 436 #define PCI_SUBSYS_VENDOR(__subsys_id) \ 437 __SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK) 438 439 #define PCI_SUBSYS_ID(__subsys_id) \ 440 __SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK) 441 442 /* 443 * Capabilities link list (PCI rev. 2.2) 444 */ 445 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 446 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 447 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 448 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 449 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 450 451 #define PCI_CAP_RESERVED0 0x00 452 #define PCI_CAP_PWRMGMT 0x01 453 #define PCI_CAP_AGP 0x02 454 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 455 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 456 #define PCI_CAP_VPD 0x03 457 #define PCI_CAP_SLOTID 0x04 458 #define PCI_CAP_MSI 0x05 459 #define PCI_CAP_CPCI_HOTSWAP 0x06 460 #define PCI_CAP_PCIX 0x07 461 #define PCI_CAP_LDT 0x08 462 #define PCI_CAP_VENDSPEC 0x09 463 #define PCI_CAP_DEBUGPORT 0x0a 464 #define PCI_CAP_CPCI_RSRCCTL 0x0b 465 #define PCI_CAP_HOTPLUG 0x0c 466 #define PCI_CAP_SUBVENDOR 0x0d 467 #define PCI_CAP_AGP8 0x0e 468 #define PCI_CAP_SECURE 0x0f 469 #define PCI_CAP_PCIEXPRESS 0x10 470 #define PCI_CAP_MSIX 0x11 471 #define PCI_CAP_SATA 0x12 472 #define PCI_CAP_PCIAF 0x13 473 474 /* 475 * Vital Product Data; access via capability pointer (PCI rev 2.2). 476 */ 477 #define PCI_VPD_ADDRESS_MASK 0x7fff 478 #define PCI_VPD_ADDRESS_SHIFT 16 479 #define PCI_VPD_ADDRESS(ofs) \ 480 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 481 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 482 #define PCI_VPD_OPFLAG 0x80000000 483 484 #define PCI_MSI_CTL 0x0 /* Message Control Register offset */ 485 #define PCI_MSI_MADDR 0x4 /* Message Address Register (least 486 * significant bits) offset 487 */ 488 #define PCI_MSI_MADDR64_LO 0x4 /* 64-bit Message Address Register 489 * (least significant bits) offset 490 */ 491 #define PCI_MSI_MADDR64_HI 0x8 /* 64-bit Message Address Register 492 * (most significant bits) offset 493 */ 494 #define PCI_MSI_MDATA 0x8 /* Message Data Register offset */ 495 #define PCI_MSI_MDATA64 0xC /* 64-bit Message Data Register 496 * offset 497 */ 498 499 #define PCI_MSI_CTL_MASK __BITS(31, 16) 500 #define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK) 501 #define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK) 502 #define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK) 503 #define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK) 504 #define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK) 505 506 /* 507 * MSI Message Address is at offset 4. 508 * MSI Message Upper Address (if 64bit) is at offset 8. 509 * MSI Message data is at offset 8 or 12 and is 16 bits. 510 * [16 bit reserved field] 511 * MSI Mask Bits (32 bit field) 512 * MSI Pending Bits (32 bit field) 513 */ 514 515 #define PCI_MSIX_CTL_ENABLE 0x80000000 516 #define PCI_MSIX_CTL_FUNCMASK 0x40000000 517 #define PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000 518 #define PCI_MSIX_CTL_TBLSIZE_SHIFT 16 519 #define PCI_MSIX_CTL_TBLSIZE(ofs) (((ofs) >> PCI_MSIX_CTL_TBLSIZE_SHIFT) & PCI_MSIX_CTL_TBLSIZE_MASK) 520 /* 521 * 2nd DWORD is the Table Offset 522 */ 523 #define PCI_MSIX_TBLOFFSET_MASK 0xfffffff8 524 #define PCI_MSIX_TBLBIR_MASK 0x00000007 525 /* 526 * 3rd DWORD is the Pending Bitmap Array Offset 527 */ 528 #define PCI_MSIX_PBAOFFSET_MASK 0xfffffff8 529 #define PCI_MSIX_PBABIR_MASK 0x00000007 530 531 struct pci_msix_table_entry { 532 uint32_t pci_msix_addr_lo; 533 uint32_t pci_msix_addr_hi; 534 uint32_t pci_msix_value; 535 uint32_t pci_msix_vendor_control; 536 }; 537 #define PCI_MSIX_VENDCTL_MASK 0x00000001 538 539 540 /* 541 * Power Management Capability; access via capability pointer. 542 */ 543 544 /* Power Management Capability Register */ 545 #define PCI_PMCR_SHIFT 16 546 #define PCI_PMCR 0x02 547 #define PCI_PMCR_D1SUPP 0x0200 548 #define PCI_PMCR_D2SUPP 0x0400 549 /* Power Management Control Status Register */ 550 #define PCI_PMCSR 0x04 551 #define PCI_PMCSR_PME_EN 0x100 552 #define PCI_PMCSR_STATE_MASK 0x03 553 #define PCI_PMCSR_STATE_D0 0x00 554 #define PCI_PMCSR_STATE_D1 0x01 555 #define PCI_PMCSR_STATE_D2 0x02 556 #define PCI_PMCSR_STATE_D3 0x03 557 #define PCI_PMCSR_PME_STS 0x8000 558 559 /* 560 * PCI-X capability. 561 */ 562 563 /* 564 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 565 * word at the capability; the lower 16 bits are the capability ID and 566 * next capability pointer). 567 * 568 * Since we always read PCI config space in 32-bit words, we define these 569 * as 32-bit values, offset and shifted appropriately. Make sure you perform 570 * the appropriate R/M/W cycles! 571 */ 572 #define PCIX_CMD 0x00 573 #define PCIX_CMD_PERR_RECOVER 0x00010000 574 #define PCIX_CMD_RELAXED_ORDER 0x00020000 575 #define PCIX_CMD_BYTECNT_MASK 0x000c0000 576 #define PCIX_CMD_BYTECNT_SHIFT 18 577 #define PCIX_CMD_BCNT_512 0x00000000 578 #define PCIX_CMD_BCNT_1024 0x00040000 579 #define PCIX_CMD_BCNT_2048 0x00080000 580 #define PCIX_CMD_BCNT_4096 0x000c0000 581 #define PCIX_CMD_SPLTRANS_MASK 0x00700000 582 #define PCIX_CMD_SPLTRANS_1 0x00000000 583 #define PCIX_CMD_SPLTRANS_2 0x00100000 584 #define PCIX_CMD_SPLTRANS_3 0x00200000 585 #define PCIX_CMD_SPLTRANS_4 0x00300000 586 #define PCIX_CMD_SPLTRANS_8 0x00400000 587 #define PCIX_CMD_SPLTRANS_12 0x00500000 588 #define PCIX_CMD_SPLTRANS_16 0x00600000 589 #define PCIX_CMD_SPLTRANS_32 0x00700000 590 591 /* 592 * Status. 32 bits at offset 4. 593 */ 594 #define PCIX_STATUS 0x04 595 #define PCIX_STATUS_FN_MASK 0x00000007 596 #define PCIX_STATUS_DEV_MASK 0x000000f8 597 #define PCIX_STATUS_BUS_MASK 0x0000ff00 598 #define PCIX_STATUS_64BIT 0x00010000 599 #define PCIX_STATUS_133 0x00020000 600 #define PCIX_STATUS_SPLDISC 0x00040000 601 #define PCIX_STATUS_SPLUNEX 0x00080000 602 #define PCIX_STATUS_DEVCPLX 0x00100000 603 #define PCIX_STATUS_MAXB_MASK 0x00600000 604 #define PCIX_STATUS_MAXB_SHIFT 21 605 #define PCIX_STATUS_MAXB_512 0x00000000 606 #define PCIX_STATUS_MAXB_1024 0x00200000 607 #define PCIX_STATUS_MAXB_2048 0x00400000 608 #define PCIX_STATUS_MAXB_4096 0x00600000 609 #define PCIX_STATUS_MAXST_MASK 0x03800000 610 #define PCIX_STATUS_MAXST_1 0x00000000 611 #define PCIX_STATUS_MAXST_2 0x00800000 612 #define PCIX_STATUS_MAXST_3 0x01000000 613 #define PCIX_STATUS_MAXST_4 0x01800000 614 #define PCIX_STATUS_MAXST_8 0x02000000 615 #define PCIX_STATUS_MAXST_12 0x02800000 616 #define PCIX_STATUS_MAXST_16 0x03000000 617 #define PCIX_STATUS_MAXST_32 0x03800000 618 #define PCIX_STATUS_MAXRS_MASK 0x1c000000 619 #define PCIX_STATUS_MAXRS_1K 0x00000000 620 #define PCIX_STATUS_MAXRS_2K 0x04000000 621 #define PCIX_STATUS_MAXRS_4K 0x08000000 622 #define PCIX_STATUS_MAXRS_8K 0x0c000000 623 #define PCIX_STATUS_MAXRS_16K 0x10000000 624 #define PCIX_STATUS_MAXRS_32K 0x14000000 625 #define PCIX_STATUS_MAXRS_64K 0x18000000 626 #define PCIX_STATUS_MAXRS_128K 0x1c000000 627 #define PCIX_STATUS_SCERR 0x20000000 628 629 /* 630 * PCI Express; access via capability pointer. 631 */ 632 #define PCIE_XCAP 0x00 /* Capability List & Capabilities Register */ 633 #define PCIE_XCAP_MASK __BITS(31, 16) 634 /* Capability Version */ 635 #define PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK) 636 #define PCIE_XCAP_VER_1_0 __SHIFTIN(1, PCIE_XCAP_VER_MASK) 637 #define PCIE_XCAP_VER_2_0 __SHIFTIN(2, PCIE_XCAP_VER_MASK) 638 #define PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK) 639 #define PCIE_XCAP_TYPE_PCIE_DEV __SHIFTIN(0x0, PCIE_XCAP_TYPE_MASK) 640 #define PCIE_XCAP_TYPE_PCI_DEV __SHIFTIN(0x1, PCIE_XCAP_TYPE_MASK) 641 #define PCIE_XCAP_TYPE_ROOT __SHIFTIN(0x4, PCIE_XCAP_TYPE_MASK) 642 #define PCIE_XCAP_TYPE_UP __SHIFTIN(0x5, PCIE_XCAP_TYPE_MASK) 643 #define PCIE_XCAP_TYPE_DOWN __SHIFTIN(0x6, PCIE_XCAP_TYPE_MASK) 644 #define PCIE_XCAP_TYPE_PCIE2PCI __SHIFTIN(0x7, PCIE_XCAP_TYPE_MASK) 645 #define PCIE_XCAP_TYPE_PCI2PCIE __SHIFTIN(0x8, PCIE_XCAP_TYPE_MASK) 646 #define PCIE_XCAP_TYPE_ROOT_INTEP __SHIFTIN(0x9, PCIE_XCAP_TYPE_MASK) 647 #define PCIE_XCAP_TYPE_ROOT_EVNTC __SHIFTIN(0xa, PCIE_XCAP_TYPE_MASK) 648 #define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */ 649 #define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK) 650 #define PCIE_DCAP 0x04 /* Device Capabilities Register */ 651 #define PCIE_DCAP_MAX_PAYLOAD __BITS(2, 0) /* Max Payload Size Supported */ 652 #define PCIE_DCAP_PHANTOM_FUNCS __BITS(4, 3) /* Phantom Functions Supported*/ 653 #define PCIE_DCAP_EXT_TAG_FIELD __BIT(5) /* Extended Tag Field Support */ 654 #define PCIE_DCAP_L0S_LATENCY __BITS(8, 6) /* Endpoint L0 Accptbl Latency*/ 655 #define PCIE_DCAP_L1_LATENCY __BITS(11, 9) /* Endpoint L1 Accptbl Latency*/ 656 #define PCIE_DCAP_ATTN_BUTTON __BIT(12) /* Attention Indicator Button */ 657 #define PCIE_DCAP_ATTN_IND __BIT(13) /* Attention Indicator Present*/ 658 #define PCIE_DCAP_PWR_IND __BIT(14) /* Power Indicator Present */ 659 #define PCIE_DCAP_ROLE_ERR_RPT __BIT(15) /* Role-Based Error Reporting */ 660 #define PCIE_DCAP_SLOT_PWR_LIM_VAL __BITS(25, 18) /* Cap. Slot PWR Limit Val */ 661 #define PCIE_DCAP_SLOT_PWR_LIM_SCALE __BITS(27, 26) /* Cap. SlotPWRLimit Scl */ 662 #define PCIE_DCAP_FLR __BIT(28) /* Function-Level Reset Cap. */ 663 #define PCIE_DCSR 0x08 /* Device Control & Status Register */ 664 #define PCIE_DCSR_ENA_COR_ERR __BIT(0) /* Correctable Error Report En*/ 665 #define PCIE_DCSR_ENA_NFER __BIT(1) /* Non-Fatal Error Report En. */ 666 #define PCIE_DCSR_ENA_FER __BIT(2) /* Fatal Error Reporting Enabl*/ 667 #define PCIE_DCSR_ENA_URR __BIT(3) /* Unsupported Request Rpt En */ 668 #define PCIE_DCSR_ENA_RELAX_ORD __BIT(4) /* Enable Relaxed Ordering */ 669 #define PCIE_DCSR_MAX_PAYLOAD __BITS(7, 5) /* Max Payload Size */ 670 #define PCIE_DCSR_EXT_TAG_FIELD __BIT(8) /* Extended Tag Field Enable */ 671 #define PCIE_DCSR_PHANTOM_FUNCS __BIT(9) /* Phantom Functions Enable */ 672 #define PCIE_DCSR_AUX_POWER_PM __BIT(10) /* Aux Power PM Enable */ 673 #define PCIE_DCSR_ENA_NO_SNOOP __BIT(11) /* Enable No Snoop */ 674 #define PCIE_DCSR_MAX_READ_REQ __BITS(14, 12) /* Max Read Request Size */ 675 #define PCIE_DCSR_BRDG_CFG_RETRY __BIT(15) /* Bridge Config Retry Enable */ 676 #define PCIE_DCSR_INITIATE_FLR __BIT(15) /* Initiate Function-Level Rst*/ 677 #define PCIE_DCSR_CED __BIT(0 + 16) /* Correctable Error Detected */ 678 #define PCIE_DCSR_NFED __BIT(1 + 16) /* Non-Fatal Error Detected */ 679 #define PCIE_DCSR_FED __BIT(2 + 16) /* Fatal Error Detected */ 680 #define PCIE_DCSR_URD __BIT(3 + 16) /* Unsupported Req. Detected */ 681 #define PCIE_DCSR_AUX_PWR __BIT(4 + 16) /* Aux Power Detected */ 682 #define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */ 683 #define PCIE_LCAP 0x0c /* Link Capabilities Register */ 684 #define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */ 685 #define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */ 686 #define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */ 687 #define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */ 688 #define PCIE_LCAP_L1_EXIT __BITS(17, 15) /* L1 Exit Latency */ 689 #define PCIE_LCAP_CLOCK_PM __BIT(18) /* Clock Power Management */ 690 #define PCIE_LCAP_SURPRISE_DOWN __BIT(19) /* Surprise Down Err Rpt Cap. */ 691 #define PCIE_LCAP_DL_ACTIVE __BIT(20) /* Data Link Layer Link Active*/ 692 #define PCIE_LCAP_LINK_BW_NOTIFY __BIT(21) /* Link BW Notification Capabl*/ 693 #define PCIE_LCAP_ASPM_COMPLIANCE __BIT(22) /* ASPM Optionally Compliance */ 694 #define PCIE_LCAP_PORT __BITS(31, 24) /* Port Number */ 695 #define PCIE_LCSR 0x10 /* Link Control & Status Register */ 696 #define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/ 697 #define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */ 698 #define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundry Ctl*/ 699 #define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */ 700 #define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */ 701 #define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */ 702 #define PCIE_LCSR_EXTNDSYNC __BIT(7) /* Extended Synch */ 703 #define PCIE_LCSR_ENCLKPM __BIT(8) /* Enable Clock Power Managmt */ 704 #define PCIE_LCSR_HAWD __BIT(9) /* HW Autonomous Width Disable*/ 705 #define PCIE_LCSR_LBMIE __BIT(10) /* Link BW Management Intr En */ 706 #define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */ 707 #define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */ 708 #define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */ 709 #define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */ 710 #define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */ 711 #define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */ 712 #define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/ 713 #define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */ 714 #define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */ 715 #define PCIE_SLCAP 0x14 /* Slot Capabilities Register */ 716 #define PCIE_SLCAP_ABP __BIT(0) /* Attention Button Present */ 717 #define PCIE_SLCAP_PCP __BIT(1) /* Power Controller Present */ 718 #define PCIE_SLCAP_MSP __BIT(2) /* MRL Sensor Present */ 719 #define PCIE_SLCAP_AIP __BIT(3) /* Attention Indicator Present*/ 720 #define PCIE_SLCAP_PIP __BIT(4) /* Power Indicator Present */ 721 #define PCIE_SLCAP_HPS __BIT(5) /* Hot-Plug Surprise */ 722 #define PCIE_SLCAP_HPC __BIT(6) /* Hot-Plug Capable */ 723 #define PCIE_SLCAP_SPLV __BITS(14, 7) /* Slot Power Limit Value */ 724 #define PCIE_SLCAP_SPLS __BITS(16, 15) /* Slot Power Limit Scale */ 725 #define PCIE_SLCAP_EIP __BIT(17) /* Electromechanical Interlock*/ 726 #define PCIE_SLCAP_NCCS __BIT(18) /* No Command Completed Supp. */ 727 #define PCIE_SLCAP_PSN __BITS(31, 19) /* Physical Slot Number */ 728 #define PCIE_SLCSR 0x18 /* Slot Control & Status Register */ 729 #define PCIE_SLCSR_ABE __BIT(0) /* Attention Button Pressed En*/ 730 #define PCIE_SLCSR_PFE __BIT(1) /* Power Button Pressed Enable*/ 731 #define PCIE_SLCSR_MSE __BIT(2) /* MRL Sensor Changed Enable */ 732 #define PCIE_SLCSR_PDE __BIT(3) /* Presence Detect Changed Ena*/ 733 #define PCIE_SLCSR_CCE __BIT(4) /* Command Completed Intr. En */ 734 #define PCIE_SLCSR_HPE __BIT(5) /* Hot Plug Interrupt Enable */ 735 #define PCIE_SLCSR_AIC __BITS(7, 6) /* Attention Indicator Control*/ 736 #define PCIE_SLCSR_PIC __BITS(9, 8) /* Power Indicator Control */ 737 #define PCIE_SLCSR_PCC __BIT(10) /* Power Controller Control */ 738 #define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/ 739 #define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/ 740 #define PCIE_SLCSR_ABP __BIT(0 + 16) /* Attention Button Pressed */ 741 #define PCIE_SLCSR_PFD __BIT(1 + 16) /* Power Fault Detected */ 742 #define PCIE_SLCSR_MSC __BIT(2 + 16) /* MRL Sensor Changed */ 743 #define PCIE_SLCSR_PDC __BIT(3 + 16) /* Presence Detect Changed */ 744 #define PCIE_SLCSR_CC __BIT(4 + 16) /* Command Completed */ 745 #define PCIE_SLCSR_MS __BIT(5 + 16) /* MRL Sensor State */ 746 #define PCIE_SLCSR_PDS __BIT(6 + 16) /* Presence Detect State */ 747 #define PCIE_SLCSR_EIS __BIT(7 + 16) /* Electromechanical Interlock*/ 748 #define PCIE_SLCSR_LACS __BIT(8 + 16) /* Data Link Layer State Chg. */ 749 #define PCIE_RCR 0x1c /* Root Control & Capabilities Reg. */ 750 #define PCIE_RCR_SERR_CER __BIT(0) /* SERR on Correctable Err. En*/ 751 #define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */ 752 #define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */ 753 #define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */ 754 #define PCIE_RSR 0x20 /* Root Status Register */ 755 #define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */ 756 #define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */ 757 #define PCIE_RSR_PME_PEND __BIT(17) /* PME Pending */ 758 #define PCIE_DCAP2 0x24 /* Device Capabilities 2 Register */ 759 #define PCIE_DCAP2_COMPT_RANGE __BITS(3,0) /* Compl. Timeout Ranges Supp */ 760 #define PCIE_DCAP2_COMPT_DIS __BIT(4) /* Compl. Timeout Disable Supp*/ 761 #define PCIE_DCAP2_ARI_FWD __BIT(5) /* ARI Forward Supported */ 762 #define PCIE_DCAP2_ATOM_ROUT __BIT(6) /* AtomicOp Routing Supported */ 763 #define PCIE_DCAP2_32ATOM __BIT(7) /* 32bit AtomicOp Compl. Supp */ 764 #define PCIE_DCAP2_64ATOM __BIT(8) /* 64bit AtomicOp Compl. Supp */ 765 #define PCIE_DCAP2_128CAS __BIT(9) /* 128bit Cas Completer Supp. */ 766 #define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */ 767 #define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */ 768 #define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */ 769 #define PCIE_DCAP2_OBFF __BITS(19, 18) /* OBPF */ 770 #define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */ 771 #define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */ 772 #define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */ 773 #define PCIE_DCSR2 0x28 /* Device Control & Status 2 Register */ 774 #define PCIE_DCSR2_COMPT_VAL __BITS(3, 0) /* Completion Timeout Value */ 775 #define PCIE_DCSR2_COMPT_DIS __BIT(4) /* Completion Timeout Disable */ 776 #define PCIE_DCSR2_ARI_FWD __BIT(5) /* ARI Forwarding Enable */ 777 #define PCIE_DCSR2_ATOM_REQ __BIT(6) /* AtomicOp Requester Enable */ 778 #define PCIE_DCSR2_ATOM_EBLK __BIT(7) /* AtomicOp Egress Blocking */ 779 #define PCIE_DCSR2_IDO_REQ __BIT(8) /* IDO Request Enable */ 780 #define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */ 781 #define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */ 782 #define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBPF Enable */ 783 #define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */ 784 #define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */ 785 #define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */ 786 #define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */ 787 #define PCIE_LCSR2 0x30 /* Link Control & Status 2 Register */ 788 #define PCIE_LCSR2_TGT_LSPEED __BITS(3, 0) /* Target Link Speed */ 789 #define PCIE_LCSR2_ENT_COMPL __BIT(4) /* Enter Compliance */ 790 #define PCIE_LCSR2_HW_AS_DIS __BIT(5) /* HW Autonomous Speed Disabl */ 791 #define PCIE_LCSR2_SEL_DEEMP __BIT(6) /* Selectable De-emphasis */ 792 #define PCIE_LCSR2_TX_MARGIN __BITS(9, 7) /* Transmit Margin */ 793 #define PCIE_LCSR2_EN_MCOMP __BIT(10) /* Enter Modified Compliance */ 794 #define PCIE_LCSR2_COMP_SOS __BIT(11) /* Compliance SOS */ 795 #define PCIE_LCSR2_COMP_DEEMP __BITS(15, 12) /* Compliance Present/De-emph */ 796 #define PCIE_LCSR2_DEEMP_LVL __BIT(0 + 16) /* Current De-emphasis Level */ 797 #define PCIE_LCSR2_EQ_COMPL __BIT(1 + 16) /* Equalization Complete */ 798 #define PCIE_LCSR2_EQP1_SUC __BIT(2 + 16) /* Equaliz Phase 1 Successful */ 799 #define PCIE_LCSR2_EQP2_SUC __BIT(3 + 16) /* Equaliz Phase 2 Successful */ 800 #define PCIE_LCSR2_EQP3_SUC __BIT(4 + 16) /* Equaliz Phase 3 Successful */ 801 #define PCIE_LCSR2_LNKEQ_REQ __BIT(5 + 16) /* Link Equalization Request */ 802 803 #define PCIE_SLCAP2 0x34 /* Slot Capabilities 2 Register */ 804 #define PCIE_SLCSR2 0x38 /* Slot Control & Status 2 Register */ 805 806 /* 807 * Interrupt Configuration Register; contains interrupt pin and line. 808 */ 809 #define PCI_INTERRUPT_REG 0x3c 810 811 typedef u_int8_t pci_intr_latency_t; 812 typedef u_int8_t pci_intr_grant_t; 813 typedef u_int8_t pci_intr_pin_t; 814 typedef u_int8_t pci_intr_line_t; 815 816 #define PCI_MAX_LAT_SHIFT 24 817 #define PCI_MAX_LAT_MASK 0xff 818 #define PCI_MAX_LAT(icr) \ 819 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 820 821 #define PCI_MIN_GNT_SHIFT 16 822 #define PCI_MIN_GNT_MASK 0xff 823 #define PCI_MIN_GNT(icr) \ 824 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 825 826 #define PCI_INTERRUPT_GRANT_SHIFT 24 827 #define PCI_INTERRUPT_GRANT_MASK 0xff 828 #define PCI_INTERRUPT_GRANT(icr) \ 829 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 830 831 #define PCI_INTERRUPT_LATENCY_SHIFT 16 832 #define PCI_INTERRUPT_LATENCY_MASK 0xff 833 #define PCI_INTERRUPT_LATENCY(icr) \ 834 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 835 836 #define PCI_INTERRUPT_PIN_SHIFT 8 837 #define PCI_INTERRUPT_PIN_MASK 0xff 838 #define PCI_INTERRUPT_PIN(icr) \ 839 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 840 841 #define PCI_INTERRUPT_LINE_SHIFT 0 842 #define PCI_INTERRUPT_LINE_MASK 0xff 843 #define PCI_INTERRUPT_LINE(icr) \ 844 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 845 846 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 847 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 848 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 849 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 850 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 851 852 #define PCI_INTERRUPT_PIN_NONE 0x00 853 #define PCI_INTERRUPT_PIN_A 0x01 854 #define PCI_INTERRUPT_PIN_B 0x02 855 #define PCI_INTERRUPT_PIN_C 0x03 856 #define PCI_INTERRUPT_PIN_D 0x04 857 #define PCI_INTERRUPT_PIN_MAX 0x04 858 859 /* Header Type 1 (Bridge) configuration registers */ 860 #define PCI_BRIDGE_BUS_REG 0x18 861 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 862 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 863 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 864 865 #define PCI_BRIDGE_STATIO_REG 0x1C 866 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 867 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 868 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 869 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 870 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 871 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 872 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 873 874 #define PCI_BRIDGE_MEMORY_REG 0x20 875 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 876 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 877 #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff 878 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff 879 880 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 881 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 882 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 883 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff 884 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff 885 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 886 887 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 888 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 889 890 #define PCI_BRIDGE_IOHIGH_REG 0x30 891 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 892 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 893 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 894 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 895 896 #define PCI_BRIDGE_CONTROL_REG 0x3C 897 #define PCI_BRIDGE_CONTROL_SHIFT 16 898 #define PCI_BRIDGE_CONTROL_MASK 0xffff 899 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 900 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 901 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 902 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 903 /* Reserved (1 << 4) */ 904 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 905 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 906 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 907 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 908 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 909 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 910 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 911 /* Reserved (1 << 12) - (1 << 15) */ 912 913 /* 914 * Vital Product Data resource tags. 915 */ 916 struct pci_vpd_smallres { 917 uint8_t vpdres_byte0; /* length of data + tag */ 918 /* Actual data. */ 919 } __packed; 920 921 struct pci_vpd_largeres { 922 uint8_t vpdres_byte0; 923 uint8_t vpdres_len_lsb; /* length of data only */ 924 uint8_t vpdres_len_msb; 925 /* Actual data. */ 926 } __packed; 927 928 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 929 930 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 931 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 932 933 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 934 935 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 936 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 937 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 938 939 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 940 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 941 942 struct pci_vpd { 943 uint8_t vpd_key0; 944 uint8_t vpd_key1; 945 uint8_t vpd_len; /* length of data only */ 946 /* Actual data. */ 947 } __packed; 948 949 /* 950 * Recommended VPD fields: 951 * 952 * PN Part number of assembly 953 * FN FRU part number 954 * EC EC level of assembly 955 * MN Manufacture ID 956 * SN Serial Number 957 * 958 * Conditionally recommended VPD fields: 959 * 960 * LI Load ID 961 * RL ROM Level 962 * RM Alterable ROM Level 963 * NA Network Address 964 * DD Device Driver Level 965 * DG Diagnostic Level 966 * LL Loadable Microcode Level 967 * VI Vendor ID/Device ID 968 * FU Function Number 969 * SI Subsystem Vendor ID/Subsystem ID 970 * 971 * Additional VPD fields: 972 * 973 * Z0-ZZ User/Product Specific 974 */ 975 976 /* 977 * PCI Expansion Rom 978 */ 979 980 struct pci_rom_header { 981 uint16_t romh_magic; /* 0xAA55 little endian */ 982 uint8_t romh_reserved[22]; 983 uint16_t romh_data_ptr; /* pointer to pci_rom struct */ 984 } __packed; 985 986 #define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */ 987 988 struct pci_rom { 989 uint32_t rom_signature; 990 pci_vendor_id_t rom_vendor; 991 pci_product_id_t rom_product; 992 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ 993 uint16_t rom_data_len; 994 uint8_t rom_data_rev; 995 pci_interface_t rom_interface; /* the class reg is 24-bits */ 996 pci_subclass_t rom_subclass; /* in little endian */ 997 pci_class_t rom_class; 998 uint16_t rom_len; /* code length / 512 byte */ 999 uint16_t rom_rev; /* code revision level */ 1000 uint8_t rom_code_type; /* type of code */ 1001 uint8_t rom_indicator; 1002 uint16_t rom_reserved; 1003 /* Actual data. */ 1004 } __packed; 1005 1006 #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ 1007 #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ 1008 #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ 1009 #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ 1010 #define PCI_ROM_CODE_TYPE_EFI 3 /* EFI Image */ 1011 1012 #define PCI_ROM_INDICATOR_LAST 0x80 1013 1014 /* 1015 * Threshold below which 32bit PCI DMA needs bouncing. 1016 */ 1017 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 1018 1019 /* 1020 * PCI-X 2.0 Extended Capability List 1021 */ 1022 1023 #define PCI_EXTCAPLIST_BASE 0x100 1024 1025 #define PCI_EXTCAPLIST_CAP(ecr) ((ecr) & 0xffff) 1026 #define PCI_EXTCAPLIST_VERSION(ecr) (((ecr) >> 16) & 0xf) 1027 #define PCI_EXTCAPLIST_NEXT(ecr) (((ecr) >> 20) & 0xfff) 1028 1029 #endif /* _DEV_PCI_PCIREG_H_ */ 1030