106f32e7eSjoerg//=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 ---*- tablegen -*-=// 206f32e7eSjoerg// 306f32e7eSjoerg// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 406f32e7eSjoerg// See https://llvm.org/LICENSE.txt for license information. 506f32e7eSjoerg// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 606f32e7eSjoerg// 706f32e7eSjoerg//===----------------------------------------------------------------------===// 806f32e7eSjoerg// 906f32e7eSjoerg// This file defines the scheduling model for Cavium ThunderX2T99 1006f32e7eSjoerg// processors. 1106f32e7eSjoerg// Based on Broadcom Vulcan. 1206f32e7eSjoerg// 1306f32e7eSjoerg//===----------------------------------------------------------------------===// 1406f32e7eSjoerg 1506f32e7eSjoerg//===----------------------------------------------------------------------===// 1606f32e7eSjoerg// 2. Pipeline Description. 1706f32e7eSjoerg 1806f32e7eSjoergdef ThunderX2T99Model : SchedMachineModel { 1906f32e7eSjoerg let IssueWidth = 4; // 4 micro-ops dispatched at a time. 2006f32e7eSjoerg let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer. 2106f32e7eSjoerg let LoadLatency = 4; // Optimistic load latency. 2206f32e7eSjoerg let MispredictPenalty = 12; // Extra cycles for mispredicted branch. 2306f32e7eSjoerg // Determined via a mix of micro-arch details and experimentation. 2406f32e7eSjoerg let LoopMicroOpBufferSize = 128; 2506f32e7eSjoerg let PostRAScheduler = 1; // Using PostRA sched. 2606f32e7eSjoerg let CompleteModel = 1; 2706f32e7eSjoerg 28*da58b97aSjoerg list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 29*da58b97aSjoerg PAUnsupported.F); 3006f32e7eSjoerg // FIXME: Remove when all errors have been fixed. 3106f32e7eSjoerg let FullInstRWOverlapCheck = 0; 3206f32e7eSjoerg} 3306f32e7eSjoerg 3406f32e7eSjoerglet SchedModel = ThunderX2T99Model in { 3506f32e7eSjoerg 3606f32e7eSjoerg// Define the issue ports. 3706f32e7eSjoerg 3806f32e7eSjoerg// Port 0: ALU, FP/SIMD. 3906f32e7eSjoergdef THX2T99P0 : ProcResource<1>; 4006f32e7eSjoerg 4106f32e7eSjoerg// Port 1: ALU, FP/SIMD, integer mul/div. 4206f32e7eSjoergdef THX2T99P1 : ProcResource<1>; 4306f32e7eSjoerg 4406f32e7eSjoerg// Port 2: ALU, Branch. 4506f32e7eSjoergdef THX2T99P2 : ProcResource<1>; 4606f32e7eSjoerg 4706f32e7eSjoerg// Port 3: Store data. 4806f32e7eSjoergdef THX2T99P3 : ProcResource<1>; 4906f32e7eSjoerg 5006f32e7eSjoerg// Port 4: Load/store. 5106f32e7eSjoergdef THX2T99P4 : ProcResource<1>; 5206f32e7eSjoerg 5306f32e7eSjoerg// Port 5: Load/store. 5406f32e7eSjoergdef THX2T99P5 : ProcResource<1>; 5506f32e7eSjoerg 5606f32e7eSjoerg// Define groups for the functional units on each issue port. Each group 5706f32e7eSjoerg// created will be used by a WriteRes later on. 5806f32e7eSjoerg// 5906f32e7eSjoerg// NOTE: Some groups only contain one member. This is a way to create names for 6006f32e7eSjoerg// the various functional units that share a single issue port. For example, 6106f32e7eSjoerg// "THX2T99I1" for ALU ops on port 1 and "THX2T99F1" for FP ops on port 1. 6206f32e7eSjoerg 6306f32e7eSjoerg// Integer divide and multiply micro-ops only on port 1. 6406f32e7eSjoergdef THX2T99I1 : ProcResGroup<[THX2T99P1]>; 6506f32e7eSjoerg 6606f32e7eSjoerg// Branch micro-ops only on port 2. 6706f32e7eSjoergdef THX2T99I2 : ProcResGroup<[THX2T99P2]>; 6806f32e7eSjoerg 6906f32e7eSjoerg// ALU micro-ops on ports 0, 1, and 2. 7006f32e7eSjoergdef THX2T99I012 : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2]>; 7106f32e7eSjoerg 7206f32e7eSjoerg// Crypto FP/SIMD micro-ops only on port 1. 7306f32e7eSjoergdef THX2T99F1 : ProcResGroup<[THX2T99P1]>; 7406f32e7eSjoerg 7506f32e7eSjoerg// FP/SIMD micro-ops on ports 0 and 1. 7606f32e7eSjoergdef THX2T99F01 : ProcResGroup<[THX2T99P0, THX2T99P1]>; 7706f32e7eSjoerg 7806f32e7eSjoerg// Store data micro-ops only on port 3. 7906f32e7eSjoergdef THX2T99SD : ProcResGroup<[THX2T99P3]>; 8006f32e7eSjoerg 8106f32e7eSjoerg// Load/store micro-ops on ports 4 and 5. 8206f32e7eSjoergdef THX2T99LS01 : ProcResGroup<[THX2T99P4, THX2T99P5]>; 8306f32e7eSjoerg 8406f32e7eSjoerg// 60 entry unified scheduler. 8506f32e7eSjoergdef THX2T99Any : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2, 8606f32e7eSjoerg THX2T99P3, THX2T99P4, THX2T99P5]> { 8706f32e7eSjoerg let BufferSize = 60; 8806f32e7eSjoerg} 8906f32e7eSjoerg 9006f32e7eSjoerg// Define commonly used write types for InstRW specializations. 9106f32e7eSjoerg// All definitions follow the format: THX2T99Write_<NumCycles>Cyc_<Resources>. 9206f32e7eSjoerg 9306f32e7eSjoerg// 3 cycles on I1. 9406f32e7eSjoergdef THX2T99Write_3Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 9506f32e7eSjoerg let Latency = 3; 9606f32e7eSjoerg let NumMicroOps = 2; 9706f32e7eSjoerg} 9806f32e7eSjoerg 9906f32e7eSjoerg// 1 cycles on I2. 10006f32e7eSjoergdef THX2T99Write_1Cyc_I2 : SchedWriteRes<[THX2T99I2]> { 10106f32e7eSjoerg let Latency = 1; 10206f32e7eSjoerg let NumMicroOps = 2; 10306f32e7eSjoerg} 10406f32e7eSjoerg 10506f32e7eSjoerg// 4 cycles on I1. 10606f32e7eSjoergdef THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 10706f32e7eSjoerg let Latency = 4; 10806f32e7eSjoerg let NumMicroOps = 2; 10906f32e7eSjoerg} 11006f32e7eSjoerg 11106f32e7eSjoerg// 23 cycles on I1. 11206f32e7eSjoergdef THX2T99Write_23Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 11306f32e7eSjoerg let Latency = 23; 11406f32e7eSjoerg let ResourceCycles = [13, 23]; 11506f32e7eSjoerg let NumMicroOps = 4; 11606f32e7eSjoerg} 11706f32e7eSjoerg 11806f32e7eSjoerg// 39 cycles on I1. 11906f32e7eSjoergdef THX2T99Write_39Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 12006f32e7eSjoerg let Latency = 39; 12106f32e7eSjoerg let ResourceCycles = [13, 39]; 12206f32e7eSjoerg let NumMicroOps = 4; 12306f32e7eSjoerg} 12406f32e7eSjoerg 12506f32e7eSjoerg// 1 cycle on I0, I1, or I2. 12606f32e7eSjoergdef THX2T99Write_1Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 12706f32e7eSjoerg let Latency = 1; 12806f32e7eSjoerg let NumMicroOps = 2; 12906f32e7eSjoerg} 13006f32e7eSjoerg 13106f32e7eSjoerg// 2 cycles on I0, I1, or I2. 13206f32e7eSjoergdef THX2T99Write_2Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 13306f32e7eSjoerg let Latency = 2; 13406f32e7eSjoerg let NumMicroOps = 2; 13506f32e7eSjoerg} 13606f32e7eSjoerg 13706f32e7eSjoerg// 4 cycles on I0, I1, or I2. 13806f32e7eSjoergdef THX2T99Write_4Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 13906f32e7eSjoerg let Latency = 2; 14006f32e7eSjoerg let NumMicroOps = 3; 14106f32e7eSjoerg} 14206f32e7eSjoerg 14306f32e7eSjoerg// 5 cycles on I0, I1, or I2. 14406f32e7eSjoergdef THX2T99Write_5Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 14506f32e7eSjoerg let Latency = 2; 14606f32e7eSjoerg let NumMicroOps = 3; 14706f32e7eSjoerg} 14806f32e7eSjoerg 14906f32e7eSjoerg// 5 cycles on F1. 15006f32e7eSjoergdef THX2T99Write_5Cyc_F1 : SchedWriteRes<[THX2T99F1]> { 15106f32e7eSjoerg let Latency = 5; 15206f32e7eSjoerg let NumMicroOps = 2; 15306f32e7eSjoerg} 15406f32e7eSjoerg 15506f32e7eSjoerg// 7 cycles on F1. 15606f32e7eSjoergdef THX2T99Write_7Cyc_F1 : SchedWriteRes<[THX2T99F1]> { 15706f32e7eSjoerg let Latency = 7; 15806f32e7eSjoerg let NumMicroOps = 2; 15906f32e7eSjoerg} 16006f32e7eSjoerg 16106f32e7eSjoerg// 4 cycles on F0 or F1. 16206f32e7eSjoergdef THX2T99Write_4Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 16306f32e7eSjoerg let Latency = 4; 16406f32e7eSjoerg let NumMicroOps = 2; 16506f32e7eSjoerg} 16606f32e7eSjoerg 16706f32e7eSjoerg// 5 cycles on F0 or F1. 16806f32e7eSjoergdef THX2T99Write_5Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 16906f32e7eSjoerg let Latency = 5; 17006f32e7eSjoerg let NumMicroOps = 2; 17106f32e7eSjoerg} 17206f32e7eSjoerg 17306f32e7eSjoerg// 6 cycles on F0 or F1. 17406f32e7eSjoergdef THX2T99Write_6Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 17506f32e7eSjoerg let Latency = 6; 17606f32e7eSjoerg let NumMicroOps = 3; 17706f32e7eSjoerg} 17806f32e7eSjoerg 17906f32e7eSjoerg// 7 cycles on F0 or F1. 18006f32e7eSjoergdef THX2T99Write_7Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 18106f32e7eSjoerg let Latency = 7; 18206f32e7eSjoerg let NumMicroOps = 3; 18306f32e7eSjoerg} 18406f32e7eSjoerg 18506f32e7eSjoerg// 8 cycles on F0 or F1. 18606f32e7eSjoergdef THX2T99Write_8Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 18706f32e7eSjoerg let Latency = 8; 18806f32e7eSjoerg let NumMicroOps = 3; 18906f32e7eSjoerg} 19006f32e7eSjoerg 19106f32e7eSjoerg// 10 cycles on F0 or F1. 19206f32e7eSjoergdef THX2T99Write_10Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 19306f32e7eSjoerg let Latency = 10; 19406f32e7eSjoerg let NumMicroOps = 3; 19506f32e7eSjoerg} 19606f32e7eSjoerg 19706f32e7eSjoerg// 16 cycles on F0 or F1. 19806f32e7eSjoergdef THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 19906f32e7eSjoerg let Latency = 16; 20006f32e7eSjoerg let NumMicroOps = 3; 20106f32e7eSjoerg let ResourceCycles = [8]; 20206f32e7eSjoerg} 20306f32e7eSjoerg 20406f32e7eSjoerg// 23 cycles on F0 or F1. 20506f32e7eSjoergdef THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 20606f32e7eSjoerg let Latency = 23; 20706f32e7eSjoerg let NumMicroOps = 3; 20806f32e7eSjoerg let ResourceCycles = [11]; 20906f32e7eSjoerg} 21006f32e7eSjoerg 21106f32e7eSjoerg// 1 cycles on LS0 or LS1. 21206f32e7eSjoergdef THX2T99Write_1Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 21306f32e7eSjoerg let Latency = 0; 21406f32e7eSjoerg} 21506f32e7eSjoerg 21606f32e7eSjoerg// 1 cycles on LS0 or LS1 and I0, I1, or I2. 21706f32e7eSjoergdef THX2T99Write_1Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 21806f32e7eSjoerg let Latency = 0; 21906f32e7eSjoerg let NumMicroOps = 2; 22006f32e7eSjoerg} 22106f32e7eSjoerg 22206f32e7eSjoerg// 1 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 22306f32e7eSjoergdef THX2T99Write_1Cyc_LS01_I012_I012 : 22406f32e7eSjoerg SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 22506f32e7eSjoerg let Latency = 0; 22606f32e7eSjoerg let NumMicroOps = 3; 22706f32e7eSjoerg} 22806f32e7eSjoerg 22906f32e7eSjoerg// 2 cycles on LS0 or LS1. 23006f32e7eSjoergdef THX2T99Write_2Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 23106f32e7eSjoerg let Latency = 1; 23206f32e7eSjoerg let NumMicroOps = 2; 23306f32e7eSjoerg} 23406f32e7eSjoerg 23506f32e7eSjoerg// 4 cycles on LS0 or LS1. 23606f32e7eSjoergdef THX2T99Write_4Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 23706f32e7eSjoerg let Latency = 4; 23806f32e7eSjoerg let NumMicroOps = 4; 23906f32e7eSjoerg} 24006f32e7eSjoerg 24106f32e7eSjoerg// 5 cycles on LS0 or LS1. 24206f32e7eSjoergdef THX2T99Write_5Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 24306f32e7eSjoerg let Latency = 5; 24406f32e7eSjoerg let NumMicroOps = 3; 24506f32e7eSjoerg} 24606f32e7eSjoerg 24706f32e7eSjoerg// 6 cycles on LS0 or LS1. 24806f32e7eSjoergdef THX2T99Write_6Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 24906f32e7eSjoerg let Latency = 6; 25006f32e7eSjoerg let NumMicroOps = 3; 25106f32e7eSjoerg} 25206f32e7eSjoerg 25306f32e7eSjoerg// 4 cycles on LS0 or LS1 and I0, I1, or I2. 25406f32e7eSjoergdef THX2T99Write_4Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 25506f32e7eSjoerg let Latency = 4; 25606f32e7eSjoerg let NumMicroOps = 3; 25706f32e7eSjoerg} 25806f32e7eSjoerg 25906f32e7eSjoerg// 4 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 26006f32e7eSjoergdef THX2T99Write_4Cyc_LS01_I012_I012 : 26106f32e7eSjoerg SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 26206f32e7eSjoerg let Latency = 4; 26306f32e7eSjoerg let NumMicroOps = 3; 26406f32e7eSjoerg} 26506f32e7eSjoerg 26606f32e7eSjoerg// 5 cycles on LS0 or LS1 and I0, I1, or I2. 26706f32e7eSjoergdef THX2T99Write_5Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 26806f32e7eSjoerg let Latency = 5; 26906f32e7eSjoerg let NumMicroOps = 3; 27006f32e7eSjoerg} 27106f32e7eSjoerg 27206f32e7eSjoerg// 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 27306f32e7eSjoergdef THX2T99Write_5Cyc_LS01_I012_I012 : 27406f32e7eSjoerg SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 27506f32e7eSjoerg let Latency = 5; 27606f32e7eSjoerg let NumMicroOps = 3; 27706f32e7eSjoerg} 27806f32e7eSjoerg 27906f32e7eSjoerg// 6 cycles on LS0 or LS1 and I0, I1, or I2. 28006f32e7eSjoergdef THX2T99Write_6Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 28106f32e7eSjoerg let Latency = 6; 28206f32e7eSjoerg let NumMicroOps = 4; 28306f32e7eSjoerg} 28406f32e7eSjoerg 28506f32e7eSjoerg// 6 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 28606f32e7eSjoergdef THX2T99Write_6Cyc_LS01_I012_I012 : 28706f32e7eSjoerg SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 28806f32e7eSjoerg let Latency = 6; 28906f32e7eSjoerg let NumMicroOps = 3; 29006f32e7eSjoerg} 29106f32e7eSjoerg 29206f32e7eSjoerg// 1 cycles on LS0 or LS1 and F0 or F1. 29306f32e7eSjoergdef THX2T99Write_1Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 29406f32e7eSjoerg let Latency = 1; 29506f32e7eSjoerg let NumMicroOps = 2; 29606f32e7eSjoerg} 29706f32e7eSjoerg 29806f32e7eSjoerg// 5 cycles on LS0 or LS1 and F0 or F1. 29906f32e7eSjoergdef THX2T99Write_5Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 30006f32e7eSjoerg let Latency = 5; 30106f32e7eSjoerg let NumMicroOps = 3; 30206f32e7eSjoerg} 30306f32e7eSjoerg 30406f32e7eSjoerg// 6 cycles on LS0 or LS1 and F0 or F1. 30506f32e7eSjoergdef THX2T99Write_6Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 30606f32e7eSjoerg let Latency = 6; 30706f32e7eSjoerg let NumMicroOps = 3; 30806f32e7eSjoerg} 30906f32e7eSjoerg 31006f32e7eSjoerg// 7 cycles on LS0 or LS1 and F0 or F1. 31106f32e7eSjoergdef THX2T99Write_7Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 31206f32e7eSjoerg let Latency = 7; 31306f32e7eSjoerg let NumMicroOps = 3; 31406f32e7eSjoerg} 31506f32e7eSjoerg 31606f32e7eSjoerg// 8 cycles on LS0 or LS1 and F0 or F1. 31706f32e7eSjoergdef THX2T99Write_8Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 31806f32e7eSjoerg let Latency = 8; 31906f32e7eSjoerg let NumMicroOps = 3; 32006f32e7eSjoerg} 32106f32e7eSjoerg 32206f32e7eSjoerg// 8 cycles on LS0 or LS1 and I0, I1, or I2. 32306f32e7eSjoergdef THX2T99Write_8Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 32406f32e7eSjoerg let Latency = 8; 32506f32e7eSjoerg let NumMicroOps = 4; 32606f32e7eSjoerg} 32706f32e7eSjoerg 32806f32e7eSjoerg// 12 cycles on LS0 or LS1 and I0, I1, or I2. 32906f32e7eSjoergdef THX2T99Write_12Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 33006f32e7eSjoerg let Latency = 12; 33106f32e7eSjoerg let NumMicroOps = 6; 33206f32e7eSjoerg} 33306f32e7eSjoerg 33406f32e7eSjoerg// 16 cycles on LS0 or LS1 and I0, I1, or I2. 33506f32e7eSjoergdef THX2T99Write_16Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 33606f32e7eSjoerg let Latency = 16; 33706f32e7eSjoerg let NumMicroOps = 8; 33806f32e7eSjoerg} 33906f32e7eSjoerg 34006f32e7eSjoerg// 24 cycles on LS0 or LS1 and I0, I1, or I2. 34106f32e7eSjoergdef THX2T99Write_24Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 34206f32e7eSjoerg let Latency = 24; 34306f32e7eSjoerg let NumMicroOps = 12; 34406f32e7eSjoerg} 34506f32e7eSjoerg 34606f32e7eSjoerg// 32 cycles on LS0 or LS1 and I0, I1, or I2. 34706f32e7eSjoergdef THX2T99Write_32Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 34806f32e7eSjoerg let Latency = 32; 34906f32e7eSjoerg let NumMicroOps = 16; 35006f32e7eSjoerg} 35106f32e7eSjoerg 35206f32e7eSjoerg// Define commonly used read types. 35306f32e7eSjoerg 35406f32e7eSjoerg// No forwarding is provided for these types. 35506f32e7eSjoergdef : ReadAdvance<ReadI, 0>; 35606f32e7eSjoergdef : ReadAdvance<ReadISReg, 0>; 35706f32e7eSjoergdef : ReadAdvance<ReadIEReg, 0>; 35806f32e7eSjoergdef : ReadAdvance<ReadIM, 0>; 35906f32e7eSjoergdef : ReadAdvance<ReadIMA, 0>; 36006f32e7eSjoergdef : ReadAdvance<ReadID, 0>; 36106f32e7eSjoergdef : ReadAdvance<ReadExtrHi, 0>; 36206f32e7eSjoergdef : ReadAdvance<ReadAdrBase, 0>; 36306f32e7eSjoergdef : ReadAdvance<ReadVLD, 0>; 36406f32e7eSjoerg 36506f32e7eSjoerg//===----------------------------------------------------------------------===// 36606f32e7eSjoerg// 3. Instruction Tables. 36706f32e7eSjoerg 36806f32e7eSjoerg//--- 36906f32e7eSjoerg// 3.1 Branch Instructions 37006f32e7eSjoerg//--- 37106f32e7eSjoerg 37206f32e7eSjoerg// Branch, immed 37306f32e7eSjoerg// Branch and link, immed 37406f32e7eSjoerg// Compare and branch 37506f32e7eSjoergdef : WriteRes<WriteBr, [THX2T99I2]> { 37606f32e7eSjoerg let Latency = 1; 37706f32e7eSjoerg let NumMicroOps = 2; 37806f32e7eSjoerg} 37906f32e7eSjoerg 38006f32e7eSjoerg// Branch, register 38106f32e7eSjoerg// Branch and link, register != LR 38206f32e7eSjoerg// Branch and link, register = LR 38306f32e7eSjoergdef : WriteRes<WriteBrReg, [THX2T99I2]> { 38406f32e7eSjoerg let Latency = 1; 38506f32e7eSjoerg let NumMicroOps = 2; 38606f32e7eSjoerg} 38706f32e7eSjoerg 38806f32e7eSjoergdef : WriteRes<WriteSys, []> { let Latency = 1; } 38906f32e7eSjoergdef : WriteRes<WriteBarrier, []> { let Latency = 1; } 39006f32e7eSjoergdef : WriteRes<WriteHint, []> { let Latency = 1; } 39106f32e7eSjoerg 39206f32e7eSjoergdef : WriteRes<WriteAtomic, []> { 39306f32e7eSjoerg let Latency = 4; 39406f32e7eSjoerg let NumMicroOps = 2; 39506f32e7eSjoerg} 39606f32e7eSjoerg 39706f32e7eSjoerg//--- 39806f32e7eSjoerg// Branch 39906f32e7eSjoerg//--- 40006f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I2], (instrs B, BL, BR, BLR)>; 40106f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I2], (instrs RET)>; 40206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^B..$")>; 40306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I2], 40406f32e7eSjoerg (instregex "^CBZ", "^CBNZ", "^TBZ", "^TBNZ")>; 40506f32e7eSjoerg 40606f32e7eSjoerg//--- 40706f32e7eSjoerg// 3.2 Arithmetic and Logical Instructions 40806f32e7eSjoerg// 3.3 Move and Shift Instructions 40906f32e7eSjoerg//--- 41006f32e7eSjoerg 41106f32e7eSjoerg 41206f32e7eSjoerg// ALU, basic 41306f32e7eSjoerg// Conditional compare 41406f32e7eSjoerg// Conditional select 41506f32e7eSjoerg// Address generation 41606f32e7eSjoergdef : WriteRes<WriteI, [THX2T99I012]> { 41706f32e7eSjoerg let Latency = 1; 41806f32e7eSjoerg let ResourceCycles = [1]; 41906f32e7eSjoerg let NumMicroOps = 2; 42006f32e7eSjoerg} 42106f32e7eSjoerg 42206f32e7eSjoergdef : InstRW<[WriteI], 42306f32e7eSjoerg (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", 42406f32e7eSjoerg "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", 42506f32e7eSjoerg "ADC(W|X)r", 42606f32e7eSjoerg "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", 42706f32e7eSjoerg "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", 42806f32e7eSjoerg "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", 42906f32e7eSjoerg "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 43006f32e7eSjoerg "SBCS(W|X)r", "CCMN(W|X)(i|r)", 43106f32e7eSjoerg "CCMP(W|X)(i|r)", "CSEL(W|X)r", 43206f32e7eSjoerg "CSINC(W|X)r", "CSINV(W|X)r", 43306f32e7eSjoerg "CSNEG(W|X)r")>; 43406f32e7eSjoerg 43506f32e7eSjoergdef : InstRW<[WriteI], (instrs COPY)>; 43606f32e7eSjoerg 43706f32e7eSjoerg// ALU, extend and/or shift 43806f32e7eSjoergdef : WriteRes<WriteISReg, [THX2T99I012]> { 43906f32e7eSjoerg let Latency = 2; 44006f32e7eSjoerg let ResourceCycles = [2]; 44106f32e7eSjoerg let NumMicroOps = 2; 44206f32e7eSjoerg} 44306f32e7eSjoerg 44406f32e7eSjoergdef : InstRW<[WriteISReg], 44506f32e7eSjoerg (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", 44606f32e7eSjoerg "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", 44706f32e7eSjoerg "ADC(W|X)r", 44806f32e7eSjoerg "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", 44906f32e7eSjoerg "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", 45006f32e7eSjoerg "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", 45106f32e7eSjoerg "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 45206f32e7eSjoerg "SBCS(W|X)r", "CCMN(W|X)(i|r)", 45306f32e7eSjoerg "CCMP(W|X)(i|r)", "CSEL(W|X)r", 45406f32e7eSjoerg "CSINC(W|X)r", "CSINV(W|X)r", 45506f32e7eSjoerg "CSNEG(W|X)r")>; 45606f32e7eSjoerg 45706f32e7eSjoergdef : WriteRes<WriteIEReg, [THX2T99I012]> { 45806f32e7eSjoerg let Latency = 1; 45906f32e7eSjoerg let ResourceCycles = [1]; 46006f32e7eSjoerg let NumMicroOps = 2; 46106f32e7eSjoerg} 46206f32e7eSjoerg 46306f32e7eSjoergdef : InstRW<[WriteIEReg], 46406f32e7eSjoerg (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", 46506f32e7eSjoerg "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", 46606f32e7eSjoerg "ADC(W|X)r", 46706f32e7eSjoerg "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", 46806f32e7eSjoerg "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", 46906f32e7eSjoerg "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", 47006f32e7eSjoerg "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 47106f32e7eSjoerg "SBCS(W|X)r", "CCMN(W|X)(i|r)", 47206f32e7eSjoerg "CCMP(W|X)(i|r)", "CSEL(W|X)r", 47306f32e7eSjoerg "CSINC(W|X)r", "CSINV(W|X)r", 47406f32e7eSjoerg "CSNEG(W|X)r")>; 47506f32e7eSjoerg 47606f32e7eSjoerg// Move immed 47706f32e7eSjoergdef : WriteRes<WriteImm, [THX2T99I012]> { 47806f32e7eSjoerg let Latency = 1; 47906f32e7eSjoerg let NumMicroOps = 2; 48006f32e7eSjoerg} 48106f32e7eSjoerg 48206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I012], 48306f32e7eSjoerg (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>; 48406f32e7eSjoerg 48506f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I012], 48606f32e7eSjoerg (instrs ASRVWr, ASRVXr, LSLVWr, LSLVXr, RORVWr, RORVXr)>; 48706f32e7eSjoerg 48806f32e7eSjoerg// Variable shift 48906f32e7eSjoergdef : WriteRes<WriteIS, [THX2T99I012]> { 49006f32e7eSjoerg let Latency = 1; 49106f32e7eSjoerg let NumMicroOps = 2; 49206f32e7eSjoerg} 49306f32e7eSjoerg 49406f32e7eSjoerg//--- 49506f32e7eSjoerg// 3.4 Divide and Multiply Instructions 49606f32e7eSjoerg//--- 49706f32e7eSjoerg 49806f32e7eSjoerg// Divide, W-form 49906f32e7eSjoerg// Latency range of 13-23/13-39. 50006f32e7eSjoergdef : WriteRes<WriteID32, [THX2T99I1]> { 50106f32e7eSjoerg let Latency = 39; 50206f32e7eSjoerg let ResourceCycles = [39]; 50306f32e7eSjoerg let NumMicroOps = 4; 50406f32e7eSjoerg} 50506f32e7eSjoerg 50606f32e7eSjoerg// Divide, X-form 50706f32e7eSjoergdef : WriteRes<WriteID64, [THX2T99I1]> { 50806f32e7eSjoerg let Latency = 23; 50906f32e7eSjoerg let ResourceCycles = [23]; 51006f32e7eSjoerg let NumMicroOps = 4; 51106f32e7eSjoerg} 51206f32e7eSjoerg 51306f32e7eSjoerg// Multiply accumulate, W-form 51406f32e7eSjoergdef : WriteRes<WriteIM32, [THX2T99I012]> { 51506f32e7eSjoerg let Latency = 5; 51606f32e7eSjoerg let NumMicroOps = 3; 51706f32e7eSjoerg} 51806f32e7eSjoerg 51906f32e7eSjoerg// Multiply accumulate, X-form 52006f32e7eSjoergdef : WriteRes<WriteIM64, [THX2T99I012]> { 52106f32e7eSjoerg let Latency = 5; 52206f32e7eSjoerg let NumMicroOps = 3; 52306f32e7eSjoerg} 52406f32e7eSjoerg 52506f32e7eSjoerg//def : InstRW<[WriteIM32, ReadIM, ReadIM, ReadIMA, THX2T99Write_5Cyc_I012], 52606f32e7eSjoerg// (instrs MADDWrrr, MSUBWrrr)>; 52706f32e7eSjoergdef : InstRW<[WriteIM32], (instrs MADDWrrr, MSUBWrrr)>; 52806f32e7eSjoergdef : InstRW<[WriteIM32], (instrs MADDXrrr, MSUBXrrr)>; 52906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_I012], 53006f32e7eSjoerg (instregex "(S|U)(MADDL|MSUBL)rrr")>; 53106f32e7eSjoerg 53206f32e7eSjoergdef : InstRW<[WriteID32], (instrs SDIVWr, UDIVWr)>; 53306f32e7eSjoergdef : InstRW<[WriteID64], (instrs SDIVXr, UDIVXr)>; 53406f32e7eSjoerg 53506f32e7eSjoerg// Bitfield extract, two reg 53606f32e7eSjoergdef : WriteRes<WriteExtr, [THX2T99I012]> { 53706f32e7eSjoerg let Latency = 1; 53806f32e7eSjoerg let NumMicroOps = 2; 53906f32e7eSjoerg} 54006f32e7eSjoerg 54106f32e7eSjoerg// Multiply high 54206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_I1], (instrs SMULHrr, UMULHrr)>; 54306f32e7eSjoerg 54406f32e7eSjoerg// Miscellaneous Data-Processing Instructions 54506f32e7eSjoerg// Bitfield extract 54606f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I012], (instrs EXTRWrri, EXTRXrri)>; 54706f32e7eSjoerg 54806f32e7eSjoerg// Bitifield move - basic 54906f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I012], 55006f32e7eSjoerg (instrs SBFMWri, SBFMXri, UBFMWri, UBFMXri)>; 55106f32e7eSjoerg 55206f32e7eSjoerg// Bitfield move, insert 55306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>; 55406f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>; 55506f32e7eSjoerg 55606f32e7eSjoerg// Count leading 55706f32e7eSjoergdef : InstRW<[THX2T99Write_3Cyc_I1], (instregex "^CLS(W|X)r$", 55806f32e7eSjoerg "^CLZ(W|X)r$")>; 55906f32e7eSjoerg 56006f32e7eSjoerg// Reverse bits 56106f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_I012], (instrs RBITWr, RBITXr)>; 56206f32e7eSjoerg 56306f32e7eSjoerg// Cryptography Extensions 56406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AES[DE]")>; 56506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AESI?MC")>; 56606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL")>; 56706f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1SU0")>; 56806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1(H|SU1)")>; 56906f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1[CMP]")>; 57006f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA256SU0")>; 57106f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA256(H|H2|SU1)")>; 57206f32e7eSjoerg 57306f32e7eSjoerg// CRC Instructions 57406f32e7eSjoerg// def : InstRW<[THX2T99Write_4Cyc_I1], (instregex "^CRC32", "^CRC32C")>; 57506f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_I1], 57606f32e7eSjoerg (instrs CRC32Brr, CRC32Hrr, CRC32Wrr, CRC32Xrr)>; 57706f32e7eSjoerg 57806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_I1], 57906f32e7eSjoerg (instrs CRC32CBrr, CRC32CHrr, CRC32CWrr, CRC32CXrr)>; 58006f32e7eSjoerg 58106f32e7eSjoerg// Reverse bits/bytes 58206f32e7eSjoerg// NOTE: Handled by WriteI. 58306f32e7eSjoerg 58406f32e7eSjoerg//--- 58506f32e7eSjoerg// 3.6 Load Instructions 58606f32e7eSjoerg// 3.10 FP Load Instructions 58706f32e7eSjoerg//--- 58806f32e7eSjoerg 58906f32e7eSjoerg// Load register, literal 59006f32e7eSjoerg// Load register, unscaled immed 59106f32e7eSjoerg// Load register, immed unprivileged 59206f32e7eSjoerg// Load register, unsigned immed 59306f32e7eSjoergdef : WriteRes<WriteLD, [THX2T99LS01]> { 59406f32e7eSjoerg let Latency = 4; 59506f32e7eSjoerg let NumMicroOps = 4; 59606f32e7eSjoerg} 59706f32e7eSjoerg 59806f32e7eSjoerg// Load register, immed post-index 59906f32e7eSjoerg// NOTE: Handled by WriteLD, WriteI. 60006f32e7eSjoerg// Load register, immed pre-index 60106f32e7eSjoerg// NOTE: Handled by WriteLD, WriteAdr. 60206f32e7eSjoergdef : WriteRes<WriteAdr, [THX2T99I012]> { 60306f32e7eSjoerg let Latency = 1; 60406f32e7eSjoerg let NumMicroOps = 2; 60506f32e7eSjoerg} 60606f32e7eSjoerg 60706f32e7eSjoerg// Load pair, immed offset, normal 60806f32e7eSjoerg// Load pair, immed offset, signed words, base != SP 60906f32e7eSjoerg// Load pair, immed offset signed words, base = SP 61006f32e7eSjoerg// LDP only breaks into *one* LS micro-op. Thus 61106f32e7eSjoerg// the resources are handled by WriteLD. 61206f32e7eSjoergdef : WriteRes<WriteLDHi, []> { 61306f32e7eSjoerg let Latency = 5; 61406f32e7eSjoerg let NumMicroOps = 5; 61506f32e7eSjoerg} 61606f32e7eSjoerg 61706f32e7eSjoerg// Load register offset, basic 61806f32e7eSjoerg// Load register, register offset, scale by 4/8 61906f32e7eSjoerg// Load register, register offset, scale by 2 62006f32e7eSjoerg// Load register offset, extend 62106f32e7eSjoerg// Load register, register offset, extend, scale by 4/8 62206f32e7eSjoerg// Load register, register offset, extend, scale by 2 62306f32e7eSjoergdef THX2T99WriteLDIdx : SchedWriteVariant<[ 62406f32e7eSjoerg SchedVar<ScaledIdxPred, [THX2T99Write_6Cyc_LS01_I012_I012]>, 62506f32e7eSjoerg SchedVar<NoSchedPred, [THX2T99Write_5Cyc_LS01_I012]>]>; 62606f32e7eSjoergdef : SchedAlias<WriteLDIdx, THX2T99WriteLDIdx>; 62706f32e7eSjoerg 62806f32e7eSjoergdef THX2T99ReadAdrBase : SchedReadVariant<[ 62906f32e7eSjoerg SchedVar<ScaledIdxPred, [ReadDefault]>, 63006f32e7eSjoerg SchedVar<NoSchedPred, [ReadDefault]>]>; 63106f32e7eSjoergdef : SchedAlias<ReadAdrBase, THX2T99ReadAdrBase>; 63206f32e7eSjoerg 63306f32e7eSjoerg// Load pair, immed pre-index, normal 63406f32e7eSjoerg// Load pair, immed pre-index, signed words 63506f32e7eSjoerg// Load pair, immed post-index, normal 63606f32e7eSjoerg// Load pair, immed post-index, signed words 63706f32e7eSjoerg// NOTE: Handled by WriteLD, WriteLDHi, WriteAdr. 63806f32e7eSjoerg 63906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPDi)>; 64006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPQi)>; 64106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPSi)>; 64206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPWi)>; 64306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPXi)>; 64406f32e7eSjoerg 64506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPDi)>; 64606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPQi)>; 64706f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPSi)>; 64806f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPSWi)>; 64906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPWi)>; 65006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPXi)>; 65106f32e7eSjoerg 65206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRBui)>; 65306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRDui)>; 65406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRHui)>; 65506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01], (instrs LDRQui)>; 65606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01], (instrs LDRSui)>; 65706f32e7eSjoerg 65806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRDl)>; 65906f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRQl)>; 66006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRWl)>; 66106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRXl)>; 66206f32e7eSjoerg 66306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRBi)>; 66406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRHi)>; 66506f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRWi)>; 66606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRXi)>; 66706f32e7eSjoerg 66806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSBWi)>; 66906f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSBXi)>; 67006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSHWi)>; 67106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSHXi)>; 67206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSWi)>; 67306f32e7eSjoerg 67406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 67506f32e7eSjoerg (instrs LDPDpre)>; 67606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 67706f32e7eSjoerg (instrs LDPQpre)>; 67806f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 67906f32e7eSjoerg (instrs LDPSpre)>; 68006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 68106f32e7eSjoerg (instrs LDPWpre)>; 68206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 68306f32e7eSjoerg (instrs LDPWpre)>; 68406f32e7eSjoerg 68506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRBpre)>; 68606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRDpre)>; 68706f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRHpre)>; 68806f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRQpre)>; 68906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRSpre)>; 69006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRWpre)>; 69106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRXpre)>; 69206f32e7eSjoerg 69306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBWpre)>; 69406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBXpre)>; 69506f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBWpost)>; 69606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBXpost)>; 69706f32e7eSjoerg 69806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHWpre)>; 69906f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHXpre)>; 70006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHWpost)>; 70106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHXpost)>; 70206f32e7eSjoerg 70306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRBBpre)>; 70406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRBBpost)>; 70506f32e7eSjoerg 70606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRHHpre)>; 70706f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRHHpost)>; 70806f32e7eSjoerg 70906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 71006f32e7eSjoerg (instrs LDPDpost)>; 71106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 71206f32e7eSjoerg (instrs LDPQpost)>; 71306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 71406f32e7eSjoerg (instrs LDPSpost)>; 71506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 71606f32e7eSjoerg (instrs LDPWpost)>; 71706f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 71806f32e7eSjoerg (instrs LDPXpost)>; 71906f32e7eSjoerg 72006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>; 72106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>; 72206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>; 72306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>; 72406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>; 72506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRWpost)>; 72606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRXpost)>; 72706f32e7eSjoerg 72806f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 72906f32e7eSjoerg (instrs LDPDpre)>; 73006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 73106f32e7eSjoerg (instrs LDPQpre)>; 73206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 73306f32e7eSjoerg (instrs LDPSpre)>; 73406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 73506f32e7eSjoerg (instrs LDPWpre)>; 73606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 73706f32e7eSjoerg (instrs LDPXpre)>; 73806f32e7eSjoerg 73906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRBpre)>; 74006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRDpre)>; 74106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRHpre)>; 74206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRQpre)>; 74306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRSpre)>; 74406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRWpre)>; 74506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRXpre)>; 74606f32e7eSjoerg 74706f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 74806f32e7eSjoerg (instrs LDPDpost)>; 74906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 75006f32e7eSjoerg (instrs LDPQpost)>; 75106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 75206f32e7eSjoerg (instrs LDPSpost)>; 75306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 75406f32e7eSjoerg (instrs LDPWpost)>; 75506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 75606f32e7eSjoerg (instrs LDPXpost)>; 75706f32e7eSjoerg 75806f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRBpost)>; 75906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRDpost)>; 76006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRHpost)>; 76106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRQpost)>; 76206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRSpost)>; 76306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRWpost)>; 76406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRXpost)>; 76506f32e7eSjoerg 76606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRBroW)>; 76706f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRDroW)>; 76806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHroW)>; 76906f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHHroW)>; 77006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRQroW)>; 77106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSroW)>; 77206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHWroW)>; 77306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHXroW)>; 77406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRWroW)>; 77506f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRXroW)>; 77606f32e7eSjoerg 77706f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRBroX)>; 77806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRDroX)>; 77906f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHHroX)>; 78006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHroX)>; 78106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRQroX)>; 78206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSroX)>; 78306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHWroX)>; 78406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHXroX)>; 78506f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRWroX)>; 78606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRXroX)>; 78706f32e7eSjoerg 78806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 78906f32e7eSjoerg (instrs LDRBroW)>; 79006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 79106f32e7eSjoerg (instrs LDRBroW)>; 79206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 79306f32e7eSjoerg (instrs LDRDroW)>; 79406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 79506f32e7eSjoerg (instrs LDRHroW)>; 79606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 79706f32e7eSjoerg (instrs LDRHHroW)>; 79806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 79906f32e7eSjoerg (instrs LDRQroW)>; 80006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 80106f32e7eSjoerg (instrs LDRSroW)>; 80206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 80306f32e7eSjoerg (instrs LDRSHWroW)>; 80406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 80506f32e7eSjoerg (instrs LDRSHXroW)>; 80606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 80706f32e7eSjoerg (instrs LDRWroW)>; 80806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 80906f32e7eSjoerg (instrs LDRXroW)>; 81006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 81106f32e7eSjoerg (instrs LDRBroX)>; 81206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 81306f32e7eSjoerg (instrs LDRDroX)>; 81406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 81506f32e7eSjoerg (instrs LDRHroX)>; 81606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 81706f32e7eSjoerg (instrs LDRHHroX)>; 81806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 81906f32e7eSjoerg (instrs LDRQroX)>; 82006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 82106f32e7eSjoerg (instrs LDRSroX)>; 82206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 82306f32e7eSjoerg (instrs LDRSHWroX)>; 82406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 82506f32e7eSjoerg (instrs LDRSHXroX)>; 82606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 82706f32e7eSjoerg (instrs LDRWroX)>; 82806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 82906f32e7eSjoerg (instrs LDRXroX)>; 83006f32e7eSjoerg 83106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURBi)>; 83206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURBBi)>; 83306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURDi)>; 83406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURHi)>; 83506f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURHHi)>; 83606f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURQi)>; 83706f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSi)>; 83806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURXi)>; 83906f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSBWi)>; 84006f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSBXi)>; 84106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSHWi)>; 84206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSHXi)>; 84306f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSWi)>; 84406f32e7eSjoerg 84506f32e7eSjoerg//--- 84606f32e7eSjoerg// Prefetch 84706f32e7eSjoerg//--- 84806f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMl)>; 84906f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFUMi)>; 85006f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMui)>; 85106f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMroW)>; 85206f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMroX)>; 85306f32e7eSjoerg 85406f32e7eSjoerg//-- 85506f32e7eSjoerg// 3.7 Store Instructions 85606f32e7eSjoerg// 3.11 FP Store Instructions 85706f32e7eSjoerg//-- 85806f32e7eSjoerg 85906f32e7eSjoerg// Store register, unscaled immed 86006f32e7eSjoerg// Store register, immed unprivileged 86106f32e7eSjoerg// Store register, unsigned immed 86206f32e7eSjoergdef : WriteRes<WriteST, [THX2T99LS01, THX2T99SD]> { 86306f32e7eSjoerg let Latency = 1; 86406f32e7eSjoerg let NumMicroOps = 2; 86506f32e7eSjoerg} 86606f32e7eSjoerg 86706f32e7eSjoerg// Store register, immed post-index 86806f32e7eSjoerg// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase 86906f32e7eSjoerg 87006f32e7eSjoerg// Store register, immed pre-index 87106f32e7eSjoerg// NOTE: Handled by WriteAdr, WriteST 87206f32e7eSjoerg 87306f32e7eSjoerg// Store register, register offset, basic 87406f32e7eSjoerg// Store register, register offset, scaled by 4/8 87506f32e7eSjoerg// Store register, register offset, scaled by 2 87606f32e7eSjoerg// Store register, register offset, extend 87706f32e7eSjoerg// Store register, register offset, extend, scale by 4/8 87806f32e7eSjoerg// Store register, register offset, extend, scale by 1 87906f32e7eSjoergdef : WriteRes<WriteSTIdx, [THX2T99LS01, THX2T99SD, THX2T99I012]> { 88006f32e7eSjoerg let Latency = 1; 88106f32e7eSjoerg let NumMicroOps = 3; 88206f32e7eSjoerg} 88306f32e7eSjoerg 88406f32e7eSjoerg// Store pair, immed offset, W-form 88506f32e7eSjoerg// Store pair, immed offset, X-form 88606f32e7eSjoergdef : WriteRes<WriteSTP, [THX2T99LS01, THX2T99SD]> { 88706f32e7eSjoerg let Latency = 1; 88806f32e7eSjoerg let NumMicroOps = 2; 88906f32e7eSjoerg} 89006f32e7eSjoerg 89106f32e7eSjoerg// Store pair, immed post-index, W-form 89206f32e7eSjoerg// Store pair, immed post-index, X-form 89306f32e7eSjoerg// Store pair, immed pre-index, W-form 89406f32e7eSjoerg// Store pair, immed pre-index, X-form 89506f32e7eSjoerg// NOTE: Handled by WriteAdr, WriteSTP. 89606f32e7eSjoerg 89706f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURBi)>; 89806f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURBBi)>; 89906f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURDi)>; 90006f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURHi)>; 90106f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURHHi)>; 90206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURQi)>; 90306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURSi)>; 90406f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURWi)>; 90506f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURXi)>; 90606f32e7eSjoerg 90706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRBi)>; 90806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRHi)>; 90906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRWi)>; 91006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRXi)>; 91106f32e7eSjoerg 91206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPDi)>; 91306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPQi)>; 91406f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPXi)>; 91506f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPWi)>; 91606f32e7eSjoerg 91706f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPDi)>; 91806f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPQi)>; 91906f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPXi)>; 92006f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPWi)>; 92106f32e7eSjoerg 92206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRBui)>; 92306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRBui)>; 92406f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRDui)>; 92506f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRDui)>; 92606f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRHui)>; 92706f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRHui)>; 92806f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRQui)>; 92906f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRQui)>; 93006f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRXui)>; 93106f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRXui)>; 93206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRWui)>; 93306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRWui)>; 93406f32e7eSjoerg 93506f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 93606f32e7eSjoerg (instrs STPDpre, STPDpost)>; 93706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 93806f32e7eSjoerg (instrs STPDpre, STPDpost)>; 93906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 94006f32e7eSjoerg (instrs STPDpre, STPDpost)>; 94106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 94206f32e7eSjoerg (instrs STPDpre, STPDpost)>; 94306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 94406f32e7eSjoerg (instrs STPQpre, STPQpost)>; 94506f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 94606f32e7eSjoerg (instrs STPQpre, STPQpost)>; 94706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 94806f32e7eSjoerg (instrs STPQpre, STPQpost)>; 94906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 95006f32e7eSjoerg (instrs STPQpre, STPQpost)>; 95106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 95206f32e7eSjoerg (instrs STPSpre, STPSpost)>; 95306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 95406f32e7eSjoerg (instrs STPSpre, STPSpost)>; 95506f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 95606f32e7eSjoerg (instrs STPSpre, STPSpost)>; 95706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 95806f32e7eSjoerg (instrs STPSpre, STPSpost)>; 95906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 96006f32e7eSjoerg (instrs STPWpre, STPWpost)>; 96106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 96206f32e7eSjoerg (instrs STPWpre, STPWpost)>; 96306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 96406f32e7eSjoerg (instrs STPWpre, STPWpost)>; 96506f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 96606f32e7eSjoerg (instrs STPWpre, STPWpost)>; 96706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 96806f32e7eSjoerg (instrs STPXpre, STPXpost)>; 96906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 97006f32e7eSjoerg (instrs STPXpre, STPXpost)>; 97106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 97206f32e7eSjoerg (instrs STPXpre, STPXpost)>; 97306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 97406f32e7eSjoerg (instrs STPXpre, STPXpost)>; 97506f32e7eSjoerg 97606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 97706f32e7eSjoerg (instrs STRBpre, STRBpost)>; 97806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 97906f32e7eSjoerg (instrs STRBpre, STRBpost)>; 98006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 98106f32e7eSjoerg (instrs STRBpre, STRBpost)>; 98206f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 98306f32e7eSjoerg (instrs STRBpre, STRBpost)>; 98406f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 98506f32e7eSjoerg (instrs STRBBpre, STRBBpost)>; 98606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 98706f32e7eSjoerg (instrs STRBBpre, STRBBpost)>; 98806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 98906f32e7eSjoerg (instrs STRBBpre, STRBBpost)>; 99006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 99106f32e7eSjoerg (instrs STRBBpre, STRBBpost)>; 99206f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 99306f32e7eSjoerg (instrs STRDpre, STRDpost)>; 99406f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 99506f32e7eSjoerg (instrs STRDpre, STRDpost)>; 99606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 99706f32e7eSjoerg (instrs STRDpre, STRDpost)>; 99806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 99906f32e7eSjoerg (instrs STRDpre, STRDpost)>; 100006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 100106f32e7eSjoerg (instrs STRHpre, STRHpost)>; 100206f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 100306f32e7eSjoerg (instrs STRHpre, STRHpost)>; 100406f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 100506f32e7eSjoerg (instrs STRHpre, STRHpost)>; 100606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 100706f32e7eSjoerg (instrs STRHpre, STRHpost)>; 100806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 100906f32e7eSjoerg (instrs STRHHpre, STRHHpost)>; 101006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 101106f32e7eSjoerg (instrs STRHHpre, STRHHpost)>; 101206f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 101306f32e7eSjoerg (instrs STRHHpre, STRHHpost)>; 101406f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 101506f32e7eSjoerg (instrs STRHHpre, STRHHpost)>; 101606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 101706f32e7eSjoerg (instrs STRQpre, STRQpost)>; 101806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 101906f32e7eSjoerg (instrs STRQpre, STRQpost)>; 102006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 102106f32e7eSjoerg (instrs STRQpre, STRQpost)>; 102206f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 102306f32e7eSjoerg (instrs STRQpre, STRQpost)>; 102406f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 102506f32e7eSjoerg (instrs STRSpre, STRSpost)>; 102606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 102706f32e7eSjoerg (instrs STRSpre, STRSpost)>; 102806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 102906f32e7eSjoerg (instrs STRSpre, STRSpost)>; 103006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 103106f32e7eSjoerg (instrs STRSpre, STRSpost)>; 103206f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 103306f32e7eSjoerg (instrs STRWpre, STRWpost)>; 103406f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 103506f32e7eSjoerg (instrs STRWpre, STRWpost)>; 103606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 103706f32e7eSjoerg (instrs STRWpre, STRWpost)>; 103806f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 103906f32e7eSjoerg (instrs STRWpre, STRWpost)>; 104006f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 104106f32e7eSjoerg (instrs STRXpre, STRXpost)>; 104206f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 104306f32e7eSjoerg (instrs STRXpre, STRXpost)>; 104406f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 104506f32e7eSjoerg (instrs STRXpre, STRXpost)>; 104606f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 104706f32e7eSjoerg (instrs STRXpre, STRXpost)>; 104806f32e7eSjoerg 104906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 105006f32e7eSjoerg (instrs STRBroW, STRBroX)>; 105106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 105206f32e7eSjoerg (instrs STRBroW, STRBroX)>; 105306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 105406f32e7eSjoerg (instrs STRBBroW, STRBBroX)>; 105506f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 105606f32e7eSjoerg (instrs STRBBroW, STRBBroX)>; 105706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 105806f32e7eSjoerg (instrs STRDroW, STRDroX)>; 105906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 106006f32e7eSjoerg (instrs STRDroW, STRDroX)>; 106106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 106206f32e7eSjoerg (instrs STRHroW, STRHroX)>; 106306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 106406f32e7eSjoerg (instrs STRHroW, STRHroX)>; 106506f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 106606f32e7eSjoerg (instrs STRHHroW, STRHHroX)>; 106706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 106806f32e7eSjoerg (instrs STRHHroW, STRHHroX)>; 106906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 107006f32e7eSjoerg (instrs STRQroW, STRQroX)>; 107106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 107206f32e7eSjoerg (instrs STRQroW, STRQroX)>; 107306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 107406f32e7eSjoerg (instrs STRSroW, STRSroX)>; 107506f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 107606f32e7eSjoerg (instrs STRSroW, STRSroX)>; 107706f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 107806f32e7eSjoerg (instrs STRWroW, STRWroX)>; 107906f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 108006f32e7eSjoerg (instrs STRWroW, STRWroX)>; 108106f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 108206f32e7eSjoerg (instrs STRXroW, STRXroX)>; 108306f32e7eSjoergdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 108406f32e7eSjoerg (instrs STRXroW, STRXroX)>; 108506f32e7eSjoerg 108606f32e7eSjoerg//--- 108706f32e7eSjoerg// 3.8 FP Data Processing Instructions 108806f32e7eSjoerg//--- 108906f32e7eSjoerg 109006f32e7eSjoerg// FP absolute value 109106f32e7eSjoerg// FP min/max 109206f32e7eSjoerg// FP negate 109306f32e7eSjoergdef : WriteRes<WriteF, [THX2T99F01]> { 109406f32e7eSjoerg let Latency = 5; 109506f32e7eSjoerg let NumMicroOps = 2; 109606f32e7eSjoerg} 109706f32e7eSjoerg 109806f32e7eSjoerg// FP arithmetic 109906f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FADD", "^FSUB")>; 110006f32e7eSjoerg 110106f32e7eSjoerg// FP compare 110206f32e7eSjoergdef : WriteRes<WriteFCmp, [THX2T99F01]> { 110306f32e7eSjoerg let Latency = 5; 110406f32e7eSjoerg let NumMicroOps = 2; 110506f32e7eSjoerg} 110606f32e7eSjoerg 110706f32e7eSjoerg// FP Mul, Div, Sqrt 110806f32e7eSjoergdef : WriteRes<WriteFDiv, [THX2T99F01]> { 110906f32e7eSjoerg let Latency = 22; 111006f32e7eSjoerg let ResourceCycles = [19]; 111106f32e7eSjoerg} 111206f32e7eSjoerg 111306f32e7eSjoergdef THX2T99XWriteFDiv : SchedWriteRes<[THX2T99F01]> { 111406f32e7eSjoerg let Latency = 16; 111506f32e7eSjoerg let ResourceCycles = [8]; 111606f32e7eSjoerg let NumMicroOps = 4; 111706f32e7eSjoerg} 111806f32e7eSjoerg 111906f32e7eSjoergdef THX2T99XWriteFDivSP : SchedWriteRes<[THX2T99F01]> { 112006f32e7eSjoerg let Latency = 16; 112106f32e7eSjoerg let ResourceCycles = [8]; 112206f32e7eSjoerg let NumMicroOps = 4; 112306f32e7eSjoerg} 112406f32e7eSjoerg 112506f32e7eSjoergdef THX2T99XWriteFDivDP : SchedWriteRes<[THX2T99F01]> { 112606f32e7eSjoerg let Latency = 23; 112706f32e7eSjoerg let ResourceCycles = [12]; 112806f32e7eSjoerg let NumMicroOps = 4; 112906f32e7eSjoerg} 113006f32e7eSjoerg 113106f32e7eSjoergdef THX2T99XWriteFSqrtSP : SchedWriteRes<[THX2T99F01]> { 113206f32e7eSjoerg let Latency = 16; 113306f32e7eSjoerg let ResourceCycles = [8]; 113406f32e7eSjoerg let NumMicroOps = 4; 113506f32e7eSjoerg} 113606f32e7eSjoerg 113706f32e7eSjoergdef THX2T99XWriteFSqrtDP : SchedWriteRes<[THX2T99F01]> { 113806f32e7eSjoerg let Latency = 23; 113906f32e7eSjoerg let ResourceCycles = [12]; 114006f32e7eSjoerg let NumMicroOps = 4; 114106f32e7eSjoerg} 114206f32e7eSjoerg 114306f32e7eSjoerg// FP divide, S-form 114406f32e7eSjoerg// FP square root, S-form 114506f32e7eSjoergdef : InstRW<[THX2T99XWriteFDivSP], (instrs FDIVSrr)>; 114606f32e7eSjoergdef : InstRW<[THX2T99XWriteFSqrtSP], (instrs FSQRTSr)>; 114706f32e7eSjoergdef : InstRW<[THX2T99XWriteFDivSP], (instregex "^FDIVv.*32$")>; 114806f32e7eSjoergdef : InstRW<[THX2T99XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>; 114906f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>; 115006f32e7eSjoerg 115106f32e7eSjoerg// FP divide, D-form 115206f32e7eSjoerg// FP square root, D-form 115306f32e7eSjoergdef : InstRW<[THX2T99XWriteFDivDP], (instrs FDIVDrr)>; 115406f32e7eSjoergdef : InstRW<[THX2T99XWriteFSqrtDP], (instrs FSQRTDr)>; 115506f32e7eSjoergdef : InstRW<[THX2T99XWriteFDivDP], (instregex "^FDIVv.*64$")>; 115606f32e7eSjoergdef : InstRW<[THX2T99XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>; 115706f32e7eSjoergdef : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>; 115806f32e7eSjoerg 115906f32e7eSjoerg// FP multiply 116006f32e7eSjoerg// FP multiply accumulate 116106f32e7eSjoergdef : WriteRes<WriteFMul, [THX2T99F01]> { 116206f32e7eSjoerg let Latency = 6; 116306f32e7eSjoerg let ResourceCycles = [2]; 116406f32e7eSjoerg let NumMicroOps = 3; 116506f32e7eSjoerg} 116606f32e7eSjoerg 116706f32e7eSjoergdef THX2T99XWriteFMul : SchedWriteRes<[THX2T99F01]> { 116806f32e7eSjoerg let Latency = 6; 116906f32e7eSjoerg let ResourceCycles = [2]; 117006f32e7eSjoerg let NumMicroOps = 3; 117106f32e7eSjoerg} 117206f32e7eSjoerg 117306f32e7eSjoergdef THX2T99XWriteFMulAcc : SchedWriteRes<[THX2T99F01]> { 117406f32e7eSjoerg let Latency = 6; 117506f32e7eSjoerg let ResourceCycles = [2]; 117606f32e7eSjoerg let NumMicroOps = 3; 117706f32e7eSjoerg} 117806f32e7eSjoerg 117906f32e7eSjoergdef : InstRW<[THX2T99XWriteFMul], (instregex "^FMUL", "^FNMUL")>; 118006f32e7eSjoergdef : InstRW<[THX2T99XWriteFMulAcc], 118106f32e7eSjoerg (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>; 118206f32e7eSjoerg 118306f32e7eSjoerg// FP round to integral 118406f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 118506f32e7eSjoerg (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>; 118606f32e7eSjoerg 118706f32e7eSjoerg// FP select 118806f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_F01], (instregex "^FCSEL")>; 118906f32e7eSjoerg 119006f32e7eSjoerg//--- 119106f32e7eSjoerg// 3.9 FP Miscellaneous Instructions 119206f32e7eSjoerg//--- 119306f32e7eSjoerg 119406f32e7eSjoerg// FP convert, from vec to vec reg 119506f32e7eSjoerg// FP convert, from gen to vec reg 119606f32e7eSjoerg// FP convert, from vec to gen reg 119706f32e7eSjoergdef : WriteRes<WriteFCvt, [THX2T99F01]> { 119806f32e7eSjoerg let Latency = 7; 119906f32e7eSjoerg let NumMicroOps = 3; 120006f32e7eSjoerg} 120106f32e7eSjoerg 120206f32e7eSjoerg// FP move, immed 120306f32e7eSjoerg// FP move, register 120406f32e7eSjoergdef : WriteRes<WriteFImm, [THX2T99F01]> { 120506f32e7eSjoerg let Latency = 4; 120606f32e7eSjoerg let NumMicroOps = 2; 120706f32e7eSjoerg} 120806f32e7eSjoerg 120906f32e7eSjoerg// FP transfer, from gen to vec reg 121006f32e7eSjoerg// FP transfer, from vec to gen reg 121106f32e7eSjoergdef : WriteRes<WriteFCopy, [THX2T99F01]> { 121206f32e7eSjoerg let Latency = 4; 121306f32e7eSjoerg let NumMicroOps = 2; 121406f32e7eSjoerg} 121506f32e7eSjoerg 121606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>; 121706f32e7eSjoerg 121806f32e7eSjoerg//--- 121906f32e7eSjoerg// 3.12 ASIMD Integer Instructions 122006f32e7eSjoerg//--- 122106f32e7eSjoerg 122206f32e7eSjoerg// ASIMD absolute diff, D-form 122306f32e7eSjoerg// ASIMD absolute diff, Q-form 122406f32e7eSjoerg// ASIMD absolute diff accum, D-form 122506f32e7eSjoerg// ASIMD absolute diff accum, Q-form 122606f32e7eSjoerg// ASIMD absolute diff accum long 122706f32e7eSjoerg// ASIMD absolute diff long 122806f32e7eSjoerg// ASIMD arith, basic 122906f32e7eSjoerg// ASIMD arith, complex 123006f32e7eSjoerg// ASIMD compare 123106f32e7eSjoerg// ASIMD logical (AND, BIC, EOR) 123206f32e7eSjoerg// ASIMD max/min, basic 123306f32e7eSjoerg// ASIMD max/min, reduce, 4H/4S 123406f32e7eSjoerg// ASIMD max/min, reduce, 8B/8H 123506f32e7eSjoerg// ASIMD max/min, reduce, 16B 123606f32e7eSjoerg// ASIMD multiply, D-form 123706f32e7eSjoerg// ASIMD multiply, Q-form 123806f32e7eSjoerg// ASIMD multiply accumulate long 123906f32e7eSjoerg// ASIMD multiply accumulate saturating long 124006f32e7eSjoerg// ASIMD multiply long 124106f32e7eSjoerg// ASIMD pairwise add and accumulate 124206f32e7eSjoerg// ASIMD shift accumulate 124306f32e7eSjoerg// ASIMD shift by immed, basic 124406f32e7eSjoerg// ASIMD shift by immed and insert, basic, D-form 124506f32e7eSjoerg// ASIMD shift by immed and insert, basic, Q-form 124606f32e7eSjoerg// ASIMD shift by immed, complex 124706f32e7eSjoerg// ASIMD shift by register, basic, D-form 124806f32e7eSjoerg// ASIMD shift by register, basic, Q-form 124906f32e7eSjoerg// ASIMD shift by register, complex, D-form 125006f32e7eSjoerg// ASIMD shift by register, complex, Q-form 125106f32e7eSjoergdef : WriteRes<WriteV, [THX2T99F01]> { 125206f32e7eSjoerg let Latency = 7; 125306f32e7eSjoerg let NumMicroOps = 4; 125406f32e7eSjoerg let ResourceCycles = [4]; 125506f32e7eSjoerg} 125606f32e7eSjoerg 125706f32e7eSjoerg// ASIMD arith, reduce, 4H/4S 125806f32e7eSjoerg// ASIMD arith, reduce, 8B/8H 125906f32e7eSjoerg// ASIMD arith, reduce, 16B 126006f32e7eSjoerg 126106f32e7eSjoerg// ASIMD logical (MVN (alias for NOT), ORN, ORR) 126206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 126306f32e7eSjoerg (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>; 126406f32e7eSjoerg 126506f32e7eSjoerg// ASIMD arith, reduce 126606f32e7eSjoergdef : InstRW<[THX2T99Write_10Cyc_F01], 126706f32e7eSjoerg (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>; 126806f32e7eSjoerg 126906f32e7eSjoerg// ASIMD polynomial (8x8) multiply long 127006f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^(S|U|SQD)MULL")>; 127106f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 127206f32e7eSjoerg (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>; 127306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL(v8i8|v16i8)")>; 127406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^PMULL(v1i64|v2i64)")>; 127506f32e7eSjoerg 127606f32e7eSjoerg// ASIMD absolute diff accum, D-form 127706f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 127806f32e7eSjoerg (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; 127906f32e7eSjoerg// ASIMD absolute diff accum, Q-form 128006f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 128106f32e7eSjoerg (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; 128206f32e7eSjoerg// ASIMD absolute diff accum long 128306f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 128406f32e7eSjoerg (instregex "^[SU]ABAL")>; 128506f32e7eSjoerg// ASIMD arith, reduce, 4H/4S 128606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 128706f32e7eSjoerg (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 128806f32e7eSjoerg// ASIMD arith, reduce, 8B 128906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 129006f32e7eSjoerg (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 129106f32e7eSjoerg// ASIMD arith, reduce, 16B/16H 129206f32e7eSjoergdef : InstRW<[THX2T99Write_10Cyc_F01], 129306f32e7eSjoerg (instregex "^[SU]?ADDL?Vv16i8v$")>; 129406f32e7eSjoerg// ASIMD max/min, reduce, 4H/4S 129506f32e7eSjoergdef : InstRW<[THX2T99Write_10Cyc_F01], 129606f32e7eSjoerg (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 129706f32e7eSjoerg// ASIMD max/min, reduce, 8B/8H 129806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 129906f32e7eSjoerg (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 130006f32e7eSjoerg// ASIMD max/min, reduce, 16B/16H 130106f32e7eSjoergdef : InstRW<[THX2T99Write_10Cyc_F01], 130206f32e7eSjoerg (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 130306f32e7eSjoerg// ASIMD multiply, D-form 130406f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 130506f32e7eSjoerg (instregex "^(P?MUL|SQR?DMULH)" # 130606f32e7eSjoerg "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" # 130706f32e7eSjoerg "(_indexed)?$")>; 130806f32e7eSjoerg// ASIMD multiply, Q-form 130906f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 131006f32e7eSjoerg (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 131106f32e7eSjoerg// ASIMD multiply accumulate, D-form 131206f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 131306f32e7eSjoerg (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; 131406f32e7eSjoerg// ASIMD multiply accumulate, Q-form 131506f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 131606f32e7eSjoerg (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; 131706f32e7eSjoerg// ASIMD shift accumulate 131806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 131906f32e7eSjoerg (instregex "SRSRAv","SSRAv","URSRAv","USRAv")>; 132006f32e7eSjoerg 132106f32e7eSjoerg// ASIMD shift by immed, basic 132206f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 132306f32e7eSjoerg (instregex "RSHRNv","SHRNv", "SQRSHRNv","SQRSHRUNv", 132406f32e7eSjoerg "SQSHRNv","SQSHRUNv", "UQRSHRNv", 132506f32e7eSjoerg "UQSHRNv","SQXTNv","SQXTUNv","UQXTNv")>; 132606f32e7eSjoerg// ASIMD shift by immed, complex 132706f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU]?(Q|R){1,2}SHR")>; 132806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SQSHLU")>; 132906f32e7eSjoerg// ASIMD shift by register, basic, Q-form 133006f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 133106f32e7eSjoerg (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 133206f32e7eSjoerg// ASIMD shift by register, complex, D-form 133306f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 133406f32e7eSjoerg (instregex "^[SU][QR]{1,2}SHL" # 133506f32e7eSjoerg "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 133606f32e7eSjoerg// ASIMD shift by register, complex, Q-form 133706f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 133806f32e7eSjoerg (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 133906f32e7eSjoerg 134006f32e7eSjoerg// ASIMD Arithmetic 134106f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 134206f32e7eSjoerg (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>; 134306f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 134406f32e7eSjoerg (instregex "(ADD|SUB)(v16i8|v8i16|v4i32|v2i64)")>; 134506f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(ADD|SUB)HNv.*")>; 134606f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(RADD|RSUB)HNv.*")>; 134706f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 134806f32e7eSjoerg (instregex "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD", 134906f32e7eSjoerg "^SUQADD", "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>; 135006f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 135106f32e7eSjoerg (instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>; 135206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 135306f32e7eSjoerg (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|" # 135406f32e7eSjoerg "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>; 135506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 135606f32e7eSjoerg (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>; 135706f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADALP","^UADALP")>; 135806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLPv","^UADDLPv")>; 135906f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLV","^UADDLV")>; 136006f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 136106f32e7eSjoerg (instregex "^ADDVv","^SMAXVv","^UMAXVv","^SMINVv","^UMINVv")>; 136206f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 136306f32e7eSjoerg (instregex "^SABAv","^UABAv","^SABALv","^UABALv")>; 136406f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 136506f32e7eSjoerg (instregex "^SQADDv","^SQSUBv","^UQADDv","^UQSUBv")>; 136606f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SUQADDv","^USQADDv")>; 136706f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 136806f32e7eSjoerg (instregex "^ADDHNv","^RADDHNv", "^RSUBHNv", 136906f32e7eSjoerg "^SQABS", "^SQADD", "^SQNEG", "^SQSUB", 137006f32e7eSjoerg "^SRHADD", "^SUBHNv", "^SUQADD", 137106f32e7eSjoerg "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>; 137206f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 137306f32e7eSjoerg (instregex "^CMEQv","^CMGEv","^CMGTv", 137406f32e7eSjoerg "^CMLEv","^CMLTv", "^CMHIv","^CMHSv")>; 137506f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 137606f32e7eSjoerg (instregex "^SMAXv","^SMINv","^UMAXv","^UMINv", 137706f32e7eSjoerg "^SMAXPv","^SMINPv","^UMAXPv","^UMINPv")>; 137806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 137906f32e7eSjoerg (instregex "^SABDv","^UABDv", "^SABDLv","^UABDLv")>; 138006f32e7eSjoerg 138106f32e7eSjoerg//--- 138206f32e7eSjoerg// 3.13 ASIMD Floating-point Instructions 138306f32e7eSjoerg//--- 138406f32e7eSjoerg 138506f32e7eSjoerg// ASIMD FP absolute value 138606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FABSv")>; 138706f32e7eSjoerg 138806f32e7eSjoerg// ASIMD FP arith, normal, D-form 138906f32e7eSjoerg// ASIMD FP arith, normal, Q-form 139006f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], 139106f32e7eSjoerg (instregex "^FABDv", "^FADDv", "^FSUBv")>; 139206f32e7eSjoerg 139306f32e7eSjoerg// ASIMD FP arith,pairwise, D-form 139406f32e7eSjoerg// ASIMD FP arith, pairwise, Q-form 139506f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FADDPv")>; 139606f32e7eSjoerg 139706f32e7eSjoerg// ASIMD FP compare, D-form 139806f32e7eSjoerg// ASIMD FP compare, Q-form 139906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FACGEv", "^FACGTv")>; 140006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FCMEQv", "^FCMGEv", 140106f32e7eSjoerg "^FCMGTv", "^FCMLEv", 140206f32e7eSjoerg "^FCMLTv")>; 140306f32e7eSjoerg 140406f32e7eSjoerg// ASIMD FP round, D-form 140506f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 140606f32e7eSjoerg (instregex "^FRINT[AIMNPXZ](v2f32)")>; 140706f32e7eSjoerg// ASIMD FP round, Q-form 140806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 140906f32e7eSjoerg (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; 141006f32e7eSjoerg 141106f32e7eSjoerg// ASIMD FP convert, long 141206f32e7eSjoerg// ASIMD FP convert, narrow 141306f32e7eSjoerg// ASIMD FP convert, other, D-form 141406f32e7eSjoerg// ASIMD FP convert, other, Q-form 141506f32e7eSjoerg// NOTE: Handled by WriteV. 141606f32e7eSjoerg 141706f32e7eSjoerg// ASIMD FP convert, long and narrow 141806f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^FCVT(L|N|XN)v")>; 141906f32e7eSjoerg// ASIMD FP convert, other, D-form 142006f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 142106f32e7eSjoerg (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; 142206f32e7eSjoerg// ASIMD FP convert, other, Q-form 142306f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 142406f32e7eSjoerg (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; 142506f32e7eSjoerg 142606f32e7eSjoerg// ASIMD FP divide, D-form, F32 142706f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_F01], (instrs FDIVv2f32)>; 142806f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_F01], (instregex "FDIVv2f32")>; 142906f32e7eSjoerg 143006f32e7eSjoerg// ASIMD FP divide, Q-form, F32 143106f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_F01], (instrs FDIVv4f32)>; 143206f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_F01], (instregex "FDIVv4f32")>; 143306f32e7eSjoerg 143406f32e7eSjoerg// ASIMD FP divide, Q-form, F64 143506f32e7eSjoergdef : InstRW<[THX2T99Write_23Cyc_F01], (instrs FDIVv2f64)>; 143606f32e7eSjoergdef : InstRW<[THX2T99Write_23Cyc_F01], (instregex "FDIVv2f64")>; 143706f32e7eSjoerg 143806f32e7eSjoerg// ASIMD FP max/min, normal, D-form 143906f32e7eSjoerg// ASIMD FP max/min, normal, Q-form 144006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXv", "^FMAXNMv", 144106f32e7eSjoerg "^FMINv", "^FMINNMv")>; 144206f32e7eSjoerg 144306f32e7eSjoerg// ASIMD FP max/min, pairwise, D-form 144406f32e7eSjoerg// ASIMD FP max/min, pairwise, Q-form 144506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXPv", "^FMAXNMPv", 144606f32e7eSjoerg "^FMINPv", "^FMINNMPv")>; 144706f32e7eSjoerg 144806f32e7eSjoerg// ASIMD FP max/min, reduce 144906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXVv", "^FMAXNMVv", 145006f32e7eSjoerg "^FMINVv", "^FMINNMVv")>; 145106f32e7eSjoerg 145206f32e7eSjoerg// ASIMD FP multiply, D-form, FZ 145306f32e7eSjoerg// ASIMD FP multiply, D-form, no FZ 145406f32e7eSjoerg// ASIMD FP multiply, Q-form, FZ 145506f32e7eSjoerg// ASIMD FP multiply, Q-form, no FZ 145606f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMULv", "^FMULXv")>; 145706f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], 145806f32e7eSjoerg (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 145906f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], 146006f32e7eSjoerg (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; 146106f32e7eSjoerg 146206f32e7eSjoerg// ASIMD FP multiply accumulate, Dform, FZ 146306f32e7eSjoerg// ASIMD FP multiply accumulate, Dform, no FZ 146406f32e7eSjoerg// ASIMD FP multiply accumulate, Qform, FZ 146506f32e7eSjoerg// ASIMD FP multiply accumulate, Qform, no FZ 146606f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMLAv", "^FMLSv")>; 146706f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], 146806f32e7eSjoerg (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 146906f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], 147006f32e7eSjoerg (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; 147106f32e7eSjoerg 147206f32e7eSjoerg// ASIMD FP negate 147306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FNEGv")>; 147406f32e7eSjoerg 147506f32e7eSjoerg//-- 147606f32e7eSjoerg// 3.14 ASIMD Miscellaneous Instructions 147706f32e7eSjoerg//-- 147806f32e7eSjoerg 147906f32e7eSjoerg// ASIMD bit reverse 148006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^RBITv")>; 148106f32e7eSjoerg 148206f32e7eSjoerg// ASIMD bitwise insert, D-form 148306f32e7eSjoerg// ASIMD bitwise insert, Q-form 148406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 1485*da58b97aSjoerg (instregex "^BIFv", "^BITv", "^BSLv", "^BSPv")>; 148606f32e7eSjoerg 148706f32e7eSjoerg// ASIMD count, D-form 148806f32e7eSjoerg// ASIMD count, Q-form 148906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 149006f32e7eSjoerg (instregex "^CLSv", "^CLZv", "^CNTv")>; 149106f32e7eSjoerg 149206f32e7eSjoerg// ASIMD duplicate, gen reg 149306f32e7eSjoerg// ASIMD duplicate, element 149406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv")>; 149506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^CPY")>; 149606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv.+gpr")>; 149706f32e7eSjoerg 149806f32e7eSjoerg// ASIMD extract 149906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^EXTv")>; 150006f32e7eSjoerg 150106f32e7eSjoerg// ASIMD extract narrow 150206f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^XTNv")>; 150306f32e7eSjoerg 150406f32e7eSjoerg// ASIMD extract narrow, saturating 150506f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_F01], 150606f32e7eSjoerg (instregex "^SQXTNv", "^SQXTUNv", "^UQXTNv")>; 150706f32e7eSjoerg 150806f32e7eSjoerg// ASIMD insert, element to element 150906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>; 151006f32e7eSjoerg 151106f32e7eSjoerg// ASIMD transfer, element to gen reg 151206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>; 151306f32e7eSjoerg 151406f32e7eSjoerg// ASIMD move, integer immed 151506f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>; 151606f32e7eSjoerg 151706f32e7eSjoerg// ASIMD move, FP immed 151806f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>; 151906f32e7eSjoerg 152006f32e7eSjoerg// ASIMD reciprocal estimate, D-form 152106f32e7eSjoerg// ASIMD reciprocal estimate, Q-form 152206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 152306f32e7eSjoerg (instregex "^FRECPEv", "^FRECPXv", "^URECPEv", 152406f32e7eSjoerg "^FRSQRTEv", "^URSQRTEv")>; 152506f32e7eSjoerg 152606f32e7eSjoerg// ASIMD reciprocal step, D-form, FZ 152706f32e7eSjoerg// ASIMD reciprocal step, D-form, no FZ 152806f32e7eSjoerg// ASIMD reciprocal step, Q-form, FZ 152906f32e7eSjoerg// ASIMD reciprocal step, Q-form, no FZ 153006f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FRECPSv", "^FRSQRTSv")>; 153106f32e7eSjoerg 153206f32e7eSjoerg// ASIMD reverse 153306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], 153406f32e7eSjoerg (instregex "^REV16v", "^REV32v", "^REV64v")>; 153506f32e7eSjoerg 153606f32e7eSjoerg// ASIMD table lookup, D-form 153706f32e7eSjoerg// ASIMD table lookup, Q-form 153806f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_F01], (instregex "^TBLv", "^TBXv")>; 153906f32e7eSjoerg 154006f32e7eSjoerg// ASIMD transfer, element to word or word 154106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>; 154206f32e7eSjoerg 154306f32e7eSjoerg// ASIMD transfer, element to gen reg 154406f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "(S|U)MOVv.*")>; 154506f32e7eSjoerg 154606f32e7eSjoerg// ASIMD transfer gen reg to element 154706f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>; 154806f32e7eSjoerg 154906f32e7eSjoerg// ASIMD transpose 155006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1v", "^TRN2v", 155106f32e7eSjoerg "^UZP1v", "^UZP2v")>; 155206f32e7eSjoerg 155306f32e7eSjoerg// ASIMD unzip/zip 155406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>; 155506f32e7eSjoerg 155606f32e7eSjoerg//-- 155706f32e7eSjoerg// 3.15 ASIMD Load Instructions 155806f32e7eSjoerg//-- 155906f32e7eSjoerg 156006f32e7eSjoerg// ASIMD load, 1 element, multiple, 1 reg, D-form 156106f32e7eSjoerg// ASIMD load, 1 element, multiple, 1 reg, Q-form 156206f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], 156306f32e7eSjoerg (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 156406f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01, WriteAdr], 156506f32e7eSjoerg (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 156606f32e7eSjoerg 156706f32e7eSjoerg// ASIMD load, 1 element, multiple, 2 reg, D-form 156806f32e7eSjoerg// ASIMD load, 1 element, multiple, 2 reg, Q-form 156906f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01], 157006f32e7eSjoerg (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 157106f32e7eSjoergdef : InstRW<[THX2T99Write_4Cyc_LS01, WriteAdr], 157206f32e7eSjoerg (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 157306f32e7eSjoerg 157406f32e7eSjoerg// ASIMD load, 1 element, multiple, 3 reg, D-form 157506f32e7eSjoerg// ASIMD load, 1 element, multiple, 3 reg, Q-form 157606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01], 157706f32e7eSjoerg (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 157806f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01, WriteAdr], 157906f32e7eSjoerg (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 158006f32e7eSjoerg 158106f32e7eSjoerg// ASIMD load, 1 element, multiple, 4 reg, D-form 158206f32e7eSjoerg// ASIMD load, 1 element, multiple, 4 reg, Q-form 158306f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01], 158406f32e7eSjoerg (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 158506f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01, WriteAdr], 158606f32e7eSjoerg (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 158706f32e7eSjoerg 158806f32e7eSjoerg// ASIMD load, 1 element, one lane, B/H/S 158906f32e7eSjoerg// ASIMD load, 1 element, one lane, D 159006f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD1i(8|16|32|64)$")>; 159106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 159206f32e7eSjoerg (instregex "^LD1i(8|16|32|64)_POST$")>; 159306f32e7eSjoerg 159406f32e7eSjoerg// ASIMD load, 1 element, all lanes, D-form, B/H/S 159506f32e7eSjoerg// ASIMD load, 1 element, all lanes, D-form, D 159606f32e7eSjoerg// ASIMD load, 1 element, all lanes, Q-form 159706f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], 159806f32e7eSjoerg (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 159906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 160006f32e7eSjoerg (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 160106f32e7eSjoerg 160206f32e7eSjoerg// ASIMD load, 2 element, multiple, D-form, B/H/S 160306f32e7eSjoerg// ASIMD load, 2 element, multiple, Q-form, D 160406f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], 160506f32e7eSjoerg (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)$")>; 160606f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 160706f32e7eSjoerg (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 160806f32e7eSjoerg 160906f32e7eSjoerg// ASIMD load, 2 element, one lane, B/H 161006f32e7eSjoerg// ASIMD load, 2 element, one lane, S 161106f32e7eSjoerg// ASIMD load, 2 element, one lane, D 161206f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD2i(8|16|32|64)$")>; 161306f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 161406f32e7eSjoerg (instregex "^LD2i(8|16|32|64)_POST$")>; 161506f32e7eSjoerg 161606f32e7eSjoerg// ASIMD load, 2 element, all lanes, D-form, B/H/S 161706f32e7eSjoerg// ASIMD load, 2 element, all lanes, D-form, D 161806f32e7eSjoerg// ASIMD load, 2 element, all lanes, Q-form 161906f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], 162006f32e7eSjoerg (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 162106f32e7eSjoergdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 162206f32e7eSjoerg (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 162306f32e7eSjoerg 162406f32e7eSjoerg// ASIMD load, 3 element, multiple, D-form, B/H/S 162506f32e7eSjoerg// ASIMD load, 3 element, multiple, Q-form, B/H/S 162606f32e7eSjoerg// ASIMD load, 3 element, multiple, Q-form, D 162706f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_LS01_F01], 162806f32e7eSjoerg (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)$")>; 162906f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_LS01_F01, WriteAdr], 163006f32e7eSjoerg (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 163106f32e7eSjoerg 163206f32e7eSjoerg// ASIMD load, 3 element, one lone, B/H 163306f32e7eSjoerg// ASIMD load, 3 element, one lane, S 163406f32e7eSjoerg// ASIMD load, 3 element, one lane, D 163506f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_LS01_F01], (instregex "^LD3i(8|16|32|64)$")>; 163606f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_LS01_F01, WriteAdr], 163706f32e7eSjoerg (instregex "^LD3i(8|16|32|64)_POST$")>; 163806f32e7eSjoerg 163906f32e7eSjoerg// ASIMD load, 3 element, all lanes, D-form, B/H/S 164006f32e7eSjoerg// ASIMD load, 3 element, all lanes, D-form, D 164106f32e7eSjoerg// ASIMD load, 3 element, all lanes, Q-form, B/H/S 164206f32e7eSjoerg// ASIMD load, 3 element, all lanes, Q-form, D 164306f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_LS01_F01], 164406f32e7eSjoerg (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 164506f32e7eSjoergdef : InstRW<[THX2T99Write_7Cyc_LS01_F01, WriteAdr], 164606f32e7eSjoerg (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 164706f32e7eSjoerg 164806f32e7eSjoerg// ASIMD load, 4 element, multiple, D-form, B/H/S 164906f32e7eSjoerg// ASIMD load, 4 element, multiple, Q-form, B/H/S 165006f32e7eSjoerg// ASIMD load, 4 element, multiple, Q-form, D 165106f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_LS01_F01], 165206f32e7eSjoerg (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>; 165306f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_LS01_F01, WriteAdr], 165406f32e7eSjoerg (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 165506f32e7eSjoerg 165606f32e7eSjoerg// ASIMD load, 4 element, one lane, B/H 165706f32e7eSjoerg// ASIMD load, 4 element, one lane, S 165806f32e7eSjoerg// ASIMD load, 4 element, one lane, D 165906f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_F01], (instregex "^LD4i(8|16|32|64)$")>; 166006f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_F01, WriteAdr], 166106f32e7eSjoerg (instregex "^LD4i(8|16|32|64)_POST$")>; 166206f32e7eSjoerg 166306f32e7eSjoerg// ASIMD load, 4 element, all lanes, D-form, B/H/S 166406f32e7eSjoerg// ASIMD load, 4 element, all lanes, D-form, D 166506f32e7eSjoerg// ASIMD load, 4 element, all lanes, Q-form, B/H/S 166606f32e7eSjoerg// ASIMD load, 4 element, all lanes, Q-form, D 166706f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_F01], 166806f32e7eSjoerg (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 166906f32e7eSjoergdef : InstRW<[THX2T99Write_6Cyc_LS01_F01, WriteAdr], 167006f32e7eSjoerg (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 167106f32e7eSjoerg 167206f32e7eSjoerg//-- 167306f32e7eSjoerg// 3.16 ASIMD Store Instructions 167406f32e7eSjoerg//-- 167506f32e7eSjoerg 167606f32e7eSjoerg// ASIMD store, 1 element, multiple, 1 reg, D-form 167706f32e7eSjoerg// ASIMD store, 1 element, multiple, 1 reg, Q-form 167806f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], 167906f32e7eSjoerg (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 168006f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 168106f32e7eSjoerg (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 168206f32e7eSjoerg 168306f32e7eSjoerg// ASIMD store, 1 element, multiple, 2 reg, D-form 168406f32e7eSjoerg// ASIMD store, 1 element, multiple, 2 reg, Q-form 168506f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], 168606f32e7eSjoerg (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 168706f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 168806f32e7eSjoerg (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 168906f32e7eSjoerg 169006f32e7eSjoerg// ASIMD store, 1 element, multiple, 3 reg, D-form 169106f32e7eSjoerg// ASIMD store, 1 element, multiple, 3 reg, Q-form 169206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], 169306f32e7eSjoerg (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 169406f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 169506f32e7eSjoerg (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 169606f32e7eSjoerg 169706f32e7eSjoerg// ASIMD store, 1 element, multiple, 4 reg, D-form 169806f32e7eSjoerg// ASIMD store, 1 element, multiple, 4 reg, Q-form 169906f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01], 170006f32e7eSjoerg (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 170106f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 170206f32e7eSjoerg (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 170306f32e7eSjoerg 170406f32e7eSjoerg// ASIMD store, 1 element, one lane, B/H/S 170506f32e7eSjoerg// ASIMD store, 1 element, one lane, D 170606f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 170706f32e7eSjoerg (instregex "^ST1i(8|16|32|64)$")>; 170806f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 170906f32e7eSjoerg (instregex "^ST1i(8|16|32|64)_POST$")>; 171006f32e7eSjoerg 171106f32e7eSjoerg// ASIMD store, 2 element, multiple, D-form, B/H/S 171206f32e7eSjoerg// ASIMD store, 2 element, multiple, Q-form, B/H/S 171306f32e7eSjoerg// ASIMD store, 2 element, multiple, Q-form, D 171406f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 171506f32e7eSjoerg (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)$")>; 171606f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 171706f32e7eSjoerg (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 171806f32e7eSjoerg 171906f32e7eSjoerg// ASIMD store, 2 element, one lane, B/H/S 172006f32e7eSjoerg// ASIMD store, 2 element, one lane, D 172106f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 172206f32e7eSjoerg (instregex "^ST2i(8|16|32|64)$")>; 172306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 172406f32e7eSjoerg (instregex "^ST2i(8|16|32|64)_POST$")>; 172506f32e7eSjoerg 172606f32e7eSjoerg// ASIMD store, 3 element, multiple, D-form, B/H/S 172706f32e7eSjoerg// ASIMD store, 3 element, multiple, Q-form, B/H/S 172806f32e7eSjoerg// ASIMD store, 3 element, multiple, Q-form, D 172906f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 173006f32e7eSjoerg (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)$")>; 173106f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 173206f32e7eSjoerg (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 173306f32e7eSjoerg 173406f32e7eSjoerg// ASIMD store, 3 element, one lane, B/H 173506f32e7eSjoerg// ASIMD store, 3 element, one lane, S 173606f32e7eSjoerg// ASIMD store, 3 element, one lane, D 173706f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST3i(8|16|32|64)$")>; 173806f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 173906f32e7eSjoerg (instregex "^ST3i(8|16|32|64)_POST$")>; 174006f32e7eSjoerg 174106f32e7eSjoerg// ASIMD store, 4 element, multiple, D-form, B/H/S 174206f32e7eSjoerg// ASIMD store, 4 element, multiple, Q-form, B/H/S 174306f32e7eSjoerg// ASIMD store, 4 element, multiple, Q-form, D 174406f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 174506f32e7eSjoerg (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>; 174606f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 174706f32e7eSjoerg (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 174806f32e7eSjoerg 174906f32e7eSjoerg// ASIMD store, 4 element, one lane, B/H 175006f32e7eSjoerg// ASIMD store, 4 element, one lane, S 175106f32e7eSjoerg// ASIMD store, 4 element, one lane, D 175206f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST4i(8|16|32|64)$")>; 175306f32e7eSjoergdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 175406f32e7eSjoerg (instregex "^ST4i(8|16|32|64)_POST$")>; 175506f32e7eSjoerg 175606f32e7eSjoerg// V8.1a Atomics (LSE) 175706f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 175806f32e7eSjoerg (instrs CASB, CASH, CASW, CASX)>; 175906f32e7eSjoerg 176006f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 176106f32e7eSjoerg (instrs CASAB, CASAH, CASAW, CASAX)>; 176206f32e7eSjoerg 176306f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 176406f32e7eSjoerg (instrs CASLB, CASLH, CASLW, CASLX)>; 176506f32e7eSjoerg 176606f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 176706f32e7eSjoerg (instrs CASALB, CASALH, CASALW, CASALX)>; 176806f32e7eSjoerg 176906f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 177006f32e7eSjoerg (instrs LDLARB, LDLARH, LDLARW, LDLARX)>; 177106f32e7eSjoerg 177206f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 177306f32e7eSjoerg (instrs LDADDB, LDADDH, LDADDW, LDADDX)>; 177406f32e7eSjoerg 177506f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 177606f32e7eSjoerg (instrs LDADDAB, LDADDAH, LDADDAW, LDADDAX)>; 177706f32e7eSjoerg 177806f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 177906f32e7eSjoerg (instrs LDADDLB, LDADDLH, LDADDLW, LDADDLX)>; 178006f32e7eSjoerg 178106f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 178206f32e7eSjoerg (instrs LDADDALB, LDADDALH, LDADDALW, LDADDALX)>; 178306f32e7eSjoerg 178406f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 178506f32e7eSjoerg (instrs LDCLRB, LDCLRH, LDCLRW, LDCLRX)>; 178606f32e7eSjoerg 178706f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 178806f32e7eSjoerg (instrs LDCLRAB, LDCLRAH, LDCLRAW, LDCLRAX)>; 178906f32e7eSjoerg 179006f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 179106f32e7eSjoerg (instrs LDCLRLB, LDCLRLH, LDCLRLW, LDCLRLX)>; 179206f32e7eSjoerg 179306f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 179406f32e7eSjoerg (instrs LDCLRALB, LDCLRALH, LDCLRALW, LDCLRALX)>; 179506f32e7eSjoerg 179606f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 179706f32e7eSjoerg (instrs LDEORB, LDEORH, LDEORW, LDEORX)>; 179806f32e7eSjoerg 179906f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 180006f32e7eSjoerg (instrs LDEORAB, LDEORAH, LDEORAW, LDEORAX)>; 180106f32e7eSjoerg 180206f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 180306f32e7eSjoerg (instrs LDEORLB, LDEORLH, LDEORLW, LDEORLX)>; 180406f32e7eSjoerg 180506f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 180606f32e7eSjoerg (instrs LDEORALB, LDEORALH, LDEORALW, LDEORALX)>; 180706f32e7eSjoerg 180806f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 180906f32e7eSjoerg (instrs LDSETB, LDSETH, LDSETW, LDSETX)>; 181006f32e7eSjoerg 181106f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 181206f32e7eSjoerg (instrs LDSETAB, LDSETAH, LDSETAW, LDSETAX)>; 181306f32e7eSjoerg 181406f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 181506f32e7eSjoerg (instrs LDSETLB, LDSETLH, LDSETLW, LDSETLX)>; 181606f32e7eSjoerg 181706f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 181806f32e7eSjoerg (instrs LDSETALB, LDSETALH, LDSETALW, LDSETALX)>; 181906f32e7eSjoerg 182006f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 182106f32e7eSjoerg (instrs LDSMAXB, LDSMAXH, LDSMAXW, LDSMAXX, 182206f32e7eSjoerg LDSMAXAB, LDSMAXAH, LDSMAXAW, LDSMAXAX, 182306f32e7eSjoerg LDSMAXLB, LDSMAXLH, LDSMAXLW, LDSMAXLX, 182406f32e7eSjoerg LDSMAXALB, LDSMAXALH, LDSMAXALW, LDSMAXALX)>; 182506f32e7eSjoerg 182606f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 182706f32e7eSjoerg (instrs LDSMINB, LDSMINH, LDSMINW, LDSMINX, 182806f32e7eSjoerg LDSMINAB, LDSMINAH, LDSMINAW, LDSMINAX, 182906f32e7eSjoerg LDSMINLB, LDSMINLH, LDSMINLW, LDSMINLX, 183006f32e7eSjoerg LDSMINALB, LDSMINALH, LDSMINALW, LDSMINALX)>; 183106f32e7eSjoerg 183206f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 183306f32e7eSjoerg (instrs LDUMAXB, LDUMAXH, LDUMAXW, LDUMAXX, 183406f32e7eSjoerg LDUMAXAB, LDUMAXAH, LDUMAXAW, LDUMAXAX, 183506f32e7eSjoerg LDUMAXLB, LDUMAXLH, LDUMAXLW, LDUMAXLX, 183606f32e7eSjoerg LDUMAXALB, LDUMAXALH, LDUMAXALW, LDUMAXALX)>; 183706f32e7eSjoerg 183806f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 183906f32e7eSjoerg (instrs LDUMINB, LDUMINH, LDUMINW, LDUMINX, 184006f32e7eSjoerg LDUMINAB, LDUMINAH, LDUMINAW, LDUMINAX, 184106f32e7eSjoerg LDUMINLB, LDUMINLH, LDUMINLW, LDUMINLX, 184206f32e7eSjoerg LDUMINALB, LDUMINALH, LDUMINALW, LDUMINALX)>; 184306f32e7eSjoerg 184406f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 184506f32e7eSjoerg (instrs SWPB, SWPH, SWPW, SWPX)>; 184606f32e7eSjoerg 184706f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 184806f32e7eSjoerg (instrs SWPAB, SWPAH, SWPAW, SWPAX)>; 184906f32e7eSjoerg 185006f32e7eSjoergdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 185106f32e7eSjoerg (instrs SWPLB, SWPLH, SWPLW, SWPLX)>; 185206f32e7eSjoerg 185306f32e7eSjoergdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 185406f32e7eSjoerg (instrs SWPALB, SWPALH, SWPALW, SWPALX)>; 185506f32e7eSjoerg 185606f32e7eSjoergdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 185706f32e7eSjoerg (instrs STLLRB, STLLRH, STLLRW, STLLRX)>; 185806f32e7eSjoerg 185906f32e7eSjoerg} // SchedModel = ThunderX2T99Model 186006f32e7eSjoerg 1861