1*da58b97aSjoerg//===-- M68kInstrCompiler.td - Pseudos and Patterns ------*- tablegen -*-===// 2*da58b97aSjoerg// 3*da58b97aSjoerg// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*da58b97aSjoerg// See https://llvm.org/LICENSE.txt for license information. 5*da58b97aSjoerg// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*da58b97aSjoerg// 7*da58b97aSjoerg//===----------------------------------------------------------------------===// 8*da58b97aSjoerg/// 9*da58b97aSjoerg/// \file 10*da58b97aSjoerg/// This file describes the various pseudo instructions used by the compiler, 11*da58b97aSjoerg/// as well as Pat patterns used during instruction selection. 12*da58b97aSjoerg/// 13*da58b97aSjoerg//===----------------------------------------------------------------------===// 14*da58b97aSjoerg 15*da58b97aSjoerg//===----------------------------------------------------------------------===// 16*da58b97aSjoerg// ConstantPool, GlobalAddress, ExternalSymbol, and JumpTable 17*da58b97aSjoerg//===----------------------------------------------------------------------===// 18*da58b97aSjoerg 19*da58b97aSjoergdef : Pat<(i32 (MxWrapper tconstpool :$src)), (MOV32ri tconstpool :$src)>; 20*da58b97aSjoergdef : Pat<(i32 (MxWrapper tglobaladdr :$src)), (MOV32ri tglobaladdr :$src)>; 21*da58b97aSjoergdef : Pat<(i32 (MxWrapper texternalsym :$src)), (MOV32ri texternalsym :$src)>; 22*da58b97aSjoergdef : Pat<(i32 (MxWrapper tjumptable :$src)), (MOV32ri tjumptable :$src)>; 23*da58b97aSjoergdef : Pat<(i32 (MxWrapper tblockaddress :$src)), (MOV32ri tblockaddress :$src)>; 24*da58b97aSjoerg 25*da58b97aSjoergdef : Pat<(add MxDRD32:$src, (MxWrapper tconstpool:$opd)), 26*da58b97aSjoerg (ADD32ri MxDRD32:$src, tconstpool:$opd)>; 27*da58b97aSjoergdef : Pat<(add MxARD32:$src, (MxWrapper tjumptable:$opd)), 28*da58b97aSjoerg (ADD32ri MxARD32:$src, tjumptable:$opd)>; 29*da58b97aSjoergdef : Pat<(add MxARD32:$src, (MxWrapper tglobaladdr :$opd)), 30*da58b97aSjoerg (ADD32ri MxARD32:$src, tglobaladdr:$opd)>; 31*da58b97aSjoergdef : Pat<(add MxARD32:$src, (MxWrapper texternalsym:$opd)), 32*da58b97aSjoerg (ADD32ri MxARD32:$src, texternalsym:$opd)>; 33*da58b97aSjoergdef : Pat<(add MxARD32:$src, (MxWrapper tblockaddress:$opd)), 34*da58b97aSjoerg (ADD32ri MxARD32:$src, tblockaddress:$opd)>; 35*da58b97aSjoerg 36*da58b97aSjoergdef : Pat<(store (i32 (MxWrapper tglobaladdr:$src)), iPTR:$dst), 37*da58b97aSjoerg (MOV32ji MxARI32:$dst, tglobaladdr:$src)>; 38*da58b97aSjoergdef : Pat<(store (i32 (MxWrapper texternalsym:$src)), iPTR:$dst), 39*da58b97aSjoerg (MOV32ji MxARI32:$dst, texternalsym:$src)>; 40*da58b97aSjoergdef : Pat<(store (i32 (MxWrapper tblockaddress:$src)), iPTR:$dst), 41*da58b97aSjoerg (MOV32ji MxARI32:$dst, tblockaddress:$src)>; 42*da58b97aSjoerg 43*da58b97aSjoergdef : Pat<(i32 (MxWrapperPC tconstpool :$src)), (LEA32q tconstpool :$src)>; 44*da58b97aSjoergdef : Pat<(i32 (MxWrapperPC tglobaladdr :$src)), (LEA32q tglobaladdr :$src)>; 45*da58b97aSjoergdef : Pat<(i32 (MxWrapperPC texternalsym :$src)), (LEA32q texternalsym :$src)>; 46*da58b97aSjoergdef : Pat<(i32 (MxWrapperPC tjumptable :$src)), (LEA32q tjumptable :$src)>; 47*da58b97aSjoergdef : Pat<(i32 (MxWrapperPC tblockaddress :$src)), (LEA32q tblockaddress :$src)>; 48*da58b97aSjoerg 49*da58b97aSjoerg 50*da58b97aSjoerg//===----------------------------------------------------------------------===// 51*da58b97aSjoerg// Conditional Move Pseudo Instructions 52*da58b97aSjoerg// 53*da58b97aSjoerg// CMOV* - Used to implement the SELECT DAG operation. Expanded after 54*da58b97aSjoerg// instruction selection into a branch sequence. 55*da58b97aSjoerg//===----------------------------------------------------------------------===// 56*da58b97aSjoerg 57*da58b97aSjoerglet usesCustomInserter = 1, Uses = [CCR] in 58*da58b97aSjoergclass MxCMove<MxType TYPE> 59*da58b97aSjoerg : MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$t, TYPE.ROp:$f, i8imm:$cond), 60*da58b97aSjoerg [(set TYPE.VT:$dst, 61*da58b97aSjoerg (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>; 62*da58b97aSjoerg 63*da58b97aSjoergdef CMOV8d : MxCMove<MxType8d>; 64*da58b97aSjoergdef CMOV16d : MxCMove<MxType16d>; 65*da58b97aSjoergdef CMOV32r : MxCMove<MxType32r>; 66*da58b97aSjoerg 67*da58b97aSjoerg 68*da58b97aSjoerg//===----------------------------------------------------------------------===// 69*da58b97aSjoerg// Calls 70*da58b97aSjoerg//===----------------------------------------------------------------------===// 71*da58b97aSjoerg 72*da58b97aSjoerg// ADJCALLSTACKDOWN/UP implicitly use/def %SP because they may be expanded into 73*da58b97aSjoerg// a stack adjustment and the codegen must know that they may modify the stack 74*da58b97aSjoerg// pointer before prolog-epilog rewriting occurs. 75*da58b97aSjoerg// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 76*da58b97aSjoerg// sub / add which can clobber CCR. 77*da58b97aSjoerglet Defs = [SP, CCR], Uses = [SP] in { 78*da58b97aSjoerg 79*da58b97aSjoerg def ADJCALLSTACKDOWN 80*da58b97aSjoerg : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 81*da58b97aSjoerg [(MxCallSeqStart timm:$amt1, timm:$amt2)]>; 82*da58b97aSjoerg 83*da58b97aSjoerg def ADJCALLSTACKUP 84*da58b97aSjoerg : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 85*da58b97aSjoerg [(MxCallSeqEnd timm:$amt1, timm:$amt2)]>; 86*da58b97aSjoerg 87*da58b97aSjoerg} // Defs 88*da58b97aSjoerg 89*da58b97aSjoerg//===----------------------------------------------------------------------===// 90*da58b97aSjoerg// Tail Call 91*da58b97aSjoerg//===----------------------------------------------------------------------===// 92*da58b97aSjoerg 93*da58b97aSjoerg// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 94*da58b97aSjoerg// can never use callee-saved registers. That is the purpose of the XR32_TC 95*da58b97aSjoerg// register classes. 96*da58b97aSjoerg 97*da58b97aSjoerg// FIXME TC is disabled for PIC mode because the global base 98*da58b97aSjoerg// register which is part of the address mode may be assigned a 99*da58b97aSjoerg// callee-saved register. 100*da58b97aSjoergdef : Pat<(MxTCRet (load MxCP_ARII:$dst), imm:$adj), 101*da58b97aSjoerg (TCRETURNj (MOV32af_TC MxARII32:$dst), imm:$adj)>, 102*da58b97aSjoerg Requires<[IsNotPIC]>; 103*da58b97aSjoerg 104*da58b97aSjoergdef : Pat<(MxTCRet AR32_TC:$dst, imm:$adj), 105*da58b97aSjoerg (TCRETURNj MxARI32_TC:$dst, imm:$adj)>; 106*da58b97aSjoerg 107*da58b97aSjoergdef : Pat<(MxTCRet (i32 tglobaladdr:$dst), imm:$adj), 108*da58b97aSjoerg (TCRETURNq MxPCD32:$dst, imm:$adj)>; 109*da58b97aSjoerg 110*da58b97aSjoergdef : Pat<(MxTCRet (i32 texternalsym:$dst), imm:$adj), 111*da58b97aSjoerg (TCRETURNq MxPCD32:$dst, imm:$adj)>; 112*da58b97aSjoerg 113*da58b97aSjoerg 114*da58b97aSjoerg//===----------------------------------------------------------------------===// 115*da58b97aSjoerg// Segmented Stack 116*da58b97aSjoerg// 117*da58b97aSjoerg// When using segmented stacks these are lowered into instructions which first 118*da58b97aSjoerg// check if the current stacklet has enough free memory. If it does, memory is 119*da58b97aSjoerg// allocated by bumping the stack pointer. Otherwise memory is allocated from 120*da58b97aSjoerg// the heap. 121*da58b97aSjoerg//===----------------------------------------------------------------------===// 122*da58b97aSjoerg 123*da58b97aSjoerglet Defs = [SP, CCR], Uses = [SP] in 124*da58b97aSjoerglet usesCustomInserter = 1 in 125*da58b97aSjoergdef SALLOCA : MxPseudo<(outs MxARD32:$dst), (ins MxARD32:$size), 126*da58b97aSjoerg [(set iPTR:$dst, (MxSegAlloca iPTR:$size))]>; 127