1*da58b97aSjoerg//===------ M68kInstrShiftRotate.td - Logical Instrs -----*- tablegen -*-===// 2*da58b97aSjoerg// 3*da58b97aSjoerg// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*da58b97aSjoerg// See https://llvm.org/LICENSE.txt for license information. 5*da58b97aSjoerg// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*da58b97aSjoerg// 7*da58b97aSjoerg//===----------------------------------------------------------------------===// 8*da58b97aSjoerg/// 9*da58b97aSjoerg/// \file 10*da58b97aSjoerg/// This file describes the logical instructions in the M68k architecture. 11*da58b97aSjoerg/// Here is the current status of the file: 12*da58b97aSjoerg/// 13*da58b97aSjoerg/// Machine: 14*da58b97aSjoerg/// 15*da58b97aSjoerg/// SHL [~] ASR [~] LSR [~] SWAP [ ] 16*da58b97aSjoerg/// ROL [~] ROR [~] ROXL [ ] ROXR [ ] 17*da58b97aSjoerg/// 18*da58b97aSjoerg/// Map: 19*da58b97aSjoerg/// 20*da58b97aSjoerg/// [ ] - was not touched at all 21*da58b97aSjoerg/// [!] - requires extarnal stuff implemented 22*da58b97aSjoerg/// [~] - in progress but usable 23*da58b97aSjoerg/// [x] - done 24*da58b97aSjoerg/// 25*da58b97aSjoerg//===----------------------------------------------------------------------===// 26*da58b97aSjoerg 27*da58b97aSjoergdef MxRODI_R : MxBead1Bit<0>; 28*da58b97aSjoergdef MxRODI_L : MxBead1Bit<1>; 29*da58b97aSjoerg 30*da58b97aSjoergdef MxROOP_AS : MxBead2Bits<0b00>; 31*da58b97aSjoergdef MxROOP_LS : MxBead2Bits<0b01>; 32*da58b97aSjoergdef MxROOP_ROX : MxBead2Bits<0b10>; 33*da58b97aSjoergdef MxROOP_RO : MxBead2Bits<0b11>; 34*da58b97aSjoerg 35*da58b97aSjoerg/// ------------+---------+---+------+---+------+--------- 36*da58b97aSjoerg/// F E D C | B A 9 | 8 | 7 6 | 5 | 4 3 | 2 1 0 37*da58b97aSjoerg/// ------------+---------+---+------+---+------+--------- 38*da58b97aSjoerg/// 1 1 1 0 | REG/IMM | D | SIZE |R/I| OP | REG 39*da58b97aSjoerg/// ------------+---------+---+------+---+------+--------- 40*da58b97aSjoergclass MxSREncoding_R<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE> 41*da58b97aSjoerg : MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<1>, SIZE, DIRECTION, 42*da58b97aSjoerg MxBeadDReg<2>, MxBead4Bits<0b1110>>; 43*da58b97aSjoerg 44*da58b97aSjoergclass MxSREncoding_I<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE> 45*da58b97aSjoerg : MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<0>, SIZE, DIRECTION, 46*da58b97aSjoerg MxBead3Imm<2, 1>, MxBead4Bits<0b1110>>; 47*da58b97aSjoerg 48*da58b97aSjoerg// $reg <- $reg op $reg 49*da58b97aSjoergclass MxSR_DD<string MN, MxType TYPE, SDNode NODE, 50*da58b97aSjoerg MxBead1Bit RODI, MxBead2Bits ROOP> 51*da58b97aSjoerg : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd), 52*da58b97aSjoerg MN#"."#TYPE.Prefix#"\t$opd, $dst", 53*da58b97aSjoerg [(set TYPE.VT:$dst, (NODE TYPE.VT:$src, TYPE.VT:$opd))], 54*da58b97aSjoerg MxSREncoding_R<RODI, ROOP, 55*da58b97aSjoerg !cast<MxEncSize>("MxEncSize"#TYPE.Size)>>; 56*da58b97aSjoerg 57*da58b97aSjoerg// $reg <- $reg op $imm 58*da58b97aSjoergclass MxSR_DI<string MN, MxType TYPE, SDNode NODE, 59*da58b97aSjoerg MxBead1Bit RODI, MxBead2Bits ROOP> 60*da58b97aSjoerg : MxInst<(outs TYPE.ROp:$dst), 61*da58b97aSjoerg (ins TYPE.ROp:$src, !cast<Operand>("Mxi"#TYPE.Size#"imm"):$opd), 62*da58b97aSjoerg MN#"."#TYPE.Prefix#"\t$opd, $dst", 63*da58b97aSjoerg [(set TYPE.VT:$dst, 64*da58b97aSjoerg (NODE TYPE.VT:$src, 65*da58b97aSjoerg !cast<ImmLeaf>("Mximm"#TYPE.Size#"_1to8"):$opd))], 66*da58b97aSjoerg MxSREncoding_I<RODI, ROOP, 67*da58b97aSjoerg !cast<MxEncSize>("MxEncSize"#TYPE.Size)>>; 68*da58b97aSjoerg 69*da58b97aSjoergmulticlass MxSROp<string MN, SDNode NODE, MxBead1Bit RODI, MxBead2Bits ROOP> { 70*da58b97aSjoerg 71*da58b97aSjoerg let Defs = [CCR] in { 72*da58b97aSjoerg let Constraints = "$src = $dst" in { 73*da58b97aSjoerg 74*da58b97aSjoerg def NAME#"8dd" : MxSR_DD<MN, MxType8d, NODE, RODI, ROOP>; 75*da58b97aSjoerg def NAME#"16dd" : MxSR_DD<MN, MxType16d, NODE, RODI, ROOP>; 76*da58b97aSjoerg def NAME#"32dd" : MxSR_DD<MN, MxType32d, NODE, RODI, ROOP>; 77*da58b97aSjoerg 78*da58b97aSjoerg def NAME#"8di" : MxSR_DI<MN, MxType8d, NODE, RODI, ROOP>; 79*da58b97aSjoerg def NAME#"16di" : MxSR_DI<MN, MxType16d, NODE, RODI, ROOP>; 80*da58b97aSjoerg def NAME#"32di" : MxSR_DI<MN, MxType32d, NODE, RODI, ROOP>; 81*da58b97aSjoerg 82*da58b97aSjoerg } // $src = $dst 83*da58b97aSjoerg } // Defs = [CCR] 84*da58b97aSjoerg 85*da58b97aSjoerg} // MxBiArOp_RF 86*da58b97aSjoerg 87*da58b97aSjoergdefm SHL : MxSROp<"lsl", shl, MxRODI_L, MxROOP_LS>; 88*da58b97aSjoergdefm LSR : MxSROp<"lsr", srl, MxRODI_R, MxROOP_LS>; 89*da58b97aSjoergdefm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>; 90*da58b97aSjoerg 91*da58b97aSjoergdefm ROL : MxSROp<"rol", rotl, MxRODI_L, MxROOP_RO>; 92*da58b97aSjoergdefm ROR : MxSROp<"ror", rotr, MxRODI_R, MxROOP_RO>; 93