1 /* Opcode table for the ARC. 2 Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010 3 Free Software Foundation, Inc. 4 Contributed by Doug Evans (dje@cygnus.com). 5 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 7 the GNU Binutils. 8 9 GAS/GDB is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS/GDB is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GAS or GDB; see the file COPYING3. If not, write to 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 /* List of the various cpu types. 25 The tables currently use bit masks to say whether the instruction or 26 whatever is supported by a particular cpu. This lets us have one entry 27 apply to several cpus. 28 29 The `base' cpu must be 0. The cpu type is treated independently of 30 endianness. The complete `mach' number includes endianness. 31 These values are internal to opcodes/bfd/binutils/gas. */ 32 #define ARC_MACH_5 0 33 #define ARC_MACH_6 1 34 #define ARC_MACH_7 2 35 #define ARC_MACH_8 4 36 37 /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ 38 #define ARC_MACH_BIG 16 39 40 /* Mask of number of bits necessary to record cpu type. */ 41 #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) 42 43 /* Mask of number of bits necessary to record cpu type + endianness. */ 44 #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) 45 46 /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ 47 48 typedef unsigned int arc_insn; 49 50 struct arc_opcode { 51 char *syntax; /* syntax of insn */ 52 unsigned long mask, value; /* recognize insn if (op&mask) == value */ 53 int flags; /* various flag bits */ 54 55 /* Values for `flags'. */ 56 57 /* Return CPU number, given flag bits. */ 58 #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 59 60 /* Return MACH number, given flag bits. */ 61 #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) 62 63 /* First opcode flag bit available after machine mask. */ 64 #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) 65 66 /* This insn is a conditional branch. */ 67 #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) 68 #define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) 69 #define SYNTAX_LENGTH (SYNTAX_3OP ) 70 #define SYNTAX_2OP (SYNTAX_3OP << 1) 71 #define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) 72 #define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) 73 #define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) 74 75 #define I(x) (((x) & 31) << 27) 76 #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) 77 #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) 78 #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) 79 #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ 80 81 /* These values are used to optimize assembly and disassembly. Each insn 82 is on a list of related insns (same first letter for assembly, same 83 insn code for disassembly). */ 84 85 struct arc_opcode *next_asm; /* Next instr to try during assembly. */ 86 struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ 87 88 /* Macros to create the hash values for the lists. */ 89 #define ARC_HASH_OPCODE(string) \ 90 ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) 91 #define ARC_HASH_ICODE(insn) \ 92 ((unsigned int) (insn) >> 27) 93 94 /* Macros to access `next_asm', `next_dis' so users needn't care about the 95 underlying mechanism. */ 96 #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) 97 #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) 98 }; 99 100 /* this is an "insert at front" linked list per Metaware spec 101 that new definitions override older ones. */ 102 extern struct arc_opcode *arc_ext_opcodes; 103 104 struct arc_operand_value { 105 char *name; /* eg: "eq" */ 106 short value; /* eg: 1 */ 107 unsigned char type; /* index into `arc_operands' */ 108 unsigned char flags; /* various flag bits */ 109 110 /* Values for `flags'. */ 111 112 /* Return CPU number, given flag bits. */ 113 #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 114 /* Return MACH number, given flag bits. */ 115 #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) 116 }; 117 118 struct arc_ext_operand_value { 119 struct arc_ext_operand_value *next; 120 struct arc_operand_value operand; 121 }; 122 123 extern struct arc_ext_operand_value *arc_ext_operands; 124 125 struct arc_operand { 126 /* One of the insn format chars. */ 127 unsigned char fmt; 128 129 /* The number of bits in the operand (may be unused for a modifier). */ 130 unsigned char bits; 131 132 /* How far the operand is left shifted in the instruction, or 133 the modifier's flag bit (may be unused for a modifier. */ 134 unsigned char shift; 135 136 /* Various flag bits. */ 137 int flags; 138 139 /* Values for `flags'. */ 140 141 /* This operand is a suffix to the opcode. */ 142 #define ARC_OPERAND_SUFFIX 1 143 144 /* This operand is a relative branch displacement. The disassembler 145 prints these symbolically if possible. */ 146 #define ARC_OPERAND_RELATIVE_BRANCH 2 147 148 /* This operand is an absolute branch address. The disassembler 149 prints these symbolically if possible. */ 150 #define ARC_OPERAND_ABSOLUTE_BRANCH 4 151 152 /* This operand is an address. The disassembler 153 prints these symbolically if possible. */ 154 #define ARC_OPERAND_ADDRESS 8 155 156 /* This operand is a long immediate value. */ 157 #define ARC_OPERAND_LIMM 0x10 158 159 /* This operand takes signed values. */ 160 #define ARC_OPERAND_SIGNED 0x20 161 162 /* This operand takes signed values, but also accepts a full positive 163 range of values. That is, if bits is 16, it takes any value from 164 -0x8000 to 0xffff. */ 165 #define ARC_OPERAND_SIGNOPT 0x40 166 167 /* This operand should be regarded as a negative number for the 168 purposes of overflow checking (i.e., the normal most negative 169 number is disallowed and one more than the normal most positive 170 number is allowed). This flag will only be set for a signed 171 operand. */ 172 #define ARC_OPERAND_NEGATIVE 0x80 173 174 /* This operand doesn't really exist. The program uses these operands 175 in special ways. */ 176 #define ARC_OPERAND_FAKE 0x100 177 178 /* separate flags operand for j and jl instructions */ 179 #define ARC_OPERAND_JUMPFLAGS 0x200 180 181 /* allow warnings and errors to be issued after call to insert_xxxxxx */ 182 #define ARC_OPERAND_WARN 0x400 183 #define ARC_OPERAND_ERROR 0x800 184 185 /* this is a load operand */ 186 #define ARC_OPERAND_LOAD 0x8000 187 188 /* this is a store operand */ 189 #define ARC_OPERAND_STORE 0x10000 190 191 /* Modifier values. */ 192 /* A dot is required before a suffix. Eg: .le */ 193 #define ARC_MOD_DOT 0x1000 194 195 /* A normal register is allowed (not used, but here for completeness). */ 196 #define ARC_MOD_REG 0x2000 197 198 /* An auxiliary register name is expected. */ 199 #define ARC_MOD_AUXREG 0x4000 200 201 /* Sum of all ARC_MOD_XXX bits. */ 202 #define ARC_MOD_BITS 0x7000 203 204 /* Non-zero if the operand type is really a modifier. */ 205 #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) 206 207 /* enforce read/write only register restrictions */ 208 #define ARC_REGISTER_READONLY 0x01 209 #define ARC_REGISTER_WRITEONLY 0x02 210 #define ARC_REGISTER_NOSHORT_CUT 0x04 211 212 /* Insertion function. This is used by the assembler. To insert an 213 operand value into an instruction, check this field. 214 215 If it is NULL, execute 216 i |= (p & ((1 << o->bits) - 1)) << o->shift; 217 (I is the instruction which we are filling in, O is a pointer to 218 this structure, and OP is the opcode value; this assumes twos 219 complement arithmetic). 220 221 If this field is not NULL, then simply call it with the 222 instruction and the operand value. It will return the new value 223 of the instruction. If the ERRMSG argument is not NULL, then if 224 the operand value is illegal, *ERRMSG will be set to a warning 225 string (the operand will be inserted in any case). If the 226 operand value is legal, *ERRMSG will be unchanged. 227 228 REG is non-NULL when inserting a register value. */ 229 230 arc_insn (*insert) 231 (arc_insn insn, const struct arc_operand *operand, int mods, 232 const struct arc_operand_value *reg, long value, const char **errmsg); 233 234 /* Extraction function. This is used by the disassembler. To 235 extract this operand type from an instruction, check this field. 236 237 If it is NULL, compute 238 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 239 if ((o->flags & ARC_OPERAND_SIGNED) != 0 240 && (op & (1 << (o->bits - 1))) != 0) 241 op -= 1 << o->bits; 242 (I is the instruction, O is a pointer to this structure, and OP 243 is the result; this assumes twos complement arithmetic). 244 245 If this field is not NULL, then simply call it with the 246 instruction value. It will return the value of the operand. If 247 the INVALID argument is not NULL, *INVALID will be set to 248 non-zero if this operand type can not actually be extracted from 249 this operand (i.e., the instruction does not match). If the 250 operand is valid, *INVALID will not be changed. 251 252 INSN is a pointer to an array of two `arc_insn's. The first element is 253 the insn, the second is the limm if present. 254 255 Operands that have a printable form like registers and suffixes have 256 their struct arc_operand_value pointer stored in OPVAL. */ 257 258 long (*extract) 259 (arc_insn *insn, const struct arc_operand *operand, int mods, 260 const struct arc_operand_value **opval, int *invalid); 261 }; 262 263 /* Bits that say what version of cpu we have. These should be passed to 264 arc_init_opcode_tables. At present, all there is is the cpu type. */ 265 266 /* CPU number, given value passed to `arc_init_opcode_tables'. */ 267 #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 268 /* MACH number, given value passed to `arc_init_opcode_tables'. */ 269 #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) 270 271 /* Special register values: */ 272 #define ARC_REG_SHIMM_UPDATE 61 273 #define ARC_REG_SHIMM 63 274 #define ARC_REG_LIMM 62 275 276 /* Non-zero if REG is a constant marker. */ 277 #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) 278 279 /* Positions and masks of various fields: */ 280 #define ARC_SHIFT_REGA 21 281 #define ARC_SHIFT_REGB 15 282 #define ARC_SHIFT_REGC 9 283 #define ARC_MASK_REG 63 284 285 /* Delay slot types. */ 286 #define ARC_DELAY_NONE 0 /* no delay slot */ 287 #define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ 288 #define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ 289 290 /* Non-zero if X will fit in a signed 9 bit field. */ 291 #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) 292 293 extern const struct arc_operand arc_operands[]; 294 extern const int arc_operand_count; 295 extern struct arc_opcode arc_opcodes[]; 296 extern const int arc_opcodes_count; 297 extern const struct arc_operand_value arc_suffixes[]; 298 extern const int arc_suffixes_count; 299 extern const struct arc_operand_value arc_reg_names[]; 300 extern const int arc_reg_names_count; 301 extern unsigned char arc_operand_map[]; 302 303 /* Utility fns in arc-opc.c. */ 304 int arc_get_opcode_mach (int, int); 305 306 /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ 307 void arc_opcode_init_tables (int); 308 void arc_opcode_init_insert (void); 309 void arc_opcode_init_extract (void); 310 const struct arc_opcode *arc_opcode_lookup_asm (const char *); 311 const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); 312 int arc_opcode_limm_p (long *); 313 const struct arc_operand_value *arc_opcode_lookup_suffix 314 (const struct arc_operand *type, int value); 315 int arc_opcode_supported (const struct arc_opcode *); 316 int arc_opval_supported (const struct arc_operand_value *); 317 int arc_limm_fixup_adjust (arc_insn); 318 int arc_insn_is_j (arc_insn); 319 int arc_insn_not_jl (arc_insn); 320 int arc_operand_type (int); 321 struct arc_operand_value *get_ext_suffix (char *); 322 int arc_get_noshortcut_flag (void); 323