1 /* Assemble V850 instructions.
2 Copyright (C) 1996-2020 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "sysdep.h"
22 #include <stdio.h>
23 #include "opcode/v850.h"
24 #include "bfd.h"
25 #include "opintl.h"
26
27 /* Regular opcodes. */
28 #define OP(x) ((x & 0x3f) << 5)
29 #define OP_MASK OP (0x3f)
30
31 /* Conditional branch opcodes (Format III). */
32 #define BOP(x) ((0x58 << 4) | (x & 0x0f))
33 #define BOP_MASK ((0x78 << 4) | 0x0f)
34
35 /* Conditional branch opcodes (Format VII). */
36 #define BOP7(x) (0x107e0 | (x & 0xf))
37 #define BOP7_MASK (0x1ffe0 | 0xf)
38
39 /* One-word opcodes. */
40 #define one(x) ((unsigned int) (x))
41
42 /* Two-word opcodes. */
43 #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
44
45
46 /* The functions used to insert and extract complicated operands. */
47
48 /* Note: There is a conspiracy between these functions and
49 v850_insert_operand() in gas/config/tc-v850.c. Error messages
50 containing the string 'out of range' will be ignored unless a
51 specific command line option is given to GAS. */
52
53 static const char * not_valid = N_ ("displacement value is not in range and is not aligned");
54 static const char * out_of_range = N_ ("displacement value is out of range");
55 static const char * not_aligned = N_ ("displacement value is not aligned");
56
57 static const char * immediate_out_of_range = N_ ("immediate value is out of range");
58 static const char * branch_out_of_range = N_ ("branch value out of range");
59 static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset");
60 static const char * branch_to_odd_offset = N_ ("branch to odd offset");
61 static const char * pos_out_of_range = N_ ("position value is out of range");
62 static const char * width_out_of_range = N_ ("width value is out of range");
63 static const char * selid_out_of_range = N_ ("SelID is out of range");
64 static const char * vector8_out_of_range = N_ ("vector8 is out of range");
65 static const char * vector5_out_of_range = N_ ("vector5 is out of range");
66 static const char * imm10_out_of_range = N_ ("imm10 is out of range");
67 static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range");
68
69 int
v850_msg_is_out_of_range(const char * msg)70 v850_msg_is_out_of_range (const char* msg)
71 {
72 return msg == out_of_range
73 || msg == immediate_out_of_range
74 || msg == branch_out_of_range;
75 }
76
77 static unsigned long
insert_i5div1(unsigned long insn,long value,const char ** errmsg)78 insert_i5div1 (unsigned long insn, long value, const char ** errmsg)
79 {
80 if (value > 30 || value < 2)
81 {
82 if (value & 1)
83 * errmsg = _(not_valid);
84 else
85 * errmsg = _(out_of_range);
86 }
87 else if (value & 1)
88 * errmsg = _(not_aligned);
89
90 value = (32 - value)/2;
91
92 return (insn | ((value << (2+16)) & 0x3c0000));
93 }
94
95 static unsigned long
extract_i5div1(unsigned long insn,int * invalid)96 extract_i5div1 (unsigned long insn, int * invalid)
97 {
98 unsigned long ret = (insn & 0x003c0000) >> (16+2);
99 ret = 32 - (ret * 2);
100
101 if (invalid != 0)
102 *invalid = (ret > 30 || ret < 2) ? 1 : 0;
103 return ret;
104 }
105
106 static unsigned long
insert_i5div2(unsigned long insn,long value,const char ** errmsg)107 insert_i5div2 (unsigned long insn, long value, const char ** errmsg)
108 {
109 if (value > 30 || value < 4)
110 {
111 if (value & 1)
112 * errmsg = _(not_valid);
113 else
114 * errmsg = _(out_of_range);
115 }
116 else if (value & 1)
117 * errmsg = _(not_aligned);
118
119 value = (32 - value)/2;
120
121 return insn | ((value << (2 + 16)) & 0x3c0000);
122 }
123
124 static unsigned long
extract_i5div2(unsigned long insn,int * invalid)125 extract_i5div2 (unsigned long insn, int * invalid)
126 {
127 unsigned long ret = (insn & 0x003c0000) >> (16+2);
128 ret = 32 - (ret * 2);
129
130 if (invalid != 0)
131 *invalid = (ret > 30 || ret < 4) ? 1 : 0;
132 return ret;
133 }
134
135 static unsigned long
insert_i5div3(unsigned long insn,long value,const char ** errmsg)136 insert_i5div3 (unsigned long insn, long value, const char ** errmsg)
137 {
138 if (value > 32 || value < 2)
139 {
140 if (value & 1)
141 * errmsg = _(not_valid);
142 else
143 * errmsg = _(out_of_range);
144 }
145 else if (value & 1)
146 * errmsg = _(not_aligned);
147
148 value = (32 - value)/2;
149
150 return insn | ((value << (2+16)) & 0x3c0000);
151 }
152
153 static unsigned long
extract_i5div3(unsigned long insn,int * invalid)154 extract_i5div3 (unsigned long insn, int * invalid)
155 {
156 unsigned long ret = (insn & 0x003c0000) >> (16+2);
157 ret = 32 - (ret * 2);
158
159 if (invalid != 0)
160 *invalid = (ret > 32 || ret < 2) ? 1 : 0;
161 return ret;
162 }
163
164 static unsigned long
insert_d5_4(unsigned long insn,long value,const char ** errmsg)165 insert_d5_4 (unsigned long insn, long value, const char ** errmsg)
166 {
167 if (value > 0x1f || value < 0)
168 {
169 if (value & 1)
170 * errmsg = _(not_valid);
171 else
172 * errmsg = _(out_of_range);
173 }
174 else if (value & 1)
175 * errmsg = _(not_aligned);
176
177 value >>= 1;
178
179 return insn | (value & 0x0f);
180 }
181
182 static unsigned long
extract_d5_4(unsigned long insn,int * invalid)183 extract_d5_4 (unsigned long insn, int * invalid)
184 {
185 unsigned long ret = (insn & 0x0f);
186
187 ret <<= 1;
188
189 if (invalid != 0)
190 *invalid = 0;
191 return ret;
192 }
193
194 static unsigned long
insert_d8_6(unsigned long insn,long value,const char ** errmsg)195 insert_d8_6 (unsigned long insn, long value, const char ** errmsg)
196 {
197 if (value > 0xff || value < 0)
198 {
199 if ((value % 4) != 0)
200 * errmsg = _(not_valid);
201 else
202 * errmsg = _(out_of_range);
203 }
204 else if ((value % 4) != 0)
205 * errmsg = _(not_aligned);
206
207 value >>= 1;
208
209 return insn | (value & 0x7e);
210 }
211
212 static unsigned long
extract_d8_6(unsigned long insn,int * invalid)213 extract_d8_6 (unsigned long insn, int * invalid)
214 {
215 unsigned long ret = (insn & 0x7e);
216
217 ret <<= 1;
218
219 if (invalid != 0)
220 *invalid = 0;
221 return ret;
222 }
223
224 static unsigned long
insert_d8_7(unsigned long insn,long value,const char ** errmsg)225 insert_d8_7 (unsigned long insn, long value, const char ** errmsg)
226 {
227 if (value > 0xff || value < 0)
228 {
229 if ((value % 2) != 0)
230 * errmsg = _(not_valid);
231 else
232 * errmsg = _(out_of_range);
233 }
234 else if ((value % 2) != 0)
235 * errmsg = _(not_aligned);
236
237 value >>= 1;
238
239 return insn | (value & 0x7f);
240 }
241
242 static unsigned long
extract_d8_7(unsigned long insn,int * invalid)243 extract_d8_7 (unsigned long insn, int * invalid)
244 {
245 unsigned long ret = (insn & 0x7f);
246
247 ret <<= 1;
248
249 if (invalid != 0)
250 *invalid = 0;
251 return ret;
252 }
253
254 static unsigned long
insert_v8(unsigned long insn,long value,const char ** errmsg)255 insert_v8 (unsigned long insn, long value, const char ** errmsg)
256 {
257 if (value > 0xff || value < 0)
258 * errmsg = _(immediate_out_of_range);
259
260 return insn | (value & 0x1f) | ((value & 0xe0) << (27-5));
261 }
262
263 static unsigned long
extract_v8(unsigned long insn,int * invalid)264 extract_v8 (unsigned long insn, int * invalid)
265 {
266 unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0);
267
268 if (invalid != 0)
269 *invalid = 0;
270 return ret;
271 }
272
273 static unsigned long
insert_d9(unsigned long insn,long value,const char ** errmsg)274 insert_d9 (unsigned long insn, long value, const char ** errmsg)
275 {
276 if (value > 0xff || value < -0x100)
277 {
278 if ((value % 2) != 0)
279 * errmsg = branch_out_of_range_and_odd_offset;
280 else
281 * errmsg = branch_out_of_range;
282 }
283 else if ((value % 2) != 0)
284 * errmsg = branch_to_odd_offset;
285
286 return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3);
287 }
288
289 static unsigned long
extract_d9(unsigned long insn,int * invalid)290 extract_d9 (unsigned long insn, int * invalid)
291 {
292 signed long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e);
293
294 ret = (ret ^ 0x100) - 0x100;
295
296 if (invalid != 0)
297 *invalid = 0;
298 return ret;
299 }
300
301 static unsigned long
insert_u16_loop(unsigned long insn,long value,const char ** errmsg)302 insert_u16_loop (unsigned long insn, long value, const char ** errmsg)
303 {
304 /* Loop displacement is encoded as a positive value,
305 even though the instruction branches backwards. */
306 if (value < 0 || value > 0xffff)
307 {
308 if ((value % 2) != 0)
309 * errmsg = branch_out_of_range_and_odd_offset;
310 else
311 * errmsg = branch_out_of_range;
312 }
313 else if ((value % 2) != 0)
314 * errmsg = branch_to_odd_offset;
315
316 return insn | ((value & 0xfffe) << 16);
317 }
318
319 static unsigned long
extract_u16_loop(unsigned long insn,int * invalid)320 extract_u16_loop (unsigned long insn, int * invalid)
321 {
322 long ret = (insn >> 16) & 0xfffe;
323
324 if (invalid != 0)
325 *invalid = 0;
326 return ret;
327 }
328
329 static unsigned long
insert_d16_15(unsigned long insn,long value,const char ** errmsg)330 insert_d16_15 (unsigned long insn, long value, const char ** errmsg)
331 {
332 if (value > 0x7fff || value < -0x8000)
333 {
334 if ((value % 2) != 0)
335 * errmsg = _(not_valid);
336 else
337 * errmsg = _(out_of_range);
338 }
339 else if ((value % 2) != 0)
340 * errmsg = _(not_aligned);
341
342 return insn | ((value & 0xfffe) << 16);
343 }
344
345 static unsigned long
extract_d16_15(unsigned long insn,int * invalid)346 extract_d16_15 (unsigned long insn, int * invalid)
347 {
348 signed long ret = (insn >> 16) & 0xfffe;
349
350 ret = (ret ^ 0x8000) - 0x8000;
351
352 if (invalid != 0)
353 *invalid = 0;
354 return ret;
355 }
356
357 static unsigned long
insert_d16_16(unsigned long insn,signed long value,const char ** errmsg)358 insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg)
359 {
360 if (value > 0x7fff || value < -0x8000)
361 * errmsg = _(out_of_range);
362
363 return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5);
364 }
365
366 static unsigned long
extract_d16_16(unsigned long insn,int * invalid)367 extract_d16_16 (unsigned long insn, int * invalid)
368 {
369 signed long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1);
370
371 ret = (ret ^ 0x8000) - 0x8000;
372
373 if (invalid != 0)
374 *invalid = 0;
375 return ret;
376 }
377
378 static unsigned long
insert_d17_16(unsigned long insn,long value,const char ** errmsg)379 insert_d17_16 (unsigned long insn, long value, const char ** errmsg)
380 {
381 if (value > 0xffff || value < -0x10000)
382 * errmsg = _(out_of_range);
383
384 return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4));
385 }
386
387 static unsigned long
extract_d17_16(unsigned long insn,int * invalid)388 extract_d17_16 (unsigned long insn, int * invalid)
389 {
390 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000);
391
392 ret = (ret ^ 0x10000) - 0x10000;
393
394 if (invalid != 0)
395 *invalid = 0;
396 return (unsigned long)ret;
397 }
398
399 static unsigned long
insert_d22(unsigned long insn,long value,const char ** errmsg)400 insert_d22 (unsigned long insn, long value, const char ** errmsg)
401 {
402 if (value > 0x1fffff || value < -0x200000)
403 {
404 if ((value % 2) != 0)
405 * errmsg = branch_out_of_range_and_odd_offset;
406 else
407 * errmsg = branch_out_of_range;
408 }
409 else if ((value % 2) != 0)
410 * errmsg = branch_to_odd_offset;
411
412 return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16);
413 }
414
415 static unsigned long
extract_d22(unsigned long insn,int * invalid)416 extract_d22 (unsigned long insn, int * invalid)
417 {
418 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000);
419
420 ret = (ret ^ 0x200000) - 0x200000;
421
422 if (invalid != 0)
423 *invalid = 0;
424 return (unsigned long) ret;
425 }
426
427 static unsigned long
insert_d23(unsigned long insn,long value,const char ** errmsg)428 insert_d23 (unsigned long insn, long value, const char ** errmsg)
429 {
430 if (value > 0x3fffff || value < -0x400000)
431 * errmsg = out_of_range;
432
433 return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7));
434 }
435
436 static unsigned long
insert_d23_align1(unsigned long insn,long value,const char ** errmsg)437 insert_d23_align1 (unsigned long insn, long value, const char ** errmsg)
438 {
439 if (value > 0x3fffff || value < -0x400000)
440 {
441 if (value & 0x1)
442 * errmsg = _(not_valid);
443 else
444 * errmsg = _(out_of_range);
445 }
446 else if (value & 0x1)
447 * errmsg = _(not_aligned);
448
449 return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7));
450 }
451
452 static unsigned long
extract_d23(unsigned long insn,int * invalid)453 extract_d23 (unsigned long insn, int * invalid)
454 {
455 signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80);
456
457 ret = (ret ^ 0x400000) - 0x400000;
458
459 if (invalid != 0)
460 *invalid = 0;
461 return (unsigned long) ret;
462 }
463
464 static unsigned long
insert_i9(unsigned long insn,signed long value,const char ** errmsg)465 insert_i9 (unsigned long insn, signed long value, const char ** errmsg)
466 {
467 if (value > 0xff || value < -0x100)
468 * errmsg = _(immediate_out_of_range);
469
470 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
471 }
472
473 static unsigned long
extract_i9(unsigned long insn,int * invalid)474 extract_i9 (unsigned long insn, int * invalid)
475 {
476 signed long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f);
477
478 ret = (ret ^ 0x100) - 0x100;
479
480 if (invalid != 0)
481 *invalid = 0;
482 return ret;
483 }
484
485 static unsigned long
insert_u9(unsigned long insn,long v,const char ** errmsg)486 insert_u9 (unsigned long insn, long v, const char ** errmsg)
487 {
488 unsigned long value = (unsigned long) v;
489
490 if (value > 0x1ff)
491 * errmsg = _(immediate_out_of_range);
492
493 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
494 }
495
496 static unsigned long
extract_u9(unsigned long insn,int * invalid)497 extract_u9 (unsigned long insn, int * invalid)
498 {
499 unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f);
500
501 if (invalid != 0)
502 *invalid = 0;
503 return ret;
504 }
505
506 static unsigned long
insert_spe(unsigned long insn,long v,const char ** errmsg)507 insert_spe (unsigned long insn, long v, const char ** errmsg)
508 {
509 unsigned long value = (unsigned long) v;
510
511 if (value != 3)
512 * errmsg = _("invalid register for stack adjustment");
513
514 return insn & ~0x180000;
515 }
516
517 static unsigned long
extract_spe(unsigned long insn ATTRIBUTE_UNUSED,int * invalid)518 extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid)
519 {
520 if (invalid != 0)
521 *invalid = 0;
522
523 return 3;
524 }
525
526 static unsigned long
insert_r4(unsigned long insn,long v,const char ** errmsg)527 insert_r4 (unsigned long insn, long v, const char ** errmsg)
528 {
529 unsigned long value = (unsigned long) v;
530
531 if (value >= 32)
532 * errmsg = _("invalid register name");
533
534 return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16);
535 }
536
537 static unsigned long
extract_r4(unsigned long insn,int * invalid)538 extract_r4 (unsigned long insn, int * invalid)
539 {
540 unsigned long r4;
541 unsigned long insn2;
542
543 insn2 = insn >> 16;
544 r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e));
545
546 if (invalid != 0)
547 *invalid = 0;
548
549 return r4;
550 }
551
552 static unsigned long G_pos;
553
554 static unsigned long
insert_POS(unsigned long insn,long pos,const char ** errmsg)555 insert_POS (unsigned long insn, long pos, const char ** errmsg)
556 {
557 if (pos > 0x1f || pos < 0)
558 * errmsg = _(pos_out_of_range);
559
560 G_pos = (unsigned long) pos;
561
562 return insn; /* Not an oparaton until WIDTH. */
563 }
564
565 static unsigned long
extract_POS_U(unsigned long insn,int * invalid)566 extract_POS_U (unsigned long insn, int * invalid)
567 {
568 unsigned long pos,lsb;
569 unsigned long insn2;
570 insn2 = insn >> 16;
571
572 lsb = ((insn2 & 0x0800) >> 8)
573 | ((insn2 & 0x000e) >> 1);
574 lsb += 16;
575 pos = lsb;
576
577 if (invalid != 0)
578 *invalid = 0;
579
580 return pos;
581 }
582
583 static unsigned long
extract_POS_L(unsigned long insn,int * invalid)584 extract_POS_L (unsigned long insn, int * invalid)
585 {
586 unsigned long pos,lsb;
587 unsigned long insn2;
588 insn2 = insn >> 16;
589
590 lsb = ((insn2 & 0x0800) >> 8)
591 | ((insn2 & 0x000e) >> 1);
592 pos = lsb;
593
594 if (invalid != 0)
595 *invalid = 0;
596
597 return pos;
598 }
599
600 static unsigned long
insert_WIDTH(unsigned long insn,long width,const char ** errmsg)601 insert_WIDTH (unsigned long insn, long width, const char ** errmsg)
602 {
603 unsigned long msb, lsb, opc, ret;
604 unsigned long msb_expand, lsb_expand;
605
606 msb = (unsigned long)width + G_pos - 1;
607 lsb = G_pos;
608 opc = 0;
609 G_pos = 0;
610
611 if (width > 0x20 || width < 0)
612 * errmsg = _(width_out_of_range);
613
614 if ((msb >= 16) && (lsb >= 16))
615 opc = 0x0090;
616 else if ((msb >= 16) && (lsb < 16))
617 opc = 0x00b0;
618 else if ((msb < 16) && (lsb < 16))
619 opc = 0x00d0;
620 else
621 * errmsg = _(width_out_of_range);
622
623 msb &= 0x0f;
624 msb_expand = msb << 12;
625 lsb &= 0x0f;
626 lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1);
627
628 ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16);
629
630 return ret;
631 }
632
633 static unsigned long
extract_WIDTH_U(unsigned long insn,int * invalid)634 extract_WIDTH_U (unsigned long insn, int * invalid)
635 {
636 unsigned long width, msb, lsb;
637 unsigned long insn2;
638 insn2 = insn >> 16;
639
640 msb = ((insn2 & 0xf000) >> 12);
641 msb += 16;
642 lsb = ((insn2 & 0x0800) >> 8)
643 | ((insn2 & 0x000e) >> 1);
644 lsb += 16;
645
646 if (invalid != 0)
647 *invalid = 0;
648
649 width = msb - lsb + 1;
650
651 return width;
652 }
653
654 static unsigned long
extract_WIDTH_M(unsigned long insn,int * invalid)655 extract_WIDTH_M (unsigned long insn, int * invalid)
656 {
657 unsigned long width, msb, lsb;
658 unsigned long insn2;
659 insn2 = insn >> 16;
660
661 msb = ((insn2 & 0xf000) >> 12) ;
662 msb += 16;
663 lsb = ((insn2 & 0x0800) >> 8)
664 | ((insn2 & 0x000e) >> 1);
665
666 if (invalid != 0)
667 *invalid = 0;
668
669 width = msb - lsb + 1;
670
671 return width;
672 }
673
674 static unsigned long
extract_WIDTH_L(unsigned long insn,int * invalid)675 extract_WIDTH_L (unsigned long insn, int * invalid)
676 {
677 unsigned long width, msb, lsb;
678 unsigned long insn2;
679 insn2 = insn >> 16;
680
681 msb = ((insn2 & 0xf000) >> 12) ;
682 lsb = ((insn2 & 0x0800) >> 8)
683 | ((insn2 & 0x000e) >> 1);
684
685 if (invalid != 0)
686 *invalid = 0;
687
688 width = msb - lsb + 1;
689
690 return width;
691 }
692
693 static unsigned long
insert_SELID(unsigned long insn,long selid,const char ** errmsg)694 insert_SELID (unsigned long insn, long selid, const char ** errmsg)
695 {
696 if ((unsigned long) selid > 0x1f)
697 * errmsg = _(selid_out_of_range);
698
699 return insn | ((selid & 0x1fUL) << 27);
700 }
701
702 static unsigned long
extract_SELID(unsigned long insn,int * invalid)703 extract_SELID (unsigned long insn, int * invalid)
704 {
705 unsigned long selid;
706 unsigned long insn2;
707
708 insn2 = insn >> 16;
709
710 selid = ((insn2 & 0xf800) >> 11);
711
712 if (invalid != 0)
713 *invalid = 0;
714
715 return selid;
716 }
717
718 static unsigned long
insert_VECTOR8(unsigned long insn,long vector8,const char ** errmsg)719 insert_VECTOR8 (unsigned long insn, long vector8, const char ** errmsg)
720 {
721 unsigned long ret;
722 unsigned long VVV,vvvvv;
723
724 if (vector8 > 0xff || vector8 < 0)
725 * errmsg = _(vector8_out_of_range);
726
727 VVV = (vector8 & 0xe0) >> 5;
728 vvvvv = (vector8 & 0x1f);
729
730 ret = (insn | (VVV << 27) | vvvvv);
731
732 return ret;
733 }
734
735 static unsigned long
extract_VECTOR8(unsigned long insn,int * invalid)736 extract_VECTOR8 (unsigned long insn, int * invalid)
737 {
738 unsigned long vector8;
739 unsigned long VVV,vvvvv;
740 unsigned long insn2;
741
742 insn2 = insn >> 16;
743 VVV = ((insn2 & 0x3800) >> 11);
744 vvvvv = (insn & 0x001f);
745 vector8 = VVV << 5 | vvvvv;
746
747 if (invalid != 0)
748 *invalid = 0;
749
750 return vector8;
751 }
752
753 static unsigned long
insert_VECTOR5(unsigned long insn,long vector5,const char ** errmsg)754 insert_VECTOR5 (unsigned long insn, long vector5, const char ** errmsg)
755 {
756 unsigned long ret;
757 unsigned long vvvvv;
758
759 if (vector5 > 0x1f || vector5 < 0)
760 * errmsg = _(vector5_out_of_range);
761
762 vvvvv = (vector5 & 0x1f);
763
764 ret = (insn | vvvvv);
765
766 return ret;
767 }
768
769 static unsigned long
extract_VECTOR5(unsigned long insn,int * invalid)770 extract_VECTOR5 (unsigned long insn, int * invalid)
771 {
772 unsigned long vector5;
773
774 vector5 = (insn & 0x001f);
775
776 if (invalid != 0)
777 *invalid = 0;
778
779 return vector5;
780 }
781
782 static unsigned long
insert_CACHEOP(unsigned long insn,long cacheop,const char ** errmsg ATTRIBUTE_UNUSED)783 insert_CACHEOP (unsigned long insn, long cacheop, const char ** errmsg ATTRIBUTE_UNUSED)
784 {
785 unsigned long ret;
786 unsigned long pp,PPPPP;
787
788 pp = (cacheop & 0x60) >> 5;
789 PPPPP = (cacheop & 0x1f);
790
791 ret = insn | (pp << 11) | (PPPPP << 27);
792
793 return ret;
794 }
795
796 static unsigned long
extract_CACHEOP(unsigned long insn,int * invalid)797 extract_CACHEOP (unsigned long insn, int * invalid)
798 {
799 unsigned long ret;
800 unsigned long pp,PPPPP;
801 unsigned long insn2;
802
803 insn2 = insn >> 16;
804
805 PPPPP = ((insn2 & 0xf800) >> 11);
806 pp = ((insn & 0x1800) >> 11);
807
808 ret = (pp << 5) | PPPPP;
809
810 if (invalid != 0)
811 *invalid = 0;
812
813 return ret;
814 }
815
816 static unsigned long
insert_PREFOP(unsigned long insn,long prefop,const char ** errmsg ATTRIBUTE_UNUSED)817 insert_PREFOP (unsigned long insn, long prefop, const char ** errmsg ATTRIBUTE_UNUSED)
818 {
819 unsigned long ret;
820 unsigned long PPPPP;
821
822 PPPPP = (prefop & 0x1f);
823
824 ret = insn | (PPPPP << 27);
825
826 return ret;
827 }
828
829 static unsigned long
extract_PREFOP(unsigned long insn,int * invalid)830 extract_PREFOP (unsigned long insn, int * invalid)
831 {
832 unsigned long ret;
833 unsigned long PPPPP;
834 unsigned long insn2;
835
836 insn2 = insn >> 16;
837
838 PPPPP = (insn2 & 0xf800) >> 11;
839
840 ret = PPPPP;
841
842 if (invalid != 0)
843 *invalid = 0;
844
845 return ret;
846 }
847
848 static unsigned long
insert_IMM10U(unsigned long insn,long value,const char ** errmsg)849 insert_IMM10U (unsigned long insn, long value, const char ** errmsg)
850 {
851 unsigned long imm10, ret;
852 unsigned long iiiii,IIIII;
853
854 if (value > 0x3ff || value < 0)
855 * errmsg = _(imm10_out_of_range);
856
857 imm10 = ((unsigned long) value) & 0x3ff;
858 IIIII = (imm10 >> 5) & 0x1f;
859 iiiii = imm10 & 0x1f;
860
861 ret = insn | IIIII << 27 | iiiii;
862
863 return ret;
864 }
865
866 static unsigned long
extract_IMM10U(unsigned long insn,int * invalid)867 extract_IMM10U (unsigned long insn, int * invalid)
868 {
869 unsigned long ret;
870 unsigned long iiiii,IIIII;
871 unsigned long insn2;
872 insn2 = insn >> 16;
873
874 IIIII = ((insn2 & 0xf800) >> 11);
875 iiiii = (insn & 0x001f);
876
877 ret = (IIIII << 5) | iiiii;
878
879 if (invalid != 0)
880 *invalid = 0;
881
882 return ret;
883 }
884
885 static unsigned long
insert_SRSEL1(unsigned long insn,long value,const char ** errmsg)886 insert_SRSEL1 (unsigned long insn, long value, const char ** errmsg)
887 {
888 unsigned long imm10, ret;
889 unsigned long sr,selid;
890
891 if (value > 0x3ff || value < 0)
892 * errmsg = _(sr_selid_out_of_range);
893
894 imm10 = (unsigned long) value;
895 selid = (imm10 & 0x3e0) >> 5;
896 sr = imm10 & 0x1f;
897
898 ret = insn | selid << 27 | sr;
899
900 return ret;
901 }
902
903 static unsigned long
extract_SRSEL1(unsigned long insn,int * invalid)904 extract_SRSEL1 (unsigned long insn, int * invalid)
905 {
906 unsigned long ret;
907 unsigned long sr, selid;
908 unsigned long insn2;
909
910 insn2 = insn >> 16;
911
912 selid = ((insn2 & 0xf800) >> 11);
913 sr = (insn & 0x001f);
914
915 ret = (selid << 5) | sr;
916
917 if (invalid != 0)
918 *invalid = 0;
919
920 return ret;
921 }
922
923 static unsigned long
insert_SRSEL2(unsigned long insn,long value,const char ** errmsg)924 insert_SRSEL2 (unsigned long insn, long value, const char ** errmsg)
925 {
926 unsigned long imm10, ret;
927 unsigned long sr, selid;
928
929 if (value > 0x3ff || value < 0)
930 * errmsg = _(sr_selid_out_of_range);
931
932 imm10 = (unsigned long) value;
933 selid = (imm10 & 0x3e0) >> 5;
934 sr = imm10 & 0x1f;
935
936 ret = insn | selid << 27 | sr << 11;
937
938 return ret;
939 }
940
941 static unsigned long
extract_SRSEL2(unsigned long insn,int * invalid)942 extract_SRSEL2 (unsigned long insn, int * invalid)
943 {
944 unsigned long ret;
945 unsigned long sr, selid;
946 unsigned long insn2;
947
948 insn2 = insn >> 16;
949
950 selid = ((insn2 & 0xf800) >> 11);
951 sr = ((insn & 0xf800) >> 11);
952
953 ret = (selid << 5) | sr;
954
955 if (invalid != 0)
956 *invalid = 0;
957
958 return ret;
959 }
960
961 /* Warning: code in gas/config/tc-v850.c examines the contents of this array.
962 If you change any of the values here, be sure to look for side effects in
963 that code. */
964 const struct v850_operand v850_operands[] =
965 {
966 #define UNUSED 0
967 { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE },
968
969 /* The R1 field in a format 1, 6, 7, 9, C insn. */
970 #define R1 (UNUSED + 1)
971 { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
972
973 /* As above, but register 0 is not allowed. */
974 #define R1_NOTR0 (R1 + 1)
975 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
976
977 /* Even register is allowed. */
978 #define R1_EVEN (R1_NOTR0 + 1)
979 { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
980
981 /* Bang (bit reverse). */
982 #define R1_BANG (R1_EVEN + 1)
983 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE },
984
985 /* Percent (modulo). */
986 #define R1_PERCENT (R1_BANG + 1)
987 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE },
988
989 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */
990 #define R2 (R1_PERCENT + 1)
991 { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
992
993 /* As above, but register 0 is not allowed. */
994 #define R2_NOTR0 (R2 + 1)
995 { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
996
997 /* Even register is allowed. */
998 #define R2_EVEN (R2_NOTR0 + 1)
999 { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
1000
1001 /* Reg2 in dispose instruction. */
1002 #define R2_DISPOSE (R2_EVEN + 1)
1003 { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
1004
1005 /* The R3 field in a format 11, 12, C insn. */
1006 #define R3 (R2_DISPOSE + 1)
1007 { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
1008
1009 /* As above, but register 0 is not allowed. */
1010 #define R3_NOTR0 (R3 + 1)
1011 { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
1012
1013 /* As above, but odd number registers are not allowed. */
1014 #define R3_EVEN (R3_NOTR0 + 1)
1015 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
1016
1017 /* As above, but register 0 is not allowed. */
1018 #define R3_EVEN_NOTR0 (R3_EVEN + 1)
1019 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE },
1020
1021 /* Forth register in FPU Instruction. */
1022 #define R4 (R3_EVEN_NOTR0 + 1)
1023 { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE },
1024
1025 /* As above, but odd number registers are not allowed. */
1026 #define R4_EVEN (R4 + 1)
1027 { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
1028
1029 /* Stack pointer in prepare instruction. */
1030 #define SP (R4_EVEN + 1)
1031 { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE },
1032
1033 /* EP Register. */
1034 #define EP (SP + 1)
1035 { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE },
1036
1037 /* A list of registers in a prepare/dispose instruction. */
1038 #define LIST12 (EP + 1)
1039 { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE },
1040
1041 /* System register operands. */
1042 #define OLDSR1 (LIST12 + 1)
1043 { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
1044
1045 #define SR1 (OLDSR1 + 1)
1046 { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE },
1047
1048 /* The R2 field as a system register. */
1049 #define OLDSR2 (SR1 + 1)
1050 { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
1051
1052 #define SR2 (OLDSR2 + 1)
1053 { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE },
1054
1055 /* FPU CC bit position. */
1056 #define FFF (SR2 + 1)
1057 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
1058
1059 /* The 4 bit condition code in a setf instruction. */
1060 #define CCCC (FFF + 1)
1061 { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
1062
1063 /* Condition code in adf,sdf. */
1064 #define CCCC_NOTSA (CCCC + 1)
1065 { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE },
1066
1067 /* Condition code in conditional moves. */
1068 #define MOVCC (CCCC_NOTSA + 1)
1069 { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
1070
1071 /* Condition code in FPU. */
1072 #define FLOAT_CCCC (MOVCC + 1)
1073 { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE },
1074
1075 /* The 1 bit immediate field in format C insn. */
1076 #define VI1 (FLOAT_CCCC + 1)
1077 { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE },
1078
1079 /* The 1 bit immediate field in format C insn. */
1080 #define VC1 (VI1 + 1)
1081 { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1082
1083 /* The 2 bit immediate field in format C insn. */
1084 #define DI2 (VC1 + 1)
1085 { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE },
1086
1087 /* The 2 bit immediate field in format C insn. */
1088 #define VI2 (DI2 + 1)
1089 { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1090
1091 /* The 2 bit immediate field in format C - DUP insn. */
1092 #define VI2DUP (VI2 + 1)
1093 { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE },
1094
1095 /* The 3 bit immediate field in format 8 insn. */
1096 #define B3 (VI2DUP + 1)
1097 { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE },
1098
1099 /* The 3 bit immediate field in format C insn. */
1100 #define DI3 (B3 + 1)
1101 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
1102
1103 /* The 3 bit immediate field in format C insn. */
1104 #define I3U (DI3 + 1)
1105 { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1106
1107 /* The 4 bit immediate field in format C insn. */
1108 #define I4U (I3U + 1)
1109 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1110
1111 /* The 4 bit immediate field in fetrap. */
1112 #define I4U_NOTIMM0 (I4U + 1)
1113 { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE },
1114
1115 /* The unsigned disp4 field in a sld.bu. */
1116 #define D4U (I4U_NOTIMM0 + 1)
1117 { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET },
1118
1119 /* The imm5 field in a format 2 insn. */
1120 #define I5 (D4U + 1)
1121 { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
1122
1123 /* The imm5 field in a format 11 insn. */
1124 #define I5DIV1 (I5 + 1)
1125 { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE },
1126
1127 #define I5DIV2 (I5DIV1 + 1)
1128 { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE },
1129
1130 #define I5DIV3 (I5DIV2 + 1)
1131 { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE },
1132
1133 /* The unsigned imm5 field in a format 2 insn. */
1134 #define I5U (I5DIV3 + 1)
1135 { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1136
1137 /* The imm5 field in a prepare/dispose instruction. */
1138 #define IMM5 (I5U + 1)
1139 { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE },
1140
1141 /* The unsigned disp5 field in a sld.hu. */
1142 #define D5_4U (IMM5 + 1)
1143 { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET },
1144
1145 /* The IMM6 field in a callt instruction. */
1146 #define IMM6 (D5_4U + 1)
1147 { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET },
1148
1149 /* The signed disp7 field in a format 4 insn. */
1150 #define D7U (IMM6 + 1)
1151 { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET },
1152
1153 /* The unsigned DISP8 field in a format 4 insn. */
1154 #define D8_7U (D7U + 1)
1155 { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET },
1156
1157 /* The unsigned DISP8 field in a format 4 insn. */
1158 #define D8_6U (D8_7U + 1)
1159 { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET },
1160
1161 /* The unsigned DISP8 field in a format 4 insn. */
1162 #define V8 (D8_6U + 1)
1163 { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE },
1164
1165 /* The imm9 field in a multiply word. */
1166 #define I9 (V8 + 1)
1167 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
1168
1169 /* The unsigned imm9 field in a multiply word. */
1170 #define U9 (I9 + 1)
1171 { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE },
1172
1173 /* The DISP9 field in a format 3 insn. */
1174 #define D9 (U9 + 1)
1175 { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
1176
1177 /* The DISP9 field in a format 3 insn, relaxable. */
1178 #define D9_RELAX (D9 + 1)
1179 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
1180
1181 /* The imm16 field in a format 6 insn. */
1182 #define I16 (D9_RELAX + 1)
1183 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 },
1184
1185 /* The signed 16 bit immediate following a prepare instruction. */
1186 #define IMM16LO (I16 + 1)
1187 { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 },
1188
1189 /* The hi 16 bit immediate following a 32 bit instruction. */
1190 #define IMM16HI (IMM16LO + 1)
1191 { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 },
1192
1193 /* The unsigned imm16 in a format 6 insn. */
1194 #define I16U (IMM16HI + 1)
1195 { 16, 16, NULL, NULL, 0, BFD_RELOC_16 },
1196
1197 /* The disp16 field in a format 8 insn. */
1198 #define D16 (I16U + 1)
1199 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 },
1200
1201 /* The disp16 field in an format 7 unsigned byte load insn. */
1202 #define D16_16 (D16 + 1)
1203 { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET },
1204
1205 /* The disp16 field in a format 6 insn. */
1206 #define D16_15 (D16_16 + 1)
1207 { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 },
1208
1209 /* The unsigned DISP16 field in a format 7 insn. */
1210 #define D16_LOOP (D16_15 + 1)
1211 { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL },
1212
1213 /* The DISP17 field in a format 7 insn. */
1214 #define D17_16 (D16_LOOP + 1)
1215 { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL },
1216
1217 /* The DISP22 field in a format 4 insn, relaxable.
1218 This _must_ follow D9_RELAX; the assembler assumes that the longer
1219 version immediately follows the shorter version for relaxing. */
1220 #define D22 (D17_16 + 1)
1221 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL },
1222
1223 #define D23 (D22 + 1)
1224 { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
1225
1226 #define D23_ALIGN1 (D23 + 1)
1227 { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
1228
1229 /* The 32 bit immediate following a 32 bit instruction. */
1230 #define IMM32 (D23_ALIGN1 + 1)
1231 { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 },
1232
1233 #define D32_31 (IMM32 + 1)
1234 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS },
1235
1236 #define D32_31_PCREL (D32_31 + 1)
1237 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL },
1238
1239 #define POS_U (D32_31_PCREL + 1)
1240 { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE },
1241
1242 #define POS_M (POS_U + 1)
1243 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
1244
1245 #define POS_L (POS_M + 1)
1246 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
1247
1248 #define WIDTH_U (POS_L + 1)
1249 { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE },
1250
1251 #define WIDTH_M (WIDTH_U + 1)
1252 { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE },
1253
1254 #define WIDTH_L (WIDTH_M + 1)
1255 { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE },
1256
1257 #define SELID (WIDTH_L + 1)
1258 { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE },
1259
1260 #define RIE_IMM5 (SELID + 1)
1261 { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE },
1262
1263 #define RIE_IMM4 (RIE_IMM5 + 1)
1264 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1265
1266 #define VECTOR8 (RIE_IMM4 + 1)
1267 { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE },
1268
1269 #define VECTOR5 (VECTOR8 + 1)
1270 { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE },
1271
1272 #define VR1 (VECTOR5 + 1)
1273 { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
1274
1275 #define VR2 (VR1 + 1)
1276 { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
1277
1278 #define CACHEOP (VR2 + 1)
1279 { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE },
1280
1281 #define PREFOP (CACHEOP + 1)
1282 { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE },
1283
1284 #define IMM10U (PREFOP + 1)
1285 { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE },
1286 };
1287
1288
1289 /* Reg - Reg instruction format (Format I). */
1290 #define IF1 {R1, R2}
1291
1292 /* Imm - Reg instruction format (Format II). */
1293 #define IF2 {I5, R2}
1294
1295 /* Conditional branch instruction format (Format III). */
1296 #define IF3 {D9_RELAX}
1297
1298 /* 3 operand instruction (Format VI). */
1299 #define IF6 {I16, R1, R2}
1300
1301 /* 3 operand instruction (Format VI). */
1302 #define IF6U {I16U, R1, R2}
1303
1304 /* Conditional branch instruction format (Format VII). */
1305 #define IF7 {D17_16}
1306
1307
1308 /* The opcode table.
1309
1310 The format of the opcode table is:
1311
1312 NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR
1313
1314 NAME is the name of the instruction.
1315 OPCODE is the instruction opcode.
1316 MASK is the opcode mask; this is used to tell the disassembler
1317 which bits in the actual opcode must match OPCODE.
1318 OPERANDS is the list of operands.
1319 MEMOP specifies which operand (if any) is a memory operand.
1320 PROCESSORS specifies which CPU(s) support the opcode.
1321
1322 The disassembler reads the table in order and prints the first
1323 instruction which matches, so this table is sorted to put more
1324 specific instructions before more general instructions. It is also
1325 sorted by major opcode.
1326
1327 The table is also sorted by name. This is used by the assembler.
1328 When parsing an instruction the assembler finds the first occurance
1329 of the name of the instruciton in this table and then attempts to
1330 match the instruction's arguments with description of the operands
1331 associated with the entry it has just found in this table. If the
1332 match fails the assembler looks at the next entry in this table.
1333 If that entry has the same name as the previous entry, then it
1334 tries to match the instruction against that entry and so on. This
1335 is how the assembler copes with multiple, different formats of the
1336 same instruction. */
1337
1338 const struct v850_opcode v850_opcodes[] =
1339 {
1340 /* Standard instructions. */
1341 { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
1342 { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
1343
1344 { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
1345
1346 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1347
1348 { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL },
1349
1350 { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1351
1352 /* Signed integer. */
1353 { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1354 { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1355 { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1356 { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1357 /* Unsigned integer. */
1358 { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1359 { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1360 { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1361 { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1362 /* Common. */
1363 { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1364 { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1365 /* Others. */
1366 { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1367 { "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1368 { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1369 { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1370 { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1371 { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1372 { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1373 { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1374 { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1375 { "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1376 { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1377 { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1378
1379 /* Signed integer. */
1380 { "bge", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1381 { "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1382 { "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1383 { "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1384 /* Unsigned integer. */
1385 { "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1386 { "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1387 { "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1388 { "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1389 /* Common. */
1390 { "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1391 { "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1392 /* Others. */
1393 { "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1394 { "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1395 { "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1396 { "bnc", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1397 { "bnv", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1398 { "bnz", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1399 { "bp", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1400 { "br", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1401 { "bsa", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1402 { "bt", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1403 { "bv", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1404 { "bz", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1405 /* Bcond disp17 Gas local alias(not defined in spec). */
1406
1407 /* Signed integer. */
1408 { "bge17", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1409 { "bgt17", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1410 { "ble17", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1411 { "blt17", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1412 /* Unsigned integer. */
1413 { "bh17", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1414 { "bl17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1415 { "bnh17", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1416 { "bnl17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1417 /* Common. */
1418 { "be17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1419 { "bne17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1420 /* Others. */
1421 { "bc17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1422 { "bf17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1423 { "bn17", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1424 { "bnc17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1425 { "bnv17", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1426 { "bnz17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1427 { "bp17", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1428 { "br17", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1429 { "bsa17", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1430 { "bt17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1431 { "bv17", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1432 { "bz17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1433
1434 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1435
1436 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1437
1438 /* v850e3v5 bitfield instructions. */
1439 { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP },
1440 { "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP },
1441 { "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP },
1442 /* Gas local alias(not defined in spec). */
1443 { "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1444 { "binsm",two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1445 { "binsl",two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1446
1447 { "cache", two (0xe7e0, 0x0160), two (0xe7e0, 0x07ff), {CACHEOP, R1}, 2, PROCESSOR_V850E3V5_UP },
1448
1449 { "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 },
1450
1451 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP },
1452
1453 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1454 { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1455
1456 { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1457 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
1458
1459 { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
1460 { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
1461
1462 { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1463
1464 { "dbcp", one (0xe840), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1465
1466 { "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1467
1468 { "dbpush", two (0x5fe0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1469
1470 { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1471
1472 { "dbtag", two (0xcfe0, 0x0160), two (0xffe0, 0x07ff), {IMM10U}, 0, PROCESSOR_V850E3V5_UP },
1473
1474 { "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1475
1476 { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1477
1478 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
1479 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
1480
1481 { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1482
1483 { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1484 { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL },
1485
1486 { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1487
1488 { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1489
1490 { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1491 { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1492
1493 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1494
1495 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1496
1497 { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1498
1499 { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1500
1501 { "dst", two (0x07e0, 0x0134), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1502
1503 { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1504
1505 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1506
1507 { "est", two (0x07e0, 0x0132), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1508
1509 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1510
1511 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP },
1512
1513 { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1514
1515 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1516
1517 { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1518
1519 { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP },
1520 { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP },
1521
1522 { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP},
1523 { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL},
1524 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
1525 /* Gas local alias (not defined in spec). */
1526 { "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS},
1527 /* Gas local alias of jarl imm22 (not defined in spec). */
1528 { "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS},
1529 /* Gas local alias of jarl imm32 (not defined in spec). */
1530 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1531 { "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1532
1533 { "jmp", two (0x06e0, 0x0000), two (0xffe0, 0x0001), {D32_31, R1}, 2, PROCESSOR_V850E3V5_UP },
1534 { "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 },
1535 { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL },
1536 /* Gas local alias of jmp disp22(not defined in spec). */
1537 { "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
1538 /* Gas local alias of jmp disp32(not defined in spec). */
1539 { "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1540 { "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1541
1542 { "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL },
1543 { "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP },
1544 /* Gas local alias of mov imm22(not defined in spec). */
1545 { "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
1546 /* Gas local alias of mov imm32(not defined in spec). */
1547 { "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1548
1549 /* Alias of bcond (same as CA850). */
1550 { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1551 { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1552 { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1553 { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1554 /* Unsigned integer. */
1555 { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1556 { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1557 { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1558 { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1559 /* Common. */
1560 { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1561 { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1562 /* Others. */
1563 { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1564 { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1565 { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1566 { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1567 { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1568 { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1569 { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1570 { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1571 { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1572
1573
1574 { "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1575
1576 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL },
1577 { "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP },
1578 { "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1579
1580 { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1581 { "ld.bu", two (0x07a0, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP },
1582 { "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1583
1584 { "ld.dw", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP },
1585 { "ld.dw23", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1586
1587 { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL },
1588 { "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1589 { "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1590
1591 { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1592 { "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1593 { "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1594
1595 { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL },
1596 { "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1597 { "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1598
1599 { "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, PROCESSOR_V850E3V5_UP },
1600
1601 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1602 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1603 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, OLDSR2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
1604
1605 { "ldtc.gr", two (0x07e0, 0x0032), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP },
1606 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1607 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1608
1609 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },
1610 { "ldtc.pc", two (0x07e0, 0xf832), two (0x07e0, 0xffff), {R1}, 0, PROCESSOR_V850E3V5_UP },
1611
1612 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1613 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1614
1615 { "loop", two (0x06e0, 0x0001), two (0xffe0, 0x0001), {R1, D16_LOOP}, 0, PROCESSOR_V850E3V5_UP },
1616
1617 { "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1618
1619 { "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP },
1620
1621 { "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP },
1622
1623 { "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1624
1625 { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1626 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1627 { "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 },
1628 /* Gas local alias of mov imm32(not defined in spec). */
1629 { "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS },
1630
1631 { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1632
1633 { "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1634
1635 { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1636 { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 },
1637
1638 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1639 { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1640
1641 { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1642
1643 { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1644 { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 },
1645
1646 { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL },
1647
1648 { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL },
1649
1650 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1651 { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1652
1653 { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL },
1654
1655 { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1656
1657 { "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1658
1659 { "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, PROCESSOR_V850E3V5_UP },
1660
1661 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
1662 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 },
1663 { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 },
1664 { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 },
1665 { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 },
1666
1667 { "pushsp", two (0x47e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1668
1669 { "rotl", two (0x07e0, 0x00c6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1670 { "rotl", two (0x07e0, 0x00c4), two (0x07e0, 0x07ff), {I5U, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1671
1672 { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1673
1674 { "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1675 { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1676 { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1677
1678 { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 },
1679
1680 { "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1681 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1682 { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1683
1684 { "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1685 { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1686
1687 { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1688
1689 { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1690
1691 { "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1692
1693 { "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1694
1695 { "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1696
1697 { "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1698
1699 { "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1700
1701 { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1702 { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1703 { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1704 { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1705
1706 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1707 { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1708
1709 { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL },
1710
1711 { "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1712 { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1713 { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1714
1715 { "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1716 { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1717 { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1718
1719 { "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL },
1720
1721 { "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1722
1723 { "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL },
1724
1725 { "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1726
1727 { "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL },
1728
1729 { "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1730
1731 { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL },
1732
1733 { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL },
1734
1735 { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL },
1736
1737 { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1738 { "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1739
1740 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL },
1741 { "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP },
1742 { "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1743
1744 { "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP },
1745 { "st.dw23", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1746
1747 { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL },
1748 { "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP },
1749 { "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1750
1751 { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL },
1752 { "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP },
1753 { "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1754
1755 { "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, PROCESSOR_V850E3V5_UP },
1756
1757 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1758 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1759 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {OLDSR1, R2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
1760
1761 { "sttc.gr", two (0x07e0, 0x0052), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP },
1762 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1763 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1764 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1765 { "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, PROCESSOR_V850E3V5_UP },
1766
1767 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1768 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1769
1770 { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL },
1771
1772 { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL },
1773
1774 { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
1775
1776 { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1777
1778 { "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1779
1780 { "tlbai", two (0x87e0, 0x8960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1781 { "tlbr", two (0x87e0, 0xe960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1782 { "tlbs", two (0x87e0, 0xc160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1783 { "tlbvi", two (0x87e0, 0x8160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1784 { "tlbw", two (0x87e0, 0xe160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1785
1786 { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL },
1787
1788 { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL },
1789
1790 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1791 { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1792
1793 { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL },
1794
1795 { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1796
1797 { "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1798
1799 { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1800
1801 /* Floating point operation. */
1802 { "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1803 { "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1804 { "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1805 { "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1806 { "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1807 { "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1808 { "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1809 { "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1810 { "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1811 { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1812 { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1813 { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1814 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1815 /* Default value for FFF is 0(not defined in spec). */
1816 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1817 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1818 /* Default value for FFF is 0(not defined in spec). */
1819 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1820 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3_UP },
1821 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1822 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3_UP },
1823 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3_UP },
1824 { "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1825 { "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1826 { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1827 { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1828 { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1829 { "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1830 { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1831 { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1832 { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1833 { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1834 { "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1835 { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1836 { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1837 { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1838 { "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1839 { "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1840 { "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1841 { "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1842 { "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1843 { "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1844 { "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1845 { "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1846 { "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1847 { "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1848 { "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1849 { "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1850 { "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1851 { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1852 { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1853 { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1854 { "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1855 { "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1856 { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1857 { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1858 { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1859 { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1860 { "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1861 { "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1862 { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1863 { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1864 { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1865 { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1866 { "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1867 { "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1868 { "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1869 { "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1870 { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1871 { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1872
1873 { "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1874 { "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1875 { "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1876 { "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1877 { "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1878 { "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1879 { "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1880 { "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1881
1882 { "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1883 { "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1884 { "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1885 { "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1886 { "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1887 { "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1888 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP },
1889 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1890 { "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1891 { "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1892 { "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1893 { "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1894 { "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1895 { "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1896 { "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1897 { "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1898
1899 /* Special instruction (from gdb) mov 1, r0. */
1900 { "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL },
1901
1902 { "synci", one (0x001c), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1903
1904 { "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1905 { "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1906 { "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1907 { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP },
1908 /* Alias of syncp. */
1909 { "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS },
1910 { "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1911 { "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1912 { "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {RIE_IMM5,RIE_IMM4}, 0, PROCESSOR_V850E2V3_UP },
1913
1914 { 0, 0, 0, {0}, 0, 0 },
1915 } ;
1916
1917 const int v850_num_opcodes =
1918 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
1919