12a6b7db3Sskrll /* cr16-opc.c -- Table of opcodes for the CR16 processor. 2*f22f0ef4Schristos Copyright (C) 2007-2022 Free Software Foundation, Inc. 32a6b7db3Sskrll Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com) 42a6b7db3Sskrll 52a6b7db3Sskrll This file is part of the GNU opcodes library. 62a6b7db3Sskrll 72a6b7db3Sskrll This library is free software; you can redistribute it and/or modify 82a6b7db3Sskrll it under the terms of the GNU General Public License as published by 92a6b7db3Sskrll the Free Software Foundation; either version 3, or (at your option) 102a6b7db3Sskrll any later version. 112a6b7db3Sskrll 122a6b7db3Sskrll It is distributed in the hope that it will be useful, but WITHOUT 132a6b7db3Sskrll ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 142a6b7db3Sskrll or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 152a6b7db3Sskrll License for more details. 162a6b7db3Sskrll 172a6b7db3Sskrll You should have received a copy of the GNU General Public License 182a6b7db3Sskrll along with this program; if not, write to the Free Software Foundation, 192a6b7db3Sskrll Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 202a6b7db3Sskrll 212a6b7db3Sskrll #include <stdio.h> 222a6b7db3Sskrll #include "libiberty.h" 232a6b7db3Sskrll #include "symcat.h" 242a6b7db3Sskrll #include "opcode/cr16.h" 252a6b7db3Sskrll 262a6b7db3Sskrll const inst cr16_instruction[] = 272a6b7db3Sskrll { 282a6b7db3Sskrll /* Create an arithmetic instruction - INST[bw]. */ 292a6b7db3Sskrll #define ARITH_BYTE_INST(NAME, OPC, OP1) \ 302a6b7db3Sskrll /* opc8 imm4 r */ \ 312a6b7db3Sskrll {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{uimm4_1,20}, {regr,16}}}, \ 322a6b7db3Sskrll /* opc8 imm16 r */ \ 332a6b7db3Sskrll {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \ 342a6b7db3Sskrll /* opc8 r r */ \ 352a6b7db3Sskrll {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} 362a6b7db3Sskrll 37b3ac4aedSchristos /* For Logical operations, allow unsigned imm16 also. */ 382a6b7db3Sskrll #define ARITH1_BYTE_INST(NAME, OPC, OP1) \ 392a6b7db3Sskrll /* opc8 imm16 r */ \ 402a6b7db3Sskrll {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}} 412a6b7db3Sskrll 422a6b7db3Sskrll 432a6b7db3Sskrll ARITH_BYTE_INST ("andb", 0x20, uimm16), 442a6b7db3Sskrll ARITH1_BYTE_INST ("andb", 0x20, imm16), 452a6b7db3Sskrll ARITH_BYTE_INST ("andw", 0x22, uimm16), 462a6b7db3Sskrll ARITH1_BYTE_INST ("andw", 0x22, imm16), 472a6b7db3Sskrll 482a6b7db3Sskrll ARITH_BYTE_INST ("orb", 0x24, uimm16), 492a6b7db3Sskrll ARITH1_BYTE_INST ("orb", 0x24, imm16), 502a6b7db3Sskrll ARITH_BYTE_INST ("orw", 0x26, uimm16), 512a6b7db3Sskrll ARITH1_BYTE_INST ("orw", 0x26, imm16), 522a6b7db3Sskrll 532a6b7db3Sskrll ARITH_BYTE_INST ("xorb", 0x28, uimm16), 542a6b7db3Sskrll ARITH1_BYTE_INST ("xorb", 0x28, imm16), 552a6b7db3Sskrll ARITH_BYTE_INST ("xorw", 0x2A, uimm16), 562a6b7db3Sskrll ARITH1_BYTE_INST ("xorw", 0x2A, imm16), 572a6b7db3Sskrll 582a6b7db3Sskrll ARITH_BYTE_INST ("addub", 0x2C, imm16), 592a6b7db3Sskrll ARITH_BYTE_INST ("adduw", 0x2E, imm16), 602a6b7db3Sskrll ARITH_BYTE_INST ("addb", 0x30, imm16), 612a6b7db3Sskrll ARITH_BYTE_INST ("addw", 0x32, imm16), 622a6b7db3Sskrll ARITH_BYTE_INST ("addcb", 0x34, imm16), 632a6b7db3Sskrll ARITH_BYTE_INST ("addcw", 0x36, imm16), 642a6b7db3Sskrll 652a6b7db3Sskrll ARITH_BYTE_INST ("subb", 0x38, imm16), 662a6b7db3Sskrll ARITH_BYTE_INST ("subw", 0x3A, imm16), 672a6b7db3Sskrll ARITH_BYTE_INST ("subcb", 0x3C, imm16), 682a6b7db3Sskrll ARITH_BYTE_INST ("subcw", 0x3E, imm16), 692a6b7db3Sskrll 702a6b7db3Sskrll ARITH_BYTE_INST ("cmpb", 0x50, imm16), 712a6b7db3Sskrll ARITH_BYTE_INST ("cmpw", 0x52, imm16), 722a6b7db3Sskrll 732a6b7db3Sskrll ARITH_BYTE_INST ("movb", 0x58, imm16), 742a6b7db3Sskrll ARITH_BYTE_INST ("movw", 0x5A, imm16), 752a6b7db3Sskrll 762a6b7db3Sskrll ARITH_BYTE_INST ("mulb", 0x64, imm16), 772a6b7db3Sskrll ARITH_BYTE_INST ("mulw", 0x66, imm16), 782a6b7db3Sskrll 792a6b7db3Sskrll #define ARITH_BYTE_INST1(NAME, OPC) \ 802a6b7db3Sskrll /* opc8 r r */ \ 812a6b7db3Sskrll {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} 822a6b7db3Sskrll 832a6b7db3Sskrll ARITH_BYTE_INST1 ("movxb", 0x5C), 842a6b7db3Sskrll ARITH_BYTE_INST1 ("movzb", 0x5D), 852a6b7db3Sskrll ARITH_BYTE_INST1 ("mulsb", 0x0B), 862a6b7db3Sskrll 872a6b7db3Sskrll #define ARITH_BYTE_INST2(NAME, OPC) \ 882a6b7db3Sskrll /* opc8 r rp */ \ 892a6b7db3Sskrll {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regp,16}}} 902a6b7db3Sskrll 912a6b7db3Sskrll ARITH_BYTE_INST2 ("movxw", 0x5E), 922a6b7db3Sskrll ARITH_BYTE_INST2 ("movzw", 0x5F), 932a6b7db3Sskrll ARITH_BYTE_INST2 ("mulsw", 0x62), 942a6b7db3Sskrll ARITH_BYTE_INST2 ("muluw", 0x63), 952a6b7db3Sskrll 962a6b7db3Sskrll /* Create an arithmetic instruction - INST[d]- with 3 types. */ 972a6b7db3Sskrll #define ARITH_INST_D(NAME, OPC) \ 982a6b7db3Sskrll /* opc8 imm4 rp */ \ 992a6b7db3Sskrll {NAME, 1, OPC, 24, ARITH_INS, {{uimm4_1,20}, {regp,16}}}, \ 1002a6b7db3Sskrll /* opc8 imm16 rp */ \ 1012a6b7db3Sskrll {NAME, 2, (OPC<<4)+0xB, 20, ARITH_INS, {{imm16,0}, {regp,16}}}, \ 1022a6b7db3Sskrll /* opc8 rp rp */ \ 1032a6b7db3Sskrll {NAME, 1, OPC+1, 24, ARITH_INS, {{regp,20}, {regp,16}}} 1042a6b7db3Sskrll 1052a6b7db3Sskrll /* Create an arithmetic instruction - INST[d]-20 bit types. */ 1062a6b7db3Sskrll #define ARITH_INST20(NAME, OPC) \ 1072a6b7db3Sskrll /* opc8 uimm20 rp */ \ 1082a6b7db3Sskrll {NAME, 2, OPC, 24, ARITH_INS, {{uimm20,0}, {regp,20}}} 1092a6b7db3Sskrll 1102a6b7db3Sskrll /* Create an arithmetic instruction - INST[d]-32 bit types. */ 1112a6b7db3Sskrll #define ARITH_INST32(NAME, OPC, OP1) \ 1122a6b7db3Sskrll /* opc12 imm32 rp */ \ 1132a6b7db3Sskrll {NAME, 3, OPC, 20, ARITH_INS, {{OP1,0}, {regp,16}}} 1142a6b7db3Sskrll 1152a6b7db3Sskrll /* Create an arithmetic instruction - INST[d]-32bit types(reg pairs).*/ 1162a6b7db3Sskrll #define ARITH_INST32RP(NAME, OPC) \ 1172a6b7db3Sskrll /* opc24 rp rp */ \ 1182a6b7db3Sskrll {NAME, 2, OPC, 12, ARITH_INS, {{regp,4}, {regp,0}}} 1192a6b7db3Sskrll 1202a6b7db3Sskrll ARITH_INST_D ("movd", 0x54), 1212a6b7db3Sskrll ARITH_INST20 ("movd", 0x05), 1222a6b7db3Sskrll ARITH_INST32 ("movd", 0x007, imm32), 1232a6b7db3Sskrll ARITH_INST_D ("addd", 0x60), 1242a6b7db3Sskrll ARITH_INST20 ("addd", 0x04), 1252a6b7db3Sskrll ARITH_INST32 ("addd", 0x002, imm32), 1262a6b7db3Sskrll ARITH_INST32 ("subd", 0x003, imm32), 1272a6b7db3Sskrll ARITH_INST32RP ("subd", 0x0014C), 1282a6b7db3Sskrll ARITH_INST_D ("cmpd", 0x56), 1292a6b7db3Sskrll ARITH_INST32 ("cmpd", 0x009, imm32), 1302a6b7db3Sskrll ARITH_INST32 ("andd", 0x004, uimm32), 1312a6b7db3Sskrll ARITH_INST32RP ("andd", 0x0014B), 1322a6b7db3Sskrll ARITH_INST32 ("ord", 0x005, uimm32), 1332a6b7db3Sskrll ARITH_INST32RP ("ord", 0x00149), 1342a6b7db3Sskrll ARITH_INST32 ("xord", 0x006, uimm32), 1352a6b7db3Sskrll ARITH_INST32RP ("xord", 0x0014A), 1362a6b7db3Sskrll 1372a6b7db3Sskrll /* Create a shift instruction. */ 1382a6b7db3Sskrll #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 1392a6b7db3Sskrll /* opc imm r */ \ 1402a6b7db3Sskrll {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 1412a6b7db3Sskrll /* opc imm r */ \ 1422a6b7db3Sskrll {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\ 1432a6b7db3Sskrll /* opc r r */ \ 1442a6b7db3Sskrll {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} 1452a6b7db3Sskrll 1462a6b7db3Sskrll SHIFT_INST_A("ashub", 0x80, 0x41, 23, imm4, regr), 1472a6b7db3Sskrll SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp), 1482a6b7db3Sskrll SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr), 1492a6b7db3Sskrll 1502a6b7db3Sskrll #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 1512a6b7db3Sskrll /* opc imm r */ \ 1522a6b7db3Sskrll {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 1532a6b7db3Sskrll /* opc r r */ \ 1542a6b7db3Sskrll {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} 1552a6b7db3Sskrll 1562a6b7db3Sskrll SHIFT_INST_L("lshb", 0x13, 0x44, 23, imm4, regr), 1572a6b7db3Sskrll SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp), 1582a6b7db3Sskrll SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr), 1592a6b7db3Sskrll 1602a6b7db3Sskrll /* Create a conditional branch instruction. */ 1612a6b7db3Sskrll #define BRANCH_INST(NAME, OPC) \ 1622a6b7db3Sskrll /* opc4 c4 dispe9 */ \ 1632a6b7db3Sskrll {NAME, 1, OPC, 28, BRANCH_INS | RELAXABLE, {{cc,20}, {dispe9,16}}},\ 1642a6b7db3Sskrll /* opc4 c4 disps17 */ \ 1652a6b7db3Sskrll {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS | RELAXABLE, {{cc,20}, {disps17,0}}},\ 1662a6b7db3Sskrll /* opc4 c4 disps25 */ \ 1672a6b7db3Sskrll {NAME, 3, (OPC<<4), 16 , BRANCH_INS | RELAXABLE, {{cc,4}, {disps25,16}}} 1682a6b7db3Sskrll 1692a6b7db3Sskrll BRANCH_INST ("b", 0x1), 1702a6b7db3Sskrll 1712a6b7db3Sskrll /* Create a 'Branch if Equal to 0' instruction. */ 1722a6b7db3Sskrll #define BRANCH_NEQ_INST(NAME, OPC) \ 1732a6b7db3Sskrll /* opc8 disps5 r */ \ 1742a6b7db3Sskrll {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {disps5,20}}} 1752a6b7db3Sskrll 1762a6b7db3Sskrll BRANCH_NEQ_INST ("beq0b", 0x0C), 1772a6b7db3Sskrll BRANCH_NEQ_INST ("bne0b", 0x0D), 1782a6b7db3Sskrll BRANCH_NEQ_INST ("beq0w", 0x0E), 1792a6b7db3Sskrll BRANCH_NEQ_INST ("bne0w", 0x0F), 1802a6b7db3Sskrll 1812a6b7db3Sskrll 1822a6b7db3Sskrll /* Create an instruction using a single register operand. */ 1832a6b7db3Sskrll #define REG1_INST(NAME, OPC) \ 1842a6b7db3Sskrll /* opc8 c4 r */ \ 1852a6b7db3Sskrll {NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}} 1862a6b7db3Sskrll 1872a6b7db3Sskrll #define REGP1_INST(NAME, OPC) \ 1882a6b7db3Sskrll /* opc8 c4 r */ \ 1892a6b7db3Sskrll {NAME, 1, OPC, 20, NO_TYPE_INS, {{regp,16}}} 1902a6b7db3Sskrll 1912a6b7db3Sskrll /* Same as REG1_INST, with additional FLAGS. */ 1922a6b7db3Sskrll #define REG1_FLAG_INST(NAME, OPC, FLAGS) \ 1932a6b7db3Sskrll /* opc8 c4 r */ \ 1942a6b7db3Sskrll {NAME, 1, OPC, 20, NO_TYPE_INS | FLAGS, {{regp,16}}} 1952a6b7db3Sskrll 1962a6b7db3Sskrll /* JCond instructions */ 1972a6b7db3Sskrll REGP1_INST ("jeq", 0x0A0), 1982a6b7db3Sskrll REGP1_INST ("jne", 0x0A1), 1992a6b7db3Sskrll REGP1_INST ("jcs", 0x0A2), 2002a6b7db3Sskrll REGP1_INST ("jcc", 0x0A3), 2012a6b7db3Sskrll REGP1_INST ("jhi", 0x0A4), 2022a6b7db3Sskrll REGP1_INST ("jls", 0x0A5), 2032a6b7db3Sskrll REGP1_INST ("jgt", 0x0A6), 2042a6b7db3Sskrll REGP1_INST ("jle", 0x0A7), 2052a6b7db3Sskrll REGP1_INST ("jfs", 0x0A8), 2062a6b7db3Sskrll REGP1_INST ("jfc", 0x0A9), 2072a6b7db3Sskrll REGP1_INST ("jlo", 0x0AA), 2082a6b7db3Sskrll REGP1_INST ("jhs", 0x0AB), 2092a6b7db3Sskrll REGP1_INST ("jlt", 0x0AC), 2102a6b7db3Sskrll REGP1_INST ("jge", 0x0AD), 2112a6b7db3Sskrll REGP1_INST ("jump", 0x0AE), 2122a6b7db3Sskrll REGP1_INST ("jusr", 0x0AF), 2132a6b7db3Sskrll 2142a6b7db3Sskrll /* SCond instructions */ 2152a6b7db3Sskrll REG1_INST ("seq", 0x080), 2162a6b7db3Sskrll REG1_INST ("sne", 0x081), 2172a6b7db3Sskrll REG1_INST ("scs", 0x082), 2182a6b7db3Sskrll REG1_INST ("scc", 0x083), 2192a6b7db3Sskrll REG1_INST ("shi", 0x084), 2202a6b7db3Sskrll REG1_INST ("sls", 0x085), 2212a6b7db3Sskrll REG1_INST ("sgt", 0x086), 2222a6b7db3Sskrll REG1_INST ("sle", 0x087), 2232a6b7db3Sskrll REG1_INST ("sfs", 0x088), 2242a6b7db3Sskrll REG1_INST ("sfc", 0x089), 2252a6b7db3Sskrll REG1_INST ("slo", 0x08A), 2262a6b7db3Sskrll REG1_INST ("shs", 0x08B), 2272a6b7db3Sskrll REG1_INST ("slt", 0x08C), 2282a6b7db3Sskrll REG1_INST ("sge", 0x08D), 2292a6b7db3Sskrll 2302a6b7db3Sskrll 2312a6b7db3Sskrll /* Create an instruction using two register operands. */ 2322a6b7db3Sskrll #define REG3_INST(NAME, OPC) \ 2332a6b7db3Sskrll /* opc24 r r rp */ \ 2342a6b7db3Sskrll {NAME, 2, OPC, 12, NO_TYPE_INS, {{regr,4}, {regr,0}, {regp,8}}} 2352a6b7db3Sskrll 2362a6b7db3Sskrll /* MULTIPLY INSTRUCTIONS */ 2372a6b7db3Sskrll REG3_INST ("macqw", 0x0014d), 2382a6b7db3Sskrll REG3_INST ("macuw", 0x0014e), 2392a6b7db3Sskrll REG3_INST ("macsw", 0x0014f), 2402a6b7db3Sskrll 2412a6b7db3Sskrll /* Create a branch instruction. */ 2422a6b7db3Sskrll #define BR_INST(NAME, OPC) \ 2432a6b7db3Sskrll /* opc12 ra disps25 */ \ 2442a6b7db3Sskrll {NAME, 2, OPC, 24, NO_TYPE_INS, {{rra,0}, {disps25,0}}} 2452a6b7db3Sskrll 2462a6b7db3Sskrll #define BR_INST_RP(NAME, OPC) \ 2472a6b7db3Sskrll /* opc8 rp disps25 */ \ 2482a6b7db3Sskrll {NAME, 3, OPC, 12, NO_TYPE_INS, {{regp,4}, {disps25,16}}} 2492a6b7db3Sskrll 2502a6b7db3Sskrll BR_INST ("bal", 0xC0), 2512a6b7db3Sskrll BR_INST_RP ("bal", 0x00102), 2522a6b7db3Sskrll 2532a6b7db3Sskrll #define REGPP2_INST(NAME, OPC) \ 2542a6b7db3Sskrll /* opc16 rp rp */ \ 2552a6b7db3Sskrll {NAME, 2, OPC, 12, NO_TYPE_INS, {{regp,0}, {regp,4}}} 2562a6b7db3Sskrll /* Jump and link instructions. */ 2572a6b7db3Sskrll REGP1_INST ("jal",0x00D), 2582a6b7db3Sskrll REGPP2_INST ("jal",0x00148), 2592a6b7db3Sskrll 2602a6b7db3Sskrll 2612a6b7db3Sskrll /* Instructions including a register list (opcode is represented as a mask). */ 2622a6b7db3Sskrll #define REGLIST_INST(NAME, OPC, TYPE) \ 2632a6b7db3Sskrll /* opc7 r count3 RA */ \ 2642a6b7db3Sskrll {NAME,1, (OPC<<1)+1, 23, TYPE, {{uimm3_1,20},{regr,16},{regr,0}}}, \ 2652a6b7db3Sskrll /* opc8 r count3 */ \ 2662a6b7db3Sskrll {NAME, 1, OPC, 24, TYPE, {{uimm3_1,20}, {regr,16}}}, \ 2672a6b7db3Sskrll /* opc12 RA */ \ 2682a6b7db3Sskrll {NAME, 1, (OPC<<8)+0x1E, 16, TYPE, {{regr,0}}} 2692a6b7db3Sskrll 2702a6b7db3Sskrll REGLIST_INST ("push", 0x01, (NO_TYPE_INS | REG_LIST)), 2712a6b7db3Sskrll REGLIST_INST ("pop", 0x02, (NO_TYPE_INS | REG_LIST)), 2722a6b7db3Sskrll REGLIST_INST ("popret", 0x03, (NO_TYPE_INS | REG_LIST)), 2732a6b7db3Sskrll 2742a6b7db3Sskrll {"loadm", 1, 0x14, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, 2752a6b7db3Sskrll {"loadmp", 1, 0x15, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, 2762a6b7db3Sskrll {"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, 2772a6b7db3Sskrll {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, 2782a6b7db3Sskrll 279fa2c2dd3Schristos /* Processor Register Manipulation instructions */ 2802a6b7db3Sskrll /* opc16 reg, preg */ 2812a6b7db3Sskrll {"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}}, 2822a6b7db3Sskrll /* opc16 regp, pregp */ 2832a6b7db3Sskrll {"lprd", 2, 0x00141, 12, NO_TYPE_INS, {{regp,0}, {pregrp,4}}}, 2842a6b7db3Sskrll /* opc16 preg, reg */ 2852a6b7db3Sskrll {"spr", 2, 0x00142, 12, NO_TYPE_INS, {{pregr,4}, {regr,0}}}, 2862a6b7db3Sskrll /* opc16 pregp, regp */ 2872a6b7db3Sskrll {"sprd", 2, 0x00143, 12, NO_TYPE_INS, {{pregrp,4}, {regp,0}}}, 2882a6b7db3Sskrll 2892a6b7db3Sskrll /* Miscellaneous. */ 2902a6b7db3Sskrll /* opc12 ui4 */ 2912a6b7db3Sskrll {"excp", 1, 0x00C, 20, NO_TYPE_INS, {{uimm4,16}}}, 2922a6b7db3Sskrll 2932a6b7db3Sskrll /* Create a bit-b instruction. */ 2942a6b7db3Sskrll #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ 2952a6b7db3Sskrll /* opcNN iN abs20 */ \ 2962a6b7db3Sskrll {NAME, 2, (OPC3+1), 23, CSTBIT_INS, {{OP,20},{abs20,0}}}, \ 2972a6b7db3Sskrll /* opcNN iN abs24 */ \ 2982a6b7db3Sskrll {NAME, 3, (OPC2+3), 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \ 2992a6b7db3Sskrll /* opcNN iN (Rindex)abs20 */ \ 3002a6b7db3Sskrll {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \ 3012a6b7db3Sskrll /* opcNN iN (prp) disps14(RPbase) */ \ 3022a6b7db3Sskrll {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \ 3032a6b7db3Sskrll /* opcNN iN disps20(Rbase) */ \ 3042a6b7db3Sskrll {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \ 3052a6b7db3Sskrll /* opcNN iN (rp) disps0(RPbase) */ \ 3062a6b7db3Sskrll {NAME, 1, OPC3-2, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \ 3072a6b7db3Sskrll /* opcNN iN (rp) disps16(RPBase) */ \ 3082a6b7db3Sskrll {NAME, 2, OPC3, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \ 3092a6b7db3Sskrll /* opcNN iN (rp) disps20(RPBase) */ \ 3102a6b7db3Sskrll {NAME, 3, (OPC2+1), 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \ 3112a6b7db3Sskrll /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ 3122a6b7db3Sskrll {NAME, 3, (OPC2+2), 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}} 3132a6b7db3Sskrll 3142a6b7db3Sskrll CSTBIT_INST_B ("cbitb", uimm3, 0x68, 0x00104, 0xD6, 0x1AA), 3152a6b7db3Sskrll CSTBIT_INST_B ("sbitb", uimm3, 0x70, 0x00108, 0xE6, 0x1CA), 3162a6b7db3Sskrll CSTBIT_INST_B ("tbitb", uimm3, 0x78, 0x0010C, 0xF6, 0x1EA), 3172a6b7db3Sskrll 3182a6b7db3Sskrll /* Create a bit-w instruction. */ 3192a6b7db3Sskrll #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ 3202a6b7db3Sskrll /* opcNN iN abs20 */ \ 3212a6b7db3Sskrll {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \ 3222a6b7db3Sskrll /* opcNN iN abs24 */ \ 3232a6b7db3Sskrll {NAME, 3, OPC2+3, 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \ 3242a6b7db3Sskrll /* opcNN iN (Rindex)abs20 */ \ 3252a6b7db3Sskrll {NAME, 2, OPC3, 25, CSTBIT_INS, {{OP,20}, {rindex8_abs20,0}}}, \ 3262a6b7db3Sskrll /* opcNN iN (prp) disps14(RPbase) */ \ 3272a6b7db3Sskrll {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \ 3282a6b7db3Sskrll /* opcNN iN disps20(Rbase) */ \ 3292a6b7db3Sskrll {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \ 3302a6b7db3Sskrll /* opcNN iN (rp) disps0(RPbase) */ \ 3312a6b7db3Sskrll {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \ 3322a6b7db3Sskrll /* opcNN iN (rp) disps16(RPBase) */ \ 3332a6b7db3Sskrll {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \ 3342a6b7db3Sskrll /* opcNN iN (rp) disps20(RPBase) */ \ 3352a6b7db3Sskrll {NAME, 3, OPC2+1, 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \ 3362a6b7db3Sskrll /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ 3372a6b7db3Sskrll {NAME, 3, OPC2+2, 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}} 3382a6b7db3Sskrll 3392a6b7db3Sskrll CSTBIT_INST_W ("cbitw", uimm4, 0x69, 0x00114, 0x36, 0x1AB), 3402a6b7db3Sskrll CSTBIT_INST_W ("sbitw", uimm4, 0x71, 0x00118, 0x3A, 0x1CB), 3412a6b7db3Sskrll CSTBIT_INST_W ("tbitw", uimm4, 0x79, 0x0011C, 0x3E, 0x1EB), 3422a6b7db3Sskrll 3432a6b7db3Sskrll /* tbit cnt */ 3442a6b7db3Sskrll {"tbit", 1, 0x06, 24, CSTBIT_INS, {{uimm4,20}, {regr,16}}}, 3452a6b7db3Sskrll /* tbit reg reg */ 3462a6b7db3Sskrll {"tbit", 1, 0x07, 24, CSTBIT_INS, {{regr,20}, {regr,16}}}, 3472a6b7db3Sskrll 3482a6b7db3Sskrll 3492a6b7db3Sskrll /* Load instructions (from memory to register). */ 3502a6b7db3Sskrll #define LD_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_S, OP_D) \ 3512a6b7db3Sskrll /* opc8 reg abs20 */ \ 3522a6b7db3Sskrll {NAME, 2, OPC3, 24, LD_STOR_INS, {{abs20,0}, {OP_D,20}}}, \ 3532a6b7db3Sskrll /* opc20 reg abs24 */ \ 3542a6b7db3Sskrll {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{abs24,16}, {OP_D,4}}}, \ 3552a6b7db3Sskrll /* opc7 reg rindex8_abs20 */ \ 3562a6b7db3Sskrll {NAME, 2, OPC5, 25, LD_STOR_INS, {{rindex8_abs20,0}, {OP_D,20}}}, \ 3572a6b7db3Sskrll /* opc4 reg disps4(RPbase) */ \ 3582a6b7db3Sskrll {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,24}, {OP_D,20}}}, \ 3592a6b7db3Sskrll /* opcNN reg disps0(RPbase) */ \ 3602a6b7db3Sskrll {NAME, 1, OPC2, 24, LD_STOR_INS, {{rpindex_disps0,0}, {OP_D,20}}}, \ 3612a6b7db3Sskrll /* opc reg disps14(RPbase) */ \ 3622a6b7db3Sskrll {NAME, 2, OPC4, 22, LD_STOR_INS, {{rpindex_disps14,0}, {OP_D,20}}}, \ 3632a6b7db3Sskrll /* opc reg -disps20(Rbase) */ \ 3642a6b7db3Sskrll {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{rbase_dispe20,16}, {OP_D,4}}}, \ 3652a6b7db3Sskrll /* opc reg disps20(Rbase) */ \ 3662a6b7db3Sskrll {NAME, 3, OPC1, 12, LD_STOR_INS, {{rbase_disps20,16}, {OP_D,4}}}, \ 3672a6b7db3Sskrll /* opc reg (rp) disps16(RPbase) */ \ 3682a6b7db3Sskrll {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{rpbase_disps16,0}, {OP_D,20}}}, \ 3692a6b7db3Sskrll /* opc16 reg (rp) disps20(RPbase) */ \ 3702a6b7db3Sskrll {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{rpbase_disps20,16}, {OP_D,4}}}, \ 3712a6b7db3Sskrll /* op reg (rp) -disps20(RPbase) */ \ 3722a6b7db3Sskrll {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{rpbase_dispe20,16}, {OP_D,4}}}, \ 3732a6b7db3Sskrll /* opc reg rrp (Rindex)disps20(RPbase) */ \ 3742a6b7db3Sskrll {NAME, 3, (OPC1+2), 12, LD_STOR_INS, {{rpindex_disps20,16}, {OP_D,4}}} 3752a6b7db3Sskrll 3762a6b7db3Sskrll LD_REG_INST ("loadb", 0x00124, 0xBE, 0x88, 0x219, 0x45, rpbase_disps4, regr), 3772a6b7db3Sskrll LD_REG_INST ("loadd", 0x00128, 0xAE, 0x87, 0x21A, 0x46, rpbase_dispe4, regp), 3782a6b7db3Sskrll LD_REG_INST ("loadw", 0x0012C, 0x9E, 0x89, 0x21B, 0x47, rpbase_dispe4, regr), 3792a6b7db3Sskrll 3802a6b7db3Sskrll /* Store instructions (from reg to memory). */ 3812a6b7db3Sskrll #define ST_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_D, OP_S) \ 3822a6b7db3Sskrll /* opc8 reg abs20 */ \ 3832a6b7db3Sskrll {NAME, 2, OPC3, 24, LD_STOR_INS, {{OP_S,20}, {abs20,0}}}, \ 3842a6b7db3Sskrll /* opc20 reg abs24 */ \ 3852a6b7db3Sskrll {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{OP_S,4}, {abs24,16}}}, \ 3862a6b7db3Sskrll /* opc7 reg rindex8_abs20 */ \ 3872a6b7db3Sskrll {NAME, 2, OPC5, 25, LD_STOR_INS, {{OP_S,20}, {rindex8_abs20,0}}}, \ 3882a6b7db3Sskrll /* opc4 reg disps4(RPbase) */ \ 3892a6b7db3Sskrll {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,20}, {OP_D,24}}}, \ 3902a6b7db3Sskrll /* opcNN reg disps0(RPbase) */ \ 3912a6b7db3Sskrll {NAME, 1, OPC2, 24, LD_STOR_INS, {{OP_S,20}, {rpindex_disps0,0}}}, \ 3922a6b7db3Sskrll /* opc reg disps14(RPbase) */ \ 3932a6b7db3Sskrll {NAME, 2, OPC4, 22, LD_STOR_INS, {{OP_S,20}, {rpindex_disps14,0}}}, \ 3942a6b7db3Sskrll /* opc reg -disps20(Rbase) */ \ 3952a6b7db3Sskrll {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{OP_S,4}, {rbase_dispe20,16}}}, \ 3962a6b7db3Sskrll /* opc reg disps20(Rbase) */ \ 3972a6b7db3Sskrll {NAME, 3, OPC1, 12, LD_STOR_INS, {{OP_S,4}, {rbase_disps20,16}}}, \ 3982a6b7db3Sskrll /* opc reg disps16(RPbase) */ \ 3992a6b7db3Sskrll {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{OP_S,20}, {rpbase_disps16,0}}}, \ 4002a6b7db3Sskrll /* opc16 reg disps20(RPbase) */ \ 4012a6b7db3Sskrll {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_disps20,16}}}, \ 4022a6b7db3Sskrll /* op reg (rp) -disps20(RPbase) */ \ 4032a6b7db3Sskrll {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_dispe20,16}}}, \ 4042a6b7db3Sskrll /* opc reg rrp (Rindex)disps20(RPbase) */ \ 4052a6b7db3Sskrll {NAME, 3, OPC1+2, 12, LD_STOR_INS, {{OP_S,4}, {rpindex_disps20,16}}} 4062a6b7db3Sskrll 4072a6b7db3Sskrll 4082a6b7db3Sskrll /* Store instructions (from imm to memory). */ 4092a6b7db3Sskrll #define ST_IMM_INST(NAME, OPC1, OPC2, OPC3, OPC4) \ 4102a6b7db3Sskrll /* opcNN iN abs20 */ \ 4112a6b7db3Sskrll {NAME, 2, OPC1, 24, LD_STOR_INS, {{uimm4,20},{abs20,0}}}, \ 4122a6b7db3Sskrll /* opcNN iN abs24 */ \ 4132a6b7db3Sskrll {NAME, 3, OPC2+3, 12, LD_STOR_INS, {{uimm4,4},{abs24,16}}}, \ 4142a6b7db3Sskrll /* opcNN iN (Rindex)abs20 */ \ 4152a6b7db3Sskrll {NAME, 2, OPC3, 25, LD_STOR_INS, {{uimm4,20}, {rindex8_abs20,0}}}, \ 4162a6b7db3Sskrll /* opcNN iN (prp) disps14(RPbase) */ \ 4172a6b7db3Sskrll {NAME, 2, OPC4, 22, LD_STOR_INS, {{uimm4,4},{rpindex_disps14,0}}}, \ 4182a6b7db3Sskrll /* opcNN iN (rp) disps0(RPbase) */ \ 4192a6b7db3Sskrll {NAME, 1, OPC1+1, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps0,16}}}, \ 4202a6b7db3Sskrll /* opcNN iN disps20(Rbase) */ \ 4212a6b7db3Sskrll {NAME, 3, OPC2, 12, LD_STOR_INS, {{uimm4,4}, {rbase_disps20,16}}}, \ 4222a6b7db3Sskrll /* opcNN iN (rp) disps16(RPBase) */ \ 4232a6b7db3Sskrll {NAME, 2, OPC1+2, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps16,0}}}, \ 4242a6b7db3Sskrll /* opcNN iN (rp) disps20(RPBase) */ \ 4252a6b7db3Sskrll {NAME, 3, OPC2+1, 12, LD_STOR_INS, {{uimm4,4}, {rpbase_disps20,16}}}, \ 4262a6b7db3Sskrll /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ 4272a6b7db3Sskrll {NAME, 3, OPC2+2, 12, LD_STOR_INS, {{uimm4,4}, {rpindex_disps20,16}}} 4282a6b7db3Sskrll 4292a6b7db3Sskrll ST_REG_INST ("storb", 0x00134, 0xFE, 0xC8, 0x319, 0x65, rpbase_disps4, regr), 4302a6b7db3Sskrll ST_IMM_INST ("storb", 0x81, 0x00120, 0x42, 0x218), 4312a6b7db3Sskrll ST_REG_INST ("stord", 0x00138, 0xEE, 0xC7, 0x31A, 0x66, rpbase_dispe4, regp), 4322a6b7db3Sskrll ST_REG_INST ("storw", 0x0013C, 0xDE, 0xC9, 0x31B, 0x67, rpbase_dispe4, regr), 4332a6b7db3Sskrll ST_IMM_INST ("storw", 0xC1, 0x00130, 0x62, 0x318), 4342a6b7db3Sskrll 4352a6b7db3Sskrll /* Create instruction with no operands. */ 4362a6b7db3Sskrll #define NO_OP_INST(NAME, OPC) \ 4372a6b7db3Sskrll /* opc16 */ \ 4382a6b7db3Sskrll {NAME, 1, OPC, 16, 0, {{0, 0}}} 4392a6b7db3Sskrll 4402a6b7db3Sskrll NO_OP_INST ("cinv[i]", 0x000A), 4412a6b7db3Sskrll NO_OP_INST ("cinv[i,u]", 0x000B), 4422a6b7db3Sskrll NO_OP_INST ("cinv[d]", 0x000C), 4432a6b7db3Sskrll NO_OP_INST ("cinv[d,u]", 0x000D), 4442a6b7db3Sskrll NO_OP_INST ("cinv[d,i]", 0x000E), 4452a6b7db3Sskrll NO_OP_INST ("cinv[d,i,u]", 0x000F), 4462a6b7db3Sskrll NO_OP_INST ("nop", 0x2C00), 4472a6b7db3Sskrll NO_OP_INST ("retx", 0x0003), 4482a6b7db3Sskrll NO_OP_INST ("di", 0x0004), 4492a6b7db3Sskrll NO_OP_INST ("ei", 0x0005), 4502a6b7db3Sskrll NO_OP_INST ("wait", 0x0006), 4512a6b7db3Sskrll NO_OP_INST ("eiwait", 0x0007), 4522a6b7db3Sskrll 4532a6b7db3Sskrll {NULL, 0, 0, 0, 0, {{0, 0}}} 4542a6b7db3Sskrll }; 4552a6b7db3Sskrll 4562a6b7db3Sskrll const unsigned int cr16_num_opcodes = ARRAY_SIZE (cr16_instruction); 4572a6b7db3Sskrll 4582a6b7db3Sskrll /* Macro to build a reg_entry, which have an opcode image : 4592a6b7db3Sskrll For example : 4602a6b7db3Sskrll REG(u4, 0x84, CR16_U_REGTYPE) 4612a6b7db3Sskrll is interpreted as : 4625ba6b03cSchristos {"u4", u4, 0x84, CR16_U_REGTYPE} 4635ba6b03cSchristos The union initializer (second member) always refers to the first 4645ba6b03cSchristos member of the union, so cast NAME to that type to avoid possible 4655ba6b03cSchristos compiler warnings when used for CR16_P_REGTYPE cases. */ 4665ba6b03cSchristos #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} 4672a6b7db3Sskrll 4682a6b7db3Sskrll #define REGP(NAME, BNAME, N, TYPE) {STRINGX(NAME), {BNAME}, N, TYPE} 4692a6b7db3Sskrll 4702a6b7db3Sskrll const reg_entry cr16_regtab[] = 4712a6b7db3Sskrll { /* Build a general purpose register r<N>. */ 4722a6b7db3Sskrll #define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE) 4732a6b7db3Sskrll 4742a6b7db3Sskrll REG_R(0), REG_R(1), REG_R(2), REG_R(3), 4752a6b7db3Sskrll REG_R(4), REG_R(5), REG_R(6), REG_R(7), 4762a6b7db3Sskrll REG_R(8), REG_R(9), REG_R(10), REG_R(11), 4772a6b7db3Sskrll REG_R(12), REG_R(13), REG_R(14), REG_R(15), 4782a6b7db3Sskrll REG(r12_L, 12, CR16_R_REGTYPE), 4792a6b7db3Sskrll REG(r13_L, 13, CR16_R_REGTYPE), 4802a6b7db3Sskrll REG(ra, 0xe, CR16_R_REGTYPE), 4812a6b7db3Sskrll REG(sp, 0xf, CR16_R_REGTYPE), 4822a6b7db3Sskrll REG(sp_L, 0xf, CR16_R_REGTYPE), 4832a6b7db3Sskrll REG(RA, 0xe, CR16_R_REGTYPE), 4842a6b7db3Sskrll }; 4852a6b7db3Sskrll 4862a6b7db3Sskrll const reg_entry cr16_regptab[] = 4872a6b7db3Sskrll { /* Build a general purpose register r<N>. */ 4882a6b7db3Sskrll 4892a6b7db3Sskrll #define REG_RP(M,N) REGP((CONCAT2(r,M),CONCAT2(r,N)), CONCAT2(r,N), N, CR16_RP_REGTYPE) 4902a6b7db3Sskrll 4912a6b7db3Sskrll REG_RP(1,0), REG_RP(2,1), REG_RP(3,2), REG_RP(4,3), 4922a6b7db3Sskrll REG_RP(5,4), REG_RP(6,5), REG_RP(7,6), REG_RP(8,7), 4932a6b7db3Sskrll REG_RP(9,8), REG_RP(10,9), REG_RP(11,10), REG_RP(12,11), 4942a6b7db3Sskrll REG((r12), 0xc, CR16_RP_REGTYPE), 4952a6b7db3Sskrll REG((r13), 0xd, CR16_RP_REGTYPE), 496*f22f0ef4Schristos /* REG((r14), 0xe, CR16_RP_REGTYPE), */ 4972a6b7db3Sskrll REG((ra), 0xe, CR16_RP_REGTYPE), 4982a6b7db3Sskrll REG((sp), 0xf, CR16_RP_REGTYPE), 4992a6b7db3Sskrll }; 5002a6b7db3Sskrll 5012a6b7db3Sskrll 5022a6b7db3Sskrll const unsigned int cr16_num_regs = ARRAY_SIZE (cr16_regtab) ; 5032a6b7db3Sskrll const unsigned int cr16_num_regps = ARRAY_SIZE (cr16_regptab) ; 5042a6b7db3Sskrll 5052a6b7db3Sskrll const reg_entry cr16_pregtab[] = 5062a6b7db3Sskrll { 5072a6b7db3Sskrll /* Build a processor register. */ 5082a6b7db3Sskrll REG(dbs, 0x0, CR16_P_REGTYPE), 5092a6b7db3Sskrll REG(dsr, 0x1, CR16_P_REGTYPE), 5102a6b7db3Sskrll REG(dcrl, 0x2, CR16_P_REGTYPE), 5112a6b7db3Sskrll REG(dcrh, 0x3, CR16_P_REGTYPE), 5122a6b7db3Sskrll REG(car0l, 0x4, CR16_P_REGTYPE), 5132a6b7db3Sskrll REG(car0h, 0x5, CR16_P_REGTYPE), 5142a6b7db3Sskrll REG(car1l, 0x6, CR16_P_REGTYPE), 5152a6b7db3Sskrll REG(car1h, 0x7, CR16_P_REGTYPE), 5162a6b7db3Sskrll REG(cfg, 0x8, CR16_P_REGTYPE), 5172a6b7db3Sskrll REG(psr, 0x9, CR16_P_REGTYPE), 5182a6b7db3Sskrll REG(intbasel, 0xa, CR16_P_REGTYPE), 5192a6b7db3Sskrll REG(intbaseh, 0xb, CR16_P_REGTYPE), 5202a6b7db3Sskrll REG(ispl, 0xc, CR16_P_REGTYPE), 5212a6b7db3Sskrll REG(isph, 0xd, CR16_P_REGTYPE), 5222a6b7db3Sskrll REG(uspl, 0xe, CR16_P_REGTYPE), 5232a6b7db3Sskrll REG(usph, 0xf, CR16_P_REGTYPE), 5242a6b7db3Sskrll }; 5252a6b7db3Sskrll 5262a6b7db3Sskrll const reg_entry cr16_pregptab[] = 5272a6b7db3Sskrll { 5282a6b7db3Sskrll REG(dbs, 0, CR16_P_REGTYPE), 5292a6b7db3Sskrll REG(dsr, 1, CR16_P_REGTYPE), 5302a6b7db3Sskrll REG(dcr, 2, CR16_P_REGTYPE), 5312a6b7db3Sskrll REG(car0, 4, CR16_P_REGTYPE), 5322a6b7db3Sskrll REG(car1, 6, CR16_P_REGTYPE), 5332a6b7db3Sskrll REG(cfg, 8, CR16_P_REGTYPE), 5342a6b7db3Sskrll REG(psr, 9, CR16_P_REGTYPE), 5352a6b7db3Sskrll REG(intbase, 10, CR16_P_REGTYPE), 5362a6b7db3Sskrll REG(isp, 12, CR16_P_REGTYPE), 5372a6b7db3Sskrll REG(usp, 14, CR16_P_REGTYPE), 5382a6b7db3Sskrll }; 5392a6b7db3Sskrll 5402a6b7db3Sskrll const unsigned int cr16_num_pregs = ARRAY_SIZE (cr16_pregtab); 5412a6b7db3Sskrll const unsigned int cr16_num_pregps = ARRAY_SIZE (cr16_pregptab); 5422a6b7db3Sskrll 5432a6b7db3Sskrll const char *cr16_b_cond_tab[]= 5442a6b7db3Sskrll { 5452a6b7db3Sskrll "eq","ne","cs","cc","hi","ls","gt","le","fs","fc", 5462a6b7db3Sskrll "lo","hs","lt","ge","r", "???" 5472a6b7db3Sskrll }; 5482a6b7db3Sskrll 5492a6b7db3Sskrll const unsigned int cr16_num_cc = ARRAY_SIZE (cr16_b_cond_tab); 5502a6b7db3Sskrll 5512a6b7db3Sskrll /* CR16 operands table. */ 5522a6b7db3Sskrll const operand_entry cr16_optab[] = 5532a6b7db3Sskrll { 5542a6b7db3Sskrll /* Index 0 is dummy, so we can count the instruction's operands. */ 5552a6b7db3Sskrll {0, nullargs, 0}, /* dummy */ 5562a6b7db3Sskrll {3, arg_ic, OP_SIGNED}, /* imm3 */ 5572a6b7db3Sskrll {4, arg_ic, OP_SIGNED}, /* imm4 */ 5582a6b7db3Sskrll {5, arg_ic, OP_SIGNED}, /* imm5 */ 5592a6b7db3Sskrll {6, arg_ic, OP_SIGNED}, /* imm6 */ 5602a6b7db3Sskrll {16, arg_ic, OP_SIGNED}, /* imm16 */ 5612a6b7db3Sskrll {20, arg_ic, OP_SIGNED}, /* imm20 */ 5622a6b7db3Sskrll {32, arg_ic, OP_SIGNED}, /* imm32 */ 5632a6b7db3Sskrll {3, arg_ic, OP_UNSIGNED}, /* uimm3 */ 5642a6b7db3Sskrll {3, arg_ic, OP_UNSIGNED|OP_DEC}, /* uimm3_1 */ 5652a6b7db3Sskrll {4, arg_ic, OP_UNSIGNED}, /* uimm4 */ 5662a6b7db3Sskrll {4, arg_ic, OP_UNSIGNED|OP_ESC}, /* uimm4_1 */ 5672a6b7db3Sskrll {5, arg_ic, OP_UNSIGNED}, /* uimm5 */ 5682a6b7db3Sskrll {16, arg_ic, OP_UNSIGNED}, /* uimm16 */ 5692a6b7db3Sskrll {20, arg_ic, OP_UNSIGNED}, /* uimm20 */ 5702a6b7db3Sskrll {32, arg_ic, OP_UNSIGNED}, /* uimm32 */ 5712a6b7db3Sskrll {5, arg_c, OP_EVEN|OP_SHIFT_DEC|OP_SIGNED}, /* disps5 */ 5722a6b7db3Sskrll {16, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps17 */ 5732a6b7db3Sskrll {24, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps25 */ 5742a6b7db3Sskrll {8, arg_c, OP_EVEN|OP_UNSIGNED}, /* dispe9 */ 5752a6b7db3Sskrll {20, arg_c, OP_UNSIGNED|OP_ABS20}, /* abs20 */ 5762a6b7db3Sskrll {24, arg_c, OP_UNSIGNED|OP_ABS24}, /* abs24 */ 5772a6b7db3Sskrll {4, arg_rp, 0}, /* rra */ 5782a6b7db3Sskrll {4, arg_rbase, 0}, /* rbase */ 5792a6b7db3Sskrll {20, arg_cr, OP_UNSIGNED}, /* rbase_disps20 */ 5802a6b7db3Sskrll {21, arg_cr, OP_NEG}, /* rbase_dispe20 */ 5812a6b7db3Sskrll {0, arg_crp, 0}, /* rpbase_disps0 */ 5822a6b7db3Sskrll {4, arg_crp, OP_EVEN|OP_SHIFT|OP_UNSIGNED|OP_ESC1},/* rpbase_dispe4 */ 5832a6b7db3Sskrll {4, arg_crp, OP_UNSIGNED|OP_ESC1}, /* rpbase_disps4 */ 5842a6b7db3Sskrll {16, arg_crp, OP_UNSIGNED}, /* rpbase_disps16 */ 5852a6b7db3Sskrll {20, arg_crp, OP_UNSIGNED}, /* rpbase_disps20 */ 5862a6b7db3Sskrll {21, arg_crp, OP_NEG}, /* rpbase_dispe20 */ 5872a6b7db3Sskrll {20, arg_idxr, OP_UNSIGNED}, /* rindex7_abs20 */ 5882a6b7db3Sskrll {20, arg_idxr, OP_UNSIGNED}, /* rindex8_abs20 */ 5892a6b7db3Sskrll {0, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps0 */ 5902a6b7db3Sskrll {14, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps14 */ 5912a6b7db3Sskrll {20, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps20 */ 5922a6b7db3Sskrll {4, arg_r, 0}, /* regr */ 5932a6b7db3Sskrll {4, arg_rp, 0}, /* reg pair */ 5942a6b7db3Sskrll {4, arg_pr, 0}, /* proc reg */ 5952a6b7db3Sskrll {4, arg_prp, 0}, /* 32 bit proc reg */ 5962a6b7db3Sskrll {4, arg_cc, OP_UNSIGNED} /* cc - code */ 5972a6b7db3Sskrll }; 5982a6b7db3Sskrll 5992a6b7db3Sskrll const unsigned int cr16_num_optab = ARRAY_SIZE (cr16_optab); 6002a6b7db3Sskrll 6012a6b7db3Sskrll /* CR16 traps/interrupts. */ 6022a6b7db3Sskrll const trap_entry cr16_traps[] = 6032a6b7db3Sskrll { 6042a6b7db3Sskrll {"svc", 5}, {"dvz", 6}, {"flg", 7}, {"bpt", 8}, {"trc", 9}, 6052a6b7db3Sskrll {"und", 10}, {"iad", 12}, {"dbg",14}, {"ise",15} 6062a6b7db3Sskrll }; 6072a6b7db3Sskrll 6082a6b7db3Sskrll const unsigned int cr16_num_traps = ARRAY_SIZE (cr16_traps); 6092a6b7db3Sskrll 6102a6b7db3Sskrll /* CR16 instructions that don't have arguments. */ 6112a6b7db3Sskrll const char * cr16_no_op_insn[] = 6122a6b7db3Sskrll { 6132a6b7db3Sskrll "cinv[i]", "cinv[i,u]", "cinv[d]", "cinv[d,u]", "cinv[d,i]", "cinv[d,i,u]", 6142a6b7db3Sskrll "di", "ei", "eiwait", "nop", "retx", "wait", NULL 6152a6b7db3Sskrll }; 616