12a6b7db3Sskrll /* crx-opc.c -- Table of opcodes for the CRX processor. 2*f22f0ef4Schristos Copyright (C) 2004-2022 Free Software Foundation, Inc. 32a6b7db3Sskrll Contributed by Tomer Levi NSC, Israel. 42a6b7db3Sskrll Originally written for GAS 2.12 by Tomer Levi. 52a6b7db3Sskrll 62a6b7db3Sskrll This file is part of the GNU opcodes library. 72a6b7db3Sskrll 82a6b7db3Sskrll This library is free software; you can redistribute it and/or modify 92a6b7db3Sskrll it under the terms of the GNU General Public License as published by 102a6b7db3Sskrll the Free Software Foundation; either version 3, or (at your option) 112a6b7db3Sskrll any later version. 122a6b7db3Sskrll 132a6b7db3Sskrll It is distributed in the hope that it will be useful, but WITHOUT 142a6b7db3Sskrll ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 152a6b7db3Sskrll or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 162a6b7db3Sskrll License for more details. 172a6b7db3Sskrll 182a6b7db3Sskrll You should have received a copy of the GNU General Public License 192a6b7db3Sskrll along with this program; if not, write to the Free Software 202a6b7db3Sskrll Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 212a6b7db3Sskrll MA 02110-1301, USA. */ 222a6b7db3Sskrll 232a6b7db3Sskrll #include <stdio.h> 242a6b7db3Sskrll #include "libiberty.h" 252a6b7db3Sskrll #include "symcat.h" 262a6b7db3Sskrll #include "opcode/crx.h" 272a6b7db3Sskrll 282a6b7db3Sskrll const inst crx_instruction[] = 292a6b7db3Sskrll { 302a6b7db3Sskrll /* Create an arithmetic instruction - INST[bw]. */ 312a6b7db3Sskrll #define ARITH_BYTE_INST(NAME, OPC) \ 322a6b7db3Sskrll /* opc8 cst4 r */ \ 332a6b7db3Sskrll {NAME, 1, OPC, 24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \ 342a6b7db3Sskrll /* opc8 i16 r */ \ 352a6b7db3Sskrll {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}}, \ 362a6b7db3Sskrll /* opc8 r r */ \ 372a6b7db3Sskrll {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} 382a6b7db3Sskrll 392a6b7db3Sskrll ARITH_BYTE_INST ("addub", 0x0), 402a6b7db3Sskrll ARITH_BYTE_INST ("addb", 0x1), 412a6b7db3Sskrll ARITH_BYTE_INST ("addcb", 0x2), 422a6b7db3Sskrll ARITH_BYTE_INST ("andb", 0x3), 432a6b7db3Sskrll ARITH_BYTE_INST ("cmpb", 0x4), 442a6b7db3Sskrll ARITH_BYTE_INST ("movb", 0x5), 452a6b7db3Sskrll ARITH_BYTE_INST ("orb", 0x6), 462a6b7db3Sskrll ARITH_BYTE_INST ("subb", 0x7), 472a6b7db3Sskrll ARITH_BYTE_INST ("subcb", 0x8), 482a6b7db3Sskrll ARITH_BYTE_INST ("xorb", 0x9), 492a6b7db3Sskrll ARITH_BYTE_INST ("mulb", 0xA), 502a6b7db3Sskrll 512a6b7db3Sskrll ARITH_BYTE_INST ("adduw", 0x10), 522a6b7db3Sskrll ARITH_BYTE_INST ("addw", 0x11), 532a6b7db3Sskrll ARITH_BYTE_INST ("addcw", 0x12), 542a6b7db3Sskrll ARITH_BYTE_INST ("andw", 0x13), 552a6b7db3Sskrll ARITH_BYTE_INST ("cmpw", 0x14), 562a6b7db3Sskrll ARITH_BYTE_INST ("movw", 0x15), 572a6b7db3Sskrll ARITH_BYTE_INST ("orw", 0x16), 582a6b7db3Sskrll ARITH_BYTE_INST ("subw", 0x17), 592a6b7db3Sskrll ARITH_BYTE_INST ("subcw", 0x18), 602a6b7db3Sskrll ARITH_BYTE_INST ("xorw", 0x19), 612a6b7db3Sskrll ARITH_BYTE_INST ("mulw", 0x1A), 622a6b7db3Sskrll 632a6b7db3Sskrll /* Create an arithmetic instruction - INST[d]. */ 642a6b7db3Sskrll #define ARITH_INST(NAME, OPC) \ 652a6b7db3Sskrll /* opc8 cst4 r */ \ 662a6b7db3Sskrll {NAME, 1, OPC, 24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \ 672a6b7db3Sskrll /* opc8 i16 r */ \ 682a6b7db3Sskrll {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0}, {regr,16}}}, \ 692a6b7db3Sskrll /* opc8 i32 r */ \ 702a6b7db3Sskrll {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0}, {regr,16}}}, \ 712a6b7db3Sskrll /* opc8 r r */ \ 722a6b7db3Sskrll {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}} 732a6b7db3Sskrll 742a6b7db3Sskrll ARITH_INST ("addud", 0x20), 752a6b7db3Sskrll ARITH_INST ("addd", 0x21), 762a6b7db3Sskrll ARITH_INST ("addcd", 0x22), 772a6b7db3Sskrll ARITH_INST ("andd", 0x23), 782a6b7db3Sskrll ARITH_INST ("cmpd", 0x24), 792a6b7db3Sskrll ARITH_INST ("movd", 0x25), 802a6b7db3Sskrll ARITH_INST ("ord", 0x26), 812a6b7db3Sskrll ARITH_INST ("subd", 0x27), 822a6b7db3Sskrll ARITH_INST ("subcd", 0x28), 832a6b7db3Sskrll ARITH_INST ("xord", 0x29), 842a6b7db3Sskrll ARITH_INST ("muld", 0x2A), 852a6b7db3Sskrll 862a6b7db3Sskrll /* Create a shift instruction. */ 872a6b7db3Sskrll #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \ 882a6b7db3Sskrll /* OPRD=ui3 -->> opc9 ui3 r */ \ 892a6b7db3Sskrll /* OPRD=ui4 -->> opc8 ui4 r */ \ 902a6b7db3Sskrll /* OPRD=ui5 -->> opc7 ui5 r */ \ 912a6b7db3Sskrll {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \ 922a6b7db3Sskrll /* opc8 r r */ \ 932a6b7db3Sskrll {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}} 942a6b7db3Sskrll 952a6b7db3Sskrll SHIFT_INST ("sllb", ui3, 0x1F8, 23, 0x4D), 962a6b7db3Sskrll SHIFT_INST ("srlb", ui3, 0x1F9, 23, 0x4E), 972a6b7db3Sskrll SHIFT_INST ("srab", ui3, 0x1FA, 23, 0x4F), 982a6b7db3Sskrll 992a6b7db3Sskrll SHIFT_INST ("sllw", ui4, 0xB6, 24, 0x5D), 1002a6b7db3Sskrll SHIFT_INST ("srlw", ui4, 0xB7, 24, 0x5E), 1012a6b7db3Sskrll SHIFT_INST ("sraw", ui4, 0xB8, 24, 0x5F), 1022a6b7db3Sskrll 1032a6b7db3Sskrll SHIFT_INST ("slld", ui5, 0x78, 25, 0x6D), 1042a6b7db3Sskrll SHIFT_INST ("srld", ui5, 0x79, 25, 0x6E), 1052a6b7db3Sskrll SHIFT_INST ("srad", ui5, 0x7A, 25, 0x6F), 1062a6b7db3Sskrll 1072a6b7db3Sskrll /* Create a conditional branch instruction. */ 1082a6b7db3Sskrll #define BRANCH_INST(NAME, OPC) \ 1092a6b7db3Sskrll /* opc4 c4 dispe9 */ \ 1102a6b7db3Sskrll {NAME, 1, OPC, 24, BRANCH_INS | RELAXABLE, {{dispe9,16}}}, \ 1112a6b7db3Sskrll /* opc4 c4 disps17 */ \ 1122a6b7db3Sskrll {NAME, 2, (OPC<<8)+0x7E, 16, BRANCH_INS | RELAXABLE, {{disps17,0}}}, \ 1132a6b7db3Sskrll /* opc4 c4 disps32 */ \ 1142a6b7db3Sskrll {NAME, 3, (OPC<<8)+0x7F, 16, BRANCH_INS | RELAXABLE, {{disps32,0}}} 1152a6b7db3Sskrll 1162a6b7db3Sskrll BRANCH_INST ("beq", 0x70), 1172a6b7db3Sskrll BRANCH_INST ("bne", 0x71), 1182a6b7db3Sskrll BRANCH_INST ("bcs", 0x72), 1192a6b7db3Sskrll BRANCH_INST ("bcc", 0x73), 1202a6b7db3Sskrll BRANCH_INST ("bhi", 0x74), 1212a6b7db3Sskrll BRANCH_INST ("bls", 0x75), 1222a6b7db3Sskrll BRANCH_INST ("bgt", 0x76), 1232a6b7db3Sskrll BRANCH_INST ("ble", 0x77), 1242a6b7db3Sskrll BRANCH_INST ("bfs", 0x78), 1252a6b7db3Sskrll BRANCH_INST ("bfc", 0x79), 1262a6b7db3Sskrll BRANCH_INST ("blo", 0x7A), 1272a6b7db3Sskrll BRANCH_INST ("bhs", 0x7B), 1282a6b7db3Sskrll BRANCH_INST ("blt", 0x7C), 1292a6b7db3Sskrll BRANCH_INST ("bge", 0x7D), 1302a6b7db3Sskrll BRANCH_INST ("br", 0x7E), 1312a6b7db3Sskrll 1322a6b7db3Sskrll /* Create a 'Branch if Equal to 0' instruction. */ 1332a6b7db3Sskrll #define BRANCH_NEQ_INST(NAME, OPC) \ 1342a6b7db3Sskrll /* opc8 dispu5 r */ \ 1352a6b7db3Sskrll {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {dispu5,20}}} 1362a6b7db3Sskrll 1372a6b7db3Sskrll BRANCH_NEQ_INST ("beq0b", 0xB0), 1382a6b7db3Sskrll BRANCH_NEQ_INST ("bne0b", 0xB1), 1392a6b7db3Sskrll BRANCH_NEQ_INST ("beq0w", 0xB2), 1402a6b7db3Sskrll BRANCH_NEQ_INST ("bne0w", 0xB3), 1412a6b7db3Sskrll BRANCH_NEQ_INST ("beq0d", 0xB4), 1422a6b7db3Sskrll BRANCH_NEQ_INST ("bne0d", 0xB5), 1432a6b7db3Sskrll 1442a6b7db3Sskrll /* Create instruction with no operands. */ 1452a6b7db3Sskrll #define NO_OP_INST(NAME, OPC) \ 1462a6b7db3Sskrll /* opc16 */ \ 1472a6b7db3Sskrll {NAME, 1, OPC, 16, 0, {{0, 0}}} 1482a6b7db3Sskrll 1492a6b7db3Sskrll NO_OP_INST ("nop", 0x3002), 1502a6b7db3Sskrll NO_OP_INST ("retx", 0x3003), 1512a6b7db3Sskrll NO_OP_INST ("di", 0x3004), 1522a6b7db3Sskrll NO_OP_INST ("ei", 0x3005), 1532a6b7db3Sskrll NO_OP_INST ("wait", 0x3006), 1542a6b7db3Sskrll NO_OP_INST ("eiwait", 0x3007), 1552a6b7db3Sskrll 1562a6b7db3Sskrll /* Create a 'Compare & Branch' instruction. */ 1572a6b7db3Sskrll #define CMPBR_INST(NAME, OPC1, OPC2, C4) \ 1582a6b7db3Sskrll /* opc12 r r c4 disps9 */ \ 1592a6b7db3Sskrll {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \ 1602a6b7db3Sskrll {{regr,16}, {regr,12}, {disps9,0}}}, \ 1612a6b7db3Sskrll /* opc12 r r c4 disps25 */ \ 1622a6b7db3Sskrll {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ 1632a6b7db3Sskrll {{regr,16}, {regr,12}, {disps25,0}}}, \ 1642a6b7db3Sskrll /* opc12 i4cst4 r c4 disps9 */ \ 1652a6b7db3Sskrll {NAME, 2, ((0x300+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ 1662a6b7db3Sskrll {{cst4,16}, {regr,12}, {disps9,0}}}, \ 1672a6b7db3Sskrll /* opc12 i4cst4 r c4 disps25 */ \ 1682a6b7db3Sskrll {NAME, 3, ((0x310+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ 1692a6b7db3Sskrll {{cst4,16}, {regr,12}, {disps25,0}}} 1702a6b7db3Sskrll 1712a6b7db3Sskrll CMPBR_INST ("cmpbeqb", 0x8, 0xC, 0x0), 1722a6b7db3Sskrll CMPBR_INST ("cmpbneb", 0x8, 0xC, 0x1), 1732a6b7db3Sskrll CMPBR_INST ("cmpbhib", 0x8, 0xC, 0x4), 1742a6b7db3Sskrll CMPBR_INST ("cmpblsb", 0x8, 0xC, 0x5), 1752a6b7db3Sskrll CMPBR_INST ("cmpbgtb", 0x8, 0xC, 0x6), 1762a6b7db3Sskrll CMPBR_INST ("cmpbleb", 0x8, 0xC, 0x7), 1772a6b7db3Sskrll CMPBR_INST ("cmpblob", 0x8, 0xC, 0xA), 1782a6b7db3Sskrll CMPBR_INST ("cmpbhsb", 0x8, 0xC, 0xB), 1792a6b7db3Sskrll CMPBR_INST ("cmpbltb", 0x8, 0xC, 0xC), 1802a6b7db3Sskrll CMPBR_INST ("cmpbgeb", 0x8, 0xC, 0xD), 1812a6b7db3Sskrll 1822a6b7db3Sskrll CMPBR_INST ("cmpbeqw", 0x9, 0xD, 0x0), 1832a6b7db3Sskrll CMPBR_INST ("cmpbnew", 0x9, 0xD, 0x1), 1842a6b7db3Sskrll CMPBR_INST ("cmpbhiw", 0x9, 0xD, 0x4), 1852a6b7db3Sskrll CMPBR_INST ("cmpblsw", 0x9, 0xD, 0x5), 1862a6b7db3Sskrll CMPBR_INST ("cmpbgtw", 0x9, 0xD, 0x6), 1872a6b7db3Sskrll CMPBR_INST ("cmpblew", 0x9, 0xD, 0x7), 1882a6b7db3Sskrll CMPBR_INST ("cmpblow", 0x9, 0xD, 0xA), 1892a6b7db3Sskrll CMPBR_INST ("cmpbhsw", 0x9, 0xD, 0xB), 1902a6b7db3Sskrll CMPBR_INST ("cmpbltw", 0x9, 0xD, 0xC), 1912a6b7db3Sskrll CMPBR_INST ("cmpbgew", 0x9, 0xD, 0xD), 1922a6b7db3Sskrll 1932a6b7db3Sskrll CMPBR_INST ("cmpbeqd", 0xA, 0xE, 0x0), 1942a6b7db3Sskrll CMPBR_INST ("cmpbned", 0xA, 0xE, 0x1), 1952a6b7db3Sskrll CMPBR_INST ("cmpbhid", 0xA, 0xE, 0x4), 1962a6b7db3Sskrll CMPBR_INST ("cmpblsd", 0xA, 0xE, 0x5), 1972a6b7db3Sskrll CMPBR_INST ("cmpbgtd", 0xA, 0xE, 0x6), 1982a6b7db3Sskrll CMPBR_INST ("cmpbled", 0xA, 0xE, 0x7), 1992a6b7db3Sskrll CMPBR_INST ("cmpblod", 0xA, 0xE, 0xA), 2002a6b7db3Sskrll CMPBR_INST ("cmpbhsd", 0xA, 0xE, 0xB), 2012a6b7db3Sskrll CMPBR_INST ("cmpbltd", 0xA, 0xE, 0xC), 2022a6b7db3Sskrll CMPBR_INST ("cmpbged", 0xA, 0xE, 0xD), 2032a6b7db3Sskrll 2042a6b7db3Sskrll /* Create an instruction using a single register operand. */ 2052a6b7db3Sskrll #define REG1_INST(NAME, OPC) \ 2062a6b7db3Sskrll /* opc8 c4 r */ \ 2072a6b7db3Sskrll {NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}} 2082a6b7db3Sskrll 2092a6b7db3Sskrll /* Same as REG1_INST, with additional FLAGS. */ 2102a6b7db3Sskrll #define REG1_FLAG_INST(NAME, OPC, FLAGS) \ 2112a6b7db3Sskrll /* opc8 c4 r */ \ 2122a6b7db3Sskrll {NAME, 1, OPC, 20, NO_TYPE_INS | FLAGS, {{regr,16}}} 2132a6b7db3Sskrll 2142a6b7db3Sskrll /* JCond instructions */ 2152a6b7db3Sskrll REG1_INST ("jeq", 0xBA0), 2162a6b7db3Sskrll REG1_INST ("jne", 0xBA1), 2172a6b7db3Sskrll REG1_INST ("jcs", 0xBA2), 2182a6b7db3Sskrll REG1_INST ("jcc", 0xBA3), 2192a6b7db3Sskrll REG1_INST ("jhi", 0xBA4), 2202a6b7db3Sskrll REG1_INST ("jls", 0xBA5), 2212a6b7db3Sskrll REG1_INST ("jgt", 0xBA6), 2222a6b7db3Sskrll REG1_INST ("jle", 0xBA7), 2232a6b7db3Sskrll REG1_INST ("jfs", 0xBA8), 2242a6b7db3Sskrll REG1_INST ("jfc", 0xBA9), 2252a6b7db3Sskrll REG1_INST ("jlo", 0xBAA), 2262a6b7db3Sskrll REG1_INST ("jhs", 0xBAB), 2272a6b7db3Sskrll REG1_INST ("jlt", 0xBAC), 2282a6b7db3Sskrll REG1_INST ("jge", 0xBAD), 2292a6b7db3Sskrll REG1_INST ("jump", 0xBAE), 2302a6b7db3Sskrll 2312a6b7db3Sskrll /* SCond instructions */ 2322a6b7db3Sskrll REG1_INST ("seq", 0xBB0), 2332a6b7db3Sskrll REG1_INST ("sne", 0xBB1), 2342a6b7db3Sskrll REG1_INST ("scs", 0xBB2), 2352a6b7db3Sskrll REG1_INST ("scc", 0xBB3), 2362a6b7db3Sskrll REG1_INST ("shi", 0xBB4), 2372a6b7db3Sskrll REG1_INST ("sls", 0xBB5), 2382a6b7db3Sskrll REG1_INST ("sgt", 0xBB6), 2392a6b7db3Sskrll REG1_INST ("sle", 0xBB7), 2402a6b7db3Sskrll REG1_INST ("sfs", 0xBB8), 2412a6b7db3Sskrll REG1_INST ("sfc", 0xBB9), 2422a6b7db3Sskrll REG1_INST ("slo", 0xBBA), 2432a6b7db3Sskrll REG1_INST ("shs", 0xBBB), 2442a6b7db3Sskrll REG1_INST ("slt", 0xBBC), 2452a6b7db3Sskrll REG1_INST ("sge", 0xBBD), 2462a6b7db3Sskrll 2472a6b7db3Sskrll /* Create an instruction using two register operands. */ 2482a6b7db3Sskrll #define REG2_INST(NAME, OPC) \ 2492a6b7db3Sskrll /* opc24 r r OR opc20 c4 r r */ \ 2502a6b7db3Sskrll {NAME, 2, 0x300800+OPC, 8, NO_TYPE_INS, {{regr,4}, {regr,0}}} 2512a6b7db3Sskrll 2522a6b7db3Sskrll /* MULTIPLY INSTRUCTIONS */ 2532a6b7db3Sskrll REG2_INST ("macsb", 0x40), 2542a6b7db3Sskrll REG2_INST ("macub", 0x41), 2552a6b7db3Sskrll REG2_INST ("macqb", 0x42), 2562a6b7db3Sskrll 2572a6b7db3Sskrll REG2_INST ("macsw", 0x50), 2582a6b7db3Sskrll REG2_INST ("macuw", 0x51), 2592a6b7db3Sskrll REG2_INST ("macqw", 0x52), 2602a6b7db3Sskrll 2612a6b7db3Sskrll REG2_INST ("macsd", 0x60), 2622a6b7db3Sskrll REG2_INST ("macud", 0x61), 2632a6b7db3Sskrll REG2_INST ("macqd", 0x62), 2642a6b7db3Sskrll 2652a6b7db3Sskrll REG2_INST ("mullsd", 0x65), 2662a6b7db3Sskrll REG2_INST ("mullud", 0x66), 2672a6b7db3Sskrll 2682a6b7db3Sskrll REG2_INST ("mulsbw", 0x3B), 2692a6b7db3Sskrll REG2_INST ("mulubw", 0x3C), 2702a6b7db3Sskrll REG2_INST ("mulswd", 0x3D), 2712a6b7db3Sskrll REG2_INST ("muluwd", 0x3E), 2722a6b7db3Sskrll 2732a6b7db3Sskrll /* SIGNEXTEND STUFF */ 2742a6b7db3Sskrll REG2_INST ("sextbw", 0x30), 2752a6b7db3Sskrll REG2_INST ("sextbd", 0x31), 2762a6b7db3Sskrll REG2_INST ("sextwd", 0x32), 2772a6b7db3Sskrll REG2_INST ("zextbw", 0x34), 2782a6b7db3Sskrll REG2_INST ("zextbd", 0x35), 2792a6b7db3Sskrll REG2_INST ("zextwd", 0x36), 2802a6b7db3Sskrll 2812a6b7db3Sskrll REG2_INST ("bswap", 0x3F), 2822a6b7db3Sskrll 2832a6b7db3Sskrll REG2_INST ("maxsb", 0x80), 2842a6b7db3Sskrll REG2_INST ("minsb", 0x81), 2852a6b7db3Sskrll REG2_INST ("maxub", 0x82), 2862a6b7db3Sskrll REG2_INST ("minub", 0x83), 2872a6b7db3Sskrll REG2_INST ("absb", 0x84), 2882a6b7db3Sskrll REG2_INST ("negb", 0x85), 2892a6b7db3Sskrll REG2_INST ("cntl0b", 0x86), 2902a6b7db3Sskrll REG2_INST ("cntl1b", 0x87), 2912a6b7db3Sskrll REG2_INST ("popcntb",0x88), 2922a6b7db3Sskrll REG2_INST ("rotlb", 0x89), 2932a6b7db3Sskrll REG2_INST ("rotrb", 0x8A), 2942a6b7db3Sskrll REG2_INST ("mulqb", 0x8B), 2952a6b7db3Sskrll REG2_INST ("addqb", 0x8C), 2962a6b7db3Sskrll REG2_INST ("subqb", 0x8D), 2972a6b7db3Sskrll REG2_INST ("cntlsb", 0x8E), 2982a6b7db3Sskrll 2992a6b7db3Sskrll REG2_INST ("maxsw", 0x90), 3002a6b7db3Sskrll REG2_INST ("minsw", 0x91), 3012a6b7db3Sskrll REG2_INST ("maxuw", 0x92), 3022a6b7db3Sskrll REG2_INST ("minuw", 0x93), 3032a6b7db3Sskrll REG2_INST ("absw", 0x94), 3042a6b7db3Sskrll REG2_INST ("negw", 0x95), 3052a6b7db3Sskrll REG2_INST ("cntl0w", 0x96), 3062a6b7db3Sskrll REG2_INST ("cntl1w", 0x97), 3072a6b7db3Sskrll REG2_INST ("popcntw",0x98), 3082a6b7db3Sskrll REG2_INST ("rotlw", 0x99), 3092a6b7db3Sskrll REG2_INST ("rotrw", 0x9A), 3102a6b7db3Sskrll REG2_INST ("mulqw", 0x9B), 3112a6b7db3Sskrll REG2_INST ("addqw", 0x9C), 3122a6b7db3Sskrll REG2_INST ("subqw", 0x9D), 3132a6b7db3Sskrll REG2_INST ("cntlsw", 0x9E), 3142a6b7db3Sskrll 3152a6b7db3Sskrll REG2_INST ("maxsd", 0xA0), 3162a6b7db3Sskrll REG2_INST ("minsd", 0xA1), 3172a6b7db3Sskrll REG2_INST ("maxud", 0xA2), 3182a6b7db3Sskrll REG2_INST ("minud", 0xA3), 3192a6b7db3Sskrll REG2_INST ("absd", 0xA4), 3202a6b7db3Sskrll REG2_INST ("negd", 0xA5), 3212a6b7db3Sskrll REG2_INST ("cntl0d", 0xA6), 3222a6b7db3Sskrll REG2_INST ("cntl1d", 0xA7), 3232a6b7db3Sskrll REG2_INST ("popcntd",0xA8), 3242a6b7db3Sskrll REG2_INST ("rotld", 0xA9), 3252a6b7db3Sskrll REG2_INST ("rotrd", 0xAA), 3262a6b7db3Sskrll REG2_INST ("mulqd", 0xAB), 3272a6b7db3Sskrll REG2_INST ("addqd", 0xAC), 3282a6b7db3Sskrll REG2_INST ("subqd", 0xAD), 3292a6b7db3Sskrll REG2_INST ("cntlsd", 0xAE), 3302a6b7db3Sskrll 3312a6b7db3Sskrll /* Conditional move instructions */ 3322a6b7db3Sskrll REG2_INST ("cmoveqd", 0x70), 3332a6b7db3Sskrll REG2_INST ("cmovned", 0x71), 3342a6b7db3Sskrll REG2_INST ("cmovcsd", 0x72), 3352a6b7db3Sskrll REG2_INST ("cmovccd", 0x73), 3362a6b7db3Sskrll REG2_INST ("cmovhid", 0x74), 3372a6b7db3Sskrll REG2_INST ("cmovlsd", 0x75), 3382a6b7db3Sskrll REG2_INST ("cmovgtd", 0x76), 3392a6b7db3Sskrll REG2_INST ("cmovled", 0x77), 3402a6b7db3Sskrll REG2_INST ("cmovfsd", 0x78), 3412a6b7db3Sskrll REG2_INST ("cmovfcd", 0x79), 3422a6b7db3Sskrll REG2_INST ("cmovlod", 0x7A), 3432a6b7db3Sskrll REG2_INST ("cmovhsd", 0x7B), 3442a6b7db3Sskrll REG2_INST ("cmovltd", 0x7C), 3452a6b7db3Sskrll REG2_INST ("cmovged", 0x7D), 3462a6b7db3Sskrll 3472a6b7db3Sskrll /* Load instructions (from memory to register). */ 3482a6b7db3Sskrll #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \ 3492a6b7db3Sskrll /* opc12 r abs16 */ \ 3502a6b7db3Sskrll {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 3512a6b7db3Sskrll {{abs16,0}, {regr,16}}}, \ 3522a6b7db3Sskrll /* opc12 r abs32 */ \ 3532a6b7db3Sskrll {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 3542a6b7db3Sskrll {{abs32,0}, {regr,16}}}, \ 3552a6b7db3Sskrll /* opc4 r rbase dispu[bwd]4 */ \ 3562a6b7db3Sskrll {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP | REVERSE_MATCH, \ 3572a6b7db3Sskrll {{rbase_dispu4,16}, {regr,24}}}, \ 3582a6b7db3Sskrll /* opc4 r rbase disps16 */ \ 3592a6b7db3Sskrll {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \ 3602a6b7db3Sskrll {{rbase_disps16,16}, {regr,24}}}, \ 3612a6b7db3Sskrll /* opc4 r rbase disps32 */ \ 3622a6b7db3Sskrll {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \ 3632a6b7db3Sskrll {{rbase_disps32,16}, {regr,24}}}, \ 3642a6b7db3Sskrll /* opc12 r rbase ridx scl2 disps6 */ \ 3652a6b7db3Sskrll {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 3662a6b7db3Sskrll {{rindex_disps6,0}, {regr,16}}}, \ 3672a6b7db3Sskrll /* opc12 r rbase ridx scl2 disps22 */ \ 3682a6b7db3Sskrll {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 3692a6b7db3Sskrll {{rindex_disps22,0}, {regr,16}}}, \ 3702a6b7db3Sskrll /* opc12 r rbase disps12 */ \ 3712a6b7db3Sskrll {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC | REVERSE_MATCH, \ 3722a6b7db3Sskrll {{rbase_disps12,12}, {regr,16}}} 3732a6b7db3Sskrll 3742a6b7db3Sskrll LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4), 3752a6b7db3Sskrll LD_REG_INST ("loadw", 0x1, 0x1, DISPUW4), 3762a6b7db3Sskrll LD_REG_INST ("loadd", 0x2, 0x2, DISPUD4), 3772a6b7db3Sskrll 3782a6b7db3Sskrll /* Store instructions (from Register to Memory). */ 3792a6b7db3Sskrll #define ST_REG_INST(NAME, OPC1, OPC2, DISP) \ 3802a6b7db3Sskrll /* opc12 r abs16 */ \ 3812a6b7db3Sskrll {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs16,0}}}, \ 3822a6b7db3Sskrll /* opc12 r abs32 */ \ 3832a6b7db3Sskrll {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs32,0}}}, \ 3842a6b7db3Sskrll /* opc4 r rbase dispu[bwd]4 */ \ 3852a6b7db3Sskrll {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP, \ 3862a6b7db3Sskrll {{regr,24}, {rbase_dispu4,16}}}, \ 3872a6b7db3Sskrll /* opc4 r rbase disps16 */ \ 3882a6b7db3Sskrll {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1, \ 3892a6b7db3Sskrll {{regr,24}, {rbase_disps16,16}}}, \ 3902a6b7db3Sskrll /* opc4 r rbase disps32 */ \ 3912a6b7db3Sskrll {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1, \ 3922a6b7db3Sskrll {{regr,24}, {rbase_disps32,16}}}, \ 3932a6b7db3Sskrll /* opc12 r rbase ridx scl2 disps6 */ \ 3942a6b7db3Sskrll {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS, \ 3952a6b7db3Sskrll {{regr,16}, {rindex_disps6,0}}}, \ 3962a6b7db3Sskrll /* opc12 r rbase ridx scl2 disps22 */ \ 3972a6b7db3Sskrll {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS, {{regr,16}, {rindex_disps22,0}}}, \ 3982a6b7db3Sskrll /* opc12 r rbase disps12 */ \ 3992a6b7db3Sskrll {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC, {{regr,16}, {rbase_disps12,12}}} 4002a6b7db3Sskrll 4012a6b7db3Sskrll /* Store instructions (Immediate to Memory). */ 4022a6b7db3Sskrll #define ST_I_INST(NAME, OPC) \ 4032a6b7db3Sskrll /* opc12 ui4 rbase disps12 */ \ 4042a6b7db3Sskrll {NAME, 2, 0x368+OPC, 20, LD_STOR_INS_INC, {{ui4,16}, {rbase_disps12,12}}}, \ 4052a6b7db3Sskrll /* opc12 ui4 abs16 */ \ 4062a6b7db3Sskrll {NAME, 2, 0x360+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs16,0}}}, \ 4072a6b7db3Sskrll /* opc12 ui4 abs32 */ \ 4082a6b7db3Sskrll {NAME, 3, 0x370+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs32,0}}}, \ 4092a6b7db3Sskrll /* opc12 ui4 rbase disps12 */ \ 4102a6b7db3Sskrll {NAME, 2, 0x364+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps12,12}}}, \ 4112a6b7db3Sskrll /* opc12 ui4 rbase disps28 */ \ 4122a6b7db3Sskrll {NAME, 3, 0x374+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps28,12}}}, \ 4132a6b7db3Sskrll /* opc12 ui4 rbase ridx scl2 disps6 */ \ 4142a6b7db3Sskrll {NAME, 2, 0x36C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps6,0}}}, \ 4152a6b7db3Sskrll /* opc12 ui4 rbase ridx scl2 disps22 */ \ 4162a6b7db3Sskrll {NAME, 3, 0x37C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps22,0}}} 4172a6b7db3Sskrll 4182a6b7db3Sskrll ST_REG_INST ("storb", 0x20, 0x4, DISPUB4), 4192a6b7db3Sskrll ST_I_INST ("storb", 0x0), 4202a6b7db3Sskrll 4212a6b7db3Sskrll ST_REG_INST ("storw", 0x21, 0x5, DISPUW4), 4222a6b7db3Sskrll ST_I_INST ("storw", 0x1), 4232a6b7db3Sskrll 4242a6b7db3Sskrll ST_REG_INST ("stord", 0x22, 0x6, DISPUD4), 4252a6b7db3Sskrll ST_I_INST ("stord", 0x2), 4262a6b7db3Sskrll 4272a6b7db3Sskrll /* Create a bit instruction. */ 4282a6b7db3Sskrll #define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \ 4292a6b7db3Sskrll /* OP=ui3 -->> opc13 ui3 */ \ 4302a6b7db3Sskrll /* OP=ui4 -->> opc12 ui4 */ \ 4312a6b7db3Sskrll /* OP=ui5 -->> opc11 ui5 */ \ 4322a6b7db3Sskrll \ 4332a6b7db3Sskrll /* opcNN iN abs16 */ \ 4342a6b7db3Sskrll {NAME, 2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}}, \ 4352a6b7db3Sskrll /* opcNN iN abs32 */ \ 4362a6b7db3Sskrll {NAME, 3, OPC1+1*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs32,0}}}, \ 4372a6b7db3Sskrll /* opcNN iN rbase */ \ 4382a6b7db3Sskrll {NAME, 1, OPC2, SHIFT+4, CSTBIT_INS, {{OP,20}, {rbase,16}}}, \ 4392a6b7db3Sskrll /* opcNN iN rbase disps12 */ \ 4402a6b7db3Sskrll {NAME, 2, OPC1+2*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps12,12}}}, \ 4412a6b7db3Sskrll /* opcNN iN rbase disps28 */ \ 4422a6b7db3Sskrll {NAME, 3, OPC1+3*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps28,12}}}, \ 4432a6b7db3Sskrll /* opcNN iN rbase ridx scl2 disps6 */ \ 4442a6b7db3Sskrll {NAME, 2, OPC1+4*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps6,0}}}, \ 4452a6b7db3Sskrll /* opcNN iN rbase ridx scl2 disps22 */ \ 4462a6b7db3Sskrll {NAME, 3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps22,0}}} 4472a6b7db3Sskrll 4482a6b7db3Sskrll CSTBIT_INST ("cbitb", ui3, 0x700, 0x20, 19, 0x1FC), 4492a6b7db3Sskrll CSTBIT_INST ("cbitw", ui4, 0x382, 0x10, 20, 0xBD), 4502a6b7db3Sskrll CSTBIT_INST ("cbitd", ui5, 0x1C3, 0x8, 21, 0x7B), 4512a6b7db3Sskrll {"cbitd", 2, 0x300838, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, 4522a6b7db3Sskrll {"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, 4532a6b7db3Sskrll 4542a6b7db3Sskrll CSTBIT_INST ("sbitb", ui3, 0x701, 0x20, 19, 0x1FD), 4552a6b7db3Sskrll CSTBIT_INST ("sbitw", ui4, 0x383, 0x10, 20, 0xBE), 4562a6b7db3Sskrll CSTBIT_INST ("sbitd", ui5, 0x1C4, 0x8, 21, 0x7C), 4572a6b7db3Sskrll {"sbitd", 2, 0x300839, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, 4582a6b7db3Sskrll {"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, 4592a6b7db3Sskrll 4602a6b7db3Sskrll CSTBIT_INST ("tbitb", ui3, 0x702, 0x20, 19, 0x1FE), 4612a6b7db3Sskrll CSTBIT_INST ("tbitw", ui4, 0x384, 0x10, 20, 0xBF), 4622a6b7db3Sskrll CSTBIT_INST ("tbitd", ui5, 0x1C5, 0x8, 21, 0x7D), 4632a6b7db3Sskrll {"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, 4642a6b7db3Sskrll {"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, 4652a6b7db3Sskrll 4662a6b7db3Sskrll /* Instructions including a register list (opcode is represented as a mask). */ 4672a6b7db3Sskrll #define REGLIST_INST(NAME, OPC, FLAG) \ 4682a6b7db3Sskrll /* opc12 r mask16 */ \ 4692a6b7db3Sskrll {NAME, 2, OPC, 20, NO_TYPE_INS | REG_LIST | FLAG, {{regr,16}, {ui16,0}}} 4702a6b7db3Sskrll 4712a6b7db3Sskrll REG1_INST ("getrfid", 0xFF9), 4722a6b7db3Sskrll REG1_INST ("setrfid", 0xFFA), 4732a6b7db3Sskrll 4742a6b7db3Sskrll REGLIST_INST ("push", 0x346, NO_RPTR), 4752a6b7db3Sskrll REG1_FLAG_INST ("push", 0xFFB, NO_SP), 4762a6b7db3Sskrll REGLIST_INST ("pushx", 0x347, NO_RPTR), 4772a6b7db3Sskrll 4782a6b7db3Sskrll REGLIST_INST ("pop", 0x324, NO_RPTR), 4792a6b7db3Sskrll REG1_FLAG_INST ("pop", 0xFFC, NO_SP), 4802a6b7db3Sskrll REGLIST_INST ("popx", 0x327, NO_RPTR), 4812a6b7db3Sskrll 4822a6b7db3Sskrll REGLIST_INST ("popret", 0x326, NO_RPTR), 4832a6b7db3Sskrll REG1_FLAG_INST ("popret",0xFFD,NO_SP), 4842a6b7db3Sskrll 4852a6b7db3Sskrll REGLIST_INST ("loadm", 0x324, NO_RPTR), 4862a6b7db3Sskrll REGLIST_INST ("loadma", 0x325, USER_REG), 4872a6b7db3Sskrll 4882a6b7db3Sskrll REGLIST_INST ("storm", 0x344, NO_RPTR), 4892a6b7db3Sskrll REGLIST_INST ("storma", 0x345, USER_REG), 4902a6b7db3Sskrll 4912a6b7db3Sskrll /* Create a branch instruction. */ 4922a6b7db3Sskrll #define BR_INST(NAME, OPC1, OPC2, INS_TYPE) \ 4932a6b7db3Sskrll /* opc12 r disps17 */ \ 4942a6b7db3Sskrll {NAME, 2, OPC1, 20, INS_TYPE | RELAXABLE, {{regr,16}, {disps17,0}}}, \ 4952a6b7db3Sskrll /* opc12 r disps32 */ \ 4962a6b7db3Sskrll {NAME, 3, OPC2, 20, INS_TYPE | RELAXABLE, {{regr,16}, {disps32,0}}} 4972a6b7db3Sskrll 4982a6b7db3Sskrll BR_INST ("bal", 0x307, 0x317, NO_TYPE_INS), 4992a6b7db3Sskrll 5002a6b7db3Sskrll /* Decrement and Branch instructions. */ 5012a6b7db3Sskrll BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS), 5022a6b7db3Sskrll BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS), 5032a6b7db3Sskrll BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS), 5042a6b7db3Sskrll 5052a6b7db3Sskrll /* Jump and link instructions. */ 5062a6b7db3Sskrll REG1_INST ("jal", 0xFF8), 5072a6b7db3Sskrll REG2_INST ("jal", 0x37), 5082a6b7db3Sskrll REG2_INST ("jalid", 0x33), 5092a6b7db3Sskrll 5102a6b7db3Sskrll /* Create a CO-processor instruction. */ 5112a6b7db3Sskrll /* esc12 c4 ui16 */ 5122a6b7db3Sskrll {"cpi", 2, 0x301, 20, COP_REG_INS, {{ui4,16}, {ui16,0}}}, 5132a6b7db3Sskrll /* esc12 c4 ui16 ui16 */ 5142a6b7db3Sskrll {"cpi", 3, 0x311, 20, COP_REG_INS, {{ui4,16}, {ui16,0}, {ui16,16}}}, 5152a6b7db3Sskrll 5162a6b7db3Sskrll #define COP_INST(NAME, OPC, TYPE, REG1, REG2) \ 5172a6b7db3Sskrll /* opc12 c4 opc8 REG1 REG2 */ \ 5182a6b7db3Sskrll {NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,4}, {REG2,0}}} 5192a6b7db3Sskrll /* A reverse form of the above macro. */ 5202a6b7db3Sskrll #define REV_COP_INST(NAME, OPC, TYPE, REG1, REG2) \ 5212a6b7db3Sskrll /* opc12 c4 opc8 REG2 REG1 */ \ 5222a6b7db3Sskrll {NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,0}, {REG2,4}}} 5232a6b7db3Sskrll 5242a6b7db3Sskrll COP_INST ("mtcr", 0, COP_REG_INS, regr, copregr), 5252a6b7db3Sskrll COP_INST ("mfcr", 1, COP_REG_INS, copregr, regr), 5262a6b7db3Sskrll COP_INST ("mtcsr", 2, COPS_REG_INS, regr, copsregr), 5272a6b7db3Sskrll COP_INST ("mfcsr", 3, COPS_REG_INS, copsregr, regr), 5282a6b7db3Sskrll COP_INST ("ldcr", 4, COP_REG_INS, regr, copregr), 5292a6b7db3Sskrll REV_COP_INST ("stcr", 5, COP_REG_INS, copregr, regr), 5302a6b7db3Sskrll COP_INST ("ldcsr", 6, COPS_REG_INS, regr, copsregr), 5312a6b7db3Sskrll REV_COP_INST ("stcsr", 7, COPS_REG_INS, copsregr, regr), 5322a6b7db3Sskrll 5332a6b7db3Sskrll /* Create a memory-related CO-processor instruction. */ 5342a6b7db3Sskrll #define COPMEM_INST(NAME, OPC, TYPE) \ 5352a6b7db3Sskrll /* opc12 c4 opc12 r mask16 */ \ 5362a6b7db3Sskrll {NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, \ 5372a6b7db3Sskrll {{ui4,16}, {regr,0}, {ui16,16}}} 5382a6b7db3Sskrll 5392a6b7db3Sskrll COPMEM_INST("loadmcr", 0, COP_REG_INS), 5402a6b7db3Sskrll COPMEM_INST("stormcr", 1, COP_REG_INS), 5412a6b7db3Sskrll COPMEM_INST("loadmcsr", 2, COPS_REG_INS), 5422a6b7db3Sskrll COPMEM_INST("stormcsr", 3, COPS_REG_INS), 5432a6b7db3Sskrll 5442a6b7db3Sskrll /* CO-processor extensions. */ 5452a6b7db3Sskrll /* opc12 c4 opc4 ui4 disps9 */ 5462a6b7db3Sskrll {"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, 5472a6b7db3Sskrll {{ui4,8}, {ui4,16}, {disps9,0}}}, 5482a6b7db3Sskrll /* opc12 c4 opc4 ui4 disps25 */ 5492a6b7db3Sskrll {"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, 5502a6b7db3Sskrll {{ui4,8}, {ui4,16}, {disps25,0}}}, 5512a6b7db3Sskrll /* opc12 c4 opc4 cpdo r r */ 5522a6b7db3Sskrll {"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, 5532a6b7db3Sskrll {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}}}, 5542a6b7db3Sskrll /* opc12 c4 opc4 cpdo r r cpdo16 */ 5552a6b7db3Sskrll {"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, 5562a6b7db3Sskrll {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}, {ui16,16}}}, 5572a6b7db3Sskrll /* esc16 r procreg */ 5582a6b7db3Sskrll {"mtpr", 2, 0x3009, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, 5592a6b7db3Sskrll /* esc16 procreg r */ 5602a6b7db3Sskrll {"mfpr", 2, 0x300A, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, 5612a6b7db3Sskrll 5622a6b7db3Sskrll /* Miscellaneous. */ 5632a6b7db3Sskrll /* opc12 ui4 */ 5642a6b7db3Sskrll {"excp", 1, 0xFFF, 20, NO_TYPE_INS, {{ui4,16}}}, 5652a6b7db3Sskrll /* opc28 ui4 */ 5662a6b7db3Sskrll {"cinv", 2, 0x3010000, 4, NO_TYPE_INS, {{ui4,0}}}, 5672a6b7db3Sskrll 5682a6b7db3Sskrll /* opc9 ui5 ui5 ui5 r r */ 5692a6b7db3Sskrll {"ram", 2, 0x7C, 23, NO_TYPE_INS, 5702a6b7db3Sskrll {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, 5712a6b7db3Sskrll {"rim", 2, 0x7D, 23, NO_TYPE_INS, 5722a6b7db3Sskrll {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, 5732a6b7db3Sskrll 5742a6b7db3Sskrll /* opc9 ui3 r */ 5752a6b7db3Sskrll {"rotb", 1, 0x1FB, 23, NO_TYPE_INS, {{ui3,20}, {regr,16}}}, 5762a6b7db3Sskrll /* opc8 ui4 r */ 5772a6b7db3Sskrll {"rotw", 1, 0xB9, 24, NO_TYPE_INS, {{ui4,20}, {regr,16}}}, 5782a6b7db3Sskrll /* opc23 ui5 r */ 5792a6b7db3Sskrll {"rotd", 2, 0x180478, 9, NO_TYPE_INS, {{ui5,4}, {regr,0}}}, 5802a6b7db3Sskrll 5812a6b7db3Sskrll {NULL, 0, 0, 0, 0, {{0, 0}}} 5822a6b7db3Sskrll }; 5832a6b7db3Sskrll 5842a6b7db3Sskrll const int crx_num_opcodes = ARRAY_SIZE (crx_instruction); 5852a6b7db3Sskrll 5862a6b7db3Sskrll /* Macro to build a reg_entry, which have an opcode image : 5872a6b7db3Sskrll For example : 5882a6b7db3Sskrll REG(u4, 0x84, CRX_U_REGTYPE) 5892a6b7db3Sskrll is interpreted as : 5905ba6b03cSchristos {"u4", u4, 0x84, CRX_U_REGTYPE} 5915ba6b03cSchristos The union initializer (second member) always refers to the first 5925ba6b03cSchristos member of the union, so cast NAME to that type to avoid possible 5935ba6b03cSchristos compiler warnings when used for non-CRX_R_REGTYPE cases. */ 5945ba6b03cSchristos #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} 5952a6b7db3Sskrll 5962a6b7db3Sskrll const reg_entry crx_regtab[] = 5972a6b7db3Sskrll { 5982a6b7db3Sskrll /* Build a general purpose register r<N>. */ 5992a6b7db3Sskrll #define REG_R(N) REG(CONCAT2(r,N), N, CRX_R_REGTYPE) 6002a6b7db3Sskrll 6012a6b7db3Sskrll REG_R(0), REG_R(1), REG_R(2), REG_R(3), 6022a6b7db3Sskrll REG_R(4), REG_R(5), REG_R(6), REG_R(7), 6032a6b7db3Sskrll REG_R(8), REG_R(9), REG_R(10), REG_R(11), 6042a6b7db3Sskrll REG_R(12), REG_R(13), REG_R(14), REG_R(15), 6052a6b7db3Sskrll REG(ra, 0xe, CRX_R_REGTYPE), 6062a6b7db3Sskrll REG(sp, 0xf, CRX_R_REGTYPE), 6072a6b7db3Sskrll 6082a6b7db3Sskrll /* Build a user register u<N>. */ 6092a6b7db3Sskrll #define REG_U(N) REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE) 6102a6b7db3Sskrll 6112a6b7db3Sskrll REG_U(0), REG_U(1), REG_U(2), REG_U(3), 6122a6b7db3Sskrll REG_U(4), REG_U(5), REG_U(6), REG_U(7), 6132a6b7db3Sskrll REG_U(8), REG_U(9), REG_U(10), REG_U(11), 6142a6b7db3Sskrll REG_U(12), REG_U(13), REG_U(14), REG_U(15), 6152a6b7db3Sskrll REG(ura, 0x8e, CRX_U_REGTYPE), 6162a6b7db3Sskrll REG(usp, 0x8f, CRX_U_REGTYPE), 6172a6b7db3Sskrll 6182a6b7db3Sskrll /* Build a configuration register. */ 6192a6b7db3Sskrll #define REG_CFG(NAME, N) REG(NAME, N, CRX_CFG_REGTYPE) 6202a6b7db3Sskrll 6212a6b7db3Sskrll REG_CFG(hi, 0x10), 6222a6b7db3Sskrll REG_CFG(lo, 0x11), 6232a6b7db3Sskrll REG_CFG(uhi, 0x90), 6242a6b7db3Sskrll REG_CFG(ulo, 0x91), 6252a6b7db3Sskrll REG_CFG(psr, 0x12), 6262a6b7db3Sskrll REG_CFG(intbase, 0x13), 6272a6b7db3Sskrll REG_CFG(isp, 0x14), 6282a6b7db3Sskrll REG_CFG(cfg, 0x15), 6292a6b7db3Sskrll REG_CFG(cpcfg, 0x16), 6302a6b7db3Sskrll REG_CFG(cen, 0x17) 6312a6b7db3Sskrll }; 6322a6b7db3Sskrll 6332a6b7db3Sskrll const int crx_num_regs = ARRAY_SIZE (crx_regtab); 6342a6b7db3Sskrll 6352a6b7db3Sskrll const reg_entry crx_copregtab[] = 6362a6b7db3Sskrll { 6372a6b7db3Sskrll /* Build a Coprocessor register c<N>. */ 6382a6b7db3Sskrll #define REG_C(N) REG(CONCAT2(c,N), N, CRX_C_REGTYPE) 6392a6b7db3Sskrll 6402a6b7db3Sskrll REG_C(0), REG_C(1), REG_C(2), REG_C(3), 6412a6b7db3Sskrll REG_C(4), REG_C(5), REG_C(6), REG_C(7), 6422a6b7db3Sskrll REG_C(8), REG_C(9), REG_C(10), REG_C(11), 6432a6b7db3Sskrll REG_C(12), REG_C(13), REG_C(14), REG_C(15), 6442a6b7db3Sskrll 6452a6b7db3Sskrll /* Build a Coprocessor Special register cs<N>. */ 6462a6b7db3Sskrll #define REG_CS(N) REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE) 6472a6b7db3Sskrll 6482a6b7db3Sskrll REG_CS(0), REG_CS(1), REG_CS(2), REG_CS(3), 6492a6b7db3Sskrll REG_CS(4), REG_CS(5), REG_CS(6), REG_CS(7), 6502a6b7db3Sskrll REG_CS(8), REG_CS(9), REG_CS(10), REG_CS(11), 6512a6b7db3Sskrll REG_CS(12), REG_CS(13), REG_CS(14), REG_CS(15) 6522a6b7db3Sskrll }; 6532a6b7db3Sskrll 6542a6b7db3Sskrll const int crx_num_copregs = ARRAY_SIZE (crx_copregtab); 6552a6b7db3Sskrll 6562a6b7db3Sskrll /* CRX operands table. */ 6572a6b7db3Sskrll const operand_entry crx_optab[] = 6582a6b7db3Sskrll { 6592a6b7db3Sskrll /* Index 0 is dummy, so we can count the instruction's operands. */ 6602a6b7db3Sskrll {0, nullargs, 0}, /* dummy */ 6612a6b7db3Sskrll {4, arg_ic, OP_CST4}, /* cst4 */ 6622a6b7db3Sskrll {16, arg_ic, OP_SIGNED}, /* i16 */ 6632a6b7db3Sskrll {32, arg_ic, OP_SIGNED}, /* i32 */ 6642a6b7db3Sskrll {3, arg_ic, OP_UNSIGNED}, /* ui3 */ 6652a6b7db3Sskrll {4, arg_ic, OP_UNSIGNED}, /* ui4 */ 6662a6b7db3Sskrll {5, arg_ic, OP_UNSIGNED}, /* ui5 */ 6672a6b7db3Sskrll {16, arg_ic, OP_UNSIGNED}, /* ui16 */ 6682a6b7db3Sskrll {8, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps9 */ 6692a6b7db3Sskrll {16, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps17 */ 6702a6b7db3Sskrll {24, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps25 */ 6712a6b7db3Sskrll {32, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps32 */ 6722a6b7db3Sskrll {4, arg_c, OP_EVEN|OP_SHIFT_DEC|OP_UNSIGNED}, /* dispu5 */ 6732a6b7db3Sskrll {8, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED|OP_ESC}, /* dispe9 */ 6742a6b7db3Sskrll {16, arg_c, OP_UNSIGNED|OP_UPPER_64KB}, /* abs16 */ 6752a6b7db3Sskrll {32, arg_c, OP_UNSIGNED}, /* abs32 */ 6762a6b7db3Sskrll {4, arg_rbase, 0}, /* rbase */ 6772a6b7db3Sskrll {4, arg_cr, OP_DISPU4}, /* rbase_dispu4 */ 6782a6b7db3Sskrll {12, arg_cr, OP_SIGNED}, /* rbase_disps12 */ 6792a6b7db3Sskrll {16, arg_cr, OP_SIGNED}, /* rbase_disps16 */ 6802a6b7db3Sskrll {28, arg_cr, OP_SIGNED}, /* rbase_disps28 */ 6812a6b7db3Sskrll {32, arg_cr, OP_SIGNED}, /* rbase_disps32 */ 6822a6b7db3Sskrll {6, arg_idxr, OP_SIGNED}, /* rindex_disps6 */ 6832a6b7db3Sskrll {22, arg_idxr, OP_SIGNED}, /* rindex_disps22 */ 6842a6b7db3Sskrll {4, arg_r, 0}, /* regr */ 6852a6b7db3Sskrll {8, arg_r, 0}, /* regr8 */ 6862a6b7db3Sskrll {4, arg_copr, 0}, /* copregr */ 6872a6b7db3Sskrll {4, arg_copsr, 0} /* copsregr */ 6882a6b7db3Sskrll }; 6892a6b7db3Sskrll 6902a6b7db3Sskrll /* CRX traps/interrupts. */ 6912a6b7db3Sskrll const trap_entry crx_traps[] = 6922a6b7db3Sskrll { 6932a6b7db3Sskrll {"nmi", 1}, {"svc", 5}, {"dvz", 6}, {"flg", 7}, 6942a6b7db3Sskrll {"bpt", 8}, {"und", 10}, {"prv", 11}, {"iberr", 12} 6952a6b7db3Sskrll }; 6962a6b7db3Sskrll 6972a6b7db3Sskrll const int crx_num_traps = ARRAY_SIZE (crx_traps); 6982a6b7db3Sskrll 6992a6b7db3Sskrll /* cst4 operand mapping: 7002a6b7db3Sskrll The value in entry <N> is mapped to the value <N> 7012a6b7db3Sskrll Value Binary mapping 7022a6b7db3Sskrll cst4_map[N] -->> N 7032a6b7db3Sskrll 7042a6b7db3Sskrll Example (for N=5): 7052a6b7db3Sskrll 7062a6b7db3Sskrll cst4_map[5]=-4 -->> 5 */ 70798f124a6Schristos const int crx_cst4_map[] = 7082a6b7db3Sskrll { 7092a6b7db3Sskrll 0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48 7102a6b7db3Sskrll }; 7112a6b7db3Sskrll 71298f124a6Schristos const int crx_cst4_maps = ARRAY_SIZE (crx_cst4_map); 7132a6b7db3Sskrll 7142a6b7db3Sskrll /* CRX instructions that don't have arguments. */ 71598f124a6Schristos const char* crx_no_op_insn[] = 7162a6b7db3Sskrll { 7172a6b7db3Sskrll "di", "ei", "eiwait", "nop", "retx", "wait", NULL 7182a6b7db3Sskrll }; 719