1*0bfacb9bSmrg /* Copyright (C) 2016-2020 Free Software Foundation, Inc. 2760c2415Smrg 3760c2415Smrg This file is free software; you can redistribute it and/or modify it under 4760c2415Smrg the terms of the GNU General Public License as published by the Free 5760c2415Smrg Software Foundation; either version 3 of the License, or (at your option) 6760c2415Smrg any later version. 7760c2415Smrg 8760c2415Smrg This file is distributed in the hope that it will be useful, but WITHOUT 9760c2415Smrg ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10760c2415Smrg FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11760c2415Smrg for more details. 12760c2415Smrg 13760c2415Smrg You should have received a copy of the GNU General Public License 14760c2415Smrg along with GCC; see the file COPYING3. If not see 15760c2415Smrg <http://www.gnu.org/licenses/>. */ 16760c2415Smrg 17760c2415Smrg #ifndef GCN_OPTS_H 18760c2415Smrg #define GCN_OPTS_H 19760c2415Smrg 20760c2415Smrg /* Which processor to generate code or schedule for. */ 21760c2415Smrg enum processor_type 22760c2415Smrg { 23760c2415Smrg PROCESSOR_FIJI, 24760c2415Smrg PROCESSOR_VEGA 25760c2415Smrg }; 26760c2415Smrg 27760c2415Smrg /* Set in gcn_option_override. */ 28760c2415Smrg extern int gcn_isa; 29760c2415Smrg 30760c2415Smrg #define TARGET_GCN3 (gcn_isa == 3) 31760c2415Smrg #define TARGET_GCN3_PLUS (gcn_isa >= 3) 32760c2415Smrg #define TARGET_GCN5 (gcn_isa == 5) 33760c2415Smrg #define TARGET_GCN5_PLUS (gcn_isa >= 5) 34760c2415Smrg 35760c2415Smrg #endif 36