110d565efSmrg;; DFA-based pipeline descriptions for MIPS Technologies 24K core. 210d565efSmrg;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com) 310d565efSmrg;; and David Ung (davidu@mips.com) 410d565efSmrg;; 510d565efSmrg;; The 24kf2_1 is a single-issue processor with a half-clocked fpu. 610d565efSmrg;; The 24kf1_1 is 24k with 1:1 clocked fpu. 710d565efSmrg;; 810d565efSmrg;; References: 910d565efSmrg;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04." 1010d565efSmrg;; 11*ec02198aSmrg;; Copyright (C) 2005-2020 Free Software Foundation, Inc. 1210d565efSmrg;; 1310d565efSmrg;; This file is part of GCC. 1410d565efSmrg;; 1510d565efSmrg;; GCC is free software; you can redistribute it and/or modify it 1610d565efSmrg;; under the terms of the GNU General Public License as published 1710d565efSmrg;; by the Free Software Foundation; either version 3, or (at your 1810d565efSmrg;; option) any later version. 1910d565efSmrg 2010d565efSmrg;; GCC is distributed in the hope that it will be useful, but WITHOUT 2110d565efSmrg;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 2210d565efSmrg;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 2310d565efSmrg;; License for more details. 2410d565efSmrg 2510d565efSmrg;; You should have received a copy of the GNU General Public License 2610d565efSmrg;; along with GCC; see the file COPYING3. If not see 2710d565efSmrg;; <http://www.gnu.org/licenses/>. 2810d565efSmrg 2910d565efSmrg(define_automaton "r24k_cpu, r24k_mdu, r24k_fpu") 3010d565efSmrg 3110d565efSmrg;; Integer execution unit. 3210d565efSmrg(define_cpu_unit "r24k_iss" "r24k_cpu") 3310d565efSmrg(define_cpu_unit "r24k_ixu_arith" "r24k_cpu") 3410d565efSmrg(define_cpu_unit "r24k_mul3a" "r24k_mdu") 3510d565efSmrg(define_cpu_unit "r24k_mul3b" "r24k_mdu") 3610d565efSmrg(define_cpu_unit "r24k_mul3c" "r24k_mdu") 3710d565efSmrg 3810d565efSmrg;; -------------------------------------------------------------- 3910d565efSmrg;; Producers 4010d565efSmrg;; -------------------------------------------------------------- 4110d565efSmrg 4210d565efSmrg;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs 4310d565efSmrg(define_insn_reservation "r24k_int_load" 2 4410d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 4510d565efSmrg (eq_attr "type" "load")) 4610d565efSmrg "r24k_iss+r24k_ixu_arith") 4710d565efSmrg 4810d565efSmrg 4910d565efSmrg;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz, 5010d565efSmrg;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll, 5110d565efSmrg;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh, 5210d565efSmrg;; xor, xori 5310d565efSmrg;; (movn/movz is not matched, we'll need to split condmov to 5410d565efSmrg;; differentiate between integer/float moves) 5510d565efSmrg(define_insn_reservation "r24k_int_arith" 1 5610d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 5710d565efSmrg (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt")) 5810d565efSmrg "r24k_iss+r24k_ixu_arith") 5910d565efSmrg 6010d565efSmrg 6110d565efSmrg;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx 6210d565efSmrg;; 3a. jr/jalr consumer 6310d565efSmrg(define_insn_reservation "r24k_int_jump" 1 6410d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 6510d565efSmrg (eq_attr "type" "call,jump")) 6610d565efSmrg "r24k_iss+r24k_ixu_arith") 6710d565efSmrg 6810d565efSmrg;; 3b. branch consumer 6910d565efSmrg(define_insn_reservation "r24k_int_branch" 1 7010d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 7110d565efSmrg (eq_attr "type" "branch")) 7210d565efSmrg "r24k_iss+r24k_ixu_arith") 7310d565efSmrg 7410d565efSmrg 7510d565efSmrg;; 4. MDU: fully pipelined multiplier 7610d565efSmrg;; mult - delivers result to hi/lo in 1 cycle (pipelined) 7710d565efSmrg(define_insn_reservation "r24k_int_mult" 1 7810d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 7910d565efSmrg (eq_attr "type" "imul")) 8010d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 8110d565efSmrg 8210d565efSmrg;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined) 8310d565efSmrg(define_insn_reservation "r24k_int_madd" 1 8410d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 8510d565efSmrg (eq_attr "type" "imadd")) 8610d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 8710d565efSmrg 8810d565efSmrg;; mul - delivers result to gpr in 5 cycles 8910d565efSmrg(define_insn_reservation "r24k_int_mul3" 5 9010d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 9110d565efSmrg (eq_attr "type" "imul3")) 9210d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5") 9310d565efSmrg 9410d565efSmrg;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles 9510d565efSmrg(define_insn_reservation "r24k_int_mfhilo" 5 9610d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 9710d565efSmrg (eq_attr "type" "mfhi,mflo")) 9810d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 9910d565efSmrg 10010d565efSmrg;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass 10110d565efSmrg(define_insn_reservation "r24k_int_mthilo" 1 10210d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 10310d565efSmrg (eq_attr "type" "mthi,mtlo")) 10410d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 10510d565efSmrg 10610d565efSmrg;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and 10710d565efSmrg;; 8bit, but is tricky to identify. 10810d565efSmrg(define_insn_reservation "r24k_int_div" 36 10910d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 11010d565efSmrg (eq_attr "type" "idiv")) 11110d565efSmrg "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36") 11210d565efSmrg 11310d565efSmrg 11410d565efSmrg;; 5. Cop: cfc1, di, ei, mfc0, mtc0 11510d565efSmrg;; (Disabled until we add proper cop0 support) 11610d565efSmrg;;(define_insn_reservation "r24k_int_cop" 3 11710d565efSmrg;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 11810d565efSmrg;; (eq_attr "type" "cop0")) 11910d565efSmrg;; "r24k_iss+r24k_ixu_arith") 12010d565efSmrg 12110d565efSmrg 12210d565efSmrg;; 6. Store 12310d565efSmrg(define_insn_reservation "r24k_int_store" 1 12410d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 12510d565efSmrg (eq_attr "type" "store")) 12610d565efSmrg "r24k_iss+r24k_ixu_arith") 12710d565efSmrg 12810d565efSmrg 12910d565efSmrg;; 7. Multiple instructions 13010d565efSmrg(define_insn_reservation "r24k_int_multi" 1 13110d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 13210d565efSmrg (eq_attr "type" "multi")) 13310d565efSmrg "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)") 13410d565efSmrg 13510d565efSmrg 13610d565efSmrg;; 8. Unknowns - Currently these include blockage, consttable and alignment 13710d565efSmrg;; rtls. They do not really affect scheduling latency, (blockage affects 13810d565efSmrg;; scheduling via log links, but not used here). 13910d565efSmrg(define_insn_reservation "r24k_int_unknown" 0 14010d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 14110d565efSmrg (eq_attr "type" "unknown,atomic,syncloop")) 14210d565efSmrg "r24k_iss") 14310d565efSmrg 14410d565efSmrg 14510d565efSmrg;; 9. Prefetch 14610d565efSmrg(define_insn_reservation "r24k_int_prefetch" 1 14710d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 14810d565efSmrg (eq_attr "type" "prefetch,prefetchx")) 14910d565efSmrg "r24k_iss+r24k_ixu_arith") 15010d565efSmrg 15110d565efSmrg 15210d565efSmrg;; -------------------------------------------------------------- 15310d565efSmrg;; Bypass to Consumer 15410d565efSmrg;; -------------------------------------------------------------- 15510d565efSmrg 15610d565efSmrg;; load->next use : 2 cycles (Default) 15710d565efSmrg;; load->load base: 3 cycles 15810d565efSmrg;; load->store base: 3 cycles 15910d565efSmrg;; load->prefetch: 3 cycles 16010d565efSmrg(define_bypass 3 "r24k_int_load" "r24k_int_load") 16110d565efSmrg(define_bypass 3 "r24k_int_load" "r24k_int_store" "!mips_store_data_bypass_p") 16210d565efSmrg(define_bypass 3 "r24k_int_load" "r24k_int_prefetch") 16310d565efSmrg 16410d565efSmrg;; arith->next use : 1 cycles (Default) 16510d565efSmrg;; arith->load base: 2 cycles 16610d565efSmrg;; arith->store base: 2 cycles 16710d565efSmrg;; arith->prefetch: 2 cycles 16810d565efSmrg(define_bypass 2 "r24k_int_arith" "r24k_int_load") 16910d565efSmrg(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!mips_store_data_bypass_p") 17010d565efSmrg(define_bypass 2 "r24k_int_arith" "r24k_int_prefetch") 17110d565efSmrg 17210d565efSmrg;; mul3->next use : 5 cycles (default) 17310d565efSmrg;; mul3->l/s base : 6 cycles 17410d565efSmrg;; mul3->prefetch : 6 cycles 17510d565efSmrg(define_bypass 6 "r24k_int_mul3" "r24k_int_load") 17610d565efSmrg(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!mips_store_data_bypass_p") 17710d565efSmrg(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch") 17810d565efSmrg 17910d565efSmrg;; mul3->madd/msub : 1 cycle 18010d565efSmrg(define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p") 18110d565efSmrg 18210d565efSmrg;; mfhilo->next use : 5 cycles (default) 18310d565efSmrg;; mfhilo->l/s base : 6 cycles 18410d565efSmrg;; mfhilo->prefetch : 6 cycles 18510d565efSmrg;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo) 18610d565efSmrg(define_bypass 6 "r24k_int_mfhilo" "r24k_int_load") 18710d565efSmrg(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" 18810d565efSmrg "!mips_store_data_bypass_p") 18910d565efSmrg(define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch") 19010d565efSmrg(define_bypass 2 "r24k_int_mthilo" "r24k_int_madd") 19110d565efSmrg 19210d565efSmrg;; cop->next use : 3 cycles (Default) 19310d565efSmrg;; cop->l/s base : 4 cycles 19410d565efSmrg;; (define_bypass 4 "r24k_int_cop" "r24k_int_load") 19510d565efSmrg;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" 19610d565efSmrg;; "!mips_store_data_bypass_p") 19710d565efSmrg 19810d565efSmrg;; multi->next use : 1 cycles (Default) 19910d565efSmrg;; multi->l/s base : 2 cycles 20010d565efSmrg;; multi->prefetch : 2 cycles 20110d565efSmrg(define_bypass 2 "r24k_int_multi" "r24k_int_load") 20210d565efSmrg(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!mips_store_data_bypass_p") 20310d565efSmrg(define_bypass 2 "r24k_int_multi" "r24k_int_prefetch") 20410d565efSmrg 20510d565efSmrg 20610d565efSmrg;; -------------------------------------------------------------- 20710d565efSmrg;; DSP instructions 20810d565efSmrg;; -------------------------------------------------------------- 20910d565efSmrg 21010d565efSmrg;; absq, addq, addsc, addu, addwc, bitrev, cmp, cmpgu, cmpu, insv, modsub, 21110d565efSmrg;; packrl, pick, preceq, preceu, precequ, precrq, precrqu, raddu, rddsp, repl, 21210d565efSmrg;; replv, shll, shllv, shra, shrav, shrl, shrlv, subq, subu, wrdsp 21310d565efSmrg(define_insn_reservation "r24k_dsp_alu" 2 21410d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 21510d565efSmrg (eq_attr "type" "dspalu,dspalusat")) 21610d565efSmrg "r24k_iss+r24k_ixu_arith") 21710d565efSmrg 21810d565efSmrg;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq 21910d565efSmrg(define_insn_reservation "r24k_dsp_mac" 1 22010d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 22110d565efSmrg (eq_attr "type" "dspmac")) 22210d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 22310d565efSmrg 22410d565efSmrg;; dpaq_sa, dpsq_sa, maq_sa 22510d565efSmrg(define_insn_reservation "r24k_dsp_mac_sat" 1 22610d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 22710d565efSmrg (eq_attr "type" "dspmacsat")) 22810d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 22910d565efSmrg 23010d565efSmrg;; extp, extpdp, extpdpv, extpv, extr, extrv 23110d565efSmrg(define_insn_reservation "r24k_dsp_acc_ext" 5 23210d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 23310d565efSmrg (eq_attr "type" "accext")) 23410d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 23510d565efSmrg 23610d565efSmrg;; mthlip, shilo, shilov 23710d565efSmrg(define_insn_reservation "r24k_dsp_acc_mod" 1 23810d565efSmrg (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 23910d565efSmrg (eq_attr "type" "accmod")) 24010d565efSmrg "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 24110d565efSmrg 24210d565efSmrg 24310d565efSmrg;; mult/madd->dsp_acc_ext : 4 cycles 24410d565efSmrg;; mult/madd->dsp_acc_mod : 4 cycles 24510d565efSmrg(define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_ext") 24610d565efSmrg(define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_mod") 24710d565efSmrg 24810d565efSmrg;; mthilo->dsp_acc_ext : 4 cycles 24910d565efSmrg;; mthilo->dsp_acc_ext : 4 cycles 25010d565efSmrg(define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_ext") 25110d565efSmrg(define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_mod") 25210d565efSmrg 25310d565efSmrg;; dsp_mac->next use : 1 cycles (default) 25410d565efSmrg;; dsp_mac->dsp_acc_ext : 4 cycles 25510d565efSmrg;; dsp_mac->dsp_acc_mod : 4 cycles 25610d565efSmrg(define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_ext") 25710d565efSmrg(define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_mod") 25810d565efSmrg 25910d565efSmrg;; dsp_mac_sat->next use : 1 cycles (default) 26010d565efSmrg;; dsp_mac_sat->mult/madd : 2 cycles 26110d565efSmrg;; dsp_mac_sat->dsp_mac : 2 cycles 26210d565efSmrg;; dsp_mac_sat->dsp_mac_sat : 2 cycles 26310d565efSmrg;; dsp_mac_sat->dsp_acc_ext : 4 cycles 26410d565efSmrg;; dsp_mac_sat->dsp_acc_mod : 4 cycles 26510d565efSmrg(define_bypass 2 "r24k_dsp_mac_sat" "r24k_int_mult") 26610d565efSmrg(define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac") 26710d565efSmrg(define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac_sat") 26810d565efSmrg(define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_ext") 26910d565efSmrg(define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_mod") 27010d565efSmrg 27110d565efSmrg;; dsp_acc_ext->next use : 5 cycles (default) 27210d565efSmrg;; dsp_acc_ext->l/s base : 6 cycles 27310d565efSmrg;; dsp_acc_ext->prefetch : 6 cycles 27410d565efSmrg(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_load") 27510d565efSmrg(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_store" 27610d565efSmrg "!mips_store_data_bypass_p") 27710d565efSmrg(define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_prefetch") 27810d565efSmrg 27910d565efSmrg;; dsp_acc_mod->next use : 1 cycles (default) 28010d565efSmrg;; dsp_acc_mod->mult/madd : 2 cycles 28110d565efSmrg;; dsp_acc_mod->dsp_mac : 2 cycles 28210d565efSmrg;; dsp_acc_mod->dsp_mac_sat : 2 cycles 28310d565efSmrg;; dsp_acc_mod->dsp_acc_ext : 4 cycles 28410d565efSmrg;; dsp_acc_mod->dsp_acc_mod : 4 cycles 28510d565efSmrg(define_bypass 2 "r24k_dsp_acc_mod" "r24k_int_mult") 28610d565efSmrg(define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac") 28710d565efSmrg(define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac_sat") 28810d565efSmrg(define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_ext") 28910d565efSmrg(define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_mod") 29010d565efSmrg 29110d565efSmrg;; dspalu->next use : 2 cycles (default) 29210d565efSmrg;; dspalu->l/s base : 3 cycles 29310d565efSmrg;; dspalu->prefetch : 3 cycles 29410d565efSmrg;; some pairs of dspalu (addsc/addwc, cmp/pick, wrdsp/insv) : 1 cycle 29510d565efSmrg(define_bypass 3 "r24k_dsp_alu" "r24k_int_load") 29610d565efSmrg(define_bypass 3 "r24k_dsp_alu" "r24k_int_store" "!mips_store_data_bypass_p") 29710d565efSmrg(define_bypass 3 "r24k_dsp_alu" "r24k_int_prefetch") 29810d565efSmrg(define_bypass 1 "r24k_dsp_alu" "r24k_dsp_alu" "mips_dspalu_bypass_p") 29910d565efSmrg 30010d565efSmrg 30110d565efSmrg;; -------------------------------------------------------------- 30210d565efSmrg;; Floating Point Instructions 30310d565efSmrg;; -------------------------------------------------------------- 30410d565efSmrg 30510d565efSmrg(define_cpu_unit "r24k_fpu_arith" "r24k_fpu") 30610d565efSmrg 30710d565efSmrg;; The 24k is a single issue cpu, and the fpu runs at half clock speed, 30810d565efSmrg;; so each fpu instruction ties up the shared instruction scheduler for 30910d565efSmrg;; 1 cycle, and the fpu scheduler for 2 cycles. 31010d565efSmrg;; 31110d565efSmrg;; These timings are therefore twice the values in the 24K manual, 31210d565efSmrg;; which are quoted in fpu clocks. 31310d565efSmrg;; 31410d565efSmrg;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use 31510d565efSmrg;; the unscaled timings 31610d565efSmrg 31710d565efSmrg(define_reservation "r24kf2_1_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)") 31810d565efSmrg 31910d565efSmrg;; fadd, fabs, fneg 32010d565efSmrg(define_insn_reservation "r24kf2_1_fadd" 8 32110d565efSmrg (and (eq_attr "cpu" "24kf2_1") 32210d565efSmrg (eq_attr "type" "fadd,fabs,fneg")) 32310d565efSmrg "r24kf2_1_fpu_iss") 32410d565efSmrg 32510d565efSmrg;; fmove, fcmove 32610d565efSmrg(define_insn_reservation "r24kf2_1_fmove" 8 32710d565efSmrg (and (eq_attr "cpu" "24kf2_1") 32810d565efSmrg (eq_attr "type" "fmove,condmove")) 32910d565efSmrg "r24kf2_1_fpu_iss") 33010d565efSmrg 33110d565efSmrg;; fload 33210d565efSmrg(define_insn_reservation "r24kf2_1_fload" 6 33310d565efSmrg (and (eq_attr "cpu" "24kf2_1") 33410d565efSmrg (eq_attr "type" "fpload,fpidxload")) 33510d565efSmrg "r24kf2_1_fpu_iss") 33610d565efSmrg 33710d565efSmrg;; fstore 33810d565efSmrg(define_insn_reservation "r24kf2_1_fstore" 2 33910d565efSmrg (and (eq_attr "cpu" "24kf2_1") 34010d565efSmrg (eq_attr "type" "fpstore")) 34110d565efSmrg "r24kf2_1_fpu_iss") 34210d565efSmrg 34310d565efSmrg;; fmul, fmadd 34410d565efSmrg(define_insn_reservation "r24kf2_1_fmul_sf" 8 34510d565efSmrg (and (eq_attr "cpu" "24kf2_1") 34610d565efSmrg (and (eq_attr "type" "fmul,fmadd") 34710d565efSmrg (eq_attr "mode" "SF"))) 34810d565efSmrg "r24kf2_1_fpu_iss") 34910d565efSmrg 35010d565efSmrg(define_insn_reservation "r24kf2_1_fmul_df" 10 35110d565efSmrg (and (eq_attr "cpu" "24kf2_1") 35210d565efSmrg (and (eq_attr "type" "fmul,fmadd") 35310d565efSmrg (eq_attr "mode" "DF"))) 35410d565efSmrg "r24kf2_1_fpu_iss,(r24k_fpu_arith*2)") 35510d565efSmrg 35610d565efSmrg 35710d565efSmrg;; fdiv, fsqrt, frsqrt 35810d565efSmrg(define_insn_reservation "r24kf2_1_fdiv_sf" 34 35910d565efSmrg (and (eq_attr "cpu" "24kf2_1") 36010d565efSmrg (and (eq_attr "type" "fdiv,fsqrt,frsqrt") 36110d565efSmrg (eq_attr "mode" "SF"))) 36210d565efSmrg "r24kf2_1_fpu_iss,(r24k_fpu_arith*26)") 36310d565efSmrg 36410d565efSmrg(define_insn_reservation "r24kf2_1_fdiv_df" 64 36510d565efSmrg (and (eq_attr "cpu" "24kf2_1") 36610d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 36710d565efSmrg (eq_attr "mode" "DF"))) 36810d565efSmrg "r24kf2_1_fpu_iss,(r24k_fpu_arith*56)") 36910d565efSmrg 37010d565efSmrg;; frsqrt 37110d565efSmrg(define_insn_reservation "r24kf2_1_frsqrt_df" 70 37210d565efSmrg (and (eq_attr "cpu" "24kf2_1") 37310d565efSmrg (and (eq_attr "type" "frsqrt") 37410d565efSmrg (eq_attr "mode" "DF"))) 37510d565efSmrg "r24kf2_1_fpu_iss,(r24k_fpu_arith*60)") 37610d565efSmrg 37710d565efSmrg;; fcmp 37810d565efSmrg(define_insn_reservation "r24kf2_1_fcmp" 4 37910d565efSmrg (and (eq_attr "cpu" "24kf2_1") 38010d565efSmrg (eq_attr "type" "fcmp")) 38110d565efSmrg "r24kf2_1_fpu_iss") 38210d565efSmrg 38310d565efSmrg;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition) 38410d565efSmrg(define_bypass 2 "r24kf2_1_fcmp" "r24kf2_1_fmove") 38510d565efSmrg 38610d565efSmrg;; fcvt (cvt.d.s, cvt.[sd].[wl]) 38710d565efSmrg(define_insn_reservation "r24kf2_1_fcvt_i2f_s2d" 8 38810d565efSmrg (and (eq_attr "cpu" "24kf2_1") 38910d565efSmrg (and (eq_attr "type" "fcvt") 39010d565efSmrg (eq_attr "cnv_mode" "I2S,I2D,S2D"))) 39110d565efSmrg "r24kf2_1_fpu_iss") 39210d565efSmrg 39310d565efSmrg;; fcvt (cvt.s.d) 39410d565efSmrg(define_insn_reservation "r24kf2_1_fcvt_s2d" 12 39510d565efSmrg (and (eq_attr "cpu" "24kf2_1") 39610d565efSmrg (and (eq_attr "type" "fcvt") 39710d565efSmrg (eq_attr "cnv_mode" "D2S"))) 39810d565efSmrg "r24kf2_1_fpu_iss") 39910d565efSmrg 40010d565efSmrg;; fcvt (cvt.[wl].[sd], etc) 40110d565efSmrg(define_insn_reservation "r24kf2_1_fcvt_f2i" 10 40210d565efSmrg (and (eq_attr "cpu" "24kf2_1") 40310d565efSmrg (and (eq_attr "type" "fcvt") 40410d565efSmrg (eq_attr "cnv_mode" "S2I,D2I"))) 40510d565efSmrg "r24kf2_1_fpu_iss") 40610d565efSmrg 40710d565efSmrg;; fxfer (mfc1, mfhc1, mtc1, mthc1) 40810d565efSmrg(define_insn_reservation "r24kf2_1_fxfer" 4 40910d565efSmrg (and (eq_attr "cpu" "24kf2_1") 41010d565efSmrg (eq_attr "type" "mfc,mtc")) 41110d565efSmrg "r24kf2_1_fpu_iss") 41210d565efSmrg 41310d565efSmrg;; -------------------------------------------------------------- 41410d565efSmrg;; Bypass to Consumer 41510d565efSmrg;; -------------------------------------------------------------- 41610d565efSmrg;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles 41710d565efSmrg;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles 41810d565efSmrg(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load") 41910d565efSmrg(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" 42010d565efSmrg "!mips_store_data_bypass_p") 42110d565efSmrg(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch") 42210d565efSmrg 42310d565efSmrg;; r24kf2_1_fxfer->l/s base : 5 cycles 42410d565efSmrg;; r24kf2_1_fxfer->prefetch : 5 cycles 42510d565efSmrg(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load") 42610d565efSmrg(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p") 42710d565efSmrg(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch") 42810d565efSmrg 42910d565efSmrg;; -------------------------------------------------------------- 43010d565efSmrg;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use 43110d565efSmrg;; the unscaled timings 43210d565efSmrg;; -------------------------------------------------------------- 43310d565efSmrg 43410d565efSmrg(define_reservation "r24kf1_1_fpu_iss" "r24k_iss+r24k_fpu_arith") 43510d565efSmrg 43610d565efSmrg;; fadd, fabs, fneg 43710d565efSmrg(define_insn_reservation "r24kf1_1_fadd" 4 43810d565efSmrg (and (eq_attr "cpu" "24kf1_1") 43910d565efSmrg (eq_attr "type" "fadd,fabs,fneg")) 44010d565efSmrg "r24kf1_1_fpu_iss") 44110d565efSmrg 44210d565efSmrg;; fmove, fcmove 44310d565efSmrg(define_insn_reservation "r24kf1_1_fmove" 4 44410d565efSmrg (and (eq_attr "cpu" "24kf1_1") 44510d565efSmrg (eq_attr "type" "fmove,condmove")) 44610d565efSmrg "r24kf1_1_fpu_iss") 44710d565efSmrg 44810d565efSmrg;; fload 44910d565efSmrg(define_insn_reservation "r24kf1_1_fload" 3 45010d565efSmrg (and (eq_attr "cpu" "24kf1_1") 45110d565efSmrg (eq_attr "type" "fpload,fpidxload")) 45210d565efSmrg "r24kf1_1_fpu_iss") 45310d565efSmrg 45410d565efSmrg;; fstore 45510d565efSmrg(define_insn_reservation "r24kf1_1_fstore" 1 45610d565efSmrg (and (eq_attr "cpu" "24kf1_1") 45710d565efSmrg (eq_attr "type" "fpstore")) 45810d565efSmrg "r24kf1_1_fpu_iss") 45910d565efSmrg 46010d565efSmrg;; fmul, fmadd 46110d565efSmrg(define_insn_reservation "r24kf1_1_fmul_sf" 4 46210d565efSmrg (and (eq_attr "cpu" "24kf1_1") 46310d565efSmrg (and (eq_attr "type" "fmul,fmadd") 46410d565efSmrg (eq_attr "mode" "SF"))) 46510d565efSmrg "r24kf1_1_fpu_iss") 46610d565efSmrg 46710d565efSmrg(define_insn_reservation "r24kf1_1_fmul_df" 5 46810d565efSmrg (and (eq_attr "cpu" "24kf1_1") 46910d565efSmrg (and (eq_attr "type" "fmul,fmadd") 47010d565efSmrg (eq_attr "mode" "DF"))) 47110d565efSmrg "r24kf1_1_fpu_iss,r24k_fpu_arith") 47210d565efSmrg 47310d565efSmrg 47410d565efSmrg;; fdiv, fsqrt, frsqrt 47510d565efSmrg(define_insn_reservation "r24kf1_1_fdiv_sf" 17 47610d565efSmrg (and (eq_attr "cpu" "24kf1_1") 47710d565efSmrg (and (eq_attr "type" "fdiv,fsqrt,frsqrt") 47810d565efSmrg (eq_attr "mode" "SF"))) 47910d565efSmrg "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)") 48010d565efSmrg 48110d565efSmrg(define_insn_reservation "r24kf1_1_fdiv_df" 32 48210d565efSmrg (and (eq_attr "cpu" "24kf1_1") 48310d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 48410d565efSmrg (eq_attr "mode" "DF"))) 48510d565efSmrg "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)") 48610d565efSmrg 48710d565efSmrg;; frsqrt 48810d565efSmrg(define_insn_reservation "r24kf1_1_frsqrt_df" 35 48910d565efSmrg (and (eq_attr "cpu" "24kf1_1") 49010d565efSmrg (and (eq_attr "type" "frsqrt") 49110d565efSmrg (eq_attr "mode" "DF"))) 49210d565efSmrg "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)") 49310d565efSmrg 49410d565efSmrg;; fcmp 49510d565efSmrg(define_insn_reservation "r24kf1_1_fcmp" 2 49610d565efSmrg (and (eq_attr "cpu" "24kf1_1") 49710d565efSmrg (eq_attr "type" "fcmp")) 49810d565efSmrg "r24kf1_1_fpu_iss") 49910d565efSmrg 50010d565efSmrg;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition) 50110d565efSmrg(define_bypass 1 "r24kf1_1_fcmp" "r24kf1_1_fmove") 50210d565efSmrg 50310d565efSmrg;; fcvt (cvt.d.s, cvt.[sd].[wl]) 50410d565efSmrg(define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4 50510d565efSmrg (and (eq_attr "cpu" "24kf1_1") 50610d565efSmrg (and (eq_attr "type" "fcvt") 50710d565efSmrg (eq_attr "cnv_mode" "I2S,I2D,S2D"))) 50810d565efSmrg "r24kf1_1_fpu_iss") 50910d565efSmrg 51010d565efSmrg;; fcvt (cvt.s.d) 51110d565efSmrg(define_insn_reservation "r24kf1_1_fcvt_s2d" 6 51210d565efSmrg (and (eq_attr "cpu" "24kf1_1") 51310d565efSmrg (and (eq_attr "type" "fcvt") 51410d565efSmrg (eq_attr "cnv_mode" "D2S"))) 51510d565efSmrg "r24kf1_1_fpu_iss") 51610d565efSmrg 51710d565efSmrg;; fcvt (cvt.[wl].[sd], etc) 51810d565efSmrg(define_insn_reservation "r24kf1_1_fcvt_f2i" 5 51910d565efSmrg (and (eq_attr "cpu" "24kf1_1") 52010d565efSmrg (and (eq_attr "type" "fcvt") 52110d565efSmrg (eq_attr "cnv_mode" "S2I,D2I"))) 52210d565efSmrg "r24kf1_1_fpu_iss") 52310d565efSmrg 52410d565efSmrg;; fxfer (mfc1, mfhc1, mtc1, mthc1) 52510d565efSmrg(define_insn_reservation "r24kf1_1_fxfer" 2 52610d565efSmrg (and (eq_attr "cpu" "24kf1_1") 52710d565efSmrg (eq_attr "type" "mfc,mtc")) 52810d565efSmrg "r24kf1_1_fpu_iss") 52910d565efSmrg 53010d565efSmrg;; -------------------------------------------------------------- 53110d565efSmrg;; Bypass to Consumer 53210d565efSmrg;; -------------------------------------------------------------- 53310d565efSmrg;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles 53410d565efSmrg;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles 53510d565efSmrg(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load") 53610d565efSmrg(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" 53710d565efSmrg "!mips_store_data_bypass_p") 53810d565efSmrg(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch") 53910d565efSmrg 54010d565efSmrg;; r24kf1_1_fxfer->l/s base : 3 cycles 54110d565efSmrg;; r24kf1_1_fxfer->prefetch : 3 cycles 54210d565efSmrg(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load") 54310d565efSmrg(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p") 54410d565efSmrg(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch") 54510d565efSmrg 546