110d565efSmrg;; DFA-based pipeline description for MIPS32 model 74k. 210d565efSmrg;; Contributed by MIPS Technologies and CodeSourcery. 310d565efSmrg;; 410d565efSmrg;; Reference: 510d565efSmrg;; "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006" 610d565efSmrg;; "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006" 710d565efSmrg;; 8*ec02198aSmrg;; Copyright (C) 2007-2020 Free Software Foundation, Inc. 910d565efSmrg;; 1010d565efSmrg;; This file is part of GCC. 1110d565efSmrg;; 1210d565efSmrg;; GCC is free software; you can redistribute it and/or modify it 1310d565efSmrg;; under the terms of the GNU General Public License as published 1410d565efSmrg;; by the Free Software Foundation; either version 3, or (at your 1510d565efSmrg;; option) any later version. 1610d565efSmrg 1710d565efSmrg;; GCC is distributed in the hope that it will be useful, but WITHOUT 1810d565efSmrg;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 1910d565efSmrg;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 2010d565efSmrg;; License for more details. 2110d565efSmrg 2210d565efSmrg;; You should have received a copy of the GNU General Public License 2310d565efSmrg;; along with GCC; see the file COPYING3. If not see 2410d565efSmrg;; <http://www.gnu.org/licenses/>. 2510d565efSmrg 2610d565efSmrg(define_automaton "r74k_mdu_pipe, r74k_alu_pipe, r74k_agen_pipe, r74k_fpu") 2710d565efSmrg(define_cpu_unit "r74k_mul" "r74k_mdu_pipe") 2810d565efSmrg(define_cpu_unit "r74k_alu" "r74k_alu_pipe") 2910d565efSmrg(define_cpu_unit "r74k_agen" "r74k_agen_pipe") 3010d565efSmrg(define_cpu_unit "r74k_fpu_arith" "r74k_fpu") 3110d565efSmrg(define_cpu_unit "r74k_fpu_ldst" "r74k_fpu") 3210d565efSmrg 3310d565efSmrg;; -------------------------------------------------------------- 3410d565efSmrg;; Producers 3510d565efSmrg;; -------------------------------------------------------------- 3610d565efSmrg 3710d565efSmrg;; ALU: Logicals/Arithmetics 3810d565efSmrg;; - Logicals, move (addu/addiu with rt = 0), Set less than, 3910d565efSmrg;; sign extend - 1 cycle 4010d565efSmrg(define_insn_reservation "r74k_int_logical" 1 4110d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 4210d565efSmrg (eq_attr "type" "logical,move,signext,slt")) 4310d565efSmrg "r74k_alu") 4410d565efSmrg 4510d565efSmrg;; - Arithmetics - 2 cycles 4610d565efSmrg(define_insn_reservation "r74k_int_arith" 2 4710d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 4810d565efSmrg (eq_attr "type" "arith,const,shift,clz")) 4910d565efSmrg "r74k_alu") 5010d565efSmrg 5110d565efSmrg(define_insn_reservation "r74k_int_nop" 0 5210d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 5310d565efSmrg (eq_attr "type" "nop")) 5410d565efSmrg "nothing") 5510d565efSmrg 5610d565efSmrg(define_insn_reservation "r74k_int_cmove" 4 5710d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 5810d565efSmrg (eq_attr "type" "condmove")) 5910d565efSmrg "r74k_agen*2") 6010d565efSmrg 6110d565efSmrg;; MDU: fully pipelined multiplier 6210d565efSmrg;; mult - delivers result to hi/lo in 4 cycle (pipelined) 6310d565efSmrg(define_insn_reservation "r74k_int_mult" 4 6410d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 6510d565efSmrg (eq_attr "type" "imul")) 6610d565efSmrg "r74k_alu+r74k_mul") 6710d565efSmrg 6810d565efSmrg;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined) 6910d565efSmrg(define_insn_reservation "r74k_int_madd" 4 7010d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 7110d565efSmrg (eq_attr "type" "imadd")) 7210d565efSmrg "r74k_alu+r74k_mul") 7310d565efSmrg 7410d565efSmrg;; mul - delivers result to general register in 7 cycles 7510d565efSmrg(define_insn_reservation "r74k_int_mul3" 7 7610d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 7710d565efSmrg (eq_attr "type" "imul3")) 7810d565efSmrg "r74k_alu+r74k_mul") 7910d565efSmrg 8010d565efSmrg;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles 8110d565efSmrg(define_insn_reservation "r74k_int_mfhilo" 7 8210d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 8310d565efSmrg (eq_attr "type" "mfhi,mflo")) 8410d565efSmrg "r74k_alu+r74k_mul") 8510d565efSmrg 8610d565efSmrg;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass 8710d565efSmrg(define_insn_reservation "r74k_int_mthilo" 7 8810d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 8910d565efSmrg (eq_attr "type" "mthi,mtlo")) 9010d565efSmrg "r74k_alu+r74k_mul") 9110d565efSmrg 9210d565efSmrg;; div - default to 50 cycles for 32bit operands. Faster for 8 bit, 9310d565efSmrg;; but is tricky to identify. 9410d565efSmrg(define_insn_reservation "r74k_int_div" 50 9510d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 9610d565efSmrg (eq_attr "type" "idiv")) 9710d565efSmrg "r74k_alu+r74k_mul*50") 9810d565efSmrg 9910d565efSmrg;; call 10010d565efSmrg(define_insn_reservation "r74k_int_call" 1 10110d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 10210d565efSmrg (eq_attr "type" "call")) 10310d565efSmrg "r74k_agen") 10410d565efSmrg 10510d565efSmrg;; branch/jump 10610d565efSmrg(define_insn_reservation "r74k_int_jump" 1 10710d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 10810d565efSmrg (eq_attr "type" "branch,jump")) 10910d565efSmrg "r74k_agen") 11010d565efSmrg 11110d565efSmrg;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs 11210d565efSmrg;; prefetch: prefetch, prefetchx 11310d565efSmrg(define_insn_reservation "r74k_int_load" 3 11410d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 11510d565efSmrg (eq_attr "type" "load,prefetch,prefetchx")) 11610d565efSmrg "r74k_agen") 11710d565efSmrg 11810d565efSmrg;; stores 11910d565efSmrg(define_insn_reservation "r74k_int_store" 1 12010d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 12110d565efSmrg (eq_attr "type" "store")) 12210d565efSmrg "r74k_agen") 12310d565efSmrg 12410d565efSmrg 12510d565efSmrg;; Unknowns - Currently these include blockage, consttable and alignment 12610d565efSmrg;; rtls. They do not really affect scheduling latency, (blockage 12710d565efSmrg;; affects scheduling via log links, but not used here). 12810d565efSmrg;; 12910d565efSmrg(define_insn_reservation "r74k_unknown" 1 13010d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 13110d565efSmrg (eq_attr "type" "unknown,atomic,syncloop")) 13210d565efSmrg "r74k_alu") 13310d565efSmrg 13410d565efSmrg(define_insn_reservation "r74k_multi" 10 13510d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 13610d565efSmrg (eq_attr "type" "multi")) 13710d565efSmrg "(r74k_alu+r74k_agen)*10") 13810d565efSmrg 13910d565efSmrg;; -------------------------------------------------------------- 14010d565efSmrg;; Bypass to Consumer 14110d565efSmrg;; -------------------------------------------------------------- 14210d565efSmrg 14310d565efSmrg;; load->next use : 3 cycles (Default) 14410d565efSmrg;; load->load base: 4 cycles 14510d565efSmrg;; load->store base: 4 cycles 14610d565efSmrg(define_bypass 4 "r74k_int_load" "r74k_int_load") 14710d565efSmrg(define_bypass 4 "r74k_int_load" "r74k_int_store" "!mips_store_data_bypass_p") 14810d565efSmrg 14910d565efSmrg;; logical/move/slt/signext->next use : 1 cycles (Default) 15010d565efSmrg;; logical/move/slt/signext->load base: 2 cycles 15110d565efSmrg;; logical/move/slt/signext->store base: 2 cycles 15210d565efSmrg(define_bypass 2 "r74k_int_logical" "r74k_int_load") 15310d565efSmrg(define_bypass 2 "r74k_int_logical" "r74k_int_store" 15410d565efSmrg "!mips_store_data_bypass_p") 15510d565efSmrg 15610d565efSmrg;; arith->next use : 2 cycles (Default) 15710d565efSmrg;; arith->load base: 3 cycles 15810d565efSmrg;; arith->store base: 3 cycles 15910d565efSmrg(define_bypass 3 "r74k_int_arith" "r74k_int_load") 16010d565efSmrg(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!mips_store_data_bypass_p") 16110d565efSmrg 16210d565efSmrg;; cmove->next use : 4 cycles (Default) 16310d565efSmrg;; cmove->load base: 5 cycles 16410d565efSmrg;; cmove->store base: 5 cycles 16510d565efSmrg(define_bypass 5 "r74k_int_cmove" "r74k_int_load") 16610d565efSmrg(define_bypass 5 "r74k_int_cmove" "r74k_int_store" 16710d565efSmrg "!mips_store_data_bypass_p") 16810d565efSmrg 16910d565efSmrg;; mult/madd/msub->int_mfhilo : 4 cycles (default) 17010d565efSmrg;; mult->madd/msub : 1 cycles 17110d565efSmrg;; madd/msub->madd/msub : 1 cycles 17210d565efSmrg(define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd" 17310d565efSmrg "mips_linked_madd_p") 17410d565efSmrg(define_bypass 1 "r74k_int_madd" "r74k_int_madd" 17510d565efSmrg "mips_linked_madd_p") 17610d565efSmrg 17710d565efSmrg 17810d565efSmrg;; -------------------------------------------------------------- 17910d565efSmrg;; DSP instructions 18010d565efSmrg;; -------------------------------------------------------------- 18110d565efSmrg 18210d565efSmrg;; Non-saturating insn have the same latency as normal ALU operations, 18310d565efSmrg(define_insn_reservation "r74k_dsp_alu" 2 18410d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 18510d565efSmrg (eq_attr "type" "dspalu")) 18610d565efSmrg "r74k_alu") 18710d565efSmrg 18810d565efSmrg;; Saturating insn takes an extra cycle. 18910d565efSmrg(define_insn_reservation "r74k_dsp_alu_sat" 3 19010d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 19110d565efSmrg (eq_attr "type" "dspalusat")) 19210d565efSmrg "r74k_alu") 19310d565efSmrg 19410d565efSmrg;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq 19510d565efSmrg;; - delivers result to hi/lo in 6 cycle (bypass at M4) 19610d565efSmrg(define_insn_reservation "r74k_dsp_mac" 6 19710d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 19810d565efSmrg (eq_attr "type" "dspmac")) 19910d565efSmrg "r74k_alu+r74k_mul") 20010d565efSmrg 20110d565efSmrg;; dpaq_sa, dpsq_sa, maq_sa 20210d565efSmrg;; - delivers result to hi/lo in 7 cycle (bypass at WB) 20310d565efSmrg(define_insn_reservation "r74k_dsp_mac_sat" 7 20410d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 20510d565efSmrg (eq_attr "type" "dspmacsat")) 20610d565efSmrg "r74k_alu+r74k_mul") 20710d565efSmrg 20810d565efSmrg;; extp, extpdp, extpdpv, extpv, extr, extrv 20910d565efSmrg;; - same latency as "mul" 21010d565efSmrg(define_insn_reservation "r74k_dsp_acc_ext" 7 21110d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 21210d565efSmrg (eq_attr "type" "accext")) 21310d565efSmrg "r74k_alu+r74k_mul") 21410d565efSmrg 21510d565efSmrg;; mthlip, shilo, shilov 21610d565efSmrg;; - same latency as "mul" 21710d565efSmrg(define_insn_reservation "r74k_dsp_acc_mod" 7 21810d565efSmrg (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") 21910d565efSmrg (eq_attr "type" "accmod")) 22010d565efSmrg "r74k_alu+r74k_mul") 22110d565efSmrg 22210d565efSmrg;; dspalu ->load/store base 22310d565efSmrg;; dspalusat->load/store base 22410d565efSmrg;; - we should never see these in real life. 22510d565efSmrg 22610d565efSmrg;; dsp_mac->dsp_mac : 1 cycles (repeat rate of 1) 22710d565efSmrg;; dsp_mac->dsp_mac_sat : 1 cycles (repeat rate of 1) 22810d565efSmrg(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac") 22910d565efSmrg(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac_sat") 23010d565efSmrg 23110d565efSmrg;; dsp_mac_sat->dsp_mac_sat : 2 cycles (repeat rate of 2) 23210d565efSmrg;; dsp_mac_sat->dsp_mac : 2 cycles (repeat rate of 2) 23310d565efSmrg(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac_sat") 23410d565efSmrg(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac") 23510d565efSmrg 23610d565efSmrg(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac") 23710d565efSmrg(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac_sat") 23810d565efSmrg 23910d565efSmrg(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac" "mips_linked_madd_p") 24010d565efSmrg(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac_sat" "mips_linked_madd_p") 24110d565efSmrg 24210d565efSmrg;; Assuming the following is true (bypass at M4) 24310d565efSmrg;; AP AF AM MB M1 M2 M3 M4 WB GR GC 24410d565efSmrg;; AP AF AM MB M1 M2 M3 M4 WB GR GC 24510d565efSmrg;; dsp_mac->dsp_acc_ext : 4 cycles 24610d565efSmrg;; dsp_mac->dsp_acc_mod : 4 cycles 24710d565efSmrg(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_ext") 24810d565efSmrg(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_mod") 24910d565efSmrg 25010d565efSmrg;; Assuming the following is true (bypass at WB) 25110d565efSmrg;; AP AF AM MB M1 M2 M3 M4 WB GR GC 25210d565efSmrg;; AP AF AM MB M1 M2 M3 M4 WB GR GC 25310d565efSmrg;; dsp_mac_sat->dsp_acc_ext : 5 cycles 25410d565efSmrg;; dsp_mac_sat->dsp_acc_mod : 5 cycles 25510d565efSmrg(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_ext") 25610d565efSmrg(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_mod") 25710d565efSmrg 25810d565efSmrg 25910d565efSmrg;; -------------------------------------------------------------- 26010d565efSmrg;; Floating Point Instructions 26110d565efSmrg;; -------------------------------------------------------------- 26210d565efSmrg 26310d565efSmrg;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio. 26410d565efSmrg 26510d565efSmrg;; fadd, fabs, fneg, 26610d565efSmrg(define_insn_reservation "r74kf1_1_fadd" 4 26710d565efSmrg (and (eq_attr "cpu" "74kf1_1") 26810d565efSmrg (eq_attr "type" "fadd,fabs,fneg")) 26910d565efSmrg "r74k_fpu_arith") 27010d565efSmrg 27110d565efSmrg(define_insn_reservation "r74kf2_1_fadd" 8 27210d565efSmrg (and (eq_attr "cpu" "74kf2_1") 27310d565efSmrg (eq_attr "type" "fadd,fabs,fneg")) 27410d565efSmrg "r74k_fpu_arith*2") 27510d565efSmrg 27610d565efSmrg(define_insn_reservation "r74kf3_2_fadd" 6 27710d565efSmrg (and (eq_attr "cpu" "74kf3_2") 27810d565efSmrg (eq_attr "type" "fadd,fabs,fneg")) 27910d565efSmrg "r74k_fpu_arith") 28010d565efSmrg 28110d565efSmrg;; fmove, fcmove 28210d565efSmrg(define_insn_reservation "r74kf1_1_fmove" 4 28310d565efSmrg (and (eq_attr "cpu" "74kf1_1") 28410d565efSmrg (eq_attr "type" "fmove")) 28510d565efSmrg "r74k_fpu_arith") 28610d565efSmrg 28710d565efSmrg(define_insn_reservation "r74kf2_1_fmove" 8 28810d565efSmrg (and (eq_attr "cpu" "74kf2_1") 28910d565efSmrg (eq_attr "type" "fmove")) 29010d565efSmrg "r74k_fpu_arith*2") 29110d565efSmrg 29210d565efSmrg(define_insn_reservation "r74kf3_2_fmove" 6 29310d565efSmrg (and (eq_attr "cpu" "74kf3_2") 29410d565efSmrg (eq_attr "type" "fmove")) 29510d565efSmrg "r74k_fpu_arith") 29610d565efSmrg 29710d565efSmrg;; fload 29810d565efSmrg(define_insn_reservation "r74kf1_1_fload" 4 29910d565efSmrg (and (eq_attr "cpu" "74kf1_1") 30010d565efSmrg (eq_attr "type" "fpload,fpidxload")) 30110d565efSmrg "r74k_agen+r74k_fpu_ldst") 30210d565efSmrg 30310d565efSmrg(define_insn_reservation "r74kf2_1_fload" 8 30410d565efSmrg (and (eq_attr "cpu" "74kf2_1") 30510d565efSmrg (eq_attr "type" "fpload,fpidxload")) 30610d565efSmrg "r74k_agen+(r74k_fpu_ldst*2)") 30710d565efSmrg 30810d565efSmrg(define_insn_reservation "r74kf3_2_fload" 6 30910d565efSmrg (and (eq_attr "cpu" "74kf3_2") 31010d565efSmrg (eq_attr "type" "fpload,fpidxload")) 31110d565efSmrg "r74k_agen+r74k_fpu_ldst") 31210d565efSmrg 31310d565efSmrg;; fstore 31410d565efSmrg(define_insn_reservation "r74kf1_1_fstore" 1 31510d565efSmrg (and (eq_attr "cpu" "74kf1_1") 31610d565efSmrg (eq_attr "type" "fpstore,fpidxstore")) 31710d565efSmrg "r74k_agen+r74k_fpu_ldst") 31810d565efSmrg 31910d565efSmrg(define_insn_reservation "r74kf2_1_fstore" 2 32010d565efSmrg (and (eq_attr "cpu" "74kf2_1") 32110d565efSmrg (eq_attr "type" "fpstore,fpidxstore")) 32210d565efSmrg "r74k_agen+(r74k_fpu_ldst*2)") 32310d565efSmrg 32410d565efSmrg(define_insn_reservation "r74kf3_2_fstore" 1 32510d565efSmrg (and (eq_attr "cpu" "74kf3_2") 32610d565efSmrg (eq_attr "type" "fpstore,fpidxstore")) 32710d565efSmrg "r74k_agen+r74k_fpu_ldst") 32810d565efSmrg 32910d565efSmrg;; fmul, fmadd 33010d565efSmrg(define_insn_reservation "r74kf1_1_fmul_sf" 4 33110d565efSmrg (and (eq_attr "cpu" "74kf1_1") 33210d565efSmrg (and (eq_attr "type" "fmul,fmadd") 33310d565efSmrg (eq_attr "mode" "SF"))) 33410d565efSmrg "r74k_fpu_arith") 33510d565efSmrg 33610d565efSmrg(define_insn_reservation "r74kf2_1_fmul_sf" 8 33710d565efSmrg (and (eq_attr "cpu" "74kf2_1") 33810d565efSmrg (and (eq_attr "type" "fmul,fmadd") 33910d565efSmrg (eq_attr "mode" "SF"))) 34010d565efSmrg "r74k_fpu_arith*2") 34110d565efSmrg 34210d565efSmrg(define_insn_reservation "r74kf3_2_fmul_sf" 6 34310d565efSmrg (and (eq_attr "cpu" "74kf3_2") 34410d565efSmrg (and (eq_attr "type" "fmul,fmadd") 34510d565efSmrg (eq_attr "mode" "SF"))) 34610d565efSmrg "r74k_fpu_arith") 34710d565efSmrg 34810d565efSmrg(define_insn_reservation "r74kf1_1_fmul_df" 5 34910d565efSmrg (and (eq_attr "cpu" "74kf1_1") 35010d565efSmrg (and (eq_attr "type" "fmul,fmadd") 35110d565efSmrg (eq_attr "mode" "DF"))) 35210d565efSmrg "r74k_fpu_arith*2") 35310d565efSmrg 35410d565efSmrg(define_insn_reservation "r74kf2_1_fmul_df" 10 35510d565efSmrg (and (eq_attr "cpu" "74kf2_1") 35610d565efSmrg (and (eq_attr "type" "fmul,fmadd") 35710d565efSmrg (eq_attr "mode" "DF"))) 35810d565efSmrg "r74k_fpu_arith*4") 35910d565efSmrg 36010d565efSmrg(define_insn_reservation "r74kf3_2_fmul_df" 7 36110d565efSmrg (and (eq_attr "cpu" "74kf3_2") 36210d565efSmrg (and (eq_attr "type" "fmul,fmadd") 36310d565efSmrg (eq_attr "mode" "DF"))) 36410d565efSmrg "r74k_fpu_arith*2") 36510d565efSmrg 36610d565efSmrg;; fdiv, fsqrt 36710d565efSmrg(define_insn_reservation "r74kf1_1_fdiv_sf" 17 36810d565efSmrg (and (eq_attr "cpu" "74kf1_1") 36910d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 37010d565efSmrg (eq_attr "mode" "SF"))) 37110d565efSmrg "r74k_fpu_arith*14") 37210d565efSmrg 37310d565efSmrg(define_insn_reservation "r74kf2_1_fdiv_sf" 34 37410d565efSmrg (and (eq_attr "cpu" "74kf2_1") 37510d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 37610d565efSmrg (eq_attr "mode" "SF"))) 37710d565efSmrg "r74k_fpu_arith*28") 37810d565efSmrg 37910d565efSmrg(define_insn_reservation "r74kf3_2_fdiv_sf" 25 38010d565efSmrg (and (eq_attr "cpu" "74kf3_2") 38110d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 38210d565efSmrg (eq_attr "mode" "SF"))) 38310d565efSmrg "r74k_fpu_arith*14") 38410d565efSmrg 38510d565efSmrg(define_insn_reservation "r74kf1_1_fdiv_df" 32 38610d565efSmrg (and (eq_attr "cpu" "74kf1_1") 38710d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 38810d565efSmrg (eq_attr "mode" "DF"))) 38910d565efSmrg "r74k_fpu_arith*29") 39010d565efSmrg 39110d565efSmrg(define_insn_reservation "r74kf2_1_fdiv_df" 64 39210d565efSmrg (and (eq_attr "cpu" "74kf2_1") 39310d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 39410d565efSmrg (eq_attr "mode" "DF"))) 39510d565efSmrg "r74k_fpu_arith*58") 39610d565efSmrg 39710d565efSmrg(define_insn_reservation "r74kf3_2_fdiv_df" 48 39810d565efSmrg (and (eq_attr "cpu" "74kf3_2") 39910d565efSmrg (and (eq_attr "type" "fdiv,fsqrt") 40010d565efSmrg (eq_attr "mode" "DF"))) 40110d565efSmrg "r74k_fpu_arith*29") 40210d565efSmrg 40310d565efSmrg;; frsqrt 40410d565efSmrg(define_insn_reservation "r74kf1_1_frsqrt_sf" 17 40510d565efSmrg (and (eq_attr "cpu" "74kf1_1") 40610d565efSmrg (and (eq_attr "type" "frsqrt") 40710d565efSmrg (eq_attr "mode" "SF"))) 40810d565efSmrg "r74k_fpu_arith*14") 40910d565efSmrg 41010d565efSmrg(define_insn_reservation "r74kf2_1_frsqrt_sf" 34 41110d565efSmrg (and (eq_attr "cpu" "74kf2_1") 41210d565efSmrg (and (eq_attr "type" "frsqrt") 41310d565efSmrg (eq_attr "mode" "SF"))) 41410d565efSmrg "r74k_fpu_arith*28") 41510d565efSmrg 41610d565efSmrg(define_insn_reservation "r74kf3_2_frsqrt_sf" 25 41710d565efSmrg (and (eq_attr "cpu" "74kf3_2") 41810d565efSmrg (and (eq_attr "type" "frsqrt") 41910d565efSmrg (eq_attr "mode" "SF"))) 42010d565efSmrg "r74k_fpu_arith*14") 42110d565efSmrg 42210d565efSmrg(define_insn_reservation "r74kf1_1_frsqrt_df" 36 42310d565efSmrg (and (eq_attr "cpu" "74kf1_1") 42410d565efSmrg (and (eq_attr "type" "frsqrt") 42510d565efSmrg (eq_attr "mode" "DF"))) 42610d565efSmrg "r74k_fpu_arith*31") 42710d565efSmrg 42810d565efSmrg(define_insn_reservation "r74kf2_1_frsqrt_df" 72 42910d565efSmrg (and (eq_attr "cpu" "74kf2_1") 43010d565efSmrg (and (eq_attr "type" "frsqrt") 43110d565efSmrg (eq_attr "mode" "DF"))) 43210d565efSmrg "r74k_fpu_arith*62") 43310d565efSmrg 43410d565efSmrg(define_insn_reservation "r74kf3_2_frsqrt_df" 54 43510d565efSmrg (and (eq_attr "cpu" "74kf3_2") 43610d565efSmrg (and (eq_attr "type" "frsqrt") 43710d565efSmrg (eq_attr "mode" "DF"))) 43810d565efSmrg "r74k_fpu_arith*31") 43910d565efSmrg 44010d565efSmrg;; fcmp 44110d565efSmrg(define_insn_reservation "r74kf1_1_fcmp" 4 44210d565efSmrg (and (eq_attr "cpu" "74kf1_1") 44310d565efSmrg (eq_attr "type" "fcmp")) 44410d565efSmrg "r74k_fpu_arith") 44510d565efSmrg 44610d565efSmrg(define_insn_reservation "r74kf2_1_fcmp" 8 44710d565efSmrg (and (eq_attr "cpu" "74kf2_1") 44810d565efSmrg (eq_attr "type" "fcmp")) 44910d565efSmrg "r74k_fpu_arith*2") 45010d565efSmrg 45110d565efSmrg(define_insn_reservation "r74kf3_2_fcmp" 6 45210d565efSmrg (and (eq_attr "cpu" "74kf3_2") 45310d565efSmrg (eq_attr "type" "fcmp")) 45410d565efSmrg "r74k_fpu_arith") 45510d565efSmrg 45610d565efSmrg;; fcvt 45710d565efSmrg(define_insn_reservation "r74kf1_1_fcvt" 4 45810d565efSmrg (and (eq_attr "cpu" "74kf1_1") 45910d565efSmrg (eq_attr "type" "fcvt")) 46010d565efSmrg "r74k_fpu_arith") 46110d565efSmrg 46210d565efSmrg(define_insn_reservation "r74kf2_1_fcvt" 8 46310d565efSmrg (and (eq_attr "cpu" "74kf2_1") 46410d565efSmrg (eq_attr "type" "fcvt")) 46510d565efSmrg "r74k_fpu_arith*2") 46610d565efSmrg 46710d565efSmrg(define_insn_reservation "r74kf3_2_fcvt" 6 46810d565efSmrg (and (eq_attr "cpu" "74kf3_2") 46910d565efSmrg (eq_attr "type" "fcvt")) 47010d565efSmrg "r74k_fpu_arith") 47110d565efSmrg 47210d565efSmrg;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1) 47310d565efSmrg(define_insn_reservation "r74kf1_1_fxfer_to_c1" 4 47410d565efSmrg (and (eq_attr "cpu" "74kf1_1") 47510d565efSmrg (eq_attr "type" "mtc")) 47610d565efSmrg "r74k_fpu_arith") 47710d565efSmrg 47810d565efSmrg(define_insn_reservation "r74kf2_1_fxfer_to_c1" 8 47910d565efSmrg (and (eq_attr "cpu" "74kf2_1") 48010d565efSmrg (eq_attr "type" "mtc")) 48110d565efSmrg "r74k_fpu_arith*2") 48210d565efSmrg 48310d565efSmrg(define_insn_reservation "r74kf3_2_fxfer_to_c1" 6 48410d565efSmrg (and (eq_attr "cpu" "74kf3_2") 48510d565efSmrg (eq_attr "type" "mtc")) 48610d565efSmrg "r74k_fpu_arith") 48710d565efSmrg 48810d565efSmrg(define_insn_reservation "r74kf1_1_fxfer_from_c1" 1 48910d565efSmrg (and (eq_attr "cpu" "74kf1_1") 49010d565efSmrg (eq_attr "type" "mfc")) 49110d565efSmrg "r74k_fpu_arith") 49210d565efSmrg 49310d565efSmrg(define_insn_reservation "r74kf2_1_fxfer_from_c1" 2 49410d565efSmrg (and (eq_attr "cpu" "74kf2_1") 49510d565efSmrg (eq_attr "type" "mfc")) 49610d565efSmrg "r74k_fpu_arith*2") 49710d565efSmrg 49810d565efSmrg(define_insn_reservation "r74kf3_2_fxfer_from_c1" 1 49910d565efSmrg (and (eq_attr "cpu" "74kf3_2") 50010d565efSmrg (eq_attr "type" "mfc")) 50110d565efSmrg "r74k_fpu_arith") 502