1;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler 2;; Copyright (C) 2012-2020 Free Software Foundation, Inc. 3;; Contributed by Andes Technology Corporation. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; ------------------------------------------------------------------------ 22;; Define Graywolf pipeline settings. 23;; ------------------------------------------------------------------------ 24 25(define_automaton "nds32_graywolf_machine") 26 27(define_cpu_unit "gw_ii_0" "nds32_graywolf_machine") 28(define_cpu_unit "gw_ii_1" "nds32_graywolf_machine") 29(define_cpu_unit "gw_ex_p0" "nds32_graywolf_machine") 30(define_cpu_unit "gw_mm_p0" "nds32_graywolf_machine") 31(define_cpu_unit "gw_wb_p0" "nds32_graywolf_machine") 32(define_cpu_unit "gw_ex_p1" "nds32_graywolf_machine") 33(define_cpu_unit "gw_mm_p1" "nds32_graywolf_machine") 34(define_cpu_unit "gw_wb_p1" "nds32_graywolf_machine") 35(define_cpu_unit "gw_iq_p2" "nds32_graywolf_machine") 36(define_cpu_unit "gw_rf_p2" "nds32_graywolf_machine") 37(define_cpu_unit "gw_e1_p2" "nds32_graywolf_machine") 38(define_cpu_unit "gw_e2_p2" "nds32_graywolf_machine") 39(define_cpu_unit "gw_e3_p2" "nds32_graywolf_machine") 40(define_cpu_unit "gw_e4_p2" "nds32_graywolf_machine") 41 42(define_reservation "gw_ii" "gw_ii_0 | gw_ii_1") 43(define_reservation "gw_ex" "gw_ex_p0 | gw_ex_p1") 44(define_reservation "gw_mm" "gw_mm_p0 | gw_mm_p1") 45(define_reservation "gw_wb" "gw_wb_p0 | gw_wb_p1") 46 47(define_reservation "gw_ii_all" "gw_ii_0 + gw_ii_1") 48 49(define_insn_reservation "nds_gw_unknown" 1 50 (and (eq_attr "type" "unknown") 51 (eq_attr "pipeline_model" "graywolf")) 52 "gw_ii, gw_ex, gw_mm, gw_wb") 53 54(define_insn_reservation "nds_gw_misc" 1 55 (and (eq_attr "type" "misc") 56 (eq_attr "pipeline_model" "graywolf")) 57 "gw_ii, gw_ex, gw_mm, gw_wb") 58 59(define_insn_reservation "nds_gw_mmu" 1 60 (and (eq_attr "type" "mmu") 61 (eq_attr "pipeline_model" "graywolf")) 62 "gw_ii, gw_ex, gw_mm, gw_wb") 63 64(define_insn_reservation "nds_gw_alu" 1 65 (and (and (eq_attr "type" "alu") 66 (match_test "!nds32::movd44_insn_p (insn)")) 67 (eq_attr "pipeline_model" "graywolf")) 68 "gw_ii, gw_ex, gw_mm, gw_wb") 69 70(define_insn_reservation "nds_gw_movd44" 1 71 (and (and (eq_attr "type" "alu") 72 (match_test "nds32::movd44_insn_p (insn)")) 73 (eq_attr "pipeline_model" "graywolf")) 74 "gw_ii_1, gw_ex, gw_mm, gw_wb") 75 76(define_insn_reservation "nds_gw_alu_shift" 1 77 (and (eq_attr "type" "alu_shift") 78 (eq_attr "pipeline_model" "graywolf")) 79 "gw_ii, gw_ex*2, gw_mm, gw_wb") 80 81(define_insn_reservation "nds_gw_pbsad" 1 82 (and (eq_attr "type" "pbsad") 83 (eq_attr "pipeline_model" "graywolf")) 84 "gw_ii, gw_ex*3, gw_mm, gw_wb") 85 86(define_insn_reservation "nds_gw_pbsada" 1 87 (and (eq_attr "type" "pbsada") 88 (eq_attr "pipeline_model" "graywolf")) 89 "gw_ii, gw_ex*3, gw_mm, gw_wb") 90 91(define_insn_reservation "nds_gw_load" 1 92 (and (and (eq_attr "type" "load") 93 (match_test "!nds32::post_update_insn_p (insn)")) 94 (eq_attr "pipeline_model" "graywolf")) 95 "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") 96 97(define_insn_reservation "nds_gw_load_2w" 1 98 (and (and (eq_attr "type" "load") 99 (match_test "nds32::post_update_insn_p (insn)")) 100 (eq_attr "pipeline_model" "graywolf")) 101 "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") 102 103(define_insn_reservation "nds_gw_store" 1 104 (and (and (eq_attr "type" "store") 105 (match_test "!nds32::store_offset_reg_p (insn)")) 106 (eq_attr "pipeline_model" "graywolf")) 107 "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") 108 109(define_insn_reservation "nds_gw_store_3r" 1 110 (and (and (eq_attr "type" "store") 111 (match_test "nds32::store_offset_reg_p (insn)")) 112 (eq_attr "pipeline_model" "graywolf")) 113 "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") 114 115(define_insn_reservation "nds_gw_load_multiple_1" 1 116 (and (and (eq_attr "type" "load_multiple") 117 (eq_attr "combo" "1")) 118 (eq_attr "pipeline_model" "graywolf")) 119 "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") 120 121(define_insn_reservation "nds_gw_load_multiple_2" 1 122 (and (and (eq_attr "type" "load_multiple") 123 (eq_attr "combo" "2")) 124 (eq_attr "pipeline_model" "graywolf")) 125 "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") 126 127(define_insn_reservation "nds_gw_load_multiple_3" 1 128 (and (and (eq_attr "type" "load_multiple") 129 (eq_attr "combo" "3")) 130 (eq_attr "pipeline_model" "graywolf")) 131 "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") 132 133(define_insn_reservation "nds_gw_load_multiple_4" 1 134 (and (and (eq_attr "type" "load_multiple") 135 (eq_attr "combo" "4")) 136 (eq_attr "pipeline_model" "graywolf")) 137 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 138 139(define_insn_reservation "nds_gw_load_multiple_5" 1 140 (and (and (eq_attr "type" "load_multiple") 141 (eq_attr "combo" "5")) 142 (eq_attr "pipeline_model" "graywolf")) 143 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 144 145(define_insn_reservation "nds_gw_load_multiple_6" 1 146 (and (and (eq_attr "type" "load_multiple") 147 (eq_attr "combo" "6")) 148 (eq_attr "pipeline_model" "graywolf")) 149 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 150 151(define_insn_reservation "nds_gw_load_multiple_7" 1 152 (and (and (eq_attr "type" "load_multiple") 153 (eq_attr "combo" "7")) 154 (eq_attr "pipeline_model" "graywolf")) 155 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 156 157(define_insn_reservation "nds_gw_load_multiple_8" 1 158 (and (and (eq_attr "type" "load_multiple") 159 (eq_attr "combo" "8")) 160 (eq_attr "pipeline_model" "graywolf")) 161 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 162 163(define_insn_reservation "nds_gw_load_multiple_12" 1 164 (and (and (eq_attr "type" "load_multiple") 165 (eq_attr "combo" "12")) 166 (eq_attr "pipeline_model" "graywolf")) 167 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 168 169(define_insn_reservation "nds_gw_store_multiple_1" 1 170 (and (and (eq_attr "type" "store_multiple") 171 (eq_attr "combo" "1")) 172 (eq_attr "pipeline_model" "graywolf")) 173 "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") 174 175(define_insn_reservation "nds_gw_store_multiple_2" 1 176 (and (and (eq_attr "type" "store_multiple") 177 (eq_attr "combo" "2")) 178 (eq_attr "pipeline_model" "graywolf")) 179 "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") 180 181(define_insn_reservation "nds_gw_store_multiple_3" 1 182 (and (and (eq_attr "type" "store_multiple") 183 (eq_attr "combo" "3")) 184 (eq_attr "pipeline_model" "graywolf")) 185 "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") 186 187(define_insn_reservation "nds_gw_store_multiple_4" 1 188 (and (and (eq_attr "type" "store_multiple") 189 (eq_attr "combo" "4")) 190 (eq_attr "pipeline_model" "graywolf")) 191 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 192 193(define_insn_reservation "nds_gw_store_multiple_5" 1 194 (and (and (eq_attr "type" "store_multiple") 195 (eq_attr "combo" "5")) 196 (eq_attr "pipeline_model" "graywolf")) 197 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 198 199(define_insn_reservation "nds_gw_store_multiple_6" 1 200 (and (and (eq_attr "type" "store_multiple") 201 (eq_attr "combo" "6")) 202 (eq_attr "pipeline_model" "graywolf")) 203 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 204 205(define_insn_reservation "nds_gw_store_multiple_7" 1 206 (and (and (eq_attr "type" "store_multiple") 207 (eq_attr "combo" "7")) 208 (eq_attr "pipeline_model" "graywolf")) 209 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 210 211(define_insn_reservation "nds_gw_store_multiple_8" 1 212 (and (and (eq_attr "type" "store_multiple") 213 (eq_attr "combo" "8")) 214 (eq_attr "pipeline_model" "graywolf")) 215 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 216 217(define_insn_reservation "nds_gw_store_multiple_12" 1 218 (and (and (eq_attr "type" "store_multiple") 219 (eq_attr "combo" "12")) 220 (eq_attr "pipeline_model" "graywolf")) 221 "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") 222 223(define_insn_reservation "nds_gw_mul_fast1" 1 224 (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") 225 (and (eq_attr "type" "mul") 226 (eq_attr "pipeline_model" "graywolf"))) 227 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 228 229(define_insn_reservation "nds_gw_mul_fast2" 1 230 (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") 231 (and (eq_attr "type" "mul") 232 (eq_attr "pipeline_model" "graywolf"))) 233 "gw_ii_0, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") 234 235(define_insn_reservation "nds_gw_mul_slow" 1 236 (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") 237 (and (eq_attr "type" "mul") 238 (eq_attr "pipeline_model" "graywolf"))) 239 "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") 240 241(define_insn_reservation "nds_gw_mac_fast1" 1 242 (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") 243 (and (eq_attr "type" "mac") 244 (eq_attr "pipeline_model" "graywolf"))) 245 "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") 246 247(define_insn_reservation "nds_gw_mac_fast2" 1 248 (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") 249 (and (eq_attr "type" "mac") 250 (eq_attr "pipeline_model" "graywolf"))) 251 "gw_ii_all, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") 252 253(define_insn_reservation "nds_gw_mac_slow" 1 254 (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") 255 (and (eq_attr "type" "mac") 256 (eq_attr "pipeline_model" "graywolf"))) 257 "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") 258 259(define_insn_reservation "nds_gw_div" 1 260 (and (and (eq_attr "type" "div") 261 (match_test "!nds32::divmod_p (insn)")) 262 (eq_attr "pipeline_model" "graywolf")) 263 "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") 264 265(define_insn_reservation "nds_gw_div_2w" 1 266 (and (and (eq_attr "type" "div") 267 (match_test "nds32::divmod_p (insn)")) 268 (eq_attr "pipeline_model" "graywolf")) 269 "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") 270 271(define_insn_reservation "nds_gw_branch" 1 272 (and (eq_attr "type" "branch") 273 (eq_attr "pipeline_model" "graywolf")) 274 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 275 276(define_insn_reservation "nds_gw_dsp_alu" 1 277 (and (eq_attr "type" "dalu") 278 (eq_attr "pipeline_model" "graywolf")) 279 "gw_ii, gw_ex, gw_mm, gw_wb") 280 281(define_insn_reservation "nds_gw_dsp_alu64" 1 282 (and (eq_attr "type" "dalu64") 283 (eq_attr "pipeline_model" "graywolf")) 284 "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") 285 286(define_insn_reservation "nds_gw_dsp_alu_round" 1 287 (and (eq_attr "type" "daluround") 288 (eq_attr "pipeline_model" "graywolf")) 289 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 290 291(define_insn_reservation "nds_gw_dsp_cmp" 1 292 (and (eq_attr "type" "dcmp") 293 (eq_attr "pipeline_model" "graywolf")) 294 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 295 296(define_insn_reservation "nds_gw_dsp_clip" 1 297 (and (eq_attr "type" "dclip") 298 (eq_attr "pipeline_model" "graywolf")) 299 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 300 301(define_insn_reservation "nds_gw_dsp_mul" 1 302 (and (eq_attr "type" "dmul") 303 (eq_attr "pipeline_model" "graywolf")) 304 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 305 306(define_insn_reservation "nds_gw_dsp_mac" 1 307 (and (eq_attr "type" "dmac") 308 (eq_attr "pipeline_model" "graywolf")) 309 "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") 310 311(define_insn_reservation "nds_gw_dsp_insb" 1 312 (and (eq_attr "type" "dinsb") 313 (eq_attr "pipeline_model" "graywolf")) 314 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 315 316(define_insn_reservation "nds_gw_dsp_pack" 1 317 (and (eq_attr "type" "dpack") 318 (eq_attr "pipeline_model" "graywolf")) 319 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 320 321(define_insn_reservation "nds_gw_dsp_bpick" 1 322 (and (eq_attr "type" "dbpick") 323 (eq_attr "pipeline_model" "graywolf")) 324 "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") 325 326(define_insn_reservation "nds_gw_dsp_wext" 1 327 (and (eq_attr "type" "dwext") 328 (eq_attr "pipeline_model" "graywolf")) 329 "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") 330 331(define_insn_reservation "nds_gw_fpu_alu" 4 332 (and (eq_attr "type" "falu") 333 (eq_attr "pipeline_model" "graywolf")) 334 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") 335 336(define_insn_reservation "nds_gw_fpu_muls" 4 337 (and (eq_attr "type" "fmuls") 338 (eq_attr "pipeline_model" "graywolf")) 339 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") 340 341(define_insn_reservation "nds_gw_fpu_muld" 4 342 (and (eq_attr "type" "fmuld") 343 (eq_attr "pipeline_model" "graywolf")) 344 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*2, gw_e3_p2, gw_e4_p2") 345 346(define_insn_reservation "nds_gw_fpu_macs" 4 347 (and (eq_attr "type" "fmacs") 348 (eq_attr "pipeline_model" "graywolf")) 349 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*3, gw_e3_p2, gw_e4_p2") 350 351(define_insn_reservation "nds_gw_fpu_macd" 4 352 (and (eq_attr "type" "fmacd") 353 (eq_attr "pipeline_model" "graywolf")) 354 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*4, gw_e3_p2, gw_e4_p2") 355 356(define_insn_reservation "nds_gw_fpu_divs" 4 357 (and (ior (eq_attr "type" "fdivs") 358 (eq_attr "type" "fsqrts")) 359 (eq_attr "pipeline_model" "graywolf")) 360 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*14, gw_e3_p2, gw_e4_p2") 361 362(define_insn_reservation "nds_gw_fpu_divd" 4 363 (and (ior (eq_attr "type" "fdivd") 364 (eq_attr "type" "fsqrtd")) 365 (eq_attr "pipeline_model" "graywolf")) 366 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*28, gw_e3_p2, gw_e4_p2") 367 368(define_insn_reservation "nds_gw_fpu_fast_alu" 2 369 (and (ior (eq_attr "type" "fcmp") 370 (ior (eq_attr "type" "fabs") 371 (ior (eq_attr "type" "fcpy") 372 (eq_attr "type" "fcmov")))) 373 (eq_attr "pipeline_model" "graywolf")) 374 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") 375 376(define_insn_reservation "nds_gw_fpu_fmtsr" 1 377 (and (eq_attr "type" "fmtsr") 378 (eq_attr "pipeline_model" "graywolf")) 379 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") 380 381(define_insn_reservation "nds_gw_fpu_fmtdr" 1 382 (and (eq_attr "type" "fmtdr") 383 (eq_attr "pipeline_model" "graywolf")) 384 "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") 385 386(define_insn_reservation "nds_gw_fpu_fmfsr" 1 387 (and (eq_attr "type" "fmfsr") 388 (eq_attr "pipeline_model" "graywolf")) 389 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") 390 391(define_insn_reservation "nds_gw_fpu_fmfdr" 1 392 (and (eq_attr "type" "fmfdr") 393 (eq_attr "pipeline_model" "graywolf")) 394 "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") 395 396(define_insn_reservation "nds_gw_fpu_load" 3 397 (and (eq_attr "type" "fload") 398 (eq_attr "pipeline_model" "graywolf")) 399 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") 400 401(define_insn_reservation "nds_gw_fpu_store" 1 402 (and (eq_attr "type" "fstore") 403 (eq_attr "pipeline_model" "graywolf")) 404 "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") 405 406;; FPU_ADDR_OUT -> FPU_ADDR_IN 407;; Main pipeline rules don't need this because those default latency is 1. 408(define_bypass 1 409 "nds_gw_fpu_load, nds_gw_fpu_store" 410 "nds_gw_fpu_load, nds_gw_fpu_store" 411 "nds32_gw_ex_to_ex_p" 412) 413 414;; LD, MUL, MAC, DIV, DALU64, DMUL, DMAC, DALUROUND, DBPICK, DWEXT 415;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU, 416;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb 417(define_bypass 2 418 "nds_gw_load, nds_gw_load_2w,\ 419 nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ 420 nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ 421 nds_gw_div, nds_gw_div_2w,\ 422 nds_gw_dsp_alu64, nds_gw_dsp_mul, nds_gw_dsp_mac,\ 423 nds_gw_dsp_alu_round, nds_gw_dsp_bpick, nds_gw_dsp_wext" 424 "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ 425 nds_gw_pbsad, nds_gw_pbsada,\ 426 nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ 427 nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ 428 nds_gw_branch,\ 429 nds_gw_div, nds_gw_div_2w,\ 430 nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ 431 nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ 432 nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ 433 nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ 434 nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ 435 nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ 436 nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ 437 nds_gw_mmu,\ 438 nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ 439 nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ 440 nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ 441 nds_gw_dsp_wext, nds_gw_dsp_bpick" 442 "nds32_gw_mm_to_ex_p" 443) 444 445;; LMW(N, N) 446;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU 447;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb 448(define_bypass 2 449 "nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ 450 nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ 451 nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12" 452 "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ 453 nds_gw_pbsad, nds_gw_pbsada,\ 454 nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ 455 nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ 456 nds_gw_branch,\ 457 nds_gw_div, nds_gw_div_2w,\ 458 nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ 459 nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ 460 nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ 461 nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ 462 nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ 463 nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ 464 nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ 465 nds_gw_mmu,\ 466 nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ 467 nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ 468 nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ 469 nds_gw_dsp_wext, nds_gw_dsp_bpick" 470 "nds32_gw_last_load_to_ex_p" 471) 472