110d565efSmrg /* Define per-register tables for data flow info and register allocation.
2*ec02198aSmrg Copyright (C) 1987-2020 Free Software Foundation, Inc.
310d565efSmrg
410d565efSmrg This file is part of GCC.
510d565efSmrg
610d565efSmrg GCC is free software; you can redistribute it and/or modify it under
710d565efSmrg the terms of the GNU General Public License as published by the Free
810d565efSmrg Software Foundation; either version 3, or (at your option) any later
910d565efSmrg version.
1010d565efSmrg
1110d565efSmrg GCC is distributed in the hope that it will be useful, but WITHOUT ANY
1210d565efSmrg WARRANTY; without even the implied warranty of MERCHANTABILITY or
1310d565efSmrg FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1410d565efSmrg for more details.
1510d565efSmrg
1610d565efSmrg You should have received a copy of the GNU General Public License
1710d565efSmrg along with GCC; see the file COPYING3. If not see
1810d565efSmrg <http://www.gnu.org/licenses/>. */
1910d565efSmrg
2010d565efSmrg #ifndef GCC_REGS_H
2110d565efSmrg #define GCC_REGS_H
2210d565efSmrg
2310d565efSmrg #define REG_BYTES(R) mode_size[(int) GET_MODE (R)]
2410d565efSmrg
2510d565efSmrg /* When you only have the mode of a pseudo register before it has a hard
2610d565efSmrg register chosen for it, this reports the size of each hard register
2710d565efSmrg a pseudo in such a mode would get allocated to. A target may
2810d565efSmrg override this. */
2910d565efSmrg
3010d565efSmrg #ifndef REGMODE_NATURAL_SIZE
3110d565efSmrg #define REGMODE_NATURAL_SIZE(MODE) UNITS_PER_WORD
3210d565efSmrg #endif
3310d565efSmrg
3410d565efSmrg /* Maximum register number used in this function, plus one. */
3510d565efSmrg
3610d565efSmrg extern int max_regno;
3710d565efSmrg
3810d565efSmrg /* REG_N_REFS and REG_N_SETS are initialized by a call to
3910d565efSmrg regstat_init_n_sets_and_refs from the current values of
4010d565efSmrg DF_REG_DEF_COUNT and DF_REG_USE_COUNT. REG_N_REFS and REG_N_SETS
4110d565efSmrg should only be used if a pass need to change these values in some
4210d565efSmrg magical way or the pass needs to have accurate values for these
4310d565efSmrg and is not using incremental df scanning.
4410d565efSmrg
4510d565efSmrg At the end of a pass that uses REG_N_REFS and REG_N_SETS, a call
4610d565efSmrg should be made to regstat_free_n_sets_and_refs.
4710d565efSmrg
4810d565efSmrg Local alloc seems to play pretty loose with these values.
4910d565efSmrg REG_N_REFS is set to 0 if the register is used in an asm.
5010d565efSmrg Furthermore, local_alloc calls regclass to hack both REG_N_REFS and
5110d565efSmrg REG_N_SETS for three address insns. Other passes seem to have
5210d565efSmrg other special values. */
5310d565efSmrg
5410d565efSmrg
5510d565efSmrg
5610d565efSmrg /* Structure to hold values for REG_N_SETS (i) and REG_N_REFS (i). */
5710d565efSmrg
5810d565efSmrg struct regstat_n_sets_and_refs_t
5910d565efSmrg {
6010d565efSmrg int sets; /* # of times (REG n) is set */
6110d565efSmrg int refs; /* # of times (REG n) is used or set */
6210d565efSmrg };
6310d565efSmrg
6410d565efSmrg extern struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs;
6510d565efSmrg
6610d565efSmrg /* Indexed by n, gives number of times (REG n) is used or set. */
6710d565efSmrg static inline int
REG_N_REFS(int regno)6810d565efSmrg REG_N_REFS (int regno)
6910d565efSmrg {
7010d565efSmrg return regstat_n_sets_and_refs[regno].refs;
7110d565efSmrg }
7210d565efSmrg
7310d565efSmrg /* Indexed by n, gives number of times (REG n) is used or set. */
7410d565efSmrg #define SET_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs = V)
7510d565efSmrg #define INC_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs += V)
7610d565efSmrg
7710d565efSmrg /* Indexed by n, gives number of times (REG n) is set. */
7810d565efSmrg static inline int
REG_N_SETS(int regno)7910d565efSmrg REG_N_SETS (int regno)
8010d565efSmrg {
8110d565efSmrg return regstat_n_sets_and_refs[regno].sets;
8210d565efSmrg }
8310d565efSmrg
8410d565efSmrg /* Indexed by n, gives number of times (REG n) is set. */
8510d565efSmrg #define SET_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets = V)
8610d565efSmrg #define INC_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets += V)
8710d565efSmrg
8810d565efSmrg /* Given a REG, return TRUE if the reg is a PARM_DECL, FALSE otherwise. */
8910d565efSmrg extern bool reg_is_parm_p (rtx);
9010d565efSmrg
9110d565efSmrg /* Functions defined in regstat.c. */
9210d565efSmrg extern void regstat_init_n_sets_and_refs (void);
9310d565efSmrg extern void regstat_free_n_sets_and_refs (void);
9410d565efSmrg extern void regstat_compute_ri (void);
9510d565efSmrg extern void regstat_free_ri (void);
9610d565efSmrg extern bitmap regstat_get_setjmp_crosses (void);
9710d565efSmrg extern void regstat_compute_calls_crossed (void);
9810d565efSmrg extern void regstat_free_calls_crossed (void);
9910d565efSmrg extern void dump_reg_info (FILE *);
10010d565efSmrg
10110d565efSmrg /* Register information indexed by register number. This structure is
10210d565efSmrg initialized by calling regstat_compute_ri and is destroyed by
10310d565efSmrg calling regstat_free_ri. */
10410d565efSmrg struct reg_info_t
10510d565efSmrg {
10610d565efSmrg int freq; /* # estimated frequency (REG n) is used or set */
10710d565efSmrg int deaths; /* # of times (REG n) dies */
10810d565efSmrg int calls_crossed; /* # of calls (REG n) is live across */
10910d565efSmrg int basic_block; /* # of basic blocks (REG n) is used in */
11010d565efSmrg };
11110d565efSmrg
11210d565efSmrg extern struct reg_info_t *reg_info_p;
11310d565efSmrg
11410d565efSmrg /* The number allocated elements of reg_info_p. */
11510d565efSmrg extern size_t reg_info_p_size;
11610d565efSmrg
11710d565efSmrg /* Estimate frequency of references to register N. */
11810d565efSmrg
11910d565efSmrg #define REG_FREQ(N) (reg_info_p[N].freq)
12010d565efSmrg
12110d565efSmrg /* The weights for each insn varies from 0 to REG_FREQ_BASE.
12210d565efSmrg This constant does not need to be high, as in infrequently executed
12310d565efSmrg regions we want to count instructions equivalently to optimize for
12410d565efSmrg size instead of speed. */
12510d565efSmrg #define REG_FREQ_MAX 1000
12610d565efSmrg
12710d565efSmrg /* Compute register frequency from the BB frequency. When optimizing for size,
12810d565efSmrg or profile driven feedback is available and the function is never executed,
12910d565efSmrg frequency is always equivalent. Otherwise rescale the basic block
13010d565efSmrg frequency. */
131*ec02198aSmrg #define REG_FREQ_FROM_BB(bb) ((optimize_function_for_size_p (cfun) \
132*ec02198aSmrg || !cfun->cfg->count_max.initialized_p ()) \
13310d565efSmrg ? REG_FREQ_MAX \
134c7a68eb7Smrg : ((bb)->count.to_frequency (cfun) \
135c7a68eb7Smrg * REG_FREQ_MAX / BB_FREQ_MAX) \
136c7a68eb7Smrg ? ((bb)->count.to_frequency (cfun) \
137c7a68eb7Smrg * REG_FREQ_MAX / BB_FREQ_MAX) \
13810d565efSmrg : 1)
13910d565efSmrg
14010d565efSmrg /* Indexed by N, gives number of insns in which register N dies.
14110d565efSmrg Note that if register N is live around loops, it can die
14210d565efSmrg in transitions between basic blocks, and that is not counted here.
14310d565efSmrg So this is only a reliable indicator of how many regions of life there are
14410d565efSmrg for registers that are contained in one basic block. */
14510d565efSmrg
14610d565efSmrg #define REG_N_DEATHS(N) (reg_info_p[N].deaths)
14710d565efSmrg
14810d565efSmrg /* Get the number of consecutive words required to hold pseudo-reg N. */
14910d565efSmrg
15010d565efSmrg #define PSEUDO_REGNO_SIZE(N) \
15110d565efSmrg ((GET_MODE_SIZE (PSEUDO_REGNO_MODE (N)) + UNITS_PER_WORD - 1) \
15210d565efSmrg / UNITS_PER_WORD)
15310d565efSmrg
15410d565efSmrg /* Get the number of bytes required to hold pseudo-reg N. */
15510d565efSmrg
15610d565efSmrg #define PSEUDO_REGNO_BYTES(N) \
15710d565efSmrg GET_MODE_SIZE (PSEUDO_REGNO_MODE (N))
15810d565efSmrg
15910d565efSmrg /* Get the machine mode of pseudo-reg N. */
16010d565efSmrg
16110d565efSmrg #define PSEUDO_REGNO_MODE(N) GET_MODE (regno_reg_rtx[N])
16210d565efSmrg
16310d565efSmrg /* Indexed by N, gives number of CALL_INSNS across which (REG n) is live. */
16410d565efSmrg
16510d565efSmrg #define REG_N_CALLS_CROSSED(N) (reg_info_p[N].calls_crossed)
16610d565efSmrg
16710d565efSmrg /* Indexed by n, gives number of basic block that (REG n) is used in.
16810d565efSmrg If the value is REG_BLOCK_GLOBAL (-1),
16910d565efSmrg it means (REG n) is used in more than one basic block.
17010d565efSmrg REG_BLOCK_UNKNOWN (0) means it hasn't been seen yet so we don't know.
17110d565efSmrg This information remains valid for the rest of the compilation
17210d565efSmrg of the current function; it is used to control register allocation. */
17310d565efSmrg
17410d565efSmrg #define REG_BLOCK_UNKNOWN 0
17510d565efSmrg #define REG_BLOCK_GLOBAL -1
17610d565efSmrg
17710d565efSmrg #define REG_BASIC_BLOCK(N) (reg_info_p[N].basic_block)
17810d565efSmrg
17910d565efSmrg /* Vector of substitutions of register numbers,
18010d565efSmrg used to map pseudo regs into hardware regs.
18110d565efSmrg
18210d565efSmrg This can't be folded into reg_n_info without changing all of the
18310d565efSmrg machine dependent directories, since the reload functions
18410d565efSmrg in the machine dependent files access it. */
18510d565efSmrg
18610d565efSmrg extern short *reg_renumber;
18710d565efSmrg
18810d565efSmrg /* Flag set by local-alloc or global-alloc if they decide to allocate
18910d565efSmrg something in a call-clobbered register. */
19010d565efSmrg
19110d565efSmrg extern int caller_save_needed;
19210d565efSmrg
19310d565efSmrg /* Select a register mode required for caller save of hard regno REGNO. */
19410d565efSmrg #ifndef HARD_REGNO_CALLER_SAVE_MODE
19510d565efSmrg #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
196*ec02198aSmrg choose_hard_reg_mode (REGNO, NREGS, NULL)
19710d565efSmrg #endif
19810d565efSmrg
19910d565efSmrg /* Target-dependent globals. */
20010d565efSmrg struct target_regs {
20110d565efSmrg /* For each starting hard register, the number of consecutive hard
20210d565efSmrg registers that a given machine mode occupies. */
20310d565efSmrg unsigned char x_hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
20410d565efSmrg
20510d565efSmrg /* For each hard register, the widest mode object that it can contain.
20610d565efSmrg This will be a MODE_INT mode if the register can hold integers. Otherwise
20710d565efSmrg it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
20810d565efSmrg register. */
20910d565efSmrg machine_mode x_reg_raw_mode[FIRST_PSEUDO_REGISTER];
21010d565efSmrg
21110d565efSmrg /* Vector indexed by machine mode saying whether there are regs of
21210d565efSmrg that mode. */
21310d565efSmrg bool x_have_regs_of_mode[MAX_MACHINE_MODE];
21410d565efSmrg
21510d565efSmrg /* 1 if the corresponding class contains a register of the given mode. */
21610d565efSmrg char x_contains_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
21710d565efSmrg
21810d565efSmrg /* 1 if the corresponding class contains a register of the given mode
21910d565efSmrg which is not global and can therefore be allocated. */
22010d565efSmrg char x_contains_allocatable_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
22110d565efSmrg
22210d565efSmrg /* Record for each mode whether we can move a register directly to or
22310d565efSmrg from an object of that mode in memory. If we can't, we won't try
22410d565efSmrg to use that mode directly when accessing a field of that mode. */
22510d565efSmrg char x_direct_load[NUM_MACHINE_MODES];
22610d565efSmrg char x_direct_store[NUM_MACHINE_MODES];
22710d565efSmrg
22810d565efSmrg /* Record for each mode whether we can float-extend from memory. */
22910d565efSmrg bool x_float_extend_from_mem[NUM_MACHINE_MODES][NUM_MACHINE_MODES];
23010d565efSmrg };
23110d565efSmrg
23210d565efSmrg extern struct target_regs default_target_regs;
23310d565efSmrg #if SWITCHABLE_TARGET
23410d565efSmrg extern struct target_regs *this_target_regs;
23510d565efSmrg #else
23610d565efSmrg #define this_target_regs (&default_target_regs)
23710d565efSmrg #endif
23810d565efSmrg #define reg_raw_mode \
23910d565efSmrg (this_target_regs->x_reg_raw_mode)
24010d565efSmrg #define have_regs_of_mode \
24110d565efSmrg (this_target_regs->x_have_regs_of_mode)
24210d565efSmrg #define contains_reg_of_mode \
24310d565efSmrg (this_target_regs->x_contains_reg_of_mode)
24410d565efSmrg #define contains_allocatable_reg_of_mode \
24510d565efSmrg (this_target_regs->x_contains_allocatable_reg_of_mode)
24610d565efSmrg #define direct_load \
24710d565efSmrg (this_target_regs->x_direct_load)
24810d565efSmrg #define direct_store \
24910d565efSmrg (this_target_regs->x_direct_store)
25010d565efSmrg #define float_extend_from_mem \
25110d565efSmrg (this_target_regs->x_float_extend_from_mem)
25210d565efSmrg
253c7a68eb7Smrg /* Return the number of hard registers in (reg:MODE REGNO). */
254c7a68eb7Smrg
255c7a68eb7Smrg ALWAYS_INLINE unsigned char
hard_regno_nregs(unsigned int regno,machine_mode mode)256c7a68eb7Smrg hard_regno_nregs (unsigned int regno, machine_mode mode)
257c7a68eb7Smrg {
258c7a68eb7Smrg return this_target_regs->x_hard_regno_nregs[regno][mode];
259c7a68eb7Smrg }
260c7a68eb7Smrg
26110d565efSmrg /* Return an exclusive upper bound on the registers occupied by hard
26210d565efSmrg register (reg:MODE REGNO). */
26310d565efSmrg
26410d565efSmrg static inline unsigned int
end_hard_regno(machine_mode mode,unsigned int regno)26510d565efSmrg end_hard_regno (machine_mode mode, unsigned int regno)
26610d565efSmrg {
267c7a68eb7Smrg return regno + hard_regno_nregs (regno, mode);
26810d565efSmrg }
26910d565efSmrg
27010d565efSmrg /* Add to REGS all the registers required to store a value of mode MODE
27110d565efSmrg in register REGNO. */
27210d565efSmrg
27310d565efSmrg static inline void
add_to_hard_reg_set(HARD_REG_SET * regs,machine_mode mode,unsigned int regno)27410d565efSmrg add_to_hard_reg_set (HARD_REG_SET *regs, machine_mode mode,
27510d565efSmrg unsigned int regno)
27610d565efSmrg {
27710d565efSmrg unsigned int end_regno;
27810d565efSmrg
27910d565efSmrg end_regno = end_hard_regno (mode, regno);
28010d565efSmrg do
28110d565efSmrg SET_HARD_REG_BIT (*regs, regno);
28210d565efSmrg while (++regno < end_regno);
28310d565efSmrg }
28410d565efSmrg
28510d565efSmrg /* Likewise, but remove the registers. */
28610d565efSmrg
28710d565efSmrg static inline void
remove_from_hard_reg_set(HARD_REG_SET * regs,machine_mode mode,unsigned int regno)28810d565efSmrg remove_from_hard_reg_set (HARD_REG_SET *regs, machine_mode mode,
28910d565efSmrg unsigned int regno)
29010d565efSmrg {
29110d565efSmrg unsigned int end_regno;
29210d565efSmrg
29310d565efSmrg end_regno = end_hard_regno (mode, regno);
29410d565efSmrg do
29510d565efSmrg CLEAR_HARD_REG_BIT (*regs, regno);
29610d565efSmrg while (++regno < end_regno);
29710d565efSmrg }
29810d565efSmrg
29910d565efSmrg /* Return true if REGS contains the whole of (reg:MODE REGNO). */
30010d565efSmrg
30110d565efSmrg static inline bool
in_hard_reg_set_p(const_hard_reg_set regs,machine_mode mode,unsigned int regno)302*ec02198aSmrg in_hard_reg_set_p (const_hard_reg_set regs, machine_mode mode,
30310d565efSmrg unsigned int regno)
30410d565efSmrg {
30510d565efSmrg unsigned int end_regno;
30610d565efSmrg
30710d565efSmrg gcc_assert (HARD_REGISTER_NUM_P (regno));
30810d565efSmrg
30910d565efSmrg if (!TEST_HARD_REG_BIT (regs, regno))
31010d565efSmrg return false;
31110d565efSmrg
31210d565efSmrg end_regno = end_hard_regno (mode, regno);
31310d565efSmrg
31410d565efSmrg if (!HARD_REGISTER_NUM_P (end_regno - 1))
31510d565efSmrg return false;
31610d565efSmrg
31710d565efSmrg while (++regno < end_regno)
31810d565efSmrg if (!TEST_HARD_REG_BIT (regs, regno))
31910d565efSmrg return false;
32010d565efSmrg
32110d565efSmrg return true;
32210d565efSmrg }
32310d565efSmrg
32410d565efSmrg /* Return true if (reg:MODE REGNO) includes an element of REGS. */
32510d565efSmrg
32610d565efSmrg static inline bool
overlaps_hard_reg_set_p(const_hard_reg_set regs,machine_mode mode,unsigned int regno)327*ec02198aSmrg overlaps_hard_reg_set_p (const_hard_reg_set regs, machine_mode mode,
32810d565efSmrg unsigned int regno)
32910d565efSmrg {
33010d565efSmrg unsigned int end_regno;
33110d565efSmrg
33210d565efSmrg if (TEST_HARD_REG_BIT (regs, regno))
33310d565efSmrg return true;
33410d565efSmrg
33510d565efSmrg end_regno = end_hard_regno (mode, regno);
33610d565efSmrg while (++regno < end_regno)
33710d565efSmrg if (TEST_HARD_REG_BIT (regs, regno))
33810d565efSmrg return true;
33910d565efSmrg
34010d565efSmrg return false;
34110d565efSmrg }
34210d565efSmrg
34310d565efSmrg /* Like add_to_hard_reg_set, but use a REGNO/NREGS range instead of
34410d565efSmrg REGNO and MODE. */
34510d565efSmrg
34610d565efSmrg static inline void
add_range_to_hard_reg_set(HARD_REG_SET * regs,unsigned int regno,int nregs)34710d565efSmrg add_range_to_hard_reg_set (HARD_REG_SET *regs, unsigned int regno,
34810d565efSmrg int nregs)
34910d565efSmrg {
35010d565efSmrg while (nregs-- > 0)
35110d565efSmrg SET_HARD_REG_BIT (*regs, regno + nregs);
35210d565efSmrg }
35310d565efSmrg
35410d565efSmrg /* Likewise, but remove the registers. */
35510d565efSmrg
35610d565efSmrg static inline void
remove_range_from_hard_reg_set(HARD_REG_SET * regs,unsigned int regno,int nregs)35710d565efSmrg remove_range_from_hard_reg_set (HARD_REG_SET *regs, unsigned int regno,
35810d565efSmrg int nregs)
35910d565efSmrg {
36010d565efSmrg while (nregs-- > 0)
36110d565efSmrg CLEAR_HARD_REG_BIT (*regs, regno + nregs);
36210d565efSmrg }
36310d565efSmrg
36410d565efSmrg /* Like overlaps_hard_reg_set_p, but use a REGNO/NREGS range instead of
36510d565efSmrg REGNO and MODE. */
36610d565efSmrg static inline bool
range_overlaps_hard_reg_set_p(const_hard_reg_set set,unsigned regno,int nregs)367*ec02198aSmrg range_overlaps_hard_reg_set_p (const_hard_reg_set set, unsigned regno,
36810d565efSmrg int nregs)
36910d565efSmrg {
37010d565efSmrg while (nregs-- > 0)
37110d565efSmrg if (TEST_HARD_REG_BIT (set, regno + nregs))
37210d565efSmrg return true;
37310d565efSmrg return false;
37410d565efSmrg }
37510d565efSmrg
37610d565efSmrg /* Like in_hard_reg_set_p, but use a REGNO/NREGS range instead of
37710d565efSmrg REGNO and MODE. */
37810d565efSmrg static inline bool
range_in_hard_reg_set_p(const_hard_reg_set set,unsigned regno,int nregs)379*ec02198aSmrg range_in_hard_reg_set_p (const_hard_reg_set set, unsigned regno, int nregs)
38010d565efSmrg {
38110d565efSmrg while (nregs-- > 0)
38210d565efSmrg if (!TEST_HARD_REG_BIT (set, regno + nregs))
38310d565efSmrg return false;
38410d565efSmrg return true;
38510d565efSmrg }
38610d565efSmrg
38710d565efSmrg #endif /* GCC_REGS_H */
388