1*a65fc664Schristos# frv testcase to generate fp_exception 2*a65fc664Schristos# mach: fr550 3*a65fc664Schristos .include "testutils.inc" 4*a65fc664Schristos 5*a65fc664Schristos float_constants 6*a65fc664Schristos start 7*a65fc664Schristos load_float_constants 8*a65fc664Schristos 9*a65fc664Schristos .global align 10*a65fc664Schristosalign: 11*a65fc664Schristos ; clear the packing bit if the insn at 'pack:'. We can't simply use 12*a65fc664Schristos ; '.p' because the assembler will catch the error. 13*a65fc664Schristos set_gr_mem pack,gr10 14*a65fc664Schristos and_gr_immed 0x7fffffff,gr10 15*a65fc664Schristos set_mem_gr gr10,pack 16*a65fc664Schristos set_gr_addr pack,gr10 17*a65fc664Schristos flush_data_cache gr10 18*a65fc664Schristos 19*a65fc664Schristos ; Make the the source register number odd at badst. We can't simply 20*a65fc664Schristos ; code an odd register number because the assembler will catch the 21*a65fc664Schristos ; error. 22*a65fc664Schristos set_gr_mem badst,gr10 23*a65fc664Schristos or_gr_immed 0x02000000,gr10 24*a65fc664Schristos set_mem_gr gr10,badst 25*a65fc664Schristos set_gr_addr badst,gr10 26*a65fc664Schristos flush_data_cache gr10 27*a65fc664Schristos 28*a65fc664Schristos ; Make the the dest register number odd at badld. We can't simply 29*a65fc664Schristos ; code an odd register number because the assembler will catch the 30*a65fc664Schristos ; error. 31*a65fc664Schristos set_gr_mem badld,gr10 32*a65fc664Schristos or_gr_immed 0x02000000,gr10 33*a65fc664Schristos set_mem_gr gr10,badld 34*a65fc664Schristos set_gr_addr badld,gr10 35*a65fc664Schristos flush_data_cache gr10 36*a65fc664Schristos 37*a65fc664Schristos and_spr_immed -4081,tbr ; clear tbr.tt 38*a65fc664Schristos set_gr_spr tbr,gr17 39*a65fc664Schristos inc_gr_immed 0x070,gr17 ; address of exception handler 40*a65fc664Schristos set_bctrlr_0_0 gr17 41*a65fc664Schristos inc_gr_immed 0x060,gr17 ; address of exception handler 42*a65fc664Schristos set_bctrlr_0_0 gr17 43*a65fc664Schristos set_spr_immed 128,lcr 44*a65fc664Schristos set_spr_addr ok1,lr 45*a65fc664Schristos set_psr_et 1 46*a65fc664Schristos inc_gr_immed -4,sp ; for alignment 47*a65fc664Schristos 48*a65fc664Schristos set_gr_immed 0,gr20 ; PC increment 49*a65fc664Schristos set_gr_immed 0,gr15 50*a65fc664Schristos 51*a65fc664Schristos set_spr_addr ok3,lr 52*a65fc664Schristos set_gr_immed 4,gr20 ; PC increment 53*a65fc664Schristosbadst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 54*a65fc664Schristos test_gr_immed 1,gr15 55*a65fc664Schristos 56*a65fc664Schristos set_spr_addr ok4,lr 57*a65fc664Schristos set_gr_immed 8,gr20 ; PC increment 58*a65fc664Schristos nop.p 59*a65fc664Schristosbadld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 60*a65fc664Schristos test_gr_immed 2,gr15 61*a65fc664Schristos 62*a65fc664Schristos set_spr_addr ok5,lr 63*a65fc664Schristos set_gr_immed 20,gr20 ; PC increment 64*a65fc664Schristos fnegs.p fr9,fr9 65*a65fc664Schristos fnegs.p fr9,fr10 66*a65fc664Schristos fnegs.p fr9,fr11 67*a65fc664Schristospack: fnegs fr10,fr12 68*a65fc664Schristos fnegs fr10,fr13 ; packing violation 69*a65fc664Schristos test_gr_immed 3,gr15 70*a65fc664Schristos 71*a65fc664Schristos set_spr_addr ok1,lr 72*a65fc664Schristos set_gr_immed 4,gr20 ; PC increment 73*a65fc664Schristosbad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) 74*a65fc664Schristos test_gr_immed 4,gr15 75*a65fc664Schristos 76*a65fc664Schristos and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception 77*a65fc664Schristos set_fr_iimmed 0x7f7f,0xffff,fr0 78*a65fc664Schristos set_fr_iimmed 0x0000,0x0000,fr1 79*a65fc664Schristos fdivs fr0,fr1,fr2 ; div/0 -- no exception 80*a65fc664Schristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set 81*a65fc664Schristos test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set 82*a65fc664Schristos test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear 83*a65fc664Schristos 84*a65fc664Schristos set_spr_addr ok2,lr 85*a65fc664Schristos set_gr_immed 0,gr20 ; PC increment 86*a65fc664Schristos or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception 87*a65fc664Schristos set_fr_iimmed 0xdead,0xbeef,fr2 88*a65fc664Schristosdiv0: fdivs fr0,fr1,fr2 ; fp_exception - div/0 89*a65fc664Schristos test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated 90*a65fc664Schristos test_gr_immed 5,gr15 91*a65fc664Schristos 92*a65fc664Schristos and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception 93*a65fc664Schristos fsqrts fr32,fr2 ; inexact -- no exception 94*a65fc664Schristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set 95*a65fc664Schristos test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set 96*a65fc664Schristos test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear 97*a65fc664Schristos 98*a65fc664Schristos set_fr_fr fr2,fr3 ; sqrt 2 99*a65fc664Schristos set_fr_iimmed 0xdead,0xbeef,fr2 100*a65fc664Schristos set_spr_addr ok6,lr 101*a65fc664Schristos or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception 102*a65fc664Schristosinxt1: fsqrts fr32,fr2 ; fp_exception - inexact 103*a65fc664Schristos test_gr_immed 6,gr15 ; handler called 104*a65fc664Schristos test_fr_fr fr2,fr3 ; fr2 updated 105*a65fc664Schristos 106*a65fc664Schristos set_fr_iimmed 0xdead,0xbeef,fr2 107*a65fc664Schristos set_spr_addr ok7,lr 108*a65fc664Schristosinxt2: fsqrts fr32,fr2 ; fp_exception - inexact again 109*a65fc664Schristos test_gr_immed 7,gr15 ; handler called 110*a65fc664Schristos test_fr_fr fr2,fr3 ; fr2 updated 111*a65fc664Schristos 112*a65fc664Schristos pass 113*a65fc664Schristos 114*a65fc664Schristos; exception handler 1 -- illegal_instruction: bad insn 115*a65fc664Schristosok1: 116*a65fc664Schristos test_spr_immed 1,esfr1 ; esr0 active 117*a65fc664Schristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 118*a65fc664Schristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 119*a65fc664Schristos bra ret 120*a65fc664Schristos 121*a65fc664Schristos; exception handler 2 - fp_exception: divide by 0 122*a65fc664Schristosok2: 123*a65fc664Schristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 124*a65fc664Schristos test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 125*a65fc664Schristos test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set 126*a65fc664Schristos 127*a65fc664Schristos test_spr_immed 4,esfr1 ; esr2 active 128*a65fc664Schristos test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 129*a65fc664Schristos test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 130*a65fc664Schristos test_spr_addr div0,epcr2 ; epcr2 is set 131*a65fc664Schristos bra ret 132*a65fc664Schristos 133*a65fc664Schristos; exception handler 3 - illegal_instruction: register exception 134*a65fc664Schristosok3: 135*a65fc664Schristos test_spr_immed 1,esfr1 ; esr0 active 136*a65fc664Schristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 137*a65fc664Schristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 138*a65fc664Schristos bra ret 139*a65fc664Schristos 140*a65fc664Schristos; exception handler 4 - illegal_instruction: register exception 141*a65fc664Schristosok4: 142*a65fc664Schristos test_spr_immed 1,esfr1 ; esr0 active 143*a65fc664Schristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 144*a65fc664Schristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 145*a65fc664Schristos bra ret 146*a65fc664Schristos 147*a65fc664Schristos; exception handler 5 - illegal_instruction: sequence violation 148*a65fc664Schristosok5: 149*a65fc664Schristos test_spr_immed 1,esfr1 ; esr0 active 150*a65fc664Schristos test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 151*a65fc664Schristos test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 152*a65fc664Schristos bra ret 153*a65fc664Schristos 154*a65fc664Schristos; exception handler 6 - fp_exception: inexact 155*a65fc664Schristosok6: 156*a65fc664Schristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 157*a65fc664Schristos test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 158*a65fc664Schristos test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set 159*a65fc664Schristos 160*a65fc664Schristos test_spr_immed 4,esfr1 ; esr2 active 161*a65fc664Schristos test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 162*a65fc664Schristos test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 163*a65fc664Schristos test_spr_addr inxt1,epcr2 ; epcr2 is set 164*a65fc664Schristos bra ret 165*a65fc664Schristos 166*a65fc664Schristos; exception handler 7 - fp_exception: inexact again 167*a65fc664Schristosok7: 168*a65fc664Schristos test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 169*a65fc664Schristos test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 170*a65fc664Schristos test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set 171*a65fc664Schristos 172*a65fc664Schristos test_spr_immed 4,esfr1 ; esr2 active 173*a65fc664Schristos test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 174*a65fc664Schristos test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 175*a65fc664Schristos test_spr_addr inxt2,epcr2 ; epcr2 is set 176*a65fc664Schristos bra ret 177*a65fc664Schristos 178*a65fc664Schristosret: 179*a65fc664Schristos inc_gr_immed 1,gr15 180*a65fc664Schristos movsg pcsr,gr60 181*a65fc664Schristos add gr60,gr20,gr60 182*a65fc664Schristos movgs gr60,pcsr 183*a65fc664Schristos rett 0 184*a65fc664Schristos fail 185*a65fc664Schristos 186