1*1424dfb3Schristos@c Copyright (C) 1991-2020 Free Software Foundation, Inc. 2*1424dfb3Schristos@c This is part of the GAS manual. 3*1424dfb3Schristos@c For copying conditions, see the file as.texinfo. 4*1424dfb3Schristos@c man end 5*1424dfb3Schristos 6*1424dfb3Schristos@ifset GENERIC 7*1424dfb3Schristos@page 8*1424dfb3Schristos@node i386-Dependent 9*1424dfb3Schristos@chapter 80386 Dependent Features 10*1424dfb3Schristos@end ifset 11*1424dfb3Schristos@ifclear GENERIC 12*1424dfb3Schristos@node Machine Dependencies 13*1424dfb3Schristos@chapter 80386 Dependent Features 14*1424dfb3Schristos@end ifclear 15*1424dfb3Schristos 16*1424dfb3Schristos@cindex i386 support 17*1424dfb3Schristos@cindex i80386 support 18*1424dfb3Schristos@cindex x86-64 support 19*1424dfb3Schristos 20*1424dfb3SchristosThe i386 version @code{@value{AS}} supports both the original Intel 386 21*1424dfb3Schristosarchitecture in both 16 and 32-bit mode as well as AMD x86-64 architecture 22*1424dfb3Schristosextending the Intel architecture to 64-bits. 23*1424dfb3Schristos 24*1424dfb3Schristos@menu 25*1424dfb3Schristos* i386-Options:: Options 26*1424dfb3Schristos* i386-Directives:: X86 specific directives 27*1424dfb3Schristos* i386-Syntax:: Syntactical considerations 28*1424dfb3Schristos* i386-Mnemonics:: Instruction Naming 29*1424dfb3Schristos* i386-Regs:: Register Naming 30*1424dfb3Schristos* i386-Prefixes:: Instruction Prefixes 31*1424dfb3Schristos* i386-Memory:: Memory References 32*1424dfb3Schristos* i386-Jumps:: Handling of Jump Instructions 33*1424dfb3Schristos* i386-Float:: Floating Point 34*1424dfb3Schristos* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 35*1424dfb3Schristos* i386-LWP:: AMD's Lightweight Profiling Instructions 36*1424dfb3Schristos* i386-BMI:: Bit Manipulation Instruction 37*1424dfb3Schristos* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 38*1424dfb3Schristos* i386-16bit:: Writing 16-bit Code 39*1424dfb3Schristos* i386-Arch:: Specifying an x86 CPU architecture 40*1424dfb3Schristos* i386-ISA:: AMD64 ISA vs. Intel64 ISA 41*1424dfb3Schristos* i386-Bugs:: AT&T Syntax bugs 42*1424dfb3Schristos* i386-Notes:: Notes 43*1424dfb3Schristos@end menu 44*1424dfb3Schristos 45*1424dfb3Schristos@node i386-Options 46*1424dfb3Schristos@section Options 47*1424dfb3Schristos 48*1424dfb3Schristos@cindex options for i386 49*1424dfb3Schristos@cindex options for x86-64 50*1424dfb3Schristos@cindex i386 options 51*1424dfb3Schristos@cindex x86-64 options 52*1424dfb3Schristos 53*1424dfb3SchristosThe i386 version of @code{@value{AS}} has a few machine 54*1424dfb3Schristosdependent options: 55*1424dfb3Schristos 56*1424dfb3Schristos@c man begin OPTIONS 57*1424dfb3Schristos@table @gcctabopt 58*1424dfb3Schristos@cindex @samp{--32} option, i386 59*1424dfb3Schristos@cindex @samp{--32} option, x86-64 60*1424dfb3Schristos@cindex @samp{--x32} option, i386 61*1424dfb3Schristos@cindex @samp{--x32} option, x86-64 62*1424dfb3Schristos@cindex @samp{--64} option, i386 63*1424dfb3Schristos@cindex @samp{--64} option, x86-64 64*1424dfb3Schristos@item --32 | --x32 | --64 65*1424dfb3SchristosSelect the word size, either 32 bits or 64 bits. @samp{--32} 66*1424dfb3Schristosimplies Intel i386 architecture, while @samp{--x32} and @samp{--64} 67*1424dfb3Schristosimply AMD x86-64 architecture with 32-bit or 64-bit word-size 68*1424dfb3Schristosrespectively. 69*1424dfb3Schristos 70*1424dfb3SchristosThese options are only available with the ELF object file format, and 71*1424dfb3Schristosrequire that the necessary BFD support has been included (on a 32-bit 72*1424dfb3Schristosplatform you have to add --enable-64-bit-bfd to configure enable 64-bit 73*1424dfb3Schristosusage and use x86-64 as target platform). 74*1424dfb3Schristos 75*1424dfb3Schristos@item -n 76*1424dfb3SchristosBy default, x86 GAS replaces multiple nop instructions used for 77*1424dfb3Schristosalignment within code sections with multi-byte nop instructions such 78*1424dfb3Schristosas leal 0(%esi,1),%esi. This switch disables the optimization if a single 79*1424dfb3Schristosbyte nop (0x90) is explicitly specified as the fill byte for alignment. 80*1424dfb3Schristos 81*1424dfb3Schristos@cindex @samp{--divide} option, i386 82*1424dfb3Schristos@item --divide 83*1424dfb3SchristosOn SVR4-derived platforms, the character @samp{/} is treated as a comment 84*1424dfb3Schristoscharacter, which means that it cannot be used in expressions. The 85*1424dfb3Schristos@samp{--divide} option turns @samp{/} into a normal character. This does 86*1424dfb3Schristosnot disable @samp{/} at the beginning of a line starting a comment, or 87*1424dfb3Schristosaffect using @samp{#} for starting a comment. 88*1424dfb3Schristos 89*1424dfb3Schristos@cindex @samp{-march=} option, i386 90*1424dfb3Schristos@cindex @samp{-march=} option, x86-64 91*1424dfb3Schristos@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] 92*1424dfb3SchristosThis option specifies the target processor. The assembler will 93*1424dfb3Schristosissue an error message if an attempt is made to assemble an instruction 94*1424dfb3Schristoswhich will not execute on the target processor. The following 95*1424dfb3Schristosprocessor names are recognized: 96*1424dfb3Schristos@code{i8086}, 97*1424dfb3Schristos@code{i186}, 98*1424dfb3Schristos@code{i286}, 99*1424dfb3Schristos@code{i386}, 100*1424dfb3Schristos@code{i486}, 101*1424dfb3Schristos@code{i586}, 102*1424dfb3Schristos@code{i686}, 103*1424dfb3Schristos@code{pentium}, 104*1424dfb3Schristos@code{pentiumpro}, 105*1424dfb3Schristos@code{pentiumii}, 106*1424dfb3Schristos@code{pentiumiii}, 107*1424dfb3Schristos@code{pentium4}, 108*1424dfb3Schristos@code{prescott}, 109*1424dfb3Schristos@code{nocona}, 110*1424dfb3Schristos@code{core}, 111*1424dfb3Schristos@code{core2}, 112*1424dfb3Schristos@code{corei7}, 113*1424dfb3Schristos@code{l1om}, 114*1424dfb3Schristos@code{k1om}, 115*1424dfb3Schristos@code{iamcu}, 116*1424dfb3Schristos@code{k6}, 117*1424dfb3Schristos@code{k6_2}, 118*1424dfb3Schristos@code{athlon}, 119*1424dfb3Schristos@code{opteron}, 120*1424dfb3Schristos@code{k8}, 121*1424dfb3Schristos@code{amdfam10}, 122*1424dfb3Schristos@code{bdver1}, 123*1424dfb3Schristos@code{bdver2}, 124*1424dfb3Schristos@code{bdver3}, 125*1424dfb3Schristos@code{bdver4}, 126*1424dfb3Schristos@code{znver1}, 127*1424dfb3Schristos@code{znver2}, 128*1424dfb3Schristos@code{btver1}, 129*1424dfb3Schristos@code{btver2}, 130*1424dfb3Schristos@code{generic32} and 131*1424dfb3Schristos@code{generic64}. 132*1424dfb3Schristos 133*1424dfb3SchristosIn addition to the basic instruction set, the assembler can be told to 134*1424dfb3Schristosaccept various extension mnemonics. For example, 135*1424dfb3Schristos@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and 136*1424dfb3Schristos@var{vmx}. The following extensions are currently supported: 137*1424dfb3Schristos@code{8087}, 138*1424dfb3Schristos@code{287}, 139*1424dfb3Schristos@code{387}, 140*1424dfb3Schristos@code{687}, 141*1424dfb3Schristos@code{no87}, 142*1424dfb3Schristos@code{no287}, 143*1424dfb3Schristos@code{no387}, 144*1424dfb3Schristos@code{no687}, 145*1424dfb3Schristos@code{cmov}, 146*1424dfb3Schristos@code{nocmov}, 147*1424dfb3Schristos@code{fxsr}, 148*1424dfb3Schristos@code{nofxsr}, 149*1424dfb3Schristos@code{mmx}, 150*1424dfb3Schristos@code{nommx}, 151*1424dfb3Schristos@code{sse}, 152*1424dfb3Schristos@code{sse2}, 153*1424dfb3Schristos@code{sse3}, 154*1424dfb3Schristos@code{sse4a}, 155*1424dfb3Schristos@code{ssse3}, 156*1424dfb3Schristos@code{sse4.1}, 157*1424dfb3Schristos@code{sse4.2}, 158*1424dfb3Schristos@code{sse4}, 159*1424dfb3Schristos@code{nosse}, 160*1424dfb3Schristos@code{nosse2}, 161*1424dfb3Schristos@code{nosse3}, 162*1424dfb3Schristos@code{nosse4a}, 163*1424dfb3Schristos@code{nossse3}, 164*1424dfb3Schristos@code{nosse4.1}, 165*1424dfb3Schristos@code{nosse4.2}, 166*1424dfb3Schristos@code{nosse4}, 167*1424dfb3Schristos@code{avx}, 168*1424dfb3Schristos@code{avx2}, 169*1424dfb3Schristos@code{noavx}, 170*1424dfb3Schristos@code{noavx2}, 171*1424dfb3Schristos@code{adx}, 172*1424dfb3Schristos@code{rdseed}, 173*1424dfb3Schristos@code{prfchw}, 174*1424dfb3Schristos@code{smap}, 175*1424dfb3Schristos@code{mpx}, 176*1424dfb3Schristos@code{sha}, 177*1424dfb3Schristos@code{rdpid}, 178*1424dfb3Schristos@code{ptwrite}, 179*1424dfb3Schristos@code{cet}, 180*1424dfb3Schristos@code{gfni}, 181*1424dfb3Schristos@code{vaes}, 182*1424dfb3Schristos@code{vpclmulqdq}, 183*1424dfb3Schristos@code{prefetchwt1}, 184*1424dfb3Schristos@code{clflushopt}, 185*1424dfb3Schristos@code{se1}, 186*1424dfb3Schristos@code{clwb}, 187*1424dfb3Schristos@code{movdiri}, 188*1424dfb3Schristos@code{movdir64b}, 189*1424dfb3Schristos@code{enqcmd}, 190*1424dfb3Schristos@code{serialize}, 191*1424dfb3Schristos@code{tsxldtrk}, 192*1424dfb3Schristos@code{avx512f}, 193*1424dfb3Schristos@code{avx512cd}, 194*1424dfb3Schristos@code{avx512er}, 195*1424dfb3Schristos@code{avx512pf}, 196*1424dfb3Schristos@code{avx512vl}, 197*1424dfb3Schristos@code{avx512bw}, 198*1424dfb3Schristos@code{avx512dq}, 199*1424dfb3Schristos@code{avx512ifma}, 200*1424dfb3Schristos@code{avx512vbmi}, 201*1424dfb3Schristos@code{avx512_4fmaps}, 202*1424dfb3Schristos@code{avx512_4vnniw}, 203*1424dfb3Schristos@code{avx512_vpopcntdq}, 204*1424dfb3Schristos@code{avx512_vbmi2}, 205*1424dfb3Schristos@code{avx512_vnni}, 206*1424dfb3Schristos@code{avx512_bitalg}, 207*1424dfb3Schristos@code{avx512_vp2intersect}, 208*1424dfb3Schristos@code{avx512_bf16}, 209*1424dfb3Schristos@code{noavx512f}, 210*1424dfb3Schristos@code{noavx512cd}, 211*1424dfb3Schristos@code{noavx512er}, 212*1424dfb3Schristos@code{noavx512pf}, 213*1424dfb3Schristos@code{noavx512vl}, 214*1424dfb3Schristos@code{noavx512bw}, 215*1424dfb3Schristos@code{noavx512dq}, 216*1424dfb3Schristos@code{noavx512ifma}, 217*1424dfb3Schristos@code{noavx512vbmi}, 218*1424dfb3Schristos@code{noavx512_4fmaps}, 219*1424dfb3Schristos@code{noavx512_4vnniw}, 220*1424dfb3Schristos@code{noavx512_vpopcntdq}, 221*1424dfb3Schristos@code{noavx512_vbmi2}, 222*1424dfb3Schristos@code{noavx512_vnni}, 223*1424dfb3Schristos@code{noavx512_bitalg}, 224*1424dfb3Schristos@code{noavx512_vp2intersect}, 225*1424dfb3Schristos@code{noavx512_bf16}, 226*1424dfb3Schristos@code{noenqcmd}, 227*1424dfb3Schristos@code{noserialize}, 228*1424dfb3Schristos@code{notsxldtrk}, 229*1424dfb3Schristos@code{amx_int8}, 230*1424dfb3Schristos@code{noamx_int8}, 231*1424dfb3Schristos@code{amx_bf16}, 232*1424dfb3Schristos@code{noamx_bf16}, 233*1424dfb3Schristos@code{amx_tile}, 234*1424dfb3Schristos@code{noamx_tile}, 235*1424dfb3Schristos@code{vmx}, 236*1424dfb3Schristos@code{vmfunc}, 237*1424dfb3Schristos@code{smx}, 238*1424dfb3Schristos@code{xsave}, 239*1424dfb3Schristos@code{xsaveopt}, 240*1424dfb3Schristos@code{xsavec}, 241*1424dfb3Schristos@code{xsaves}, 242*1424dfb3Schristos@code{aes}, 243*1424dfb3Schristos@code{pclmul}, 244*1424dfb3Schristos@code{fsgsbase}, 245*1424dfb3Schristos@code{rdrnd}, 246*1424dfb3Schristos@code{f16c}, 247*1424dfb3Schristos@code{bmi2}, 248*1424dfb3Schristos@code{fma}, 249*1424dfb3Schristos@code{movbe}, 250*1424dfb3Schristos@code{ept}, 251*1424dfb3Schristos@code{lzcnt}, 252*1424dfb3Schristos@code{popcnt}, 253*1424dfb3Schristos@code{hle}, 254*1424dfb3Schristos@code{rtm}, 255*1424dfb3Schristos@code{invpcid}, 256*1424dfb3Schristos@code{clflush}, 257*1424dfb3Schristos@code{mwaitx}, 258*1424dfb3Schristos@code{clzero}, 259*1424dfb3Schristos@code{wbnoinvd}, 260*1424dfb3Schristos@code{pconfig}, 261*1424dfb3Schristos@code{waitpkg}, 262*1424dfb3Schristos@code{cldemote}, 263*1424dfb3Schristos@code{rdpru}, 264*1424dfb3Schristos@code{mcommit}, 265*1424dfb3Schristos@code{sev_es}, 266*1424dfb3Schristos@code{lwp}, 267*1424dfb3Schristos@code{fma4}, 268*1424dfb3Schristos@code{xop}, 269*1424dfb3Schristos@code{cx16}, 270*1424dfb3Schristos@code{syscall}, 271*1424dfb3Schristos@code{rdtscp}, 272*1424dfb3Schristos@code{3dnow}, 273*1424dfb3Schristos@code{3dnowa}, 274*1424dfb3Schristos@code{sse4a}, 275*1424dfb3Schristos@code{sse5}, 276*1424dfb3Schristos@code{svme} and 277*1424dfb3Schristos@code{padlock}. 278*1424dfb3SchristosNote that rather than extending a basic instruction set, the extension 279*1424dfb3Schristosmnemonics starting with @code{no} revoke the respective functionality. 280*1424dfb3Schristos 281*1424dfb3SchristosWhen the @code{.arch} directive is used with @option{-march}, the 282*1424dfb3Schristos@code{.arch} directive will take precedent. 283*1424dfb3Schristos 284*1424dfb3Schristos@cindex @samp{-mtune=} option, i386 285*1424dfb3Schristos@cindex @samp{-mtune=} option, x86-64 286*1424dfb3Schristos@item -mtune=@var{CPU} 287*1424dfb3SchristosThis option specifies a processor to optimize for. When used in 288*1424dfb3Schristosconjunction with the @option{-march} option, only instructions 289*1424dfb3Schristosof the processor specified by the @option{-march} option will be 290*1424dfb3Schristosgenerated. 291*1424dfb3Schristos 292*1424dfb3SchristosValid @var{CPU} values are identical to the processor list of 293*1424dfb3Schristos@option{-march=@var{CPU}}. 294*1424dfb3Schristos 295*1424dfb3Schristos@cindex @samp{-msse2avx} option, i386 296*1424dfb3Schristos@cindex @samp{-msse2avx} option, x86-64 297*1424dfb3Schristos@item -msse2avx 298*1424dfb3SchristosThis option specifies that the assembler should encode SSE instructions 299*1424dfb3Schristoswith VEX prefix. 300*1424dfb3Schristos 301*1424dfb3Schristos@cindex @samp{-msse-check=} option, i386 302*1424dfb3Schristos@cindex @samp{-msse-check=} option, x86-64 303*1424dfb3Schristos@item -msse-check=@var{none} 304*1424dfb3Schristos@itemx -msse-check=@var{warning} 305*1424dfb3Schristos@itemx -msse-check=@var{error} 306*1424dfb3SchristosThese options control if the assembler should check SSE instructions. 307*1424dfb3Schristos@option{-msse-check=@var{none}} will make the assembler not to check SSE 308*1424dfb3Schristosinstructions, which is the default. @option{-msse-check=@var{warning}} 309*1424dfb3Schristoswill make the assembler issue a warning for any SSE instruction. 310*1424dfb3Schristos@option{-msse-check=@var{error}} will make the assembler issue an error 311*1424dfb3Schristosfor any SSE instruction. 312*1424dfb3Schristos 313*1424dfb3Schristos@cindex @samp{-mavxscalar=} option, i386 314*1424dfb3Schristos@cindex @samp{-mavxscalar=} option, x86-64 315*1424dfb3Schristos@item -mavxscalar=@var{128} 316*1424dfb3Schristos@itemx -mavxscalar=@var{256} 317*1424dfb3SchristosThese options control how the assembler should encode scalar AVX 318*1424dfb3Schristosinstructions. @option{-mavxscalar=@var{128}} will encode scalar 319*1424dfb3SchristosAVX instructions with 128bit vector length, which is the default. 320*1424dfb3Schristos@option{-mavxscalar=@var{256}} will encode scalar AVX instructions 321*1424dfb3Schristoswith 256bit vector length. 322*1424dfb3Schristos 323*1424dfb3SchristosWARNING: Don't use this for production code - due to CPU errata the 324*1424dfb3Schristosresulting code may not work on certain models. 325*1424dfb3Schristos 326*1424dfb3Schristos@cindex @samp{-mvexwig=} option, i386 327*1424dfb3Schristos@cindex @samp{-mvexwig=} option, x86-64 328*1424dfb3Schristos@item -mvexwig=@var{0} 329*1424dfb3Schristos@itemx -mvexwig=@var{1} 330*1424dfb3SchristosThese options control how the assembler should encode VEX.W-ignored (WIG) 331*1424dfb3SchristosVEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX 332*1424dfb3Schristosinstructions with vex.w = 0, which is the default. 333*1424dfb3Schristos@option{-mvexwig=@var{1}} will encode WIG EVEX instructions with 334*1424dfb3Schristosvex.w = 1. 335*1424dfb3Schristos 336*1424dfb3SchristosWARNING: Don't use this for production code - due to CPU errata the 337*1424dfb3Schristosresulting code may not work on certain models. 338*1424dfb3Schristos 339*1424dfb3Schristos@cindex @samp{-mevexlig=} option, i386 340*1424dfb3Schristos@cindex @samp{-mevexlig=} option, x86-64 341*1424dfb3Schristos@item -mevexlig=@var{128} 342*1424dfb3Schristos@itemx -mevexlig=@var{256} 343*1424dfb3Schristos@itemx -mevexlig=@var{512} 344*1424dfb3SchristosThese options control how the assembler should encode length-ignored 345*1424dfb3Schristos(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG 346*1424dfb3SchristosEVEX instructions with 128bit vector length, which is the default. 347*1424dfb3Schristos@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will 348*1424dfb3Schristosencode LIG EVEX instructions with 256bit and 512bit vector length, 349*1424dfb3Schristosrespectively. 350*1424dfb3Schristos 351*1424dfb3Schristos@cindex @samp{-mevexwig=} option, i386 352*1424dfb3Schristos@cindex @samp{-mevexwig=} option, x86-64 353*1424dfb3Schristos@item -mevexwig=@var{0} 354*1424dfb3Schristos@itemx -mevexwig=@var{1} 355*1424dfb3SchristosThese options control how the assembler should encode w-ignored (WIG) 356*1424dfb3SchristosEVEX instructions. @option{-mevexwig=@var{0}} will encode WIG 357*1424dfb3SchristosEVEX instructions with evex.w = 0, which is the default. 358*1424dfb3Schristos@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with 359*1424dfb3Schristosevex.w = 1. 360*1424dfb3Schristos 361*1424dfb3Schristos@cindex @samp{-mmnemonic=} option, i386 362*1424dfb3Schristos@cindex @samp{-mmnemonic=} option, x86-64 363*1424dfb3Schristos@item -mmnemonic=@var{att} 364*1424dfb3Schristos@itemx -mmnemonic=@var{intel} 365*1424dfb3SchristosThis option specifies instruction mnemonic for matching instructions. 366*1424dfb3SchristosThe @code{.att_mnemonic} and @code{.intel_mnemonic} directives will 367*1424dfb3Schristostake precedent. 368*1424dfb3Schristos 369*1424dfb3Schristos@cindex @samp{-msyntax=} option, i386 370*1424dfb3Schristos@cindex @samp{-msyntax=} option, x86-64 371*1424dfb3Schristos@item -msyntax=@var{att} 372*1424dfb3Schristos@itemx -msyntax=@var{intel} 373*1424dfb3SchristosThis option specifies instruction syntax when processing instructions. 374*1424dfb3SchristosThe @code{.att_syntax} and @code{.intel_syntax} directives will 375*1424dfb3Schristostake precedent. 376*1424dfb3Schristos 377*1424dfb3Schristos@cindex @samp{-mnaked-reg} option, i386 378*1424dfb3Schristos@cindex @samp{-mnaked-reg} option, x86-64 379*1424dfb3Schristos@item -mnaked-reg 380*1424dfb3SchristosThis option specifies that registers don't require a @samp{%} prefix. 381*1424dfb3SchristosThe @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. 382*1424dfb3Schristos 383*1424dfb3Schristos@cindex @samp{-madd-bnd-prefix} option, i386 384*1424dfb3Schristos@cindex @samp{-madd-bnd-prefix} option, x86-64 385*1424dfb3Schristos@item -madd-bnd-prefix 386*1424dfb3SchristosThis option forces the assembler to add BND prefix to all branches, even 387*1424dfb3Schristosif such prefix was not explicitly specified in the source code. 388*1424dfb3Schristos 389*1424dfb3Schristos@cindex @samp{-mshared} option, i386 390*1424dfb3Schristos@cindex @samp{-mshared} option, x86-64 391*1424dfb3Schristos@item -mno-shared 392*1424dfb3SchristosOn ELF target, the assembler normally optimizes out non-PLT relocations 393*1424dfb3Schristosagainst defined non-weak global branch targets with default visibility. 394*1424dfb3SchristosThe @samp{-mshared} option tells the assembler to generate code which 395*1424dfb3Schristosmay go into a shared library where all non-weak global branch targets 396*1424dfb3Schristoswith default visibility can be preempted. The resulting code is 397*1424dfb3Schristosslightly bigger. This option only affects the handling of branch 398*1424dfb3Schristosinstructions. 399*1424dfb3Schristos 400*1424dfb3Schristos@cindex @samp{-mbig-obj} option, i386 401*1424dfb3Schristos@cindex @samp{-mbig-obj} option, x86-64 402*1424dfb3Schristos@item -mbig-obj 403*1424dfb3SchristosOn PE/COFF target this option forces the use of big object file 404*1424dfb3Schristosformat, which allows more than 32768 sections. 405*1424dfb3Schristos 406*1424dfb3Schristos@cindex @samp{-momit-lock-prefix=} option, i386 407*1424dfb3Schristos@cindex @samp{-momit-lock-prefix=} option, x86-64 408*1424dfb3Schristos@item -momit-lock-prefix=@var{no} 409*1424dfb3Schristos@itemx -momit-lock-prefix=@var{yes} 410*1424dfb3SchristosThese options control how the assembler should encode lock prefix. 411*1424dfb3SchristosThis option is intended as a workaround for processors, that fail on 412*1424dfb3Schristoslock prefix. This option can only be safely used with single-core, 413*1424dfb3Schristossingle-thread computers 414*1424dfb3Schristos@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. 415*1424dfb3Schristos@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, 416*1424dfb3Schristoswhich is the default. 417*1424dfb3Schristos 418*1424dfb3Schristos@cindex @samp{-mfence-as-lock-add=} option, i386 419*1424dfb3Schristos@cindex @samp{-mfence-as-lock-add=} option, x86-64 420*1424dfb3Schristos@item -mfence-as-lock-add=@var{no} 421*1424dfb3Schristos@itemx -mfence-as-lock-add=@var{yes} 422*1424dfb3SchristosThese options control how the assembler should encode lfence, mfence and 423*1424dfb3Schristossfence. 424*1424dfb3Schristos@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and 425*1424dfb3Schristossfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and 426*1424dfb3Schristos@samp{lock addl $0x0, (%esp)} in 32-bit mode. 427*1424dfb3Schristos@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and 428*1424dfb3Schristossfence as usual, which is the default. 429*1424dfb3Schristos 430*1424dfb3Schristos@cindex @samp{-mrelax-relocations=} option, i386 431*1424dfb3Schristos@cindex @samp{-mrelax-relocations=} option, x86-64 432*1424dfb3Schristos@item -mrelax-relocations=@var{no} 433*1424dfb3Schristos@itemx -mrelax-relocations=@var{yes} 434*1424dfb3SchristosThese options control whether the assembler should generate relax 435*1424dfb3Schristosrelocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and 436*1424dfb3SchristosR_X86_64_REX_GOTPCRELX, in 64-bit mode. 437*1424dfb3Schristos@option{-mrelax-relocations=@var{yes}} will generate relax relocations. 438*1424dfb3Schristos@option{-mrelax-relocations=@var{no}} will not generate relax 439*1424dfb3Schristosrelocations. The default can be controlled by a configure option 440*1424dfb3Schristos@option{--enable-x86-relax-relocations}. 441*1424dfb3Schristos 442*1424dfb3Schristos@cindex @samp{-malign-branch-boundary=} option, i386 443*1424dfb3Schristos@cindex @samp{-malign-branch-boundary=} option, x86-64 444*1424dfb3Schristos@item -malign-branch-boundary=@var{NUM} 445*1424dfb3SchristosThis option controls how the assembler should align branches with segment 446*1424dfb3Schristosprefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or 447*1424dfb3Schristosno less than 16. Branches will be aligned within @var{NUM} byte 448*1424dfb3Schristosboundary. @option{-malign-branch-boundary=0}, which is the default, 449*1424dfb3Schristosdoesn't align branches. 450*1424dfb3Schristos 451*1424dfb3Schristos@cindex @samp{-malign-branch=} option, i386 452*1424dfb3Schristos@cindex @samp{-malign-branch=} option, x86-64 453*1424dfb3Schristos@item -malign-branch=@var{TYPE}[+@var{TYPE}...] 454*1424dfb3SchristosThis option specifies types of branches to align. @var{TYPE} is 455*1424dfb3Schristoscombination of @samp{jcc}, which aligns conditional jumps, 456*1424dfb3Schristos@samp{fused}, which aligns fused conditional jumps, @samp{jmp}, 457*1424dfb3Schristoswhich aligns unconditional jumps, @samp{call} which aligns calls, 458*1424dfb3Schristos@samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect 459*1424dfb3Schristosjumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}. 460*1424dfb3Schristos 461*1424dfb3Schristos@cindex @samp{-malign-branch-prefix-size=} option, i386 462*1424dfb3Schristos@cindex @samp{-malign-branch-prefix-size=} option, x86-64 463*1424dfb3Schristos@item -malign-branch-prefix-size=@var{NUM} 464*1424dfb3SchristosThis option specifies the maximum number of prefixes on an instruction 465*1424dfb3Schristosto align branches. @var{NUM} should be between 0 and 5. The default 466*1424dfb3Schristos@var{NUM} is 5. 467*1424dfb3Schristos 468*1424dfb3Schristos@cindex @samp{-mbranches-within-32B-boundaries} option, i386 469*1424dfb3Schristos@cindex @samp{-mbranches-within-32B-boundaries} option, x86-64 470*1424dfb3Schristos@item -mbranches-within-32B-boundaries 471*1424dfb3SchristosThis option aligns conditional jumps, fused conditional jumps and 472*1424dfb3Schristosunconditional jumps within 32 byte boundary with up to 5 segment prefixes 473*1424dfb3Schristoson an instruction. It is equivalent to 474*1424dfb3Schristos@option{-malign-branch-boundary=32} 475*1424dfb3Schristos@option{-malign-branch=jcc+fused+jmp} 476*1424dfb3Schristos@option{-malign-branch-prefix-size=5}. 477*1424dfb3SchristosThe default doesn't align branches. 478*1424dfb3Schristos 479*1424dfb3Schristos@cindex @samp{-mlfence-after-load=} option, i386 480*1424dfb3Schristos@cindex @samp{-mlfence-after-load=} option, x86-64 481*1424dfb3Schristos@item -mlfence-after-load=@var{no} 482*1424dfb3Schristos@itemx -mlfence-after-load=@var{yes} 483*1424dfb3SchristosThese options control whether the assembler should generate lfence 484*1424dfb3Schristosafter load instructions. @option{-mlfence-after-load=@var{yes}} will 485*1424dfb3Schristosgenerate lfence. @option{-mlfence-after-load=@var{no}} will not generate 486*1424dfb3Schristoslfence, which is the default. 487*1424dfb3Schristos 488*1424dfb3Schristos@cindex @samp{-mlfence-before-indirect-branch=} option, i386 489*1424dfb3Schristos@cindex @samp{-mlfence-before-indirect-branch=} option, x86-64 490*1424dfb3Schristos@item -mlfence-before-indirect-branch=@var{none} 491*1424dfb3Schristos@item -mlfence-before-indirect-branch=@var{all} 492*1424dfb3Schristos@item -mlfence-before-indirect-branch=@var{register} 493*1424dfb3Schristos@itemx -mlfence-before-indirect-branch=@var{memory} 494*1424dfb3SchristosThese options control whether the assembler should generate lfence 495*1424dfb3Schristosbefore indirect near branch instructions. 496*1424dfb3Schristos@option{-mlfence-before-indirect-branch=@var{all}} will generate lfence 497*1424dfb3Schristosbefore indirect near branch via register and issue a warning before 498*1424dfb3Schristosindirect near branch via memory. 499*1424dfb3SchristosIt also implicitly sets @option{-mlfence-before-ret=@var{shl}} when 500*1424dfb3Schristosthere's no explict @option{-mlfence-before-ret=}. 501*1424dfb3Schristos@option{-mlfence-before-indirect-branch=@var{register}} will generate 502*1424dfb3Schristoslfence before indirect near branch via register. 503*1424dfb3Schristos@option{-mlfence-before-indirect-branch=@var{memory}} will issue a 504*1424dfb3Schristoswarning before indirect near branch via memory. 505*1424dfb3Schristos@option{-mlfence-before-indirect-branch=@var{none}} will not generate 506*1424dfb3Schristoslfence nor issue warning, which is the default. Note that lfence won't 507*1424dfb3Schristosbe generated before indirect near branch via register with 508*1424dfb3Schristos@option{-mlfence-after-load=@var{yes}} since lfence will be generated 509*1424dfb3Schristosafter loading branch target register. 510*1424dfb3Schristos 511*1424dfb3Schristos@cindex @samp{-mlfence-before-ret=} option, i386 512*1424dfb3Schristos@cindex @samp{-mlfence-before-ret=} option, x86-64 513*1424dfb3Schristos@item -mlfence-before-ret=@var{none} 514*1424dfb3Schristos@item -mlfence-before-ret=@var{shl} 515*1424dfb3Schristos@item -mlfence-before-ret=@var{or} 516*1424dfb3Schristos@item -mlfence-before-ret=@var{yes} 517*1424dfb3Schristos@itemx -mlfence-before-ret=@var{not} 518*1424dfb3SchristosThese options control whether the assembler should generate lfence 519*1424dfb3Schristosbefore ret. @option{-mlfence-before-ret=@var{or}} will generate 520*1424dfb3Schristosgenerate or instruction with lfence. 521*1424dfb3Schristos@option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction 522*1424dfb3Schristoswith lfence. @option{-mlfence-before-ret=@var{not}} will generate not 523*1424dfb3Schristosinstruction with lfence. @option{-mlfence-before-ret=@var{none}} will not 524*1424dfb3Schristosgenerate lfence, which is the default. 525*1424dfb3Schristos 526*1424dfb3Schristos@cindex @samp{-mx86-used-note=} option, i386 527*1424dfb3Schristos@cindex @samp{-mx86-used-note=} option, x86-64 528*1424dfb3Schristos@item -mx86-used-note=@var{no} 529*1424dfb3Schristos@itemx -mx86-used-note=@var{yes} 530*1424dfb3SchristosThese options control whether the assembler should generate 531*1424dfb3SchristosGNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED 532*1424dfb3SchristosGNU property notes. The default can be controlled by the 533*1424dfb3Schristos@option{--enable-x86-used-note} configure option. 534*1424dfb3Schristos 535*1424dfb3Schristos@cindex @samp{-mevexrcig=} option, i386 536*1424dfb3Schristos@cindex @samp{-mevexrcig=} option, x86-64 537*1424dfb3Schristos@item -mevexrcig=@var{rne} 538*1424dfb3Schristos@itemx -mevexrcig=@var{rd} 539*1424dfb3Schristos@itemx -mevexrcig=@var{ru} 540*1424dfb3Schristos@itemx -mevexrcig=@var{rz} 541*1424dfb3SchristosThese options control how the assembler should encode SAE-only 542*1424dfb3SchristosEVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits 543*1424dfb3Schristosof EVEX instruction with 00, which is the default. 544*1424dfb3Schristos@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} 545*1424dfb3Schristosand @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions 546*1424dfb3Schristoswith 01, 10 and 11 RC bits, respectively. 547*1424dfb3Schristos 548*1424dfb3Schristos@cindex @samp{-mamd64} option, x86-64 549*1424dfb3Schristos@cindex @samp{-mintel64} option, x86-64 550*1424dfb3Schristos@item -mamd64 551*1424dfb3Schristos@itemx -mintel64 552*1424dfb3SchristosThis option specifies that the assembler should accept only AMD64 or 553*1424dfb3SchristosIntel64 ISA in 64-bit mode. The default is to accept common, Intel64 554*1424dfb3Schristosonly and AMD64 ISAs. 555*1424dfb3Schristos 556*1424dfb3Schristos@cindex @samp{-O0} option, i386 557*1424dfb3Schristos@cindex @samp{-O0} option, x86-64 558*1424dfb3Schristos@cindex @samp{-O} option, i386 559*1424dfb3Schristos@cindex @samp{-O} option, x86-64 560*1424dfb3Schristos@cindex @samp{-O1} option, i386 561*1424dfb3Schristos@cindex @samp{-O1} option, x86-64 562*1424dfb3Schristos@cindex @samp{-O2} option, i386 563*1424dfb3Schristos@cindex @samp{-O2} option, x86-64 564*1424dfb3Schristos@cindex @samp{-Os} option, i386 565*1424dfb3Schristos@cindex @samp{-Os} option, x86-64 566*1424dfb3Schristos@item -O0 | -O | -O1 | -O2 | -Os 567*1424dfb3SchristosOptimize instruction encoding with smaller instruction size. @samp{-O} 568*1424dfb3Schristosand @samp{-O1} encode 64-bit register load instructions with 64-bit 569*1424dfb3Schristosimmediate as 32-bit register load instructions with 31-bit or 32-bits 570*1424dfb3Schristosimmediates, encode 64-bit register clearing instructions with 32-bit 571*1424dfb3Schristosregister clearing instructions, encode 256-bit/512-bit VEX/EVEX vector 572*1424dfb3Schristosregister clearing instructions with 128-bit VEX vector register 573*1424dfb3Schristosclearing instructions, encode 128-bit/256-bit EVEX vector 574*1424dfb3Schristosregister load/store instructions with VEX vector register load/store 575*1424dfb3Schristosinstructions, and encode 128-bit/256-bit EVEX packed integer logical 576*1424dfb3Schristosinstructions with 128-bit/256-bit VEX packed integer logical. 577*1424dfb3Schristos 578*1424dfb3Schristos@samp{-O2} includes @samp{-O1} optimization plus encodes 579*1424dfb3Schristos256-bit/512-bit EVEX vector register clearing instructions with 128-bit 580*1424dfb3SchristosEVEX vector register clearing instructions. In 64-bit mode VEX encoded 581*1424dfb3Schristosinstructions with commutative source operands will also have their 582*1424dfb3Schristossource operands swapped if this allows using the 2-byte VEX prefix form 583*1424dfb3Schristosinstead of the 3-byte one. Certain forms of AND as well as OR with the 584*1424dfb3Schristossame (register) operand specified twice will also be changed to TEST. 585*1424dfb3Schristos 586*1424dfb3Schristos@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit 587*1424dfb3Schristosand 64-bit register tests with immediate as 8-bit register test with 588*1424dfb3Schristosimmediate. @samp{-O0} turns off this optimization. 589*1424dfb3Schristos 590*1424dfb3Schristos@end table 591*1424dfb3Schristos@c man end 592*1424dfb3Schristos 593*1424dfb3Schristos@node i386-Directives 594*1424dfb3Schristos@section x86 specific Directives 595*1424dfb3Schristos 596*1424dfb3Schristos@cindex machine directives, x86 597*1424dfb3Schristos@cindex x86 machine directives 598*1424dfb3Schristos@table @code 599*1424dfb3Schristos 600*1424dfb3Schristos@cindex @code{lcomm} directive, COFF 601*1424dfb3Schristos@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] 602*1424dfb3SchristosReserve @var{length} (an absolute expression) bytes for a local common 603*1424dfb3Schristosdenoted by @var{symbol}. The section and value of @var{symbol} are 604*1424dfb3Schristosthose of the new local common. The addresses are allocated in the bss 605*1424dfb3Schristossection, so that at run-time the bytes start off zeroed. Since 606*1424dfb3Schristos@var{symbol} is not declared global, it is normally not visible to 607*1424dfb3Schristos@code{@value{LD}}. The optional third parameter, @var{alignment}, 608*1424dfb3Schristosspecifies the desired alignment of the symbol in the bss section. 609*1424dfb3Schristos 610*1424dfb3SchristosThis directive is only available for COFF based x86 targets. 611*1424dfb3Schristos 612*1424dfb3Schristos@cindex @code{largecomm} directive, ELF 613*1424dfb3Schristos@item .largecomm @var{symbol} , @var{length}[, @var{alignment}] 614*1424dfb3SchristosThis directive behaves in the same way as the @code{comm} directive 615*1424dfb3Schristosexcept that the data is placed into the @var{.lbss} section instead of 616*1424dfb3Schristosthe @var{.bss} section @ref{Comm}. 617*1424dfb3Schristos 618*1424dfb3SchristosThe directive is intended to be used for data which requires a large 619*1424dfb3Schristosamount of space, and it is only available for ELF based x86_64 620*1424dfb3Schristostargets. 621*1424dfb3Schristos 622*1424dfb3Schristos@cindex @code{value} directive 623*1424dfb3Schristos@item .value @var{expression} [, @var{expression}] 624*1424dfb3SchristosThis directive behaves in the same way as the @code{.short} directive, 625*1424dfb3Schristostaking a series of comma separated expressions and storing them as 626*1424dfb3Schristostwo-byte wide values into the current section. 627*1424dfb3Schristos 628*1424dfb3Schristos@c FIXME: Document other x86 specific directives ? Eg: .code16gcc, 629*1424dfb3Schristos 630*1424dfb3Schristos@end table 631*1424dfb3Schristos 632*1424dfb3Schristos@node i386-Syntax 633*1424dfb3Schristos@section i386 Syntactical Considerations 634*1424dfb3Schristos@menu 635*1424dfb3Schristos* i386-Variations:: AT&T Syntax versus Intel Syntax 636*1424dfb3Schristos* i386-Chars:: Special Characters 637*1424dfb3Schristos@end menu 638*1424dfb3Schristos 639*1424dfb3Schristos@node i386-Variations 640*1424dfb3Schristos@subsection AT&T Syntax versus Intel Syntax 641*1424dfb3Schristos 642*1424dfb3Schristos@cindex i386 intel_syntax pseudo op 643*1424dfb3Schristos@cindex intel_syntax pseudo op, i386 644*1424dfb3Schristos@cindex i386 att_syntax pseudo op 645*1424dfb3Schristos@cindex att_syntax pseudo op, i386 646*1424dfb3Schristos@cindex i386 syntax compatibility 647*1424dfb3Schristos@cindex syntax compatibility, i386 648*1424dfb3Schristos@cindex x86-64 intel_syntax pseudo op 649*1424dfb3Schristos@cindex intel_syntax pseudo op, x86-64 650*1424dfb3Schristos@cindex x86-64 att_syntax pseudo op 651*1424dfb3Schristos@cindex att_syntax pseudo op, x86-64 652*1424dfb3Schristos@cindex x86-64 syntax compatibility 653*1424dfb3Schristos@cindex syntax compatibility, x86-64 654*1424dfb3Schristos 655*1424dfb3Schristos@code{@value{AS}} now supports assembly using Intel assembler syntax. 656*1424dfb3Schristos@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches 657*1424dfb3Schristosback to the usual AT&T mode for compatibility with the output of 658*1424dfb3Schristos@code{@value{GCC}}. Either of these directives may have an optional 659*1424dfb3Schristosargument, @code{prefix}, or @code{noprefix} specifying whether registers 660*1424dfb3Schristosrequire a @samp{%} prefix. AT&T System V/386 assembler syntax is quite 661*1424dfb3Schristosdifferent from Intel syntax. We mention these differences because 662*1424dfb3Schristosalmost all 80386 documents use Intel syntax. Notable differences 663*1424dfb3Schristosbetween the two syntaxes are: 664*1424dfb3Schristos 665*1424dfb3Schristos@cindex immediate operands, i386 666*1424dfb3Schristos@cindex i386 immediate operands 667*1424dfb3Schristos@cindex register operands, i386 668*1424dfb3Schristos@cindex i386 register operands 669*1424dfb3Schristos@cindex jump/call operands, i386 670*1424dfb3Schristos@cindex i386 jump/call operands 671*1424dfb3Schristos@cindex operand delimiters, i386 672*1424dfb3Schristos 673*1424dfb3Schristos@cindex immediate operands, x86-64 674*1424dfb3Schristos@cindex x86-64 immediate operands 675*1424dfb3Schristos@cindex register operands, x86-64 676*1424dfb3Schristos@cindex x86-64 register operands 677*1424dfb3Schristos@cindex jump/call operands, x86-64 678*1424dfb3Schristos@cindex x86-64 jump/call operands 679*1424dfb3Schristos@cindex operand delimiters, x86-64 680*1424dfb3Schristos@itemize @bullet 681*1424dfb3Schristos@item 682*1424dfb3SchristosAT&T immediate operands are preceded by @samp{$}; Intel immediate 683*1424dfb3Schristosoperands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 684*1424dfb3SchristosAT&T register operands are preceded by @samp{%}; Intel register operands 685*1424dfb3Schristosare undelimited. AT&T absolute (as opposed to PC relative) jump/call 686*1424dfb3Schristosoperands are prefixed by @samp{*}; they are undelimited in Intel syntax. 687*1424dfb3Schristos 688*1424dfb3Schristos@cindex i386 source, destination operands 689*1424dfb3Schristos@cindex source, destination operands; i386 690*1424dfb3Schristos@cindex x86-64 source, destination operands 691*1424dfb3Schristos@cindex source, destination operands; x86-64 692*1424dfb3Schristos@item 693*1424dfb3SchristosAT&T and Intel syntax use the opposite order for source and destination 694*1424dfb3Schristosoperands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 695*1424dfb3Schristos@samp{source, dest} convention is maintained for compatibility with 696*1424dfb3Schristosprevious Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and 697*1424dfb3Schristosinstructions with 2 immediate operands, such as the @samp{enter} 698*1424dfb3Schristosinstruction, do @emph{not} have reversed order. @ref{i386-Bugs}. 699*1424dfb3Schristos 700*1424dfb3Schristos@cindex mnemonic suffixes, i386 701*1424dfb3Schristos@cindex sizes operands, i386 702*1424dfb3Schristos@cindex i386 size suffixes 703*1424dfb3Schristos@cindex mnemonic suffixes, x86-64 704*1424dfb3Schristos@cindex sizes operands, x86-64 705*1424dfb3Schristos@cindex x86-64 size suffixes 706*1424dfb3Schristos@item 707*1424dfb3SchristosIn AT&T syntax the size of memory operands is determined from the last 708*1424dfb3Schristoscharacter of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 709*1424dfb3Schristos@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long 710*1424dfb3Schristos(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes 711*1424dfb3Schristosof @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm 712*1424dfb3Schristos(256-bit vector) and zmm (512-bit vector) memory references, only when there's 713*1424dfb3Schristosno other way to disambiguate an instruction. Intel syntax accomplishes this by 714*1424dfb3Schristosprefixing memory operands (@emph{not} the instruction mnemonics) with 715*1424dfb3Schristos@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, 716*1424dfb3Schristos@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel 717*1424dfb3Schristossyntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T 718*1424dfb3Schristossyntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and 719*1424dfb3Schristos@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. 720*1424dfb3Schristos 721*1424dfb3SchristosIn 64-bit code, @samp{movabs} can be used to encode the @samp{mov} 722*1424dfb3Schristosinstruction with the 64-bit displacement or immediate operand. 723*1424dfb3Schristos 724*1424dfb3Schristos@cindex return instructions, i386 725*1424dfb3Schristos@cindex i386 jump, call, return 726*1424dfb3Schristos@cindex return instructions, x86-64 727*1424dfb3Schristos@cindex x86-64 jump, call, return 728*1424dfb3Schristos@item 729*1424dfb3SchristosImmediate form long jumps and calls are 730*1424dfb3Schristos@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 731*1424dfb3SchristosIntel syntax is 732*1424dfb3Schristos@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 733*1424dfb3Schristosinstruction 734*1424dfb3Schristosis @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 735*1424dfb3Schristos@samp{ret far @var{stack-adjust}}. 736*1424dfb3Schristos 737*1424dfb3Schristos@cindex sections, i386 738*1424dfb3Schristos@cindex i386 sections 739*1424dfb3Schristos@cindex sections, x86-64 740*1424dfb3Schristos@cindex x86-64 sections 741*1424dfb3Schristos@item 742*1424dfb3SchristosThe AT&T assembler does not provide support for multiple section 743*1424dfb3Schristosprograms. Unix style systems expect all programs to be single sections. 744*1424dfb3Schristos@end itemize 745*1424dfb3Schristos 746*1424dfb3Schristos@node i386-Chars 747*1424dfb3Schristos@subsection Special Characters 748*1424dfb3Schristos 749*1424dfb3Schristos@cindex line comment character, i386 750*1424dfb3Schristos@cindex i386 line comment character 751*1424dfb3SchristosThe presence of a @samp{#} appearing anywhere on a line indicates the 752*1424dfb3Schristosstart of a comment that extends to the end of that line. 753*1424dfb3Schristos 754*1424dfb3SchristosIf a @samp{#} appears as the first character of a line then the whole 755*1424dfb3Schristosline is treated as a comment, but in this case the line can also be a 756*1424dfb3Schristoslogical line number directive (@pxref{Comments}) or a preprocessor 757*1424dfb3Schristoscontrol command (@pxref{Preprocessing}). 758*1424dfb3Schristos 759*1424dfb3SchristosIf the @option{--divide} command-line option has not been specified 760*1424dfb3Schristosthen the @samp{/} character appearing anywhere on a line also 761*1424dfb3Schristosintroduces a line comment. 762*1424dfb3Schristos 763*1424dfb3Schristos@cindex line separator, i386 764*1424dfb3Schristos@cindex statement separator, i386 765*1424dfb3Schristos@cindex i386 line separator 766*1424dfb3SchristosThe @samp{;} character can be used to separate statements on the same 767*1424dfb3Schristosline. 768*1424dfb3Schristos 769*1424dfb3Schristos@node i386-Mnemonics 770*1424dfb3Schristos@section i386-Mnemonics 771*1424dfb3Schristos@subsection Instruction Naming 772*1424dfb3Schristos 773*1424dfb3Schristos@cindex i386 instruction naming 774*1424dfb3Schristos@cindex instruction naming, i386 775*1424dfb3Schristos@cindex x86-64 instruction naming 776*1424dfb3Schristos@cindex instruction naming, x86-64 777*1424dfb3Schristos 778*1424dfb3SchristosInstruction mnemonics are suffixed with one character modifiers which 779*1424dfb3Schristosspecify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} 780*1424dfb3Schristosand @samp{q} specify byte, word, long and quadruple word operands. If 781*1424dfb3Schristosno suffix is specified by an instruction then @code{@value{AS}} tries to 782*1424dfb3Schristosfill in the missing suffix based on the destination register operand 783*1424dfb3Schristos(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent 784*1424dfb3Schristosto @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to 785*1424dfb3Schristos@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix 786*1424dfb3Schristosassembler which assumes that a missing mnemonic suffix implies long 787*1424dfb3Schristosoperand size. (This incompatibility does not affect compiler output 788*1424dfb3Schristossince compilers always explicitly specify the mnemonic suffix.) 789*1424dfb3Schristos 790*1424dfb3SchristosWhen there is no sizing suffix and no (suitable) register operands to 791*1424dfb3Schristosdeduce the size of memory operands, with a few exceptions and where long 792*1424dfb3Schristosoperand size is possible in the first place, operand size will default 793*1424dfb3Schristosto long in 32- and 64-bit modes. Similarly it will default to short in 794*1424dfb3Schristos16-bit mode. Noteworthy exceptions are 795*1424dfb3Schristos 796*1424dfb3Schristos@itemize @bullet 797*1424dfb3Schristos@item 798*1424dfb3SchristosInstructions with an implicit on-stack operand as well as branches, 799*1424dfb3Schristoswhich default to quad in 64-bit mode. 800*1424dfb3Schristos 801*1424dfb3Schristos@item 802*1424dfb3SchristosSign- and zero-extending moves, which default to byte size source 803*1424dfb3Schristosoperands. 804*1424dfb3Schristos 805*1424dfb3Schristos@item 806*1424dfb3SchristosFloating point insns with integer operands, which default to short (for 807*1424dfb3Schristosperhaps historical reasons). 808*1424dfb3Schristos 809*1424dfb3Schristos@item 810*1424dfb3SchristosCRC32 with a 64-bit destination, which defaults to a quad source 811*1424dfb3Schristosoperand. 812*1424dfb3Schristos 813*1424dfb3Schristos@end itemize 814*1424dfb3Schristos 815*1424dfb3Schristos@cindex encoding options, i386 816*1424dfb3Schristos@cindex encoding options, x86-64 817*1424dfb3Schristos 818*1424dfb3SchristosDifferent encoding options can be specified via pseudo prefixes: 819*1424dfb3Schristos 820*1424dfb3Schristos@itemize @bullet 821*1424dfb3Schristos@item 822*1424dfb3Schristos@samp{@{disp8@}} -- prefer 8-bit displacement. 823*1424dfb3Schristos 824*1424dfb3Schristos@item 825*1424dfb3Schristos@samp{@{disp32@}} -- prefer 32-bit displacement. 826*1424dfb3Schristos 827*1424dfb3Schristos@item 828*1424dfb3Schristos@samp{@{disp16@}} -- prefer 16-bit displacement. 829*1424dfb3Schristos 830*1424dfb3Schristos@item 831*1424dfb3Schristos@samp{@{load@}} -- prefer load-form instruction. 832*1424dfb3Schristos 833*1424dfb3Schristos@item 834*1424dfb3Schristos@samp{@{store@}} -- prefer store-form instruction. 835*1424dfb3Schristos 836*1424dfb3Schristos@item 837*1424dfb3Schristos@samp{@{vex@}} -- encode with VEX prefix. 838*1424dfb3Schristos 839*1424dfb3Schristos@item 840*1424dfb3Schristos@samp{@{vex3@}} -- encode with 3-byte VEX prefix. 841*1424dfb3Schristos 842*1424dfb3Schristos@item 843*1424dfb3Schristos@samp{@{evex@}} -- encode with EVEX prefix. 844*1424dfb3Schristos 845*1424dfb3Schristos@item 846*1424dfb3Schristos@samp{@{rex@}} -- prefer REX prefix for integer and legacy vector 847*1424dfb3Schristosinstructions (x86-64 only). Note that this differs from the @samp{rex} 848*1424dfb3Schristosprefix which generates REX prefix unconditionally. 849*1424dfb3Schristos 850*1424dfb3Schristos@item 851*1424dfb3Schristos@samp{@{nooptimize@}} -- disable instruction size optimization. 852*1424dfb3Schristos@end itemize 853*1424dfb3Schristos 854*1424dfb3Schristos@cindex conversion instructions, i386 855*1424dfb3Schristos@cindex i386 conversion instructions 856*1424dfb3Schristos@cindex conversion instructions, x86-64 857*1424dfb3Schristos@cindex x86-64 conversion instructions 858*1424dfb3SchristosThe Intel-syntax conversion instructions 859*1424dfb3Schristos 860*1424dfb3Schristos@itemize @bullet 861*1424dfb3Schristos@item 862*1424dfb3Schristos@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 863*1424dfb3Schristos 864*1424dfb3Schristos@item 865*1424dfb3Schristos@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 866*1424dfb3Schristos 867*1424dfb3Schristos@item 868*1424dfb3Schristos@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 869*1424dfb3Schristos 870*1424dfb3Schristos@item 871*1424dfb3Schristos@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 872*1424dfb3Schristos 873*1424dfb3Schristos@item 874*1424dfb3Schristos@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} 875*1424dfb3Schristos(x86-64 only), 876*1424dfb3Schristos 877*1424dfb3Schristos@item 878*1424dfb3Schristos@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in 879*1424dfb3Schristos@samp{%rdx:%rax} (x86-64 only), 880*1424dfb3Schristos@end itemize 881*1424dfb3Schristos 882*1424dfb3Schristos@noindent 883*1424dfb3Schristosare called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and 884*1424dfb3Schristos@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these 885*1424dfb3Schristosinstructions. 886*1424dfb3Schristos 887*1424dfb3Schristos@cindex extension instructions, i386 888*1424dfb3Schristos@cindex i386 extension instructions 889*1424dfb3Schristos@cindex extension instructions, x86-64 890*1424dfb3Schristos@cindex x86-64 extension instructions 891*1424dfb3SchristosThe Intel-syntax extension instructions 892*1424dfb3Schristos 893*1424dfb3Schristos@itemize @bullet 894*1424dfb3Schristos@item 895*1424dfb3Schristos@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}. 896*1424dfb3Schristos 897*1424dfb3Schristos@item 898*1424dfb3Schristos@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}. 899*1424dfb3Schristos 900*1424dfb3Schristos@item 901*1424dfb3Schristos@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64} 902*1424dfb3Schristos(x86-64 only). 903*1424dfb3Schristos 904*1424dfb3Schristos@item 905*1424dfb3Schristos@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32} 906*1424dfb3Schristos 907*1424dfb3Schristos@item 908*1424dfb3Schristos@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64} 909*1424dfb3Schristos(x86-64 only). 910*1424dfb3Schristos 911*1424dfb3Schristos@item 912*1424dfb3Schristos@samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64} 913*1424dfb3Schristos(x86-64 only). 914*1424dfb3Schristos 915*1424dfb3Schristos@item 916*1424dfb3Schristos@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}. 917*1424dfb3Schristos 918*1424dfb3Schristos@item 919*1424dfb3Schristos@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}. 920*1424dfb3Schristos 921*1424dfb3Schristos@item 922*1424dfb3Schristos@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64} 923*1424dfb3Schristos(x86-64 only). 924*1424dfb3Schristos 925*1424dfb3Schristos@item 926*1424dfb3Schristos@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32} 927*1424dfb3Schristos 928*1424dfb3Schristos@item 929*1424dfb3Schristos@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64} 930*1424dfb3Schristos(x86-64 only). 931*1424dfb3Schristos@end itemize 932*1424dfb3Schristos 933*1424dfb3Schristos@noindent 934*1424dfb3Schristosare called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx}, 935*1424dfb3Schristos@samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw}, 936*1424dfb3Schristos@samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx}, 937*1424dfb3Schristos@samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx}, 938*1424dfb3Schristos@samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax. 939*1424dfb3Schristos 940*1424dfb3Schristos@cindex jump instructions, i386 941*1424dfb3Schristos@cindex call instructions, i386 942*1424dfb3Schristos@cindex jump instructions, x86-64 943*1424dfb3Schristos@cindex call instructions, x86-64 944*1424dfb3SchristosFar call/jump instructions are @samp{lcall} and @samp{ljmp} in 945*1424dfb3SchristosAT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 946*1424dfb3Schristosconvention. 947*1424dfb3Schristos 948*1424dfb3Schristos@subsection AT&T Mnemonic versus Intel Mnemonic 949*1424dfb3Schristos 950*1424dfb3Schristos@cindex i386 mnemonic compatibility 951*1424dfb3Schristos@cindex mnemonic compatibility, i386 952*1424dfb3Schristos 953*1424dfb3Schristos@code{@value{AS}} supports assembly using Intel mnemonic. 954*1424dfb3Schristos@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and 955*1424dfb3Schristos@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T 956*1424dfb3Schristossyntax for compatibility with the output of @code{@value{GCC}}. 957*1424dfb3SchristosSeveral x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, 958*1424dfb3Schristos@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, 959*1424dfb3Schristos@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 960*1424dfb3Schristosassembler with different mnemonics from those in Intel IA32 specification. 961*1424dfb3Schristos@code{@value{GCC}} generates those instructions with AT&T mnemonic. 962*1424dfb3Schristos 963*1424dfb3Schristos@itemize @bullet 964*1424dfb3Schristos@item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination 965*1424dfb3Schristosregister. @samp{movsxd} should be used to encode 16-bit or 32-bit 966*1424dfb3Schristosdestination register with both AT&T and Intel mnemonics. 967*1424dfb3Schristos@end itemize 968*1424dfb3Schristos 969*1424dfb3Schristos@node i386-Regs 970*1424dfb3Schristos@section Register Naming 971*1424dfb3Schristos 972*1424dfb3Schristos@cindex i386 registers 973*1424dfb3Schristos@cindex registers, i386 974*1424dfb3Schristos@cindex x86-64 registers 975*1424dfb3Schristos@cindex registers, x86-64 976*1424dfb3SchristosRegister operands are always prefixed with @samp{%}. The 80386 registers 977*1424dfb3Schristosconsist of 978*1424dfb3Schristos 979*1424dfb3Schristos@itemize @bullet 980*1424dfb3Schristos@item 981*1424dfb3Schristosthe 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 982*1424dfb3Schristos@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 983*1424dfb3Schristosframe pointer), and @samp{%esp} (the stack pointer). 984*1424dfb3Schristos 985*1424dfb3Schristos@item 986*1424dfb3Schristosthe 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 987*1424dfb3Schristos@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 988*1424dfb3Schristos 989*1424dfb3Schristos@item 990*1424dfb3Schristosthe 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 991*1424dfb3Schristos@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 992*1424dfb3Schristosare the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 993*1424dfb3Schristos@samp{%cx}, and @samp{%dx}) 994*1424dfb3Schristos 995*1424dfb3Schristos@item 996*1424dfb3Schristosthe 6 section registers @samp{%cs} (code section), @samp{%ds} 997*1424dfb3Schristos(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 998*1424dfb3Schristosand @samp{%gs}. 999*1424dfb3Schristos 1000*1424dfb3Schristos@item 1001*1424dfb3Schristosthe 5 processor control registers @samp{%cr0}, @samp{%cr2}, 1002*1424dfb3Schristos@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. 1003*1424dfb3Schristos 1004*1424dfb3Schristos@item 1005*1424dfb3Schristosthe 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 1006*1424dfb3Schristos@samp{%db3}, @samp{%db6}, and @samp{%db7}. 1007*1424dfb3Schristos 1008*1424dfb3Schristos@item 1009*1424dfb3Schristosthe 2 test registers @samp{%tr6} and @samp{%tr7}. 1010*1424dfb3Schristos 1011*1424dfb3Schristos@item 1012*1424dfb3Schristosthe 8 floating point register stack @samp{%st} or equivalently 1013*1424dfb3Schristos@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 1014*1424dfb3Schristos@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 1015*1424dfb3SchristosThese registers are overloaded by 8 MMX registers @samp{%mm0}, 1016*1424dfb3Schristos@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, 1017*1424dfb3Schristos@samp{%mm6} and @samp{%mm7}. 1018*1424dfb3Schristos 1019*1424dfb3Schristos@item 1020*1424dfb3Schristosthe 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, 1021*1424dfb3Schristos@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. 1022*1424dfb3Schristos@end itemize 1023*1424dfb3Schristos 1024*1424dfb3SchristosThe AMD x86-64 architecture extends the register set by: 1025*1424dfb3Schristos 1026*1424dfb3Schristos@itemize @bullet 1027*1424dfb3Schristos@item 1028*1424dfb3Schristosenhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the 1029*1424dfb3Schristosaccumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, 1030*1424dfb3Schristos@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack 1031*1424dfb3Schristospointer) 1032*1424dfb3Schristos 1033*1424dfb3Schristos@item 1034*1424dfb3Schristosthe 8 extended registers @samp{%r8}--@samp{%r15}. 1035*1424dfb3Schristos 1036*1424dfb3Schristos@item 1037*1424dfb3Schristosthe 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. 1038*1424dfb3Schristos 1039*1424dfb3Schristos@item 1040*1424dfb3Schristosthe 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. 1041*1424dfb3Schristos 1042*1424dfb3Schristos@item 1043*1424dfb3Schristosthe 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. 1044*1424dfb3Schristos 1045*1424dfb3Schristos@item 1046*1424dfb3Schristosthe 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. 1047*1424dfb3Schristos 1048*1424dfb3Schristos@item 1049*1424dfb3Schristosthe 8 debug registers: @samp{%db8}--@samp{%db15}. 1050*1424dfb3Schristos 1051*1424dfb3Schristos@item 1052*1424dfb3Schristosthe 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. 1053*1424dfb3Schristos@end itemize 1054*1424dfb3Schristos 1055*1424dfb3SchristosWith the AVX extensions more registers were made available: 1056*1424dfb3Schristos 1057*1424dfb3Schristos@itemize @bullet 1058*1424dfb3Schristos 1059*1424dfb3Schristos@item 1060*1424dfb3Schristosthe 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 1061*1424dfb3Schristosavailable in 32-bit mode). The bottom 128 bits are overlaid with the 1062*1424dfb3Schristos@samp{xmm0}--@samp{xmm15} registers. 1063*1424dfb3Schristos 1064*1424dfb3Schristos@end itemize 1065*1424dfb3Schristos 1066*1424dfb3SchristosThe AVX512 extensions added the following registers: 1067*1424dfb3Schristos 1068*1424dfb3Schristos@itemize @bullet 1069*1424dfb3Schristos 1070*1424dfb3Schristos@item 1071*1424dfb3Schristosthe 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 1072*1424dfb3Schristosavailable in 32-bit mode). The bottom 128 bits are overlaid with the 1073*1424dfb3Schristos@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are 1074*1424dfb3Schristosoverlaid with the @samp{%ymm0}--@samp{%ymm31} registers. 1075*1424dfb3Schristos 1076*1424dfb3Schristos@item 1077*1424dfb3Schristosthe 8 mask registers @samp{%k0}--@samp{%k7}. 1078*1424dfb3Schristos 1079*1424dfb3Schristos@end itemize 1080*1424dfb3Schristos 1081*1424dfb3Schristos@node i386-Prefixes 1082*1424dfb3Schristos@section Instruction Prefixes 1083*1424dfb3Schristos 1084*1424dfb3Schristos@cindex i386 instruction prefixes 1085*1424dfb3Schristos@cindex instruction prefixes, i386 1086*1424dfb3Schristos@cindex prefixes, i386 1087*1424dfb3SchristosInstruction prefixes are used to modify the following instruction. They 1088*1424dfb3Schristosare used to repeat string instructions, to provide section overrides, to 1089*1424dfb3Schristosperform bus lock operations, and to change operand and address sizes. 1090*1424dfb3Schristos(Most instructions that normally operate on 32-bit operands will use 1091*1424dfb3Schristos16-bit operands if the instruction has an ``operand size'' prefix.) 1092*1424dfb3SchristosInstruction prefixes are best written on the same line as the instruction 1093*1424dfb3Schristosthey act upon. For example, the @samp{scas} (scan string) instruction is 1094*1424dfb3Schristosrepeated with: 1095*1424dfb3Schristos 1096*1424dfb3Schristos@smallexample 1097*1424dfb3Schristos repne scas %es:(%edi),%al 1098*1424dfb3Schristos@end smallexample 1099*1424dfb3Schristos 1100*1424dfb3SchristosYou may also place prefixes on the lines immediately preceding the 1101*1424dfb3Schristosinstruction, but this circumvents checks that @code{@value{AS}} does 1102*1424dfb3Schristoswith prefixes, and will not work with all prefixes. 1103*1424dfb3Schristos 1104*1424dfb3SchristosHere is a list of instruction prefixes: 1105*1424dfb3Schristos 1106*1424dfb3Schristos@cindex section override prefixes, i386 1107*1424dfb3Schristos@itemize @bullet 1108*1424dfb3Schristos@item 1109*1424dfb3SchristosSection override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 1110*1424dfb3Schristos@samp{fs}, @samp{gs}. These are automatically added by specifying 1111*1424dfb3Schristosusing the @var{section}:@var{memory-operand} form for memory references. 1112*1424dfb3Schristos 1113*1424dfb3Schristos@cindex size prefixes, i386 1114*1424dfb3Schristos@item 1115*1424dfb3SchristosOperand/Address size prefixes @samp{data16} and @samp{addr16} 1116*1424dfb3Schristoschange 32-bit operands/addresses into 16-bit operands/addresses, 1117*1424dfb3Schristoswhile @samp{data32} and @samp{addr32} change 16-bit ones (in a 1118*1424dfb3Schristos@code{.code16} section) into 32-bit operands/addresses. These prefixes 1119*1424dfb3Schristos@emph{must} appear on the same line of code as the instruction they 1120*1424dfb3Schristosmodify. For example, in a 16-bit @code{.code16} section, you might 1121*1424dfb3Schristoswrite: 1122*1424dfb3Schristos 1123*1424dfb3Schristos@smallexample 1124*1424dfb3Schristos addr32 jmpl *(%ebx) 1125*1424dfb3Schristos@end smallexample 1126*1424dfb3Schristos 1127*1424dfb3Schristos@cindex bus lock prefixes, i386 1128*1424dfb3Schristos@cindex inhibiting interrupts, i386 1129*1424dfb3Schristos@item 1130*1424dfb3SchristosThe bus lock prefix @samp{lock} inhibits interrupts during execution of 1131*1424dfb3Schristosthe instruction it precedes. (This is only valid with certain 1132*1424dfb3Schristosinstructions; see a 80386 manual for details). 1133*1424dfb3Schristos 1134*1424dfb3Schristos@cindex coprocessor wait, i386 1135*1424dfb3Schristos@item 1136*1424dfb3SchristosThe wait for coprocessor prefix @samp{wait} waits for the coprocessor to 1137*1424dfb3Schristoscomplete the current instruction. This should never be needed for the 1138*1424dfb3Schristos80386/80387 combination. 1139*1424dfb3Schristos 1140*1424dfb3Schristos@cindex repeat prefixes, i386 1141*1424dfb3Schristos@item 1142*1424dfb3SchristosThe @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 1143*1424dfb3Schristosto string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 1144*1424dfb3Schristostimes if the current address size is 16-bits). 1145*1424dfb3Schristos@cindex REX prefixes, i386 1146*1424dfb3Schristos@item 1147*1424dfb3SchristosThe @samp{rex} family of prefixes is used by x86-64 to encode 1148*1424dfb3Schristosextensions to i386 instruction set. The @samp{rex} prefix has four 1149*1424dfb3Schristosbits --- an operand size overwrite (@code{64}) used to change operand size 1150*1424dfb3Schristosfrom 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 1151*1424dfb3Schristosregister set. 1152*1424dfb3Schristos 1153*1424dfb3SchristosYou may write the @samp{rex} prefixes directly. The @samp{rex64xyz} 1154*1424dfb3Schristosinstruction emits @samp{rex} prefix with all the bits set. By omitting 1155*1424dfb3Schristosthe @code{64}, @code{x}, @code{y} or @code{z} you may write other 1156*1424dfb3Schristosprefixes as well. Normally, there is no need to write the prefixes 1157*1424dfb3Schristosexplicitly, since gas will automatically generate them based on the 1158*1424dfb3Schristosinstruction operands. 1159*1424dfb3Schristos@end itemize 1160*1424dfb3Schristos 1161*1424dfb3Schristos@node i386-Memory 1162*1424dfb3Schristos@section Memory References 1163*1424dfb3Schristos 1164*1424dfb3Schristos@cindex i386 memory references 1165*1424dfb3Schristos@cindex memory references, i386 1166*1424dfb3Schristos@cindex x86-64 memory references 1167*1424dfb3Schristos@cindex memory references, x86-64 1168*1424dfb3SchristosAn Intel syntax indirect memory reference of the form 1169*1424dfb3Schristos 1170*1424dfb3Schristos@smallexample 1171*1424dfb3Schristos@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 1172*1424dfb3Schristos@end smallexample 1173*1424dfb3Schristos 1174*1424dfb3Schristos@noindent 1175*1424dfb3Schristosis translated into the AT&T syntax 1176*1424dfb3Schristos 1177*1424dfb3Schristos@smallexample 1178*1424dfb3Schristos@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 1179*1424dfb3Schristos@end smallexample 1180*1424dfb3Schristos 1181*1424dfb3Schristos@noindent 1182*1424dfb3Schristoswhere @var{base} and @var{index} are the optional 32-bit base and 1183*1424dfb3Schristosindex registers, @var{disp} is the optional displacement, and 1184*1424dfb3Schristos@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 1185*1424dfb3Schristosto calculate the address of the operand. If no @var{scale} is 1186*1424dfb3Schristosspecified, @var{scale} is taken to be 1. @var{section} specifies the 1187*1424dfb3Schristosoptional section register for the memory operand, and may override the 1188*1424dfb3Schristosdefault section register (see a 80386 manual for section register 1189*1424dfb3Schristosdefaults). Note that section overrides in AT&T syntax @emph{must} 1190*1424dfb3Schristosbe preceded by a @samp{%}. If you specify a section override which 1191*1424dfb3Schristoscoincides with the default section register, @code{@value{AS}} does @emph{not} 1192*1424dfb3Schristosoutput any section register override prefixes to assemble the given 1193*1424dfb3Schristosinstruction. Thus, section overrides can be specified to emphasize which 1194*1424dfb3Schristossection register is used for a given memory operand. 1195*1424dfb3Schristos 1196*1424dfb3SchristosHere are some examples of Intel and AT&T style memory references: 1197*1424dfb3Schristos 1198*1424dfb3Schristos@table @asis 1199*1424dfb3Schristos@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 1200*1424dfb3Schristos@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 1201*1424dfb3Schristosmissing, and the default section is used (@samp{%ss} for addressing with 1202*1424dfb3Schristos@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 1203*1424dfb3Schristos 1204*1424dfb3Schristos@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 1205*1424dfb3Schristos@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 1206*1424dfb3Schristos@samp{foo}. All other fields are missing. The section register here 1207*1424dfb3Schristosdefaults to @samp{%ds}. 1208*1424dfb3Schristos 1209*1424dfb3Schristos@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 1210*1424dfb3SchristosThis uses the value pointed to by @samp{foo} as a memory operand. 1211*1424dfb3SchristosNote that @var{base} and @var{index} are both missing, but there is only 1212*1424dfb3Schristos@emph{one} @samp{,}. This is a syntactic exception. 1213*1424dfb3Schristos 1214*1424dfb3Schristos@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 1215*1424dfb3SchristosThis selects the contents of the variable @samp{foo} with section 1216*1424dfb3Schristosregister @var{section} being @samp{%gs}. 1217*1424dfb3Schristos@end table 1218*1424dfb3Schristos 1219*1424dfb3SchristosAbsolute (as opposed to PC relative) call and jump operands must be 1220*1424dfb3Schristosprefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 1221*1424dfb3Schristosalways chooses PC relative addressing for jump/call labels. 1222*1424dfb3Schristos 1223*1424dfb3SchristosAny instruction that has a memory operand, but no register operand, 1224*1424dfb3Schristos@emph{must} specify its size (byte, word, long, or quadruple) with an 1225*1424dfb3Schristosinstruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, 1226*1424dfb3Schristosrespectively). 1227*1424dfb3Schristos 1228*1424dfb3SchristosThe x86-64 architecture adds an RIP (instruction pointer relative) 1229*1424dfb3Schristosaddressing. This addressing mode is specified by using @samp{rip} as a 1230*1424dfb3Schristosbase register. Only constant offsets are valid. For example: 1231*1424dfb3Schristos 1232*1424dfb3Schristos@table @asis 1233*1424dfb3Schristos@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} 1234*1424dfb3SchristosPoints to the address 1234 bytes past the end of the current 1235*1424dfb3Schristosinstruction. 1236*1424dfb3Schristos 1237*1424dfb3Schristos@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} 1238*1424dfb3SchristosPoints to the @code{symbol} in RIP relative way, this is shorter than 1239*1424dfb3Schristosthe default absolute addressing. 1240*1424dfb3Schristos@end table 1241*1424dfb3Schristos 1242*1424dfb3SchristosOther addressing modes remain unchanged in x86-64 architecture, except 1243*1424dfb3Schristosregisters used are 64-bit instead of 32-bit. 1244*1424dfb3Schristos 1245*1424dfb3Schristos@node i386-Jumps 1246*1424dfb3Schristos@section Handling of Jump Instructions 1247*1424dfb3Schristos 1248*1424dfb3Schristos@cindex jump optimization, i386 1249*1424dfb3Schristos@cindex i386 jump optimization 1250*1424dfb3Schristos@cindex jump optimization, x86-64 1251*1424dfb3Schristos@cindex x86-64 jump optimization 1252*1424dfb3SchristosJump instructions are always optimized to use the smallest possible 1253*1424dfb3Schristosdisplacements. This is accomplished by using byte (8-bit) displacement 1254*1424dfb3Schristosjumps whenever the target is sufficiently close. If a byte displacement 1255*1424dfb3Schristosis insufficient a long displacement is used. We do not support 1256*1424dfb3Schristosword (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 1257*1424dfb3Schristosinstruction with the @samp{data16} instruction prefix), since the 80386 1258*1424dfb3Schristosinsists upon masking @samp{%eip} to 16 bits after the word displacement 1259*1424dfb3Schristosis added. (See also @pxref{i386-Arch}) 1260*1424dfb3Schristos 1261*1424dfb3SchristosNote that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 1262*1424dfb3Schristos@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 1263*1424dfb3Schristosdisplacements, so that if you use these instructions (@code{@value{GCC}} does 1264*1424dfb3Schristosnot use them) you may get an error message (and incorrect code). The AT&T 1265*1424dfb3Schristos80386 assembler tries to get around this problem by expanding @samp{jcxz foo} 1266*1424dfb3Schristosto 1267*1424dfb3Schristos 1268*1424dfb3Schristos@smallexample 1269*1424dfb3Schristos jcxz cx_zero 1270*1424dfb3Schristos jmp cx_nonzero 1271*1424dfb3Schristoscx_zero: jmp foo 1272*1424dfb3Schristoscx_nonzero: 1273*1424dfb3Schristos@end smallexample 1274*1424dfb3Schristos 1275*1424dfb3Schristos@node i386-Float 1276*1424dfb3Schristos@section Floating Point 1277*1424dfb3Schristos 1278*1424dfb3Schristos@cindex i386 floating point 1279*1424dfb3Schristos@cindex floating point, i386 1280*1424dfb3Schristos@cindex x86-64 floating point 1281*1424dfb3Schristos@cindex floating point, x86-64 1282*1424dfb3SchristosAll 80387 floating point types except packed BCD are supported. 1283*1424dfb3Schristos(BCD support may be added without much difficulty). These data 1284*1424dfb3Schristostypes are 16-, 32-, and 64- bit integers, and single (32-bit), 1285*1424dfb3Schristosdouble (64-bit), and extended (80-bit) precision floating point. 1286*1424dfb3SchristosEach supported type has an instruction mnemonic suffix and a constructor 1287*1424dfb3Schristosassociated with it. Instruction mnemonic suffixes specify the operand's 1288*1424dfb3Schristosdata type. Constructors build these data types into memory. 1289*1424dfb3Schristos 1290*1424dfb3Schristos@cindex @code{float} directive, i386 1291*1424dfb3Schristos@cindex @code{single} directive, i386 1292*1424dfb3Schristos@cindex @code{double} directive, i386 1293*1424dfb3Schristos@cindex @code{tfloat} directive, i386 1294*1424dfb3Schristos@cindex @code{float} directive, x86-64 1295*1424dfb3Schristos@cindex @code{single} directive, x86-64 1296*1424dfb3Schristos@cindex @code{double} directive, x86-64 1297*1424dfb3Schristos@cindex @code{tfloat} directive, x86-64 1298*1424dfb3Schristos@itemize @bullet 1299*1424dfb3Schristos@item 1300*1424dfb3SchristosFloating point constructors are @samp{.float} or @samp{.single}, 1301*1424dfb3Schristos@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 1302*1424dfb3SchristosThese correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 1303*1424dfb3Schristosand @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 1304*1424dfb3Schristosonly supports this format via the @samp{fldt} (load 80-bit real to stack 1305*1424dfb3Schristostop) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 1306*1424dfb3Schristos 1307*1424dfb3Schristos@cindex @code{word} directive, i386 1308*1424dfb3Schristos@cindex @code{long} directive, i386 1309*1424dfb3Schristos@cindex @code{int} directive, i386 1310*1424dfb3Schristos@cindex @code{quad} directive, i386 1311*1424dfb3Schristos@cindex @code{word} directive, x86-64 1312*1424dfb3Schristos@cindex @code{long} directive, x86-64 1313*1424dfb3Schristos@cindex @code{int} directive, x86-64 1314*1424dfb3Schristos@cindex @code{quad} directive, x86-64 1315*1424dfb3Schristos@item 1316*1424dfb3SchristosInteger constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 1317*1424dfb3Schristos@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 1318*1424dfb3Schristoscorresponding instruction mnemonic suffixes are @samp{s} (single), 1319*1424dfb3Schristos@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 1320*1424dfb3Schristosthe 64-bit @samp{q} format is only present in the @samp{fildq} (load 1321*1424dfb3Schristosquad integer to stack top) and @samp{fistpq} (store quad integer and pop 1322*1424dfb3Schristosstack) instructions. 1323*1424dfb3Schristos@end itemize 1324*1424dfb3Schristos 1325*1424dfb3SchristosRegister to register operations should not use instruction mnemonic suffixes. 1326*1424dfb3Schristos@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 1327*1424dfb3Schristoswrote @samp{fst %st, %st(1)}, since all register to register operations 1328*1424dfb3Schristosuse 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 1329*1424dfb3Schristoswhich converts @samp{%st} from 80-bit to 64-bit floating point format, 1330*1424dfb3Schristosthen stores the result in the 4 byte location @samp{mem}) 1331*1424dfb3Schristos 1332*1424dfb3Schristos@node i386-SIMD 1333*1424dfb3Schristos@section Intel's MMX and AMD's 3DNow! SIMD Operations 1334*1424dfb3Schristos 1335*1424dfb3Schristos@cindex MMX, i386 1336*1424dfb3Schristos@cindex 3DNow!, i386 1337*1424dfb3Schristos@cindex SIMD, i386 1338*1424dfb3Schristos@cindex MMX, x86-64 1339*1424dfb3Schristos@cindex 3DNow!, x86-64 1340*1424dfb3Schristos@cindex SIMD, x86-64 1341*1424dfb3Schristos 1342*1424dfb3Schristos@code{@value{AS}} supports Intel's MMX instruction set (SIMD 1343*1424dfb3Schristosinstructions for integer data), available on Intel's Pentium MMX 1344*1424dfb3Schristosprocessors and Pentium II processors, AMD's K6 and K6-2 processors, 1345*1424dfb3SchristosCyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: 1346*1424dfb3Schristosinstruction set (SIMD instructions for 32-bit floating point data) 1347*1424dfb3Schristosavailable on AMD's K6-2 processor and possibly others in the future. 1348*1424dfb3Schristos 1349*1424dfb3SchristosCurrently, @code{@value{AS}} does not support Intel's floating point 1350*1424dfb3SchristosSIMD, Katmai (KNI). 1351*1424dfb3Schristos 1352*1424dfb3SchristosThe eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 1353*1424dfb3Schristos@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 1354*1424dfb3Schristos16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 1355*1424dfb3Schristosfloating point values. The MMX registers cannot be used at the same time 1356*1424dfb3Schristosas the floating point stack. 1357*1424dfb3Schristos 1358*1424dfb3SchristosSee Intel and AMD documentation, keeping in mind that the operand order in 1359*1424dfb3Schristosinstructions is reversed from the Intel syntax. 1360*1424dfb3Schristos 1361*1424dfb3Schristos@node i386-LWP 1362*1424dfb3Schristos@section AMD's Lightweight Profiling Instructions 1363*1424dfb3Schristos 1364*1424dfb3Schristos@cindex LWP, i386 1365*1424dfb3Schristos@cindex LWP, x86-64 1366*1424dfb3Schristos 1367*1424dfb3Schristos@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) 1368*1424dfb3Schristosinstruction set, available on AMD's Family 15h (Orochi) processors. 1369*1424dfb3Schristos 1370*1424dfb3SchristosLWP enables applications to collect and manage performance data, and 1371*1424dfb3Schristosreact to performance events. The collection of performance data 1372*1424dfb3Schristosrequires no context switches. LWP runs in the context of a thread and 1373*1424dfb3Schristosso several counters can be used independently across multiple threads. 1374*1424dfb3SchristosLWP can be used in both 64-bit and legacy 32-bit modes. 1375*1424dfb3Schristos 1376*1424dfb3SchristosFor detailed information on the LWP instruction set, see the 1377*1424dfb3Schristos@cite{AMD Lightweight Profiling Specification} available at 1378*1424dfb3Schristos@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. 1379*1424dfb3Schristos 1380*1424dfb3Schristos@node i386-BMI 1381*1424dfb3Schristos@section Bit Manipulation Instructions 1382*1424dfb3Schristos 1383*1424dfb3Schristos@cindex BMI, i386 1384*1424dfb3Schristos@cindex BMI, x86-64 1385*1424dfb3Schristos 1386*1424dfb3Schristos@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. 1387*1424dfb3Schristos 1388*1424dfb3SchristosBMI instructions provide several instructions implementing individual 1389*1424dfb3Schristosbit manipulation operations such as isolation, masking, setting, or 1390*1424dfb3Schristosresetting. 1391*1424dfb3Schristos 1392*1424dfb3Schristos@c Need to add a specification citation here when available. 1393*1424dfb3Schristos 1394*1424dfb3Schristos@node i386-TBM 1395*1424dfb3Schristos@section AMD's Trailing Bit Manipulation Instructions 1396*1424dfb3Schristos 1397*1424dfb3Schristos@cindex TBM, i386 1398*1424dfb3Schristos@cindex TBM, x86-64 1399*1424dfb3Schristos 1400*1424dfb3Schristos@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) 1401*1424dfb3Schristosinstruction set, available on AMD's BDVER2 processors (Trinity and 1402*1424dfb3SchristosViperfish). 1403*1424dfb3Schristos 1404*1424dfb3SchristosTBM instructions provide instructions implementing individual bit 1405*1424dfb3Schristosmanipulation operations such as isolating, masking, setting, resetting, 1406*1424dfb3Schristoscomplementing, and operations on trailing zeros and ones. 1407*1424dfb3Schristos 1408*1424dfb3Schristos@c Need to add a specification citation here when available. 1409*1424dfb3Schristos 1410*1424dfb3Schristos@node i386-16bit 1411*1424dfb3Schristos@section Writing 16-bit Code 1412*1424dfb3Schristos 1413*1424dfb3Schristos@cindex i386 16-bit code 1414*1424dfb3Schristos@cindex 16-bit code, i386 1415*1424dfb3Schristos@cindex real-mode code, i386 1416*1424dfb3Schristos@cindex @code{code16gcc} directive, i386 1417*1424dfb3Schristos@cindex @code{code16} directive, i386 1418*1424dfb3Schristos@cindex @code{code32} directive, i386 1419*1424dfb3Schristos@cindex @code{code64} directive, i386 1420*1424dfb3Schristos@cindex @code{code64} directive, x86-64 1421*1424dfb3SchristosWhile @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code 1422*1424dfb3Schristosor 64-bit x86-64 code depending on the default configuration, 1423*1424dfb3Schristosit also supports writing code to run in real mode or in 16-bit protected 1424*1424dfb3Schristosmode code segments. To do this, put a @samp{.code16} or 1425*1424dfb3Schristos@samp{.code16gcc} directive before the assembly language instructions to 1426*1424dfb3Schristosbe run in 16-bit mode. You can switch @code{@value{AS}} to writing 1427*1424dfb3Schristos32-bit code with the @samp{.code32} directive or 64-bit code with the 1428*1424dfb3Schristos@samp{.code64} directive. 1429*1424dfb3Schristos 1430*1424dfb3Schristos@samp{.code16gcc} provides experimental support for generating 16-bit 1431*1424dfb3Schristoscode from gcc, and differs from @samp{.code16} in that @samp{call}, 1432*1424dfb3Schristos@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 1433*1424dfb3Schristos@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 1434*1424dfb3Schristosdefault to 32-bit size. This is so that the stack pointer is 1435*1424dfb3Schristosmanipulated in the same way over function calls, allowing access to 1436*1424dfb3Schristosfunction parameters at the same stack offsets as in 32-bit mode. 1437*1424dfb3Schristos@samp{.code16gcc} also automatically adds address size prefixes where 1438*1424dfb3Schristosnecessary to use the 32-bit addressing modes that gcc generates. 1439*1424dfb3Schristos 1440*1424dfb3SchristosThe code which @code{@value{AS}} generates in 16-bit mode will not 1441*1424dfb3Schristosnecessarily run on a 16-bit pre-80386 processor. To write code that 1442*1424dfb3Schristosruns on such a processor, you must refrain from using @emph{any} 32-bit 1443*1424dfb3Schristosconstructs which require @code{@value{AS}} to output address or operand 1444*1424dfb3Schristossize prefixes. 1445*1424dfb3Schristos 1446*1424dfb3SchristosNote that writing 16-bit code instructions by explicitly specifying a 1447*1424dfb3Schristosprefix or an instruction mnemonic suffix within a 32-bit code section 1448*1424dfb3Schristosgenerates different machine instructions than those generated for a 1449*1424dfb3Schristos16-bit code segment. In a 32-bit code section, the following code 1450*1424dfb3Schristosgenerates the machine opcode bytes @samp{66 6a 04}, which pushes the 1451*1424dfb3Schristosvalue @samp{4} onto the stack, decrementing @samp{%esp} by 2. 1452*1424dfb3Schristos 1453*1424dfb3Schristos@smallexample 1454*1424dfb3Schristos pushw $4 1455*1424dfb3Schristos@end smallexample 1456*1424dfb3Schristos 1457*1424dfb3SchristosThe same code in a 16-bit code section would generate the machine 1458*1424dfb3Schristosopcode bytes @samp{6a 04} (i.e., without the operand size prefix), which 1459*1424dfb3Schristosis correct since the processor default operand size is assumed to be 16 1460*1424dfb3Schristosbits in a 16-bit code section. 1461*1424dfb3Schristos 1462*1424dfb3Schristos@node i386-Arch 1463*1424dfb3Schristos@section Specifying CPU Architecture 1464*1424dfb3Schristos 1465*1424dfb3Schristos@cindex arch directive, i386 1466*1424dfb3Schristos@cindex i386 arch directive 1467*1424dfb3Schristos@cindex arch directive, x86-64 1468*1424dfb3Schristos@cindex x86-64 arch directive 1469*1424dfb3Schristos 1470*1424dfb3Schristos@code{@value{AS}} may be told to assemble for a particular CPU 1471*1424dfb3Schristos(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This 1472*1424dfb3Schristosdirective enables a warning when gas detects an instruction that is not 1473*1424dfb3Schristossupported on the CPU specified. The choices for @var{cpu_type} are: 1474*1424dfb3Schristos 1475*1424dfb3Schristos@multitable @columnfractions .20 .20 .20 .20 1476*1424dfb3Schristos@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} 1477*1424dfb3Schristos@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} 1478*1424dfb3Schristos@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} 1479*1424dfb3Schristos@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} 1480*1424dfb3Schristos@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} 1481*1424dfb3Schristos@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} 1482*1424dfb3Schristos@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} 1483*1424dfb3Schristos@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} 1484*1424dfb3Schristos@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} 1485*1424dfb3Schristos@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} 1486*1424dfb3Schristos@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a} 1487*1424dfb3Schristos@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} 1488*1424dfb3Schristos@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} 1489*1424dfb3Schristos@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} 1490*1424dfb3Schristos@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} 1491*1424dfb3Schristos@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} 1492*1424dfb3Schristos@item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} 1493*1424dfb3Schristos@item @samp{.hle} 1494*1424dfb3Schristos@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} 1495*1424dfb3Schristos@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} 1496*1424dfb3Schristos@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} 1497*1424dfb3Schristos@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} 1498*1424dfb3Schristos@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} 1499*1424dfb3Schristos@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} 1500*1424dfb3Schristos@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} 1501*1424dfb3Schristos@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} 1502*1424dfb3Schristos@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} 1503*1424dfb3Schristos@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} 1504*1424dfb3Schristos@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} 1505*1424dfb3Schristos@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} 1506*1424dfb3Schristos@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile} 1507*1424dfb3Schristos@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} 1508*1424dfb3Schristos@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} 1509*1424dfb3Schristos@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} 1510*1424dfb3Schristos@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} 1511*1424dfb3Schristos@item @samp{.mcommit} @tab @samp{.sev_es} 1512*1424dfb3Schristos@end multitable 1513*1424dfb3Schristos 1514*1424dfb3SchristosApart from the warning, there are only two other effects on 1515*1424dfb3Schristos@code{@value{AS}} operation; Firstly, if you specify a CPU other than 1516*1424dfb3Schristos@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} 1517*1424dfb3Schristoswill automatically use a two byte opcode sequence. The larger three 1518*1424dfb3Schristosbyte opcode sequence is used on the 486 (and when no architecture is 1519*1424dfb3Schristosspecified) because it executes faster on the 486. Note that you can 1520*1424dfb3Schristosexplicitly request the two byte opcode by writing @samp{sarl %eax}. 1521*1424dfb3SchristosSecondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, 1522*1424dfb3Schristos@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset 1523*1424dfb3Schristosconditional jumps will be promoted when necessary to a two instruction 1524*1424dfb3Schristossequence consisting of a conditional jump of the opposite sense around 1525*1424dfb3Schristosan unconditional jump to the target. 1526*1424dfb3Schristos 1527*1424dfb3SchristosFollowing the CPU architecture (but not a sub-architecture, which are those 1528*1424dfb3Schristosstarting with a dot), you may specify @samp{jumps} or @samp{nojumps} to 1529*1424dfb3Schristoscontrol automatic promotion of conditional jumps. @samp{jumps} is the 1530*1424dfb3Schristosdefault, and enables jump promotion; All external jumps will be of the long 1531*1424dfb3Schristosvariety, and file-local jumps will be promoted as necessary. 1532*1424dfb3Schristos(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as 1533*1424dfb3Schristosbyte offset jumps, and warns about file-local conditional jumps that 1534*1424dfb3Schristos@code{@value{AS}} promotes. 1535*1424dfb3SchristosUnconditional jumps are treated as for @samp{jumps}. 1536*1424dfb3Schristos 1537*1424dfb3SchristosFor example 1538*1424dfb3Schristos 1539*1424dfb3Schristos@smallexample 1540*1424dfb3Schristos .arch i8086,nojumps 1541*1424dfb3Schristos@end smallexample 1542*1424dfb3Schristos 1543*1424dfb3Schristos@node i386-ISA 1544*1424dfb3Schristos@section AMD64 ISA vs. Intel64 ISA 1545*1424dfb3Schristos 1546*1424dfb3SchristosThere are some discrepancies between AMD64 and Intel64 ISAs. 1547*1424dfb3Schristos 1548*1424dfb3Schristos@itemize @bullet 1549*1424dfb3Schristos@item For @samp{movsxd} with 16-bit destination register, AMD64 1550*1424dfb3Schristossupports 32-bit source operand and Intel64 supports 16-bit source 1551*1424dfb3Schristosoperand. 1552*1424dfb3Schristos 1553*1424dfb3Schristos@item For far branches (with explicit memory operand), both ISAs support 1554*1424dfb3Schristos32- and 16-bit operand size. Intel64 additionally supports 64-bit 1555*1424dfb3Schristosoperand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax 1556*1424dfb3Schristosand with an explicit @samp{tbyte ptr} operand size specifier in Intel 1557*1424dfb3Schristossyntax. 1558*1424dfb3Schristos 1559*1424dfb3Schristos@item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16- 1560*1424dfb3Schristosand 32-bit operand size (32- and 48-bit memory operand) in both ISAs, 1561*1424dfb3Schristoswhile Intel64 additionally supports 64-bit operand sise (80-bit memory 1562*1424dfb3Schristosoperands). 1563*1424dfb3Schristos 1564*1424dfb3Schristos@end itemize 1565*1424dfb3Schristos 1566*1424dfb3Schristos@node i386-Bugs 1567*1424dfb3Schristos@section AT&T Syntax bugs 1568*1424dfb3Schristos 1569*1424dfb3SchristosThe UnixWare assembler, and probably other AT&T derived ix86 Unix 1570*1424dfb3Schristosassemblers, generate floating point instructions with reversed source 1571*1424dfb3Schristosand destination registers in certain cases. Unfortunately, gcc and 1572*1424dfb3Schristospossibly many other programs use this reversed syntax, so we're stuck 1573*1424dfb3Schristoswith it. 1574*1424dfb3Schristos 1575*1424dfb3SchristosFor example 1576*1424dfb3Schristos 1577*1424dfb3Schristos@smallexample 1578*1424dfb3Schristos fsub %st,%st(3) 1579*1424dfb3Schristos@end smallexample 1580*1424dfb3Schristos@noindent 1581*1424dfb3Schristosresults in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 1582*1424dfb3Schristosthan the expected @samp{%st(3) - %st}. This happens with all the 1583*1424dfb3Schristosnon-commutative arithmetic floating point operations with two register 1584*1424dfb3Schristosoperands where the source register is @samp{%st} and the destination 1585*1424dfb3Schristosregister is @samp{%st(i)}. 1586*1424dfb3Schristos 1587*1424dfb3Schristos@node i386-Notes 1588*1424dfb3Schristos@section Notes 1589*1424dfb3Schristos 1590*1424dfb3Schristos@cindex i386 @code{mul}, @code{imul} instructions 1591*1424dfb3Schristos@cindex @code{mul} instruction, i386 1592*1424dfb3Schristos@cindex @code{imul} instruction, i386 1593*1424dfb3Schristos@cindex @code{mul} instruction, x86-64 1594*1424dfb3Schristos@cindex @code{imul} instruction, x86-64 1595*1424dfb3SchristosThere is some trickery concerning the @samp{mul} and @samp{imul} 1596*1424dfb3Schristosinstructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding 1597*1424dfb3Schristosmultiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 1598*1424dfb3Schristosfor @samp{imul}) can be output only in the one operand form. Thus, 1599*1424dfb3Schristos@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 1600*1424dfb3Schristosthe expanding multiply would clobber the @samp{%edx} register, and this 1601*1424dfb3Schristoswould confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 1602*1424dfb3Schristos64-bit product in @samp{%edx:%eax}. 1603*1424dfb3Schristos 1604*1424dfb3SchristosWe have added a two operand form of @samp{imul} when the first operand 1605*1424dfb3Schristosis an immediate mode expression and the second operand is a register. 1606*1424dfb3SchristosThis is just a shorthand, so that, multiplying @samp{%eax} by 69, for 1607*1424dfb3Schristosexample, can be done with @samp{imul $69, %eax} rather than @samp{imul 1608*1424dfb3Schristos$69, %eax, %eax}. 1609*1424dfb3Schristos 1610