166e63ce3Schristos #include "config.h" 266e63ce3Schristos #include <stdio.h> 366e63ce3Schristos #include <ctype.h> 466e63ce3Schristos #include <limits.h> 566e63ce3Schristos #include "ansidecl.h" 666e63ce3Schristos #include "gdb/callback.h" 766e63ce3Schristos #include "opcode/d10v.h" 866e63ce3Schristos #include "bfd.h" 966e63ce3Schristos 1066e63ce3Schristos #define DEBUG_TRACE 0x00000001 1166e63ce3Schristos #define DEBUG_VALUES 0x00000002 1266e63ce3Schristos #define DEBUG_LINE_NUMBER 0x00000004 1366e63ce3Schristos #define DEBUG_MEMSIZE 0x00000008 1466e63ce3Schristos #define DEBUG_INSTRUCTION 0x00000010 1566e63ce3Schristos #define DEBUG_TRAP 0x00000020 1666e63ce3Schristos #define DEBUG_MEMORY 0x00000040 1766e63ce3Schristos 1866e63ce3Schristos #ifndef DEBUG 1966e63ce3Schristos #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER) 2066e63ce3Schristos #endif 2166e63ce3Schristos 2266e63ce3Schristos extern int d10v_debug; 2366e63ce3Schristos 2466e63ce3Schristos #include "gdb/remote-sim.h" 2566e63ce3Schristos #include "sim-config.h" 2666e63ce3Schristos #include "sim-types.h" 2766e63ce3Schristos 2866e63ce3Schristos typedef unsigned8 uint8; 2966e63ce3Schristos typedef unsigned16 uint16; 3066e63ce3Schristos typedef signed16 int16; 3166e63ce3Schristos typedef unsigned32 uint32; 3266e63ce3Schristos typedef signed32 int32; 3366e63ce3Schristos typedef unsigned64 uint64; 3466e63ce3Schristos typedef signed64 int64; 3566e63ce3Schristos 3666e63ce3Schristos /* FIXME: D10V defines */ 3766e63ce3Schristos typedef uint16 reg_t; 3866e63ce3Schristos 3966e63ce3Schristos struct simops 4066e63ce3Schristos { 4166e63ce3Schristos long opcode; 4266e63ce3Schristos int is_long; 4366e63ce3Schristos long mask; 4466e63ce3Schristos int format; 4566e63ce3Schristos int cycles; 4666e63ce3Schristos int unit; 4766e63ce3Schristos int exec_type; 48*c03b94e9Schristos void (*func)(SIM_DESC, SIM_CPU *); 4966e63ce3Schristos int numops; 5066e63ce3Schristos int operands[9]; 5166e63ce3Schristos }; 5266e63ce3Schristos 5366e63ce3Schristos enum _ins_type 5466e63ce3Schristos { 5566e63ce3Schristos INS_UNKNOWN, /* unknown instruction */ 5666e63ce3Schristos INS_COND_TRUE, /* # times EXExxx executed other instruction */ 5766e63ce3Schristos INS_COND_FALSE, /* # times EXExxx did not execute other instruction */ 5866e63ce3Schristos INS_COND_JUMP, /* # times JUMP skipped other instruction */ 5966e63ce3Schristos INS_CYCLES, /* # cycles */ 6066e63ce3Schristos INS_LONG, /* long instruction (both containers, ie FM == 11) */ 6166e63ce3Schristos INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */ 6266e63ce3Schristos INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */ 6366e63ce3Schristos INS_PARALLEL, /* # times instruction encoded as L || R (ie, RM == 00) */ 6466e63ce3Schristos 6566e63ce3Schristos INS_LEFT, /* normal left instructions */ 6666e63ce3Schristos INS_LEFT_PARALLEL, /* left side of || */ 6766e63ce3Schristos INS_LEFT_COND_TEST, /* EXExx test on left side */ 6866e63ce3Schristos INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */ 6966e63ce3Schristos INS_LEFT_NOPS, /* NOP on left side */ 7066e63ce3Schristos 7166e63ce3Schristos INS_RIGHT, /* normal right instructions */ 7266e63ce3Schristos INS_RIGHT_PARALLEL, /* right side of || */ 7366e63ce3Schristos INS_RIGHT_COND_TEST, /* EXExx test on right side */ 7466e63ce3Schristos INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */ 7566e63ce3Schristos INS_RIGHT_NOPS, /* NOP on right side */ 7666e63ce3Schristos 7766e63ce3Schristos INS_MAX 7866e63ce3Schristos }; 7966e63ce3Schristos 8066e63ce3Schristos extern unsigned long ins_type_counters[ (int)INS_MAX ]; 8166e63ce3Schristos 8266e63ce3Schristos enum { 8366e63ce3Schristos SP_IDX = 15, 8466e63ce3Schristos }; 8566e63ce3Schristos 8666e63ce3Schristos /* Write-back slots */ 8766e63ce3Schristos union slot_data { 8866e63ce3Schristos unsigned_1 _1; 8966e63ce3Schristos unsigned_2 _2; 9066e63ce3Schristos unsigned_4 _4; 9166e63ce3Schristos unsigned_8 _8; 9266e63ce3Schristos }; 9366e63ce3Schristos struct slot { 9466e63ce3Schristos void *dest; 9566e63ce3Schristos int size; 9666e63ce3Schristos union slot_data data; 9766e63ce3Schristos union slot_data mask; 9866e63ce3Schristos }; 9966e63ce3Schristos enum { 10066e63ce3Schristos NR_SLOTS = 16, 10166e63ce3Schristos }; 10266e63ce3Schristos #define SLOT (State.slot) 10366e63ce3Schristos #define SLOT_NR (State.slot_nr) 10466e63ce3Schristos #define SLOT_PEND_MASK(DEST, MSK, VAL) \ 10566e63ce3Schristos do \ 10666e63ce3Schristos { \ 10766e63ce3Schristos SLOT[SLOT_NR].dest = &(DEST); \ 10866e63ce3Schristos SLOT[SLOT_NR].size = sizeof (DEST); \ 10966e63ce3Schristos switch (sizeof (DEST)) \ 11066e63ce3Schristos { \ 11166e63ce3Schristos case 1: \ 11266e63ce3Schristos SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \ 11366e63ce3Schristos SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \ 11466e63ce3Schristos break; \ 11566e63ce3Schristos case 2: \ 11666e63ce3Schristos SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \ 11766e63ce3Schristos SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \ 11866e63ce3Schristos break; \ 11966e63ce3Schristos case 4: \ 12066e63ce3Schristos SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \ 12166e63ce3Schristos SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \ 12266e63ce3Schristos break; \ 12366e63ce3Schristos case 8: \ 12466e63ce3Schristos SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \ 12566e63ce3Schristos SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \ 12666e63ce3Schristos break; \ 12766e63ce3Schristos } \ 12866e63ce3Schristos SLOT_NR = (SLOT_NR + 1); \ 12966e63ce3Schristos } \ 13066e63ce3Schristos while (0) 13166e63ce3Schristos #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL) 13266e63ce3Schristos #define SLOT_DISCARD() (SLOT_NR = 0) 13366e63ce3Schristos #define SLOT_FLUSH() \ 13466e63ce3Schristos do \ 13566e63ce3Schristos { \ 13666e63ce3Schristos int i; \ 13766e63ce3Schristos for (i = 0; i < SLOT_NR; i++) \ 13866e63ce3Schristos { \ 13966e63ce3Schristos switch (SLOT[i].size) \ 14066e63ce3Schristos { \ 14166e63ce3Schristos case 1: \ 14266e63ce3Schristos *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \ 14366e63ce3Schristos *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \ 14466e63ce3Schristos break; \ 14566e63ce3Schristos case 2: \ 14666e63ce3Schristos *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \ 14766e63ce3Schristos *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \ 14866e63ce3Schristos break; \ 14966e63ce3Schristos case 4: \ 15066e63ce3Schristos *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \ 15166e63ce3Schristos *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \ 15266e63ce3Schristos break; \ 15366e63ce3Schristos case 8: \ 15466e63ce3Schristos *(unsigned_8*) SLOT[i].dest &= SLOT[i].mask._8; \ 15566e63ce3Schristos *(unsigned_8*) SLOT[i].dest |= SLOT[i].data._8; \ 15666e63ce3Schristos break; \ 15766e63ce3Schristos } \ 15866e63ce3Schristos } \ 15966e63ce3Schristos SLOT_NR = 0; \ 16066e63ce3Schristos } \ 16166e63ce3Schristos while (0) 16266e63ce3Schristos #define SLOT_DUMP() \ 16366e63ce3Schristos do \ 16466e63ce3Schristos { \ 16566e63ce3Schristos int i; \ 16666e63ce3Schristos for (i = 0; i < SLOT_NR; i++) \ 16766e63ce3Schristos { \ 16866e63ce3Schristos switch (SLOT[i].size) \ 16966e63ce3Schristos { \ 17066e63ce3Schristos case 1: \ 17166e63ce3Schristos printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \ 17266e63ce3Schristos (long) SLOT[i].dest, \ 17366e63ce3Schristos (unsigned) SLOT[i].mask._1, \ 17466e63ce3Schristos (unsigned) SLOT[i].data._1); \ 17566e63ce3Schristos break; \ 17666e63ce3Schristos case 2: \ 17766e63ce3Schristos printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \ 17866e63ce3Schristos (long) SLOT[i].dest, \ 17966e63ce3Schristos (unsigned) SLOT[i].mask._2, \ 18066e63ce3Schristos (unsigned) SLOT[i].data._2); \ 18166e63ce3Schristos break; \ 18266e63ce3Schristos case 4: \ 18366e63ce3Schristos printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \ 18466e63ce3Schristos (long) SLOT[i].dest, \ 18566e63ce3Schristos (unsigned) SLOT[i].mask._4, \ 18666e63ce3Schristos (unsigned) SLOT[i].data._4); \ 18766e63ce3Schristos break; \ 18866e63ce3Schristos case 8: \ 18966e63ce3Schristos printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \ 19066e63ce3Schristos (long) SLOT[i].dest, \ 19166e63ce3Schristos (unsigned) (SLOT[i].mask._8 >> 32), \ 19266e63ce3Schristos (unsigned) SLOT[i].mask._8, \ 19366e63ce3Schristos (unsigned) (SLOT[i].data._8 >> 32), \ 19466e63ce3Schristos (unsigned) SLOT[i].data._8); \ 19566e63ce3Schristos break; \ 19666e63ce3Schristos } \ 19766e63ce3Schristos } \ 19866e63ce3Schristos } \ 19966e63ce3Schristos while (0) 20066e63ce3Schristos 20166e63ce3Schristos /* d10v memory: There are three separate d10v memory regions IMEM, 20266e63ce3Schristos UMEM and DMEM. The IMEM and DMEM are further broken down into 20366e63ce3Schristos blocks (very like VM pages). */ 20466e63ce3Schristos 20566e63ce3Schristos enum 20666e63ce3Schristos { 20766e63ce3Schristos IMAP_BLOCK_SIZE = 0x20000, 20866e63ce3Schristos DMAP_BLOCK_SIZE = 0x4000, 20966e63ce3Schristos }; 21066e63ce3Schristos 21166e63ce3Schristos /* Implement the three memory regions using sparse arrays. Allocate 21266e63ce3Schristos memory using ``segments''. A segment must be at least as large as 21366e63ce3Schristos a BLOCK - ensures that an access that doesn't cross a block 21466e63ce3Schristos boundary can't cross a segment boundary */ 21566e63ce3Schristos 21666e63ce3Schristos enum 21766e63ce3Schristos { 21866e63ce3Schristos SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */ 21966e63ce3Schristos IMEM_SEGMENTS = 8, /* 1MB */ 22066e63ce3Schristos DMEM_SEGMENTS = 8, /* 1MB */ 22166e63ce3Schristos UMEM_SEGMENTS = 128 /* 16MB */ 22266e63ce3Schristos }; 22366e63ce3Schristos 22466e63ce3Schristos struct d10v_memory 22566e63ce3Schristos { 22666e63ce3Schristos uint8 *insn[IMEM_SEGMENTS]; 22766e63ce3Schristos uint8 *data[DMEM_SEGMENTS]; 22866e63ce3Schristos uint8 *unif[UMEM_SEGMENTS]; 22966e63ce3Schristos }; 23066e63ce3Schristos 23166e63ce3Schristos struct _state 23266e63ce3Schristos { 23366e63ce3Schristos reg_t regs[16]; /* general-purpose registers */ 23466e63ce3Schristos #define GPR(N) (State.regs[(N)] + 0) 23566e63ce3Schristos #define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL)) 23666e63ce3Schristos 23766e63ce3Schristos #define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \ 23866e63ce3Schristos | (uint16) State.regs[(N) + 1]) 23966e63ce3Schristos #define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0) 24066e63ce3Schristos 24166e63ce3Schristos reg_t cregs[16]; /* control registers */ 24266e63ce3Schristos #define CREG(N) (State.cregs[(N)] + 0) 243*c03b94e9Schristos #define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0) 244*c03b94e9Schristos #define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1) 24566e63ce3Schristos 24666e63ce3Schristos reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */ 24766e63ce3Schristos #define HELD_SP(N) (State.sp[(N)] + 0) 24866e63ce3Schristos #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL)) 24966e63ce3Schristos 25066e63ce3Schristos int64 a[2]; /* accumulators */ 25166e63ce3Schristos #define ACC(N) (State.a[(N)] + 0) 25266e63ce3Schristos #define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40) 25366e63ce3Schristos 25466e63ce3Schristos /* writeback info */ 25566e63ce3Schristos struct slot slot[NR_SLOTS]; 25666e63ce3Schristos int slot_nr; 25766e63ce3Schristos 25866e63ce3Schristos /* trace data */ 25966e63ce3Schristos struct { 26066e63ce3Schristos uint16 psw; 26166e63ce3Schristos } trace; 26266e63ce3Schristos 26366e63ce3Schristos uint8 exe; 26466e63ce3Schristos int pc_changed; 26566e63ce3Schristos 26666e63ce3Schristos /* NOTE: everything below this line is not reset by 26766e63ce3Schristos sim_create_inferior() */ 26866e63ce3Schristos 26966e63ce3Schristos struct d10v_memory mem; 27066e63ce3Schristos 27166e63ce3Schristos enum _ins_type ins_type; 27266e63ce3Schristos 27366e63ce3Schristos } State; 27466e63ce3Schristos 27566e63ce3Schristos 27666e63ce3Schristos extern uint16 OP[4]; 27766e63ce3Schristos extern struct simops Simops[]; 27866e63ce3Schristos 27966e63ce3Schristos enum 28066e63ce3Schristos { 28166e63ce3Schristos PSW_CR = 0, 28266e63ce3Schristos BPSW_CR = 1, 28366e63ce3Schristos PC_CR = 2, 28466e63ce3Schristos BPC_CR = 3, 28566e63ce3Schristos DPSW_CR = 4, 28666e63ce3Schristos DPC_CR = 5, 28766e63ce3Schristos RPT_C_CR = 7, 28866e63ce3Schristos RPT_S_CR = 8, 28966e63ce3Schristos RPT_E_CR = 9, 29066e63ce3Schristos MOD_S_CR = 10, 29166e63ce3Schristos MOD_E_CR = 11, 29266e63ce3Schristos IBA_CR = 14, 29366e63ce3Schristos }; 29466e63ce3Schristos 29566e63ce3Schristos enum 29666e63ce3Schristos { 29766e63ce3Schristos PSW_SM_BIT = 0x8000, 29866e63ce3Schristos PSW_EA_BIT = 0x2000, 29966e63ce3Schristos PSW_DB_BIT = 0x1000, 30066e63ce3Schristos PSW_DM_BIT = 0x0800, 30166e63ce3Schristos PSW_IE_BIT = 0x0400, 30266e63ce3Schristos PSW_RP_BIT = 0x0200, 30366e63ce3Schristos PSW_MD_BIT = 0x0100, 30466e63ce3Schristos PSW_FX_BIT = 0x0080, 30566e63ce3Schristos PSW_ST_BIT = 0x0040, 30666e63ce3Schristos PSW_F0_BIT = 0x0008, 30766e63ce3Schristos PSW_F1_BIT = 0x0004, 30866e63ce3Schristos PSW_C_BIT = 0x0001, 30966e63ce3Schristos }; 31066e63ce3Schristos 31166e63ce3Schristos #define PSW CREG (PSW_CR) 31266e63ce3Schristos #define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL)) 31366e63ce3Schristos #define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL)) 314*c03b94e9Schristos #define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1) 31566e63ce3Schristos 31666e63ce3Schristos #define PSW_SM ((PSW & PSW_SM_BIT) != 0) 31766e63ce3Schristos #define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL)) 31866e63ce3Schristos 31966e63ce3Schristos #define PSW_EA ((PSW & PSW_EA_BIT) != 0) 32066e63ce3Schristos #define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL)) 32166e63ce3Schristos 32266e63ce3Schristos #define PSW_DB ((PSW & PSW_DB_BIT) != 0) 32366e63ce3Schristos #define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL)) 32466e63ce3Schristos 32566e63ce3Schristos #define PSW_DM ((PSW & PSW_DM_BIT) != 0) 32666e63ce3Schristos #define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL)) 32766e63ce3Schristos 32866e63ce3Schristos #define PSW_IE ((PSW & PSW_IE_BIT) != 0) 32966e63ce3Schristos #define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL)) 33066e63ce3Schristos 33166e63ce3Schristos #define PSW_RP ((PSW & PSW_RP_BIT) != 0) 33266e63ce3Schristos #define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL)) 33366e63ce3Schristos 33466e63ce3Schristos #define PSW_MD ((PSW & PSW_MD_BIT) != 0) 33566e63ce3Schristos #define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL)) 33666e63ce3Schristos 33766e63ce3Schristos #define PSW_FX ((PSW & PSW_FX_BIT) != 0) 33866e63ce3Schristos #define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL)) 33966e63ce3Schristos 34066e63ce3Schristos #define PSW_ST ((PSW & PSW_ST_BIT) != 0) 34166e63ce3Schristos #define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL)) 34266e63ce3Schristos 34366e63ce3Schristos #define PSW_F0 ((PSW & PSW_F0_BIT) != 0) 34466e63ce3Schristos #define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL)) 34566e63ce3Schristos 34666e63ce3Schristos #define PSW_F1 ((PSW & PSW_F1_BIT) != 0) 34766e63ce3Schristos #define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL)) 34866e63ce3Schristos 34966e63ce3Schristos #define PSW_C ((PSW & PSW_C_BIT) != 0) 35066e63ce3Schristos #define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL)) 35166e63ce3Schristos 35266e63ce3Schristos /* See simopsc.:move_to_cr() for registers that can not be read-from 35366e63ce3Schristos or assigned-to directly */ 35466e63ce3Schristos 35566e63ce3Schristos #define PC CREG (PC_CR) 35666e63ce3Schristos #define SET_PC(VAL) SET_CREG (PC_CR, (VAL)) 35766e63ce3Schristos 35866e63ce3Schristos #define BPSW CREG (BPSW_CR) 35966e63ce3Schristos #define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL)) 36066e63ce3Schristos 36166e63ce3Schristos #define BPC CREG (BPC_CR) 36266e63ce3Schristos #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL)) 36366e63ce3Schristos 36466e63ce3Schristos #define DPSW CREG (DPSW_CR) 36566e63ce3Schristos #define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL)) 36666e63ce3Schristos 36766e63ce3Schristos #define DPC CREG (DPC_CR) 36866e63ce3Schristos #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL)) 36966e63ce3Schristos 37066e63ce3Schristos #define RPT_C CREG (RPT_C_CR) 37166e63ce3Schristos #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL)) 37266e63ce3Schristos 37366e63ce3Schristos #define RPT_S CREG (RPT_S_CR) 37466e63ce3Schristos #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL)) 37566e63ce3Schristos 37666e63ce3Schristos #define RPT_E CREG (RPT_E_CR) 37766e63ce3Schristos #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL)) 37866e63ce3Schristos 37966e63ce3Schristos #define MOD_S CREG (MOD_S_CR) 38066e63ce3Schristos #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL)) 38166e63ce3Schristos 38266e63ce3Schristos #define MOD_E CREG (MOD_E_CR) 38366e63ce3Schristos #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL)) 38466e63ce3Schristos 38566e63ce3Schristos #define IBA CREG (IBA_CR) 38666e63ce3Schristos #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL)) 38766e63ce3Schristos 38866e63ce3Schristos 38966e63ce3Schristos #define SIG_D10V_STOP -1 39066e63ce3Schristos #define SIG_D10V_EXIT -2 39166e63ce3Schristos #define SIG_D10V_BUS -3 39266e63ce3Schristos 393ed6a76a9Schristos /* TODO: Resolve conflicts with common headers. */ 394ed6a76a9Schristos #undef SEXT8 395ed6a76a9Schristos #undef SEXT16 396ed6a76a9Schristos #undef SEXT32 397ed6a76a9Schristos #undef MASK32 398ed6a76a9Schristos 39966e63ce3Schristos #define SEXT3(x) ((((x)&0x7)^(~3))+4) 40066e63ce3Schristos 40166e63ce3Schristos /* sign-extend a 4-bit number */ 40266e63ce3Schristos #define SEXT4(x) ((((x)&0xf)^(~7))+8) 40366e63ce3Schristos 40466e63ce3Schristos /* sign-extend an 8-bit number */ 40566e63ce3Schristos #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) 40666e63ce3Schristos 40766e63ce3Schristos /* sign-extend a 16-bit number */ 40866e63ce3Schristos #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) 40966e63ce3Schristos 41066e63ce3Schristos /* sign-extend a 32-bit number */ 41166e63ce3Schristos #define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000)) 41266e63ce3Schristos 41366e63ce3Schristos /* sign extend a 40 bit number */ 41466e63ce3Schristos #define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000)) 41566e63ce3Schristos 41666e63ce3Schristos /* sign extend a 44 bit number */ 41766e63ce3Schristos #define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000)) 41866e63ce3Schristos 41966e63ce3Schristos /* sign extend a 56 bit number */ 42066e63ce3Schristos #define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000)) 42166e63ce3Schristos 42266e63ce3Schristos /* sign extend a 60 bit number */ 42366e63ce3Schristos #define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000)) 42466e63ce3Schristos 42566e63ce3Schristos #define MAX32 SIGNED64(0x7fffffff) 42666e63ce3Schristos #define MIN32 SIGNED64(0xff80000000) 42766e63ce3Schristos #define MASK32 SIGNED64(0xffffffff) 42866e63ce3Schristos #define MASK40 SIGNED64(0xffffffffff) 42966e63ce3Schristos 43066e63ce3Schristos /* The alignment of MOD_E in the following macro depends upon "i" 43166e63ce3Schristos always being a power of 2. */ 43266e63ce3Schristos #define INC_ADDR(x,i) \ 43366e63ce3Schristos do \ 43466e63ce3Schristos { \ 43566e63ce3Schristos int test_i = i < 0 ? i : ~((i) - 1); \ 43666e63ce3Schristos if (PSW_MD && GPR (x) == (MOD_E & test_i)) \ 43766e63ce3Schristos SET_GPR (x, MOD_S & test_i); \ 43866e63ce3Schristos else \ 43966e63ce3Schristos SET_GPR (x, GPR (x) + (i)); \ 44066e63ce3Schristos } \ 44166e63ce3Schristos while (0) 44266e63ce3Schristos 443*c03b94e9Schristos extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint16 offset); 444*c03b94e9Schristos extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32); 4457af5a897Schristos extern bfd_vma decode_pc (void); 44666e63ce3Schristos 447*c03b94e9Schristos #define RB(x) (*(dmem_addr (sd, cpu, x))) 44866e63ce3Schristos #define SB(addr,data) ( RB(addr) = (data & 0xff)) 44966e63ce3Schristos 45066e63ce3Schristos #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE) 45166e63ce3Schristos #define ENDIAN_INLINE static __inline__ 45266e63ce3Schristos #include "endian.c" 45366e63ce3Schristos #undef ENDIAN_INLINE 45466e63ce3Schristos 45566e63ce3Schristos #else 4567af5a897Schristos extern uint32 get_longword (uint8 *); 4577af5a897Schristos extern uint16 get_word (uint8 *); 4587af5a897Schristos extern int64 get_longlong (uint8 *); 4597af5a897Schristos extern void write_word (uint8 *addr, uint16 data); 4607af5a897Schristos extern void write_longword (uint8 *addr, uint32 data); 4617af5a897Schristos extern void write_longlong (uint8 *addr, int64 data); 46266e63ce3Schristos #endif 46366e63ce3Schristos 464*c03b94e9Schristos #define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data) 465*c03b94e9Schristos #define RW(x) get_word (dmem_addr (sd, cpu, x)) 466*c03b94e9Schristos #define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data) 467*c03b94e9Schristos #define RLW(x) get_longword (dmem_addr (sd, cpu, x)) 46866e63ce3Schristos #define READ_16(x) get_word(x) 46966e63ce3Schristos #define WRITE_16(addr,data) write_word(addr,data) 47066e63ce3Schristos #define READ_64(x) get_longlong(x) 47166e63ce3Schristos #define WRITE_64(addr,data) write_longlong(addr,data) 47266e63ce3Schristos 47366e63ce3Schristos #define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0) 47466e63ce3Schristos 47566e63ce3Schristos #define RIE_VECTOR_START 0xffc2 47666e63ce3Schristos #define AE_VECTOR_START 0xffc3 47766e63ce3Schristos #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ 47866e63ce3Schristos #define DBT_VECTOR_START 0xffd4 47966e63ce3Schristos #define SDBT_VECTOR_START 0xffd5 48066e63ce3Schristos 48166e63ce3Schristos /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in 48266e63ce3Schristos cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) | 48366e63ce3Schristos (VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for 48466e63ce3Schristos PSW is masked for zero bits. */ 48566e63ce3Schristos 486*c03b94e9Schristos extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p); 487