1 /* $NetBSD: pci_2100_a500.c,v 1.10 2011/04/04 20:37:44 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.10 2011/04/04 20:37:44 dyoung Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/syslog.h> 44 45 #include <machine/autoconf.h> 46 47 #include <dev/eisa/eisavar.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <alpha/pci/ttwogareg.h> 53 #include <alpha/pci/ttwogavar.h> 54 #include <alpha/pci/pci_2100_a500.h> 55 56 static bus_space_tag_t pic_iot; 57 static bus_space_handle_t pic_master_ioh; 58 static bus_space_handle_t pic_slave_ioh[4]; 59 static bus_space_handle_t pic_elcr_ioh; 60 61 static const int pic_slave_to_master[4] = { 1, 3, 4, 5 }; 62 63 int dec_2100_a500_pic_intr_map(const struct pci_attach_args *, 64 pci_intr_handle_t *); 65 66 int dec_2100_a500_icic_intr_map(const struct pci_attach_args *, 67 pci_intr_handle_t *); 68 69 const char *dec_2100_a500_intr_string(void *, pci_intr_handle_t); 70 const struct evcnt *dec_2100_a500_intr_evcnt(void *, pci_intr_handle_t); 71 void *dec_2100_a500_intr_establish(void *, pci_intr_handle_t, 72 int, int (*)(void *), void *); 73 void dec_2100_a500_intr_disestablish(void *, void *); 74 75 int dec_2100_a500_eisa_intr_map(void *, u_int, eisa_intr_handle_t *); 76 const char *dec_2100_a500_eisa_intr_string(void *, int); 77 const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int); 78 void *dec_2100_a500_eisa_intr_establish(void *, int, int, int, 79 int (*)(void *), void *); 80 void dec_2100_a500_eisa_intr_disestablish(void *, void *); 81 int dec_2100_a500_eisa_intr_alloc(void *, int, int, int *); 82 83 #define PCI_STRAY_MAX 5 84 85 /* 86 * On systems with cascaded 8259s, it's actually 32. Systems which 87 * use the ICIC interrupt logic have 64, however. 88 */ 89 #define SABLE_MAX_IRQ 64 90 #define SABLE_8259_MAX_IRQ 32 91 92 void dec_2100_a500_iointr(void *, u_long); 93 94 void dec_2100_a500_pic_enable_intr(struct ttwoga_config *, int, int); 95 void dec_2100_a500_pic_init_intr(struct ttwoga_config *); 96 void dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int); 97 void dec_2100_a500_pic_eoi(struct ttwoga_config *, int); 98 99 void dec_2100_a500_icic_enable_intr(struct ttwoga_config *, int, int); 100 void dec_2100_a500_icic_init_intr(struct ttwoga_config *); 101 void dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int); 102 void dec_2100_a500_icic_eoi(struct ttwoga_config *, int); 103 104 #define T2_IRQ_EISA_START 7 105 #define T2_IRQ_EISA_COUNT 16 106 107 #define T2_IRQ_IS_EISA(irq) \ 108 ((irq) >= T2_IRQ_EISA_START && \ 109 (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT)) 110 111 const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = { 112 IST_LEVEL, /* PCI slot 0 A */ 113 IST_LEVEL, /* on-board SCSI */ 114 IST_LEVEL, /* on-board Ethernet */ 115 IST_EDGE, /* mouse */ 116 IST_LEVEL, /* PCI slot 1 A */ 117 IST_LEVEL, /* PCI slot 2 A */ 118 IST_EDGE, /* keyboard */ 119 IST_EDGE, /* floppy (EISA IRQ 0) */ 120 IST_EDGE, /* serial port 1 (EISA IRQ 1) */ 121 IST_EDGE, /* parallel port (EISA IRQ 2) */ 122 IST_NONE, /* EISA IRQ 3 (edge/level) */ 123 IST_NONE, /* EISA IRQ 4 (edge/level) */ 124 IST_NONE, /* EISA IRQ 5 (edge/level) */ 125 IST_NONE, /* EISA IRQ 6 (edge/level) */ 126 IST_NONE, /* EISA IRQ 7 (edge/level) */ 127 IST_EDGE, /* serial port 0 (EISA IRQ 8) */ 128 IST_NONE, /* EISA IRQ 9 (edge/level) */ 129 IST_NONE, /* EISA IRQ 10 (edge/level) */ 130 IST_NONE, /* EISA IRQ 11 (edge/level) */ 131 IST_NONE, /* EISA IRQ 12 (edge/level) */ 132 IST_LEVEL, /* PCI slot 2 B (EISA IRQ 13 n/c) */ 133 IST_NONE, /* EISA IRQ 14 (edge/level) */ 134 IST_NONE, /* EISA IRQ 15 (edge/level) */ 135 IST_LEVEL, /* I2C (XXX double-check this) */ 136 IST_LEVEL, /* PCI slot 0 B */ 137 IST_LEVEL, /* PCI slot 1 B */ 138 IST_LEVEL, /* PCI slot 0 C */ 139 IST_LEVEL, /* PCI slot 1 C */ 140 IST_LEVEL, /* PCI slot 2 C */ 141 IST_LEVEL, /* PCI slot 0 D */ 142 IST_LEVEL, /* PCI slot 1 D */ 143 IST_LEVEL, /* PCI slot 2 D */ 144 145 /* 146 * These are the PCI interrupts on the T3/T4 systems. See 147 * dec_2100_a500_icic_intr_map() for the mapping. 148 */ 149 IST_LEVEL, 150 IST_LEVEL, 151 IST_LEVEL, 152 IST_LEVEL, 153 IST_LEVEL, 154 IST_LEVEL, 155 IST_LEVEL, 156 IST_LEVEL, 157 IST_LEVEL, 158 IST_LEVEL, 159 IST_LEVEL, 160 IST_LEVEL, 161 IST_LEVEL, 162 IST_LEVEL, 163 IST_LEVEL, 164 IST_LEVEL, 165 IST_LEVEL, 166 IST_LEVEL, 167 IST_LEVEL, 168 IST_LEVEL, 169 IST_LEVEL, 170 IST_LEVEL, 171 IST_LEVEL, 172 IST_LEVEL, 173 IST_LEVEL, 174 IST_LEVEL, 175 IST_LEVEL, 176 IST_LEVEL, 177 IST_LEVEL, 178 IST_LEVEL, 179 IST_LEVEL, 180 IST_LEVEL, 181 }; 182 183 void 184 pci_2100_a500_pickintr(struct ttwoga_config *tcp) 185 { 186 pci_chipset_tag_t pc = &tcp->tc_pc; 187 char *cp; 188 int i; 189 190 pic_iot = &tcp->tc_iot; 191 192 pc->pc_intr_v = tcp; 193 pc->pc_intr_string = dec_2100_a500_intr_string; 194 pc->pc_intr_evcnt = dec_2100_a500_intr_evcnt; 195 pc->pc_intr_establish = dec_2100_a500_intr_establish; 196 pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish; 197 198 /* Not supported on T2. */ 199 pc->pc_pciide_compat_intr_establish = NULL; 200 201 tcp->tc_intrtab = alpha_shared_intr_alloc(SABLE_MAX_IRQ, 8); 202 for (i = 0; i < SABLE_MAX_IRQ; i++) { 203 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 204 i, tcp->tc_hose == 0 ? 205 dec_2100_a500_intr_deftype[i] : IST_LEVEL); 206 alpha_shared_intr_set_maxstrays(tcp->tc_intrtab, 207 i, PCI_STRAY_MAX); 208 209 cp = alpha_shared_intr_string(tcp->tc_intrtab, i); 210 sprintf(cp, "irq %d", T2_IRQ_IS_EISA(i) ? 211 i - T2_IRQ_EISA_START : i); 212 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 213 tcp->tc_intrtab, i), EVCNT_TYPE_INTR, NULL, 214 T2_IRQ_IS_EISA(i) ? "eisa" : "T2", cp); 215 } 216 217 /* 64 16-byte vectors per hose. */ 218 tcp->tc_vecbase = 0x800 + ((64 * 16) * tcp->tc_hose); 219 220 /* 221 * T2 uses a custom layout of cascaded 8259 PICs for interrupt 222 * control. T3 and T4 use a built-in interrupt controller. 223 * 224 * Note that the external PCI bus (Hose 1) always uses 225 * the new interrupt controller. 226 */ 227 if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) { 228 pc->pc_intr_map = dec_2100_a500_pic_intr_map; 229 tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr; 230 tcp->tc_setlevel = dec_2100_a500_pic_setlevel; 231 tcp->tc_eoi = dec_2100_a500_pic_eoi; 232 dec_2100_a500_pic_init_intr(tcp); 233 } else { 234 pc->pc_intr_map = dec_2100_a500_icic_intr_map; 235 tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr; 236 tcp->tc_setlevel = dec_2100_a500_icic_setlevel; 237 tcp->tc_eoi = dec_2100_a500_icic_eoi; 238 dec_2100_a500_icic_init_intr(tcp); 239 } 240 } 241 242 void 243 pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec) 244 { 245 246 ec->ec_v = pc->pc_intr_v; 247 ec->ec_intr_map = dec_2100_a500_eisa_intr_map; 248 ec->ec_intr_string = dec_2100_a500_eisa_intr_string; 249 ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 250 ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish; 251 ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 252 } 253 254 void 255 pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic) 256 { 257 258 ic->ic_v = pc->pc_intr_v; 259 ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 260 ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish; 261 ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 262 ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc; 263 } 264 265 /***************************************************************************** 266 * PCI interrupt support. 267 *****************************************************************************/ 268 269 int 270 dec_2100_a500_pic_intr_map(const struct pci_attach_args *pa, 271 pci_intr_handle_t *ihp) 272 { 273 /* 274 * Interrupts in the Sable are even more of a pain than other 275 * Alpha systems. The interrupt logic is made up of 5 8259 276 * PICs, arranged as follows: 277 * 278 * Slave 0 --------------------------------+ 279 * 0 PCI slot 0 A | 280 * 1 on-board SCSI | 281 * 2 on-board Ethernet | 282 * 3 mouse | 283 * 4 PCI slot 1 A | 284 * 5 PCI slot 2 A | 285 * 6 keyboard | 286 * 7 floppy (EISA IRQ 0) | 287 * | 288 * Slave 1 ------------------------+ | Master 289 * 0 serial port 1 (EISA IRQ 1) | | 0 ESC interrupt 290 * 1 parallel port (EISA IRQ 2) | +-- 1 Slave 0 291 * 2 EISA IRQ 3 | 2 reserved 292 * 3 EISA IRQ 4 +---------- 3 Slave 1 293 * 4 EISA IRQ 5 +---------- 4 Slave 2 294 * 5 EISA IRQ 6 | +-- 5 Slave 3 295 * 6 EISA IRQ 7 | | 6 reserved 296 * 7 serial port 0 (EISA IRQ 8) | | 7 n/c 297 * | | 298 * Slave 2 ------------------------+ | 299 * 0 EISA IRQ 9 | 300 * 1 EISA IRQ 10 | 301 * 2 EISA IRQ 11 | 302 * 3 EISA IRQ 12 | 303 * 4 PCI slot 2 B (EISA IRQ 13 n/c) | 304 * 5 EISA IRQ 14 | 305 * 6 EISA IRQ 15 | 306 * 7 I2C | 307 * | 308 * Slave 3 --------------------------------+ 309 * 0 PCI slot 0 B 310 * 1 PCI slot 1 B 311 * 2 PCI slot 0 C 312 * 3 PCI slot 1 C 313 * 4 PCI slot 2 C 314 * 5 PCI slot 0 D 315 * 6 PCI slot 1 D 316 * 7 PCI slot 2 D 317 * 318 * Careful readers will note that the PCEB does not handle ISA 319 * interrupts at all; when ISA interrupts are established, they 320 * must be mapped to Sable interrupts. Thankfully, this is easy 321 * to do. 322 * 323 * The T3 and T4, generally found on Lynx, use a totally different 324 * scheme because they have more PCI interrupts to handle; see below. 325 */ 326 static const int irqmap[9/*device*/][4/*pin*/] = { 327 { 0x02, -1, -1, -1 }, /* 0: on-board Ethernet */ 328 { 0x01, -1, -1, -1 }, /* 1: on-board SCSI */ 329 { -1, -1, -1, -1 }, /* 2: invalid */ 330 { -1, -1, -1, -1 }, /* 3: invalid */ 331 { -1, -1, -1, -1 }, /* 4: invalid */ 332 { -1, -1, -1, -1 }, /* 5: invalid */ 333 { 0x00, 0x18, 0x1a, 0x1d }, /* 6: PCI slot 0 */ 334 { 0x04, 0x19, 0x1b, 0x1e }, /* 7: PCI slot 1 */ 335 { 0x05, 0x14, 0x1c, 0x1f }, /* 8: PCI slot 2 */ 336 }; 337 pcitag_t bustag = pa->pa_intrtag; 338 int buspin = pa->pa_intrpin; 339 pci_chipset_tag_t pc = pa->pa_pc; 340 int device, irq; 341 342 if (buspin == 0) { 343 /* No IRQ used. */ 344 return (1); 345 } 346 347 if (buspin > 4) { 348 printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n", 349 buspin); 350 return (1); 351 } 352 353 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 354 if (device > 8) { 355 printf("dec_2100_a500_pic_intr_map: bad device %d\n", 356 device); 357 return (1); 358 } 359 360 irq = irqmap[device][buspin - 1]; 361 if (irq == -1) { 362 printf("dec_2100_a500_pic_intr_map: no mapping for " 363 "device %d pin %d\n", device, buspin); 364 return (1); 365 } 366 *ihp = irq; 367 return (0); 368 } 369 370 int 371 dec_2100_a500_icic_intr_map(const struct pci_attach_args *pa, 372 pci_intr_handle_t *ihp) 373 { 374 pcitag_t bustag = pa->pa_intrtag; 375 int buspin = pa->pa_intrpin; 376 pci_chipset_tag_t pc = pa->pa_pc; 377 int device, irq; 378 379 if (buspin == 0) { 380 /* No IRQ used. */ 381 return (1); 382 } 383 384 if (buspin > 4) { 385 printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n", 386 buspin); 387 return (1); 388 } 389 390 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 391 switch (device) { 392 case 0: /* on-board Ethernet */ 393 irq = 24; 394 break; 395 396 case 1: /* on-board SCSI */ 397 irq = 28; 398 break; 399 400 case 6: /* PCI slots */ 401 case 7: 402 case 8: 403 irq = (32 + (4 * (device - 6))) + (buspin - 1); 404 break; 405 406 default: 407 printf("dec_2100_a500_icic_intr_map: bad device %d\n", 408 device); 409 return (1); 410 } 411 412 *ihp = irq; 413 return (0); 414 } 415 416 const char * 417 dec_2100_a500_intr_string(void *v, pci_intr_handle_t ih) 418 { 419 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 420 421 if (ih >= SABLE_MAX_IRQ) 422 panic("dec_2100_a500_intr_string: bogus T2 IRQ 0x%lx", ih); 423 424 sprintf(irqstr, "T2 irq %ld", ih); 425 return (irqstr); 426 } 427 428 const struct evcnt * 429 dec_2100_a500_intr_evcnt(void *v, pci_intr_handle_t ih) 430 { 431 struct ttwoga_config *tcp = v; 432 433 if (ih >= SABLE_MAX_IRQ) 434 panic("dec_2100_a500_intr_evcnt: bogus T2 IRQ 0x%lx", ih); 435 436 return (alpha_shared_intr_evcnt(tcp->tc_intrtab, ih)); 437 } 438 439 void * 440 dec_2100_a500_intr_establish(void *v, pci_intr_handle_t ih, int level, 441 int (*func)(void *), void *arg) 442 { 443 struct ttwoga_config *tcp = v; 444 void *cookie; 445 446 if (ih >= SABLE_MAX_IRQ) 447 panic("dec_2100_a500_intr_establish: bogus IRQ 0x%lx", 448 ih); 449 450 cookie = alpha_shared_intr_establish(tcp->tc_intrtab, ih, 451 dec_2100_a500_intr_deftype[ih], level, func, arg, "T2 irq"); 452 453 if (cookie != NULL && 454 alpha_shared_intr_firstactive(tcp->tc_intrtab, ih)) { 455 scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(ih), 456 dec_2100_a500_iointr, tcp, level); 457 (*tcp->tc_enable_intr)(tcp, ih, 1); 458 } 459 460 return (cookie); 461 } 462 463 void 464 dec_2100_a500_intr_disestablish(void *v, void *cookie) 465 { 466 struct ttwoga_config *tcp = v; 467 struct alpha_shared_intrhand *ih = cookie; 468 unsigned int irq = ih->ih_num; 469 int s; 470 471 s = splhigh(); 472 473 alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 474 "T2 irq"); 475 if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 476 (*tcp->tc_enable_intr)(tcp, irq, 0); 477 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 478 irq, dec_2100_a500_intr_deftype[irq]); 479 scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq)); 480 } 481 482 splx(s); 483 } 484 485 /***************************************************************************** 486 * EISA interrupt support. 487 *****************************************************************************/ 488 489 int 490 dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 491 { 492 493 if (eirq > 15) { 494 printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n", 495 eirq); 496 *ihp = -1; 497 return (1); 498 } 499 500 /* 501 * EISA IRQ 13 is not connected. 502 */ 503 if (eirq == 13) { 504 printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not " 505 "connected\n"); 506 *ihp = -1; 507 return (1); 508 } 509 510 /* 511 * Don't map to a T2 IRQ here; we must do this when we hook the 512 * interrupt up, since ISA interrupts aren't explicitly translated. 513 */ 514 515 *ihp = eirq; 516 return (0); 517 } 518 519 const char * 520 dec_2100_a500_eisa_intr_string(void *v, int eirq) 521 { 522 static char irqstr[32]; 523 524 if (eirq > 15 || eirq == 13) 525 panic("dec_2100_a500_eisa_intr_string: bogus EISA IRQ 0x%x", 526 eirq); 527 528 sprintf(irqstr, "eisa irq %d (T2 irq %d)", eirq, 529 eirq + T2_IRQ_EISA_START); 530 return (irqstr); 531 } 532 533 const struct evcnt * 534 dec_2100_a500_eisa_intr_evcnt(void *v, int eirq) 535 { 536 struct ttwoga_config *tcp = v; 537 538 if (eirq > 15 || eirq == 13) 539 panic("dec_2100_a500_eisa_intr_evcnt: bogus EISA IRQ 0x%x", 540 eirq); 541 542 return (alpha_shared_intr_evcnt(tcp->tc_intrtab, 543 eirq + T2_IRQ_EISA_START)); 544 } 545 546 void * 547 dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level, 548 int (*fn)(void *), void *arg) 549 { 550 struct ttwoga_config *tcp = v; 551 void *cookie; 552 int irq; 553 554 if (eirq > 15 || type == IST_NONE) 555 panic("dec_2100_a500_eisa_intr_establish: bogus irq or type"); 556 557 if (eirq == 13) { 558 printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not " 559 "connected\n"); 560 return (NULL); 561 } 562 563 irq = eirq + T2_IRQ_EISA_START; 564 565 /* 566 * We can't change the trigger type of some interrupts. Don't allow 567 * level triggers to be hooked up to non-changeable edge triggers. 568 */ 569 if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) { 570 printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n"); 571 return (NULL); 572 } 573 574 cookie = alpha_shared_intr_establish(tcp->tc_intrtab, irq, 575 type, level, fn, arg, "T2 irq"); 576 577 if (cookie != NULL && 578 alpha_shared_intr_firstactive(tcp->tc_intrtab, irq)) { 579 scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(irq), 580 dec_2100_a500_iointr, tcp, level); 581 (*tcp->tc_setlevel)(tcp, eirq, 582 alpha_shared_intr_get_sharetype(tcp->tc_intrtab, 583 irq) == IST_LEVEL); 584 (*tcp->tc_enable_intr)(tcp, irq, 1); 585 } 586 587 return (cookie); 588 } 589 590 void 591 dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie) 592 { 593 struct ttwoga_config *tcp = v; 594 struct alpha_shared_intrhand *ih = cookie; 595 int s, irq = ih->ih_num; 596 597 s = splhigh(); 598 599 /* Remove it from the link. */ 600 alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 601 "T2 irq"); 602 603 if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 604 (*tcp->tc_enable_intr)(tcp, irq, 0); 605 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 606 irq, dec_2100_a500_intr_deftype[irq]); 607 scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq)); 608 } 609 610 splx(s); 611 } 612 613 int 614 dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp) 615 { 616 617 /* XXX Not supported right now. */ 618 return (1); 619 } 620 621 /***************************************************************************** 622 * Interrupt support routines. 623 *****************************************************************************/ 624 625 #define ICIC_ADDR(tcp, addr) \ 626 do { \ 627 alpha_mb(); \ 628 T2GA((tcp), T2_AIR) = (addr); \ 629 alpha_mb(); \ 630 alpha_mb(); \ 631 (void) T2GA((tcp), T2_AIR); \ 632 alpha_mb(); \ 633 alpha_mb(); \ 634 } while (0) 635 636 #define ICIC_READ(tcp) T2GA((tcp), T2_DIR) 637 #define ICIC_WRITE(tcp, val) \ 638 do { \ 639 alpha_mb(); \ 640 T2GA((tcp), T2_DIR) = (val); \ 641 alpha_mb(); \ 642 alpha_mb(); \ 643 } while (0) 644 645 void 646 dec_2100_a500_iointr(void *arg, u_long vec) 647 { 648 struct ttwoga_config *tcp = arg; 649 int irq, rv; 650 651 irq = SCB_VECTOIDX(vec - tcp->tc_vecbase); 652 653 rv = alpha_shared_intr_dispatch(tcp->tc_intrtab, irq); 654 (*tcp->tc_eoi)(tcp, irq); 655 if (rv == 0) { 656 alpha_shared_intr_stray(tcp->tc_intrtab, irq, "T2 irq"); 657 if (ALPHA_SHARED_INTR_DISABLE(tcp->tc_intrtab, irq)) 658 (*tcp->tc_enable_intr)(tcp, irq, 0); 659 } else 660 alpha_shared_intr_reset_strays(tcp->tc_intrtab, irq); 661 } 662 663 void 664 dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 665 { 666 int pic; 667 u_int8_t bit, mask; 668 669 pic = irq >> 3; 670 bit = 1 << (irq & 0x7); 671 672 mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1); 673 if (onoff) 674 mask &= ~bit; 675 else 676 mask |= bit; 677 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask); 678 } 679 680 void 681 dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 682 { 683 u_int64_t bit, mask; 684 685 bit = 1UL << irq; 686 687 ICIC_ADDR(tcp, 0x40); 688 689 mask = ICIC_READ(tcp); 690 if (onoff) 691 mask &= ~bit; 692 else 693 mask |= bit; 694 ICIC_WRITE(tcp, mask); 695 } 696 697 void 698 dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp) 699 { 700 static const int picaddr[4] = { 701 0x536, 0x53a, 0x53c, 0x53e 702 }; 703 int pic; 704 705 /* 706 * Map the master PIC. 707 */ 708 if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh)) 709 panic("dec_2100_a500_pic_init_intr: unable to map master PIC"); 710 711 /* 712 * Map all slave PICs and mask off the interrupts on them. 713 */ 714 for (pic = 0; pic < 4; pic++) { 715 if (bus_space_map(pic_iot, picaddr[pic], 2, 0, 716 &pic_slave_ioh[pic])) 717 panic("dec_2100_a500_pic_init_intr: unable to map " 718 "slave PIC %d", pic); 719 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff); 720 } 721 722 /* 723 * Map the ELCR registers. 724 */ 725 if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh)) 726 panic("dec_2100_a500_pic_init_intr: unable to map ELCR " 727 "registers"); 728 } 729 730 void 731 dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp) 732 { 733 734 ICIC_ADDR(tcp, 0x40); 735 ICIC_WRITE(tcp, 0xffffffffffffffffUL); 736 } 737 738 void 739 dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 740 { 741 int elcr; 742 u_int8_t bit, mask; 743 744 switch (eirq) { /* EISA IRQ */ 745 case 3: 746 case 4: 747 case 5: 748 case 6: 749 case 7: 750 elcr = 0; 751 bit = 1 << (eirq - 3); 752 break; 753 754 case 9: 755 case 10: 756 case 11: 757 elcr = 0; 758 bit = 1 << (eirq - 4); 759 break; 760 761 case 12: 762 elcr = 1; 763 bit = 1 << (eirq - 12); 764 break; 765 766 case 14: 767 case 15: 768 elcr = 1; 769 bit = 1 << (eirq - 13); 770 break; 771 772 default: 773 panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq); 774 } 775 776 mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 777 if (level) 778 mask |= bit; 779 else 780 mask &= ~bit; 781 bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 782 } 783 784 void 785 dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 786 { 787 u_int64_t bit, mask; 788 789 switch (eirq) { 790 case 3: 791 case 4: 792 case 5: 793 case 6: 794 case 7: 795 case 9: 796 case 10: 797 case 11: 798 case 12: 799 case 14: 800 case 15: 801 bit = 1UL << (eirq + T2_IRQ_EISA_START); 802 803 ICIC_ADDR(tcp, 0x50); 804 mask = ICIC_READ(tcp); 805 if (level) 806 mask |= bit; 807 else 808 mask &= ~bit; 809 ICIC_WRITE(tcp, mask); 810 break; 811 812 default: 813 panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq); 814 } 815 } 816 817 void 818 dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq) 819 { 820 int pic; 821 822 if (irq >= 0 && irq <= 7) 823 pic = 0; 824 else if (irq >= 8 && irq <= 15) 825 pic = 1; 826 else if (irq >= 16 && irq <= 23) 827 pic = 2; 828 else 829 pic = 3; 830 831 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0, 832 0xe0 | (irq - (8 * pic))); 833 bus_space_write_1(pic_iot, pic_master_ioh, 0, 834 0xe0 | pic_slave_to_master[pic]); 835 } 836 837 void 838 dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq) 839 { 840 841 T2GA(tcp, T2_VAR) = irq; 842 alpha_mb(); 843 alpha_mb(); /* MAGIC */ 844 } 845