xref: /netbsd/sys/arch/amiga/dev/cbsc.c (revision 95e1ffb1) 
1 /*	$NetBSD: cbsc.c,v 1.20 2005/12/11 12:16:28 christos Exp $ */
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: cbsc.c,v 1.20 2005/12/11 12:16:28 christos Exp $");
40 
41 #include <sys/types.h>
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/errno.h>
46 #include <sys/ioctl.h>
47 #include <sys/device.h>
48 #include <sys/buf.h>
49 #include <sys/proc.h>
50 #include <sys/user.h>
51 #include <sys/queue.h>
52 
53 #include <uvm/uvm_extern.h>
54 
55 #include <dev/scsipi/scsi_all.h>
56 #include <dev/scsipi/scsipi_all.h>
57 #include <dev/scsipi/scsiconf.h>
58 #include <dev/scsipi/scsi_message.h>
59 
60 #include <machine/cpu.h>
61 #include <machine/param.h>
62 
63 #include <dev/ic/ncr53c9xreg.h>
64 #include <dev/ic/ncr53c9xvar.h>
65 
66 #include <amiga/amiga/isr.h>
67 #include <amiga/dev/cbscvar.h>
68 #include <amiga/dev/zbusvar.h>
69 
70 void	cbscattach(struct device *, struct device *, void *);
71 int	cbscmatch(struct device *, struct cfdata *, void *);
72 
73 /* Linkup to the rest of the kernel */
74 CFATTACH_DECL(cbsc, sizeof(struct cbsc_softc),
75     cbscmatch, cbscattach, NULL, NULL);
76 
77 /*
78  * Functions and the switch for the MI code.
79  */
80 u_char	cbsc_read_reg(struct ncr53c9x_softc *, int);
81 void	cbsc_write_reg(struct ncr53c9x_softc *, int, u_char);
82 int	cbsc_dma_isintr(struct ncr53c9x_softc *);
83 void	cbsc_dma_reset(struct ncr53c9x_softc *);
84 int	cbsc_dma_intr(struct ncr53c9x_softc *);
85 int	cbsc_dma_setup(struct ncr53c9x_softc *, caddr_t *,
86 	    size_t *, int, size_t *);
87 void	cbsc_dma_go(struct ncr53c9x_softc *);
88 void	cbsc_dma_stop(struct ncr53c9x_softc *);
89 int	cbsc_dma_isactive(struct ncr53c9x_softc *);
90 
91 struct ncr53c9x_glue cbsc_glue = {
92 	cbsc_read_reg,
93 	cbsc_write_reg,
94 	cbsc_dma_isintr,
95 	cbsc_dma_reset,
96 	cbsc_dma_intr,
97 	cbsc_dma_setup,
98 	cbsc_dma_go,
99 	cbsc_dma_stop,
100 	cbsc_dma_isactive,
101 	0,
102 };
103 
104 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
105 u_long cbsc_max_dma = 1024;
106 extern int ser_open_speed;
107 
108 u_long cbsc_cnt_pio = 0;	/* number of PIO transfers */
109 u_long cbsc_cnt_dma = 0;	/* number of DMA transfers */
110 u_long cbsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
111 u_long cbsc_cnt_dma3 = 0;	/* number of pages combined */
112 
113 #ifdef DEBUG
114 struct {
115 	u_char hardbits;
116 	u_char status;
117 	u_char xx;
118 	u_char yy;
119 } cbsc_trace[128];
120 int cbsc_trace_ptr = 0;
121 int cbsc_trace_enable = 1;
122 void cbsc_dump(void);
123 #endif
124 
125 /*
126  * if we are a Phase5 CyberSCSI [mark I?]
127  */
128 int
129 cbscmatch(struct device *parent, struct cfdata *cf, void *aux)
130 {
131 	struct zbus_args *zap;
132 	volatile u_char *regs;
133 
134 	zap = aux;
135 	if (zap->manid != 0x2140)
136 		return(0);		/* It's not Phase5 */
137 	if (zap->prodid != 12 && zap->prodid != 11)
138 		return(0);		/* Not CyberStorm MKI SCSI */
139 	if (zap->prodid == 11 && iszthreepa(zap->pa))
140 		return(0);		/* Fastlane Z3! */
141 	regs = &((volatile u_char *)zap->va)[0xf400];
142 	if (badaddr((caddr_t)__UNVOLATILE(regs)))
143 		return(0);
144 	regs[NCR_CFG1 * 4] = 0;
145 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
146 	delay(5);
147 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
148 		return(0);
149 	return(1);
150 }
151 
152 /*
153  * Attach this instance, and then all the sub-devices
154  */
155 void
156 cbscattach(struct device *parent, struct device *self, void *aux)
157 {
158 	struct cbsc_softc *csc = (void *)self;
159 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
160 	struct zbus_args  *zap;
161 	extern u_long scsi_nosync;
162 	extern int shift_nosync;
163 	extern int ncr53c9x_debug;
164 
165 	/*
166 	 * Set up the glue for MI code early; we use some of it here.
167 	 */
168 	sc->sc_glue = &cbsc_glue;
169 
170 	/*
171 	 * Save the regs
172 	 */
173 	zap = aux;
174 	csc->sc_reg = &((volatile u_char *)zap->va)[0xf400];
175 	csc->sc_dmabase = &csc->sc_reg[0x400];
176 
177 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
178 
179 	printf(": address %p", csc->sc_reg);
180 
181 	sc->sc_id = 7;
182 
183 	/*
184 	 * It is necessary to try to load the 2nd config register here,
185 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
186 	 * will not set up the defaults correctly.
187 	 */
188 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
189 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
190 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
191 	sc->sc_rev = NCR_VARIANT_FAS216;
192 
193 	/*
194 	 * This is the value used to start sync negotiations
195 	 * Note that the NCR register "SYNCTP" is programmed
196 	 * in "clocks per byte", and has a minimum value of 4.
197 	 * The SCSI period used in negotiation is one-fourth
198 	 * of the time (in nanoseconds) needed to transfer one byte.
199 	 * Since the chip's clock is given in MHz, we have the following
200 	 * formula: 4 * period = (1000 / freq) * 4
201 	 */
202 	sc->sc_minsync = 1000 / sc->sc_freq;
203 
204 	/*
205 	 * get flags from -I argument and set cf_flags.
206 	 * NOTE: low 8 bits are to disable disconnect, and the next
207 	 *       8 bits are to disable sync.
208 	 */
209 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
210 	    & 0xffff;
211 	shift_nosync += 16;
212 
213 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
214 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
215 	shift_nosync += 16;
216 
217 #if 1
218 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
219 		sc->sc_minsync = 0;
220 #endif
221 
222 	/* Really no limit, but since we want to fit into the TCR... */
223 	sc->sc_maxxfer = 64 * 1024;
224 
225 	/*
226 	 * Configure interrupts.
227 	 */
228 	csc->sc_isr.isr_intr = ncr53c9x_intr;
229 	csc->sc_isr.isr_arg  = sc;
230 	csc->sc_isr.isr_ipl  = 2;
231 	add_isr(&csc->sc_isr);
232 
233 	/*
234 	 * Now try to attach all the sub-devices
235 	 */
236 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
237 	sc->sc_adapter.adapt_minphys = minphys;
238 	ncr53c9x_attach(sc);
239 }
240 
241 /*
242  * Glue functions.
243  */
244 
245 u_char
246 cbsc_read_reg(struct ncr53c9x_softc *sc, int reg)
247 {
248 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
249 
250 	return csc->sc_reg[reg * 4];
251 }
252 
253 void
254 cbsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
255 {
256 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
257 	u_char v = val;
258 
259 	csc->sc_reg[reg * 4] = v;
260 #ifdef DEBUG
261 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
262   reg == NCR_CMD/* && csc->sc_active*/) {
263   cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v;
264 /*  printf(" cmd %x", v);*/
265 }
266 #endif
267 }
268 
269 int
270 cbsc_dma_isintr(struct ncr53c9x_softc *sc)
271 {
272 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
273 
274 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
275 		return 0;
276 
277 	if (sc->sc_state == NCR_CONNECTED)
278 		csc->sc_portbits |= CBSC_PB_LED;
279 	else
280 		csc->sc_portbits &= ~CBSC_PB_LED;
281 	csc->sc_reg[0x802] = csc->sc_portbits;
282 
283 	if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0)
284 		return 0;
285 #ifdef DEBUG
286 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) {
287   cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
288   cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
289   cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active;
290   cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127;
291 }
292 #endif
293 	return 1;
294 }
295 
296 void
297 cbsc_dma_reset(struct ncr53c9x_softc *sc)
298 {
299 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
300 
301 	csc->sc_active = 0;
302 }
303 
304 int
305 cbsc_dma_intr(struct ncr53c9x_softc *sc)
306 {
307 	register struct cbsc_softc *csc = (struct cbsc_softc *)sc;
308 	register int	cnt;
309 
310 	NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ",
311 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
312 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
313 	if (csc->sc_active == 0) {
314 		printf("cbsc_intr--inactive DMA\n");
315 		return -1;
316 	}
317 
318 	/* update sc_dmaaddr and sc_pdmalen */
319 	cnt = csc->sc_reg[NCR_TCL * 4];
320 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
321 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
322 	if (!csc->sc_datain) {
323 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
324 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
325 	}
326 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
327 	NCR_DMA(("DMA xferred %d\n", cnt));
328 	if (csc->sc_xfr_align) {
329 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
330 		csc->sc_xfr_align = 0;
331 	}
332 	*csc->sc_dmaaddr += cnt;
333 	*csc->sc_pdmalen -= cnt;
334 	csc->sc_active = 0;
335 	return 0;
336 }
337 
338 int
339 cbsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
340                int datain, size_t *dmasize)
341 {
342 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
343 	paddr_t pa;
344 	u_char *ptr;
345 	size_t xfer;
346 
347 	csc->sc_dmaaddr = addr;
348 	csc->sc_pdmalen = len;
349 	csc->sc_datain = datain;
350 	csc->sc_dmasize = *dmasize;
351 	/*
352 	 * DMA can be nasty for high-speed serial input, so limit the
353 	 * size of this DMA operation if the serial port is running at
354 	 * a high speed (higher than 19200 for now - should be adjusted
355 	 * based on CPU type and speed?).
356 	 * XXX - add serial speed check XXX
357 	 */
358 	if (ser_open_speed > 19200 && cbsc_max_dma != 0 &&
359 	    csc->sc_dmasize > cbsc_max_dma)
360 		csc->sc_dmasize = cbsc_max_dma;
361 	ptr = *addr;			/* Kernel virtual address */
362 	pa = kvtop(ptr);		/* Physical address of DMA */
363 	xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
364 	csc->sc_xfr_align = 0;
365 	/*
366 	 * If output and unaligned, stuff odd byte into FIFO
367 	 */
368 	if (datain == 0 && (int)ptr & 1) {
369 		NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n"));
370 		pa++;
371 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
372 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
373 	}
374 	/*
375 	 * If unaligned address, read unaligned bytes into alignment buffer
376 	 */
377 	else if ((int)ptr & 1) {
378 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
379 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
380 		NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer));
381 		csc->sc_xfr_align = 1;
382 	}
383 ++cbsc_cnt_dma;		/* number of DMA operations */
384 
385 	while (xfer < csc->sc_dmasize) {
386 		if ((pa + xfer) != kvtop(*addr + xfer))
387 			break;
388 		if ((csc->sc_dmasize - xfer) < PAGE_SIZE)
389 			xfer = csc->sc_dmasize;
390 		else
391 			xfer += PAGE_SIZE;
392 ++cbsc_cnt_dma3;
393 	}
394 if (xfer != *len)
395   ++cbsc_cnt_dma2;
396 
397 	csc->sc_dmasize = xfer;
398 	*dmasize = csc->sc_dmasize;
399 	csc->sc_pa = pa;
400 #if defined(M68040) || defined(M68060)
401 	if (mmutype == MMU_68040) {
402 		if (csc->sc_xfr_align) {
403 			dma_cachectl(csc->sc_alignbuf,
404 			    sizeof(csc->sc_alignbuf));
405 		}
406 		else
407 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
408 	}
409 #endif
410 
411 	if (csc->sc_datain)
412 		pa &= ~1;
413 	else
414 		pa |= 1;
415 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
416 	csc->sc_dmabase[2] = (u_int8_t)(pa >> 16);
417 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 8);
418 	csc->sc_dmabase[6] = (u_int8_t)(pa);
419 	if (csc->sc_datain)
420 		csc->sc_portbits &= ~CBSC_PB_WRITE;
421 	else
422 		csc->sc_portbits |= CBSC_PB_WRITE;
423 	csc->sc_reg[0x802] = csc->sc_portbits;
424 	csc->sc_active = 1;
425 	return 0;
426 }
427 
428 void
429 cbsc_dma_go(struct ncr53c9x_softc *sc)
430 {
431 }
432 
433 void
434 cbsc_dma_stop(struct ncr53c9x_softc *sc)
435 {
436 }
437 
438 int
439 cbsc_dma_isactive(struct ncr53c9x_softc *sc)
440 {
441 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
442 
443 	return csc->sc_active;
444 }
445 
446 #ifdef DEBUG
447 void
448 cbsc_dump(void)
449 {
450 	int i;
451 
452 	i = cbsc_trace_ptr;
453 	printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr);
454 	do {
455 		if (cbsc_trace[i].hardbits == 0) {
456 			i = (i + 1) & 127;
457 			continue;
458 		}
459 		printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits,
460 		    cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy);
461 		if (cbsc_trace[i].status & NCRSTAT_INT)
462 			printf("NCRINT/");
463 		if (cbsc_trace[i].status & NCRSTAT_TC)
464 			printf("NCRTC/");
465 		switch(cbsc_trace[i].status & NCRSTAT_PHASE) {
466 		case 0:
467 			printf("dataout"); break;
468 		case 1:
469 			printf("datain"); break;
470 		case 2:
471 			printf("cmdout"); break;
472 		case 3:
473 			printf("status"); break;
474 		case 6:
475 			printf("msgout"); break;
476 		case 7:
477 			printf("msgin"); break;
478 		default:
479 			printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE);
480 		}
481 		printf(") ");
482 		i = (i + 1) & 127;
483 	} while (i != cbsc_trace_ptr);
484 	printf("\n");
485 }
486 #endif
487