1 /* $NetBSD: cbsc.c,v 1.31 2010/06/06 04:50:06 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include "opt_m68k_arch.h" 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cbsc.c,v 1.31 2010/06/06 04:50:06 mrg Exp $"); 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/ioctl.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 #include <sys/proc.h> 48 #include <sys/queue.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/cpu.h> 58 #include <machine/param.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <amiga/amiga/isr.h> 64 #include <amiga/dev/cbscvar.h> 65 #include <amiga/dev/zbusvar.h> 66 67 #ifdef __powerpc__ 68 #define badaddr(a) badaddr_read(a, 2, NULL) 69 #endif 70 71 int cbscmatch(device_t, cfdata_t, void *); 72 void cbscattach(device_t, device_t, void *); 73 74 /* Linkup to the rest of the kernel */ 75 CFATTACH_DECL_NEW(cbsc, sizeof(struct cbsc_softc), 76 cbscmatch, cbscattach, NULL, NULL); 77 78 /* 79 * Functions and the switch for the MI code. 80 */ 81 uint8_t cbsc_read_reg(struct ncr53c9x_softc *, int); 82 void cbsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 83 int cbsc_dma_isintr(struct ncr53c9x_softc *); 84 void cbsc_dma_reset(struct ncr53c9x_softc *); 85 int cbsc_dma_intr(struct ncr53c9x_softc *); 86 int cbsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 87 size_t *, int, size_t *); 88 void cbsc_dma_go(struct ncr53c9x_softc *); 89 void cbsc_dma_stop(struct ncr53c9x_softc *); 90 int cbsc_dma_isactive(struct ncr53c9x_softc *); 91 92 struct ncr53c9x_glue cbsc_glue = { 93 cbsc_read_reg, 94 cbsc_write_reg, 95 cbsc_dma_isintr, 96 cbsc_dma_reset, 97 cbsc_dma_intr, 98 cbsc_dma_setup, 99 cbsc_dma_go, 100 cbsc_dma_stop, 101 cbsc_dma_isactive, 102 NULL, 103 }; 104 105 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 106 u_long cbsc_max_dma = 1024; 107 extern int ser_open_speed; 108 109 u_long cbsc_cnt_pio = 0; /* number of PIO transfers */ 110 u_long cbsc_cnt_dma = 0; /* number of DMA transfers */ 111 u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 112 u_long cbsc_cnt_dma3 = 0; /* number of pages combined */ 113 114 #ifdef DEBUG 115 struct { 116 uint8_t hardbits; 117 uint8_t status; 118 uint8_t xx; 119 uint8_t yy; 120 } cbsc_trace[128]; 121 int cbsc_trace_ptr = 0; 122 int cbsc_trace_enable = 1; 123 void cbsc_dump(void); 124 #endif 125 126 /* 127 * if we are a Phase5 CyberSCSI [mark I?] 128 */ 129 int 130 cbscmatch(device_t parent, cfdata_t cf, void *aux) 131 { 132 struct zbus_args *zap; 133 volatile uint8_t *regs; 134 135 zap = aux; 136 if (zap->manid != 0x2140) 137 return 0; /* It's not Phase5 */ 138 if (zap->prodid != 12 && zap->prodid != 11) 139 return 0; /* Not CyberStorm MKI SCSI */ 140 if (zap->prodid == 11 && iszthreepa(zap->pa)) 141 return 0; /* Fastlane Z3! */ 142 regs = &((volatile uint8_t *)zap->va)[0xf400]; 143 if (badaddr((void *)__UNVOLATILE(regs))) 144 return 0; 145 regs[NCR_CFG1 * 4] = 0; 146 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 147 delay(5); 148 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 149 return 0; 150 return 1; 151 } 152 153 /* 154 * Attach this instance, and then all the sub-devices 155 */ 156 void 157 cbscattach(device_t parent, device_t self, void *aux) 158 { 159 struct cbsc_softc *csc = device_private(self); 160 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 161 struct zbus_args *zap; 162 extern u_long scsi_nosync; 163 extern int shift_nosync; 164 extern int ncr53c9x_debug; 165 166 /* 167 * Set up the glue for MI code early; we use some of it here. 168 */ 169 sc->sc_dev = self; 170 sc->sc_glue = &cbsc_glue; 171 172 /* 173 * Save the regs 174 */ 175 zap = aux; 176 csc->sc_reg = &((volatile uint8_t *)zap->va)[0xf400]; 177 csc->sc_dmabase = &csc->sc_reg[0x400]; 178 179 sc->sc_freq = 40; /* Clocked at 40 MHz */ 180 181 aprint_normal(": address %p", csc->sc_reg); 182 183 sc->sc_id = 7; 184 185 /* 186 * It is necessary to try to load the 2nd config register here, 187 * to find out what rev the FAS chip is, else the ncr53c9x_reset 188 * will not set up the defaults correctly. 189 */ 190 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 191 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 192 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 193 sc->sc_rev = NCR_VARIANT_FAS216; 194 195 /* 196 * This is the value used to start sync negotiations 197 * Note that the NCR register "SYNCTP" is programmed 198 * in "clocks per byte", and has a minimum value of 4. 199 * The SCSI period used in negotiation is one-fourth 200 * of the time (in nanoseconds) needed to transfer one byte. 201 * Since the chip's clock is given in MHz, we have the following 202 * formula: 4 * period = (1000 / freq) * 4 203 */ 204 sc->sc_minsync = 1000 / sc->sc_freq; 205 206 /* 207 * get flags from -I argument and set cf_flags. 208 * NOTE: low 8 bits are to disable disconnect, and the next 209 * 8 bits are to disable sync. 210 */ 211 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 212 & 0xffff; 213 shift_nosync += 16; 214 215 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 216 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 217 shift_nosync += 16; 218 219 #if 1 220 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 221 sc->sc_minsync = 0; 222 #endif 223 224 /* Really no limit, but since we want to fit into the TCR... */ 225 sc->sc_maxxfer = 64 * 1024; 226 227 /* 228 * Configure interrupts. 229 */ 230 csc->sc_isr.isr_intr = ncr53c9x_intr; 231 csc->sc_isr.isr_arg = sc; 232 csc->sc_isr.isr_ipl = 2; 233 add_isr(&csc->sc_isr); 234 235 /* 236 * Now try to attach all the sub-devices 237 */ 238 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 239 sc->sc_adapter.adapt_minphys = minphys; 240 ncr53c9x_attach(sc); 241 } 242 243 /* 244 * Glue functions. 245 */ 246 247 uint8_t 248 cbsc_read_reg(struct ncr53c9x_softc *sc, int reg) 249 { 250 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 251 252 return csc->sc_reg[reg * 4]; 253 } 254 255 void 256 cbsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 257 { 258 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 259 uint8_t v = val; 260 261 csc->sc_reg[reg * 4] = v; 262 #ifdef DEBUG 263 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 264 reg == NCR_CMD/* && csc->sc_active*/) { 265 cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v; 266 /* printf(" cmd %x", v);*/ 267 } 268 #endif 269 } 270 271 int 272 cbsc_dma_isintr(struct ncr53c9x_softc *sc) 273 { 274 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 275 276 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 277 return 0; 278 279 if (sc->sc_state == NCR_CONNECTED) 280 csc->sc_portbits |= CBSC_PB_LED; 281 else 282 csc->sc_portbits &= ~CBSC_PB_LED; 283 csc->sc_reg[0x802] = csc->sc_portbits; 284 285 if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0) 286 return 0; 287 #ifdef DEBUG 288 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) { 289 cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 290 cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 291 cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active; 292 cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127; 293 } 294 #endif 295 return 1; 296 } 297 298 void 299 cbsc_dma_reset(struct ncr53c9x_softc *sc) 300 { 301 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 302 303 csc->sc_active = 0; 304 } 305 306 int 307 cbsc_dma_intr(struct ncr53c9x_softc *sc) 308 { 309 register struct cbsc_softc *csc = (struct cbsc_softc *)sc; 310 register int cnt; 311 312 NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ", 313 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 314 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 315 if (csc->sc_active == 0) { 316 printf("cbsc_intr--inactive DMA\n"); 317 return -1; 318 } 319 320 /* update sc_dmaaddr and sc_pdmalen */ 321 cnt = csc->sc_reg[NCR_TCL * 4]; 322 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 323 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 324 if (!csc->sc_datain) { 325 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 326 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 327 } 328 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 329 NCR_DMA(("DMA xferred %d\n", cnt)); 330 if (csc->sc_xfr_align) { 331 memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt); 332 csc->sc_xfr_align = 0; 333 } 334 *csc->sc_dmaaddr += cnt; 335 *csc->sc_pdmalen -= cnt; 336 csc->sc_active = 0; 337 return 0; 338 } 339 340 int 341 cbsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 342 int datain, size_t *dmasize) 343 { 344 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 345 paddr_t pa; 346 uint8_t *ptr; 347 size_t xfer; 348 349 csc->sc_dmaaddr = addr; 350 csc->sc_pdmalen = len; 351 csc->sc_datain = datain; 352 csc->sc_dmasize = *dmasize; 353 /* 354 * DMA can be nasty for high-speed serial input, so limit the 355 * size of this DMA operation if the serial port is running at 356 * a high speed (higher than 19200 for now - should be adjusted 357 * based on CPU type and speed?). 358 * XXX - add serial speed check XXX 359 */ 360 if (ser_open_speed > 19200 && cbsc_max_dma != 0 && 361 csc->sc_dmasize > cbsc_max_dma) 362 csc->sc_dmasize = cbsc_max_dma; 363 ptr = *addr; /* Kernel virtual address */ 364 pa = kvtop(ptr); /* Physical address of DMA */ 365 xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 366 csc->sc_xfr_align = 0; 367 /* 368 * If output and unaligned, stuff odd byte into FIFO 369 */ 370 if (datain == 0 && (int)ptr & 1) { 371 NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n")); 372 pa++; 373 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 374 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 375 } 376 /* 377 * If unaligned address, read unaligned bytes into alignment buffer 378 */ 379 else if ((int)ptr & 1) { 380 pa = kvtop((void *)&csc->sc_alignbuf); 381 xfer = csc->sc_dmasize = min(xfer, sizeof(csc->sc_alignbuf)); 382 NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer)); 383 csc->sc_xfr_align = 1; 384 } 385 ++cbsc_cnt_dma; /* number of DMA operations */ 386 387 while (xfer < csc->sc_dmasize) { 388 if ((pa + xfer) != kvtop(*addr + xfer)) 389 break; 390 if ((csc->sc_dmasize - xfer) < PAGE_SIZE) 391 xfer = csc->sc_dmasize; 392 else 393 xfer += PAGE_SIZE; 394 ++cbsc_cnt_dma3; 395 } 396 if (xfer != *len) 397 ++cbsc_cnt_dma2; 398 399 csc->sc_dmasize = xfer; 400 *dmasize = csc->sc_dmasize; 401 csc->sc_pa = pa; 402 #if defined(M68040) || defined(M68060) 403 if (mmutype == MMU_68040) { 404 if (csc->sc_xfr_align) { 405 dma_cachectl(csc->sc_alignbuf, 406 sizeof(csc->sc_alignbuf)); 407 } 408 else 409 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 410 } 411 #endif 412 413 if (csc->sc_datain) 414 pa &= ~1; 415 else 416 pa |= 1; 417 csc->sc_dmabase[0] = (uint8_t)(pa >> 24); 418 csc->sc_dmabase[2] = (uint8_t)(pa >> 16); 419 csc->sc_dmabase[4] = (uint8_t)(pa >> 8); 420 csc->sc_dmabase[6] = (uint8_t)(pa); 421 if (csc->sc_datain) 422 csc->sc_portbits &= ~CBSC_PB_WRITE; 423 else 424 csc->sc_portbits |= CBSC_PB_WRITE; 425 csc->sc_reg[0x802] = csc->sc_portbits; 426 csc->sc_active = 1; 427 return 0; 428 } 429 430 void 431 cbsc_dma_go(struct ncr53c9x_softc *sc) 432 { 433 } 434 435 void 436 cbsc_dma_stop(struct ncr53c9x_softc *sc) 437 { 438 } 439 440 int 441 cbsc_dma_isactive(struct ncr53c9x_softc *sc) 442 { 443 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 444 445 return csc->sc_active; 446 } 447 448 #ifdef DEBUG 449 void 450 cbsc_dump(void) 451 { 452 int i; 453 454 i = cbsc_trace_ptr; 455 printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr); 456 do { 457 if (cbsc_trace[i].hardbits == 0) { 458 i = (i + 1) & 127; 459 continue; 460 } 461 printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits, 462 cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy); 463 if (cbsc_trace[i].status & NCRSTAT_INT) 464 printf("NCRINT/"); 465 if (cbsc_trace[i].status & NCRSTAT_TC) 466 printf("NCRTC/"); 467 switch(cbsc_trace[i].status & NCRSTAT_PHASE) { 468 case 0: 469 printf("dataout"); break; 470 case 1: 471 printf("datain"); break; 472 case 2: 473 printf("cmdout"); break; 474 case 3: 475 printf("status"); break; 476 case 6: 477 printf("msgout"); break; 478 case 7: 479 printf("msgin"); break; 480 default: 481 printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE); 482 } 483 printf(") "); 484 i = (i + 1) & 127; 485 } while (i != cbsc_trace_ptr); 486 printf("\n"); 487 } 488 #endif 489