xref: /netbsd/sys/arch/arm/iomd/iomd_dma.c (revision 758ec341)
1*758ec341Sbjh21 /* 	$NetBSD: iomd_dma.c,v 1.10 2006/08/05 18:22:57 bjh21 Exp $	*/
27d4a1addSreinoud 
37d4a1addSreinoud /*
47d4a1addSreinoud  * Copyright (c) 1995 Scott Stevens
57d4a1addSreinoud  * All rights reserved.
67d4a1addSreinoud  *
77d4a1addSreinoud  * Redistribution and use in source and binary forms, with or without
87d4a1addSreinoud  * modification, are permitted provided that the following conditions
97d4a1addSreinoud  * are met:
107d4a1addSreinoud  * 1. Redistributions of source code must retain the above copyright
117d4a1addSreinoud  *    notice, this list of conditions and the following disclaimer.
127d4a1addSreinoud  * 2. Redistributions in binary form must reproduce the above copyright
137d4a1addSreinoud  *    notice, this list of conditions and the following disclaimer in the
147d4a1addSreinoud  *    documentation and/or other materials provided with the distribution.
157d4a1addSreinoud  * 3. All advertising materials mentioning features or use of this software
167d4a1addSreinoud  *    must display the following acknowledgement:
177d4a1addSreinoud  *	This product includes software developed by Scott Stevens.
187d4a1addSreinoud  * 4. The name of the author may not be used to endorse or promote products
197d4a1addSreinoud  *    derived from this software without specific prior written permission.
207d4a1addSreinoud  *
217d4a1addSreinoud  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
227d4a1addSreinoud  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
237d4a1addSreinoud  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
247d4a1addSreinoud  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
257d4a1addSreinoud  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
267d4a1addSreinoud  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
277d4a1addSreinoud  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
287d4a1addSreinoud  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
297d4a1addSreinoud  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
307d4a1addSreinoud  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
317d4a1addSreinoud  *
327d4a1addSreinoud  * RiscBSD kernel project
337d4a1addSreinoud  *
347d4a1addSreinoud  * dma.c
357d4a1addSreinoud  *
367d4a1addSreinoud  * Created      : 15/03/97
377d4a1addSreinoud  */
387d4a1addSreinoud 
3908716eaeSlukem #include <sys/cdefs.h>
40*758ec341Sbjh21 __KERNEL_RCSID(0, "$NetBSD: iomd_dma.c,v 1.10 2006/08/05 18:22:57 bjh21 Exp $");
4108716eaeSlukem 
427d4a1addSreinoud #define DMA_DEBUG
437d4a1addSreinoud #include <sys/param.h>
447d4a1addSreinoud #include <sys/systm.h>
457d4a1addSreinoud #include <sys/kernel.h>
467d4a1addSreinoud 
477d4a1addSreinoud #include <uvm/uvm_extern.h>
487d4a1addSreinoud 
4928466919Sthorpej #include <machine/intr.h>
507d4a1addSreinoud #include <machine/pmap.h>
517d4a1addSreinoud #include <arm/iomd/iomdreg.h>
527d4a1addSreinoud #include <arm/iomd/iomdvar.h>
537d4a1addSreinoud #include <arm/iomd/iomd_dma.h>
547d4a1addSreinoud 
557d4a1addSreinoud 
567d4a1addSreinoud /*
57*758ec341Sbjh21  * Only for non ARM7500 machines but the kernel could be booted on a
58*758ec341Sbjh21  * different machine
597d4a1addSreinoud  */
607d4a1addSreinoud 
617d4a1addSreinoud static struct dma_ctrl ctrl[6];
627d4a1addSreinoud 
63*758ec341Sbjh21 void dma_dumpdc(struct dma_ctrl *);
647d4a1addSreinoud 
657d4a1addSreinoud void
dma_go(struct dma_ctrl * dp)66*758ec341Sbjh21 dma_go(struct dma_ctrl *dp)
677d4a1addSreinoud {
68*758ec341Sbjh21 
697d4a1addSreinoud #ifdef DMA_DEBUG
707d4a1addSreinoud 	printf("dma_go()\n");
717d4a1addSreinoud #endif
727d4a1addSreinoud 	if (dp->dc_flags & DMA_FL_READY) {
737d4a1addSreinoud 		dp->dc_flags = DMA_FL_ACTIVE;
747d4a1addSreinoud 		enable_irq(IRQ_DMACH0 + dp->dc_channel);
75*758ec341Sbjh21 	} else
767d4a1addSreinoud 		panic("dma not ready");
777d4a1addSreinoud }
787d4a1addSreinoud 
797d4a1addSreinoud int
dma_reset(struct dma_ctrl * dp)80*758ec341Sbjh21 dma_reset(struct dma_ctrl *dp)
817d4a1addSreinoud {
82*758ec341Sbjh21 
837d4a1addSreinoud #ifdef DMA_DEBUG
847d4a1addSreinoud 	printf("dma_reset()\n");
857d4a1addSreinoud 	dma_dumpdc(dp);
867d4a1addSreinoud #endif
877d4a1addSreinoud 	*dp->dc_cr = DMA_CR_CLEAR;
887d4a1addSreinoud 	dp->dc_flags = 0;
897d4a1addSreinoud 	disable_irq(IRQ_DMACH0 + dp->dc_channel);
90*758ec341Sbjh21 	return 0;
917d4a1addSreinoud }
927d4a1addSreinoud 
937d4a1addSreinoud /*
947d4a1addSreinoud  * Setup dma transfer, prior to the dma_go call
957d4a1addSreinoud  */
967d4a1addSreinoud int
dma_setup(struct dma_ctrl * dp,u_char * start,int len,int readp)97*758ec341Sbjh21 dma_setup(struct dma_ctrl *dp, u_char *start, int len, int readp)
987d4a1addSreinoud {
99*758ec341Sbjh21 
1007d4a1addSreinoud #ifdef DMA_DEBUG
101*758ec341Sbjh21 	printf("dma_setup(start = %p, len = 0x%08x, readp = %d\n",
102*758ec341Sbjh21 	    start, len, readp);
1037d4a1addSreinoud #endif
1047d4a1addSreinoud 	if (((u_int)start & (dp->dc_dmasize - 1)) ||
1057d4a1addSreinoud 	   (len & (dp->dc_dmasize - 1))) {
1067d4a1addSreinoud 		printf("dma_setup: unaligned DMA, %p (0x%08x)\n",
1077d4a1addSreinoud 			start, len);
1087d4a1addSreinoud 	}
109*758ec341Sbjh21 	*dp->dc_cr = DMA_CR_CLEAR | DMA_CR_ENABLE | (readp?DMA_CR_DIR:0) |
110*758ec341Sbjh21 	    dp->dc_dmasize;
1117d4a1addSreinoud 	*dp->dc_cr = DMA_CR_ENABLE | (readp?DMA_CR_DIR:0) | dp->dc_dmasize;
1127d4a1addSreinoud 
1137d4a1addSreinoud 	dp->dc_nextaddr = start;
1147d4a1addSreinoud 	dp->dc_len = len;
1157d4a1addSreinoud 
1167d4a1addSreinoud 	dp->dc_flags = DMA_FL_READY;
117*758ec341Sbjh21 	return 0;
1187d4a1addSreinoud }
1197d4a1addSreinoud 
1207d4a1addSreinoud /*
1217d4a1addSreinoud  * return true if DMA is active
1227d4a1addSreinoud  */
1237d4a1addSreinoud int
dma_isactive(struct dma_ctrl * dp)124*758ec341Sbjh21 dma_isactive(struct dma_ctrl *dp)
1257d4a1addSreinoud {
126*758ec341Sbjh21 
127*758ec341Sbjh21 	return dp->dc_flags & DMA_FL_ACTIVE;
1287d4a1addSreinoud }
1297d4a1addSreinoud 
1307d4a1addSreinoud /*
1317d4a1addSreinoud  * return true if interrupt pending
1327d4a1addSreinoud  */
1337d4a1addSreinoud int
dma_isintr(struct dma_ctrl * dp)134*758ec341Sbjh21 dma_isintr(struct dma_ctrl *dp)
1357d4a1addSreinoud {
136*758ec341Sbjh21 
1377d4a1addSreinoud #ifdef DMA_DEBUG
1387d4a1addSreinoud /*	printf("dma_isintr() returning %d\n", *dp->dc_st & DMA_ST_INT);*/
1397d4a1addSreinoud #endif
140*758ec341Sbjh21 	return *dp->dc_st & DMA_ST_INT;
1417d4a1addSreinoud }
1427d4a1addSreinoud 
1437d4a1addSreinoud int
dma_intr(void * cookie)144*758ec341Sbjh21 dma_intr(void *cookie)
1457d4a1addSreinoud {
146dbc5effbSbjh21 	struct dma_ctrl *dp = cookie;
1477d4a1addSreinoud 	u_char status = (*dp->dc_st) & DMA_ST_MASK;
14859c9e94bSthorpej 	paddr_t cur;
1497d4a1addSreinoud 	int len;
1507d4a1addSreinoud 	int bufap = 0;
1517d4a1addSreinoud 
1527d4a1addSreinoud #ifdef DMA_DEBUG
1537d4a1addSreinoud 	printf("dma_intr() status = 0x%02x\n", status);
1547d4a1addSreinoud #endif
1557d4a1addSreinoud 
1567d4a1addSreinoud 	if (!(dp->dc_flags & DMA_FL_ACTIVE)) {
1577d4a1addSreinoud 		/* interrupt whilst not active */
1587d4a1addSreinoud 		/* ie. last buffer programmed */
1597d4a1addSreinoud 		dma_reset(dp);
160*758ec341Sbjh21 		return 0;
1617d4a1addSreinoud 	}
1627d4a1addSreinoud 
1637d4a1addSreinoud 	switch (status) {
1647d4a1addSreinoud 	case DMA_ST_OVER | DMA_ST_INT:
1657d4a1addSreinoud 	case DMA_ST_OVER | DMA_ST_INT | DMA_ST_CHAN:
1667d4a1addSreinoud 		/* idle, either first buffer or finished */
1677d4a1addSreinoud 		if (status & DMA_ST_CHAN) {
1687d4a1addSreinoud 			/* fill buffer B */
1697d4a1addSreinoud 			bufap = 0;
1707d4a1addSreinoud 			goto fill;
1717d4a1addSreinoud 		}
1727d4a1addSreinoud 		else {
1737d4a1addSreinoud 			/* fill buffer A */
1747d4a1addSreinoud 			bufap = 1;
1757d4a1addSreinoud 			goto fill;
1767d4a1addSreinoud 		}
1777d4a1addSreinoud 		break;
1787d4a1addSreinoud 	case DMA_ST_INT:
1797d4a1addSreinoud 	case DMA_ST_INT | DMA_ST_CHAN:
1807d4a1addSreinoud 		/* buffer ready */
1817d4a1addSreinoud 		if (status & DMA_ST_CHAN) {
1827d4a1addSreinoud 			/* fill buffer A */
1837d4a1addSreinoud 			bufap = 1;
1847d4a1addSreinoud 			goto fill;
1857d4a1addSreinoud 		}
1867d4a1addSreinoud 		else {
1877d4a1addSreinoud 			/* fill buffer B */
1887d4a1addSreinoud 			bufap = 0;
1897d4a1addSreinoud 			goto fill;
1907d4a1addSreinoud 		}
1917d4a1addSreinoud 		break;
1927d4a1addSreinoud 	default:
1937d4a1addSreinoud 		/* Shouldn't be here */
1947d4a1addSreinoud #ifdef DMA_DEBUG
1957d4a1addSreinoud 		printf("DMA ch %d bad status [%x]\n", dp->dc_channel, status);
1967d4a1addSreinoud 		dma_dumpdc(dp);
1977d4a1addSreinoud #endif
1987d4a1addSreinoud 		break;
1997d4a1addSreinoud 	}
2007d4a1addSreinoud 
2017d4a1addSreinoud /*	return(0);*/
2027d4a1addSreinoud /* XXX */
2037d4a1addSreinoud #define	PHYS(x, y)	pmap_extract(pmap_kernel(), (vaddr_t)x, (paddr_t *)(y))
2047d4a1addSreinoud fill:
2057d4a1addSreinoud #ifdef DMA_DEBUG
2067d4a1addSreinoud 	printf("fill:\n");
2077d4a1addSreinoud #endif
2087d4a1addSreinoud 	if (dp->dc_len == 0) goto done;
2097d4a1addSreinoud 	PHYS(dp->dc_nextaddr, &cur);
21095281cabSthorpej 	len = PAGE_SIZE - (cur & PGOFSET);
2117d4a1addSreinoud 	if (len > dp->dc_len) {
2127d4a1addSreinoud 		/* Last buffer */
2137d4a1addSreinoud 		len = dp->dc_len;
2147d4a1addSreinoud 	}
2157d4a1addSreinoud 
2167d4a1addSreinoud #ifdef DMA_DEBUG
2177d4a1addSreinoud 	dma_dumpdc(dp);
2187d4a1addSreinoud /*	ptsc_dump_mem(dp->dc_nextaddr, len);*/
2197d4a1addSreinoud #endif
2207d4a1addSreinoud /*
2217d4a1addSreinoud  * Flush the cache for this address
2227d4a1addSreinoud  */
22359c9e94bSthorpej 	cpu_dcache_wbinv_range((vaddr_t)dp->dc_nextaddr, len);
2247d4a1addSreinoud 
2257d4a1addSreinoud 	dp->dc_nextaddr += len;
2267d4a1addSreinoud 	dp->dc_len -= len;
2277d4a1addSreinoud 
2287d4a1addSreinoud 	if (bufap) {
2297d4a1addSreinoud 		*dp->dc_cura = (u_int)cur;
2307d4a1addSreinoud 		*dp->dc_enda = ((u_int)cur + len - dp->dc_dmasize) |
2317d4a1addSreinoud 				(dp->dc_len == 0 ? DMA_END_STOP : 0);
2327d4a1addSreinoud 		if (dp->dc_len == 0) {
2337d4a1addSreinoud 			/* Last buffer, fill other buffer with garbage */
2347d4a1addSreinoud 			*dp->dc_endb = (u_int)cur;
2357d4a1addSreinoud 		}
236*758ec341Sbjh21 	} else {
2377d4a1addSreinoud 		*dp->dc_curb = (u_int)cur;
2387d4a1addSreinoud 		*dp->dc_endb = ((u_int)cur + len - dp->dc_dmasize) |
2397d4a1addSreinoud 				(dp->dc_len == 0 ? DMA_END_STOP : 0);
2407d4a1addSreinoud 		if (dp->dc_len == 0) {
2417d4a1addSreinoud 			/* Last buffer, fill other buffer with garbage */
2427d4a1addSreinoud 			*dp->dc_enda = (u_int)cur;
2437d4a1addSreinoud 		}
2447d4a1addSreinoud 	}
2457d4a1addSreinoud #ifdef DMA_DEBUG
2467d4a1addSreinoud 	dma_dumpdc(dp);
2477d4a1addSreinoud /*	ptsc_dump_mem(dp->dc_nextaddr - len, len);*/
2487d4a1addSreinoud 	printf("about to return\n");
2497d4a1addSreinoud #endif
250*758ec341Sbjh21 	return 1;
2517d4a1addSreinoud done:
2527d4a1addSreinoud #ifdef DMA_DEBUG
2537d4a1addSreinoud 	printf("done:\n");
2547d4a1addSreinoud #endif
2557d4a1addSreinoud 	dp->dc_flags = 0;
2567d4a1addSreinoud 	*dp->dc_cr = 0;
2577d4a1addSreinoud 	disable_irq(IRQ_DMACH0 + dp->dc_channel);
2587d4a1addSreinoud #ifdef DMA_DEBUG
2597d4a1addSreinoud 	printf("about to return\n");
2607d4a1addSreinoud #endif
261*758ec341Sbjh21 	return 1;
2627d4a1addSreinoud }
2637d4a1addSreinoud 
2647d4a1addSreinoud void
dma_dumpdc(struct dma_ctrl * dc)265*758ec341Sbjh21 dma_dumpdc(struct dma_ctrl *dc)
2667d4a1addSreinoud {
267*758ec341Sbjh21 
2687d4a1addSreinoud 	printf("\ndc:\t%p\n"
2697d4a1addSreinoud 		"dc_channel:\t%p=0x%08x\tdc_flags:\t%p=0x%08x\n"
2707d4a1addSreinoud 		"dc_cura:\t%p=0x%08x\tdc_enda:\t%p=0x%08x\n"
2717d4a1addSreinoud 		"dc_curb:\t%p=0x%08x\tdc_endb:\t%p=0x%08x\n"
2727d4a1addSreinoud 		"dc_cr:\t%p=0x%02x\t\tdc_st:\t%p=0x%02x\n"
2737d4a1addSreinoud 		"dc_nextaddr:\t%p=0x%08x\tdc_len:\t%p=0x%08x\n",
2747d4a1addSreinoud 		dc,
2757d4a1addSreinoud 		&dc->dc_channel, (int)dc->dc_channel,
2767d4a1addSreinoud 		&dc->dc_flags, (int)dc->dc_flags,
2777d4a1addSreinoud 		dc->dc_cura, (int)*dc->dc_cura,
2787d4a1addSreinoud 		dc->dc_enda, (int)*dc->dc_enda,
2797d4a1addSreinoud 		dc->dc_curb, (int)*dc->dc_curb,
2807d4a1addSreinoud 		dc->dc_endb, (int)*dc->dc_endb,
2817d4a1addSreinoud 		dc->dc_cr, (int)*dc->dc_cr,
2827d4a1addSreinoud 		dc->dc_st, (int)(*dc->dc_st) & DMA_ST_MASK,
2837d4a1addSreinoud 		&dc->dc_nextaddr, (int)dc->dc_nextaddr,
2847d4a1addSreinoud 		&dc->dc_len, dc->dc_len);
2857d4a1addSreinoud }
2867d4a1addSreinoud 
2877d4a1addSreinoud struct dma_ctrl *
dma_init(int ch,int extp,int dmasize,int ipl)288*758ec341Sbjh21 dma_init(int ch, int extp, int dmasize, int ipl)
2897d4a1addSreinoud {
2907d4a1addSreinoud 	struct dma_ctrl *dp = &ctrl[ch];
2917d4a1addSreinoud 	int offset = ch * 0x20;
2927d4a1addSreinoud 	volatile u_char *dmaext = (volatile u_char *)(IOMD_ADDRESS(IOMD_DMAEXT));
2937d4a1addSreinoud 
2947d4a1addSreinoud 	printf("Initialising DMA channel %d\n", ch);
2957d4a1addSreinoud 
2967d4a1addSreinoud 	dp->dc_channel = ch;
2977d4a1addSreinoud 	dp->dc_flags = 0;
2987d4a1addSreinoud 	dp->dc_dmasize = dmasize;
2997d4a1addSreinoud 	dp->dc_cura = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0CURA) + offset);
3007d4a1addSreinoud 	dp->dc_enda = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0ENDA) + offset);
3017d4a1addSreinoud 	dp->dc_curb = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0CURB) + offset);
3027d4a1addSreinoud 	dp->dc_endb = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0ENDB) + offset);
3037d4a1addSreinoud 	dp->dc_cr = (volatile u_char *)(IOMD_ADDRESS(IOMD_IO0CR) + offset);
3047d4a1addSreinoud 	dp->dc_st = (volatile u_char *)(IOMD_ADDRESS(IOMD_IO0ST) + offset);
3057d4a1addSreinoud 
3067d4a1addSreinoud 	if (extp)
3077d4a1addSreinoud 		*dmaext |= (1 << ch);
3087d4a1addSreinoud 
3097d4a1addSreinoud 	printf("about to claim interrupt\n");
3107d4a1addSreinoud 
3117d4a1addSreinoud 	dp->dc_ih.ih_func = dma_intr;
3127d4a1addSreinoud 	dp->dc_ih.ih_arg = dp;
3137d4a1addSreinoud 	dp->dc_ih.ih_level = ipl;
3147d4a1addSreinoud 	dp->dc_ih.ih_name = "dma";
3157d4a1addSreinoud 	dp->dc_ih.ih_maskaddr = (u_int) IOMD_ADDRESS(IOMD_DMARQ);
3167d4a1addSreinoud 	dp->dc_ih.ih_maskbits = (1 << ch);
3177d4a1addSreinoud 
3187d4a1addSreinoud 	if (irq_claim(IRQ_DMACH0 + ch, &dp->dc_ih))
3190f09ed48Sprovos 		panic("Cannot install DMA IRQ handler");
3207d4a1addSreinoud 
321*758ec341Sbjh21 	return dp;
3227d4a1addSreinoud }
3237d4a1addSreinoud 
324