1*758ec341Sbjh21 /* $NetBSD: iomd_irqhandler.c,v 1.11 2006/08/05 18:22:57 bjh21 Exp $ */ 27d4a1addSreinoud 37d4a1addSreinoud /* 47d4a1addSreinoud * Copyright (c) 1994-1998 Mark Brinicombe. 57d4a1addSreinoud * Copyright (c) 1994 Brini. 67d4a1addSreinoud * All rights reserved. 77d4a1addSreinoud * 87d4a1addSreinoud * This code is derived from software written for Brini by Mark Brinicombe 97d4a1addSreinoud * 107d4a1addSreinoud * Redistribution and use in source and binary forms, with or without 117d4a1addSreinoud * modification, are permitted provided that the following conditions 127d4a1addSreinoud * are met: 137d4a1addSreinoud * 1. Redistributions of source code must retain the above copyright 147d4a1addSreinoud * notice, this list of conditions and the following disclaimer. 157d4a1addSreinoud * 2. Redistributions in binary form must reproduce the above copyright 167d4a1addSreinoud * notice, this list of conditions and the following disclaimer in the 177d4a1addSreinoud * documentation and/or other materials provided with the distribution. 187d4a1addSreinoud * 3. All advertising materials mentioning features or use of this software 197d4a1addSreinoud * must display the following acknowledgement: 207d4a1addSreinoud * This product includes software developed by Mark Brinicombe 217d4a1addSreinoud * for the NetBSD Project. 227d4a1addSreinoud * 4. The name of the company nor the name of the author may be used to 237d4a1addSreinoud * endorse or promote products derived from this software without specific 247d4a1addSreinoud * prior written permission. 257d4a1addSreinoud * 267d4a1addSreinoud * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 277d4a1addSreinoud * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 287d4a1addSreinoud * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 297d4a1addSreinoud * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 307d4a1addSreinoud * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 317d4a1addSreinoud * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327d4a1addSreinoud * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337d4a1addSreinoud * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347d4a1addSreinoud * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 357d4a1addSreinoud * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367d4a1addSreinoud * 377d4a1addSreinoud * IRQ/FIQ initialisation, claim, release and handler routines 387d4a1addSreinoud * 397d4a1addSreinoud * from: irqhandler.c,v 1.14 1997/04/02 21:52:19 christos Exp $ 407d4a1addSreinoud */ 417d4a1addSreinoud 4208716eaeSlukem #include <sys/cdefs.h> 43*758ec341Sbjh21 __KERNEL_RCSID(0, "$NetBSD: iomd_irqhandler.c,v 1.11 2006/08/05 18:22:57 bjh21 Exp $"); 4408716eaeSlukem 457d4a1addSreinoud #include "opt_irqstats.h" 467d4a1addSreinoud 477d4a1addSreinoud #include <sys/param.h> 487d4a1addSreinoud #include <sys/systm.h> 497d4a1addSreinoud #include <sys/syslog.h> 507d4a1addSreinoud #include <sys/malloc.h> 517d4a1addSreinoud #include <uvm/uvm_extern.h> 527d4a1addSreinoud 537d4a1addSreinoud #include <arm/iomd/iomdreg.h> 547d4a1addSreinoud #include <arm/iomd/iomdvar.h> 557d4a1addSreinoud 5628466919Sthorpej #include <machine/intr.h> 577d4a1addSreinoud #include <machine/cpu.h> 58b393d0d3Sthorpej #include <arm/arm32/katelib.h> 597d4a1addSreinoud 607d4a1addSreinoud irqhandler_t *irqhandlers[NIRQS]; 617d4a1addSreinoud 627d4a1addSreinoud int current_intr_depth; 637d4a1addSreinoud u_int current_mask; 647d4a1addSreinoud u_int actual_mask; 657d4a1addSreinoud u_int disabled_mask; 667d4a1addSreinoud u_int spl_mask; 677d4a1addSreinoud u_int irqmasks[IPL_LEVELS]; 687d4a1addSreinoud 697d4a1addSreinoud extern u_int soft_interrupts; /* Only so we can initialise it */ 707d4a1addSreinoud 717d4a1addSreinoud extern char *_intrnames; 727d4a1addSreinoud 737d4a1addSreinoud /* Prototypes */ 747d4a1addSreinoud 75*758ec341Sbjh21 extern void set_spl_masks(void); 767d4a1addSreinoud 777d4a1addSreinoud /* 787d4a1addSreinoud * void irq_init(void) 797d4a1addSreinoud * 807d4a1addSreinoud * Initialise the IRQ/FIQ sub system 817d4a1addSreinoud */ 827d4a1addSreinoud 837d4a1addSreinoud void 84*758ec341Sbjh21 irq_init(void) 857d4a1addSreinoud { 867d4a1addSreinoud int loop; 877d4a1addSreinoud 887d4a1addSreinoud /* Clear all the IRQ handlers and the irq block masks */ 89*758ec341Sbjh21 for (loop = 0; loop < NIRQS; ++loop) 907d4a1addSreinoud irqhandlers[loop] = NULL; 917d4a1addSreinoud 927d4a1addSreinoud /* Clear the IRQ/FIQ masks in the IOMD */ 937d4a1addSreinoud IOMD_WRITE_BYTE(IOMD_IRQMSKA, 0x00); 947d4a1addSreinoud IOMD_WRITE_BYTE(IOMD_IRQMSKB, 0x00); 957d4a1addSreinoud 967d4a1addSreinoud switch (IOMD_ID) { 977d4a1addSreinoud case RPC600_IOMD_ID: 987d4a1addSreinoud break; 997d4a1addSreinoud case ARM7500_IOC_ID: 1007d4a1addSreinoud case ARM7500FE_IOC_ID: 1017d4a1addSreinoud IOMD_WRITE_BYTE(IOMD_IRQMSKC, 0x00); 1027d4a1addSreinoud IOMD_WRITE_BYTE(IOMD_IRQMSKD, 0x00); 1037d4a1addSreinoud break; 1047d4a1addSreinoud default: 1057d4a1addSreinoud printf("Unknown IOMD id (%d) found in irq_init()\n", IOMD_ID); 106*758ec341Sbjh21 } 1077d4a1addSreinoud 1087d4a1addSreinoud IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00); 1097d4a1addSreinoud IOMD_WRITE_BYTE(IOMD_DMAMSK, 0x00); 1107d4a1addSreinoud 1117d4a1addSreinoud /* 1127d4a1addSreinoud * Setup the irqmasks for the different Interrupt Priority Levels 1137d4a1addSreinoud * We will start with no bits set and these will be updated as handlers 1147d4a1addSreinoud * are installed at different IPL's. 1157d4a1addSreinoud */ 1167d4a1addSreinoud for (loop = 0; loop < IPL_LEVELS; ++loop) 1177d4a1addSreinoud irqmasks[loop] = 0; 1187d4a1addSreinoud 1197d4a1addSreinoud current_intr_depth = 0; 1207d4a1addSreinoud current_mask = 0x00000000; 1217d4a1addSreinoud disabled_mask = 0x00000000; 1227d4a1addSreinoud actual_mask = 0x00000000; 1237d4a1addSreinoud spl_mask = 0x00000000; 1247d4a1addSreinoud soft_interrupts = 0x00000000; 1257d4a1addSreinoud 1267d4a1addSreinoud set_spl_masks(); 1277d4a1addSreinoud 1287d4a1addSreinoud /* Enable IRQ's and FIQ's */ 1297d4a1addSreinoud enable_interrupts(I32_bit | F32_bit); 1307d4a1addSreinoud } 1317d4a1addSreinoud 1327d4a1addSreinoud 1337d4a1addSreinoud /* 1347d4a1addSreinoud * int irq_claim(int irq, irqhandler_t *handler) 1357d4a1addSreinoud * 1367d4a1addSreinoud * Enable an IRQ and install a handler for it. 1377d4a1addSreinoud */ 1387d4a1addSreinoud 1397d4a1addSreinoud int 140*758ec341Sbjh21 irq_claim(int irq, irqhandler_t *handler) 1417d4a1addSreinoud { 1427d4a1addSreinoud int level; 143078c5853Schris u_int oldirqstate; 1447d4a1addSreinoud 1457d4a1addSreinoud #ifdef DIAGNOSTIC 1467d4a1addSreinoud /* Sanity check */ 1477d4a1addSreinoud if (handler == NULL) 1480f09ed48Sprovos panic("NULL interrupt handler"); 1497d4a1addSreinoud if (handler->ih_func == NULL) 1500f09ed48Sprovos panic("Interrupt handler does not have a function"); 1517d4a1addSreinoud #endif /* DIAGNOSTIC */ 1527d4a1addSreinoud 1537d4a1addSreinoud /* 1547d4a1addSreinoud * IRQ_INSTRUCT indicates that we should get the irq number 1557d4a1addSreinoud * from the irq structure 1567d4a1addSreinoud */ 1577d4a1addSreinoud if (irq == IRQ_INSTRUCT) 1587d4a1addSreinoud irq = handler->ih_num; 1597d4a1addSreinoud 1607d4a1addSreinoud /* Make sure the irq number is valid */ 1617d4a1addSreinoud if (irq < 0 || irq >= NIRQS) 162*758ec341Sbjh21 return -1; 1637d4a1addSreinoud 1647d4a1addSreinoud /* Make sure the level is valid */ 1657d4a1addSreinoud if (handler->ih_level < 0 || handler->ih_level >= IPL_LEVELS) 166*758ec341Sbjh21 return -1; 1677d4a1addSreinoud 168078c5853Schris oldirqstate = disable_interrupts(I32_bit); 169078c5853Schris 1707d4a1addSreinoud /* Attach handler at top of chain */ 1717d4a1addSreinoud handler->ih_next = irqhandlers[irq]; 1727d4a1addSreinoud irqhandlers[irq] = handler; 1737d4a1addSreinoud 1747d4a1addSreinoud /* 1757d4a1addSreinoud * Reset the flags for this handler. 1767d4a1addSreinoud * As the handler is now in the chain mark it as active. 1777d4a1addSreinoud */ 1787d4a1addSreinoud handler->ih_flags = 0 | IRQ_FLAG_ACTIVE; 1797d4a1addSreinoud 1807d4a1addSreinoud /* 1817d4a1addSreinoud * Record the interrupt number for accounting. 1827d4a1addSreinoud * Done here as the accounting number may not be the same as the 1837d4a1addSreinoud * IRQ number though for the moment they are 1847d4a1addSreinoud */ 1857d4a1addSreinoud handler->ih_num = irq; 1867d4a1addSreinoud 1877d4a1addSreinoud #ifdef IRQSTATS 1887d4a1addSreinoud /* Get the interrupt name from the head of the list */ 1897d4a1addSreinoud if (handler->ih_name) { 1907d4a1addSreinoud char *ptr = _intrnames + (irq * 14); 1917d4a1addSreinoud strcpy(ptr, " "); 1927d4a1addSreinoud strncpy(ptr, handler->ih_name, 1937d4a1addSreinoud min(strlen(handler->ih_name), 13)); 1947d4a1addSreinoud } else { 1957d4a1addSreinoud char *ptr = _intrnames + (irq * 14); 1967d4a1addSreinoud sprintf(ptr, "irq %2d ", irq); 1977d4a1addSreinoud } 1987d4a1addSreinoud #endif /* IRQSTATS */ 1997d4a1addSreinoud 2007d4a1addSreinoud /* 2017d4a1addSreinoud * Update the irq masks. 2027d4a1addSreinoud * Find the lowest interrupt priority on the irq chain. 2037d4a1addSreinoud * Interrupt is allowable at priorities lower than this. 2047d4a1addSreinoud * If ih_level is out of range then don't bother to update 2057d4a1addSreinoud * the masks. 2067d4a1addSreinoud */ 2077d4a1addSreinoud if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 2087d4a1addSreinoud irqhandler_t *ptr; 2097d4a1addSreinoud 2107d4a1addSreinoud /* 2117d4a1addSreinoud * Find the lowest interrupt priority on the irq chain. 2127d4a1addSreinoud * Interrupt is allowable at priorities lower than this. 2137d4a1addSreinoud */ 2147d4a1addSreinoud ptr = irqhandlers[irq]; 2157d4a1addSreinoud if (ptr) { 2167d4a1addSreinoud int max_level; 2177d4a1addSreinoud 2187d4a1addSreinoud level = ptr->ih_level - 1; 2197d4a1addSreinoud max_level = ptr->ih_level - 1; 2207d4a1addSreinoud while (ptr) { 2217d4a1addSreinoud if (ptr->ih_level - 1 < level) 2227d4a1addSreinoud level = ptr->ih_level - 1; 2237d4a1addSreinoud else if (ptr->ih_level - 1 > max_level) 2247d4a1addSreinoud max_level = ptr->ih_level - 1; 2257d4a1addSreinoud ptr = ptr->ih_next; 2267d4a1addSreinoud } 2277d4a1addSreinoud /* Clear out any levels that we cannot now allow */ 2287d4a1addSreinoud while (max_level >=0 && max_level > level) { 2297d4a1addSreinoud irqmasks[max_level] &= ~(1 << irq); 2307d4a1addSreinoud --max_level; 2317d4a1addSreinoud } 2327d4a1addSreinoud while (level >= 0) { 2337d4a1addSreinoud irqmasks[level] |= (1 << irq); 2347d4a1addSreinoud --level; 2357d4a1addSreinoud } 2367d4a1addSreinoud } 2377d4a1addSreinoud 2387d4a1addSreinoud #include "sl.h" 2397d4a1addSreinoud #include "ppp.h" 2407d4a1addSreinoud #if NSL > 0 || NPPP > 0 2417d4a1addSreinoud /* In the presence of SLIP or PPP, splimp > spltty. */ 2427d4a1addSreinoud irqmasks[IPL_NET] &= irqmasks[IPL_TTY]; 2437d4a1addSreinoud #endif 2447d4a1addSreinoud } 2457d4a1addSreinoud 2467d4a1addSreinoud enable_irq(irq); 2477d4a1addSreinoud set_spl_masks(); 248078c5853Schris restore_interrupts(oldirqstate); 2497d4a1addSreinoud 250*758ec341Sbjh21 return 0; 2517d4a1addSreinoud } 2527d4a1addSreinoud 2537d4a1addSreinoud 2547d4a1addSreinoud /* 2557d4a1addSreinoud * int irq_release(int irq, irqhandler_t *handler) 2567d4a1addSreinoud * 2577d4a1addSreinoud * Disable an IRQ and remove a handler for it. 2587d4a1addSreinoud */ 2597d4a1addSreinoud 2607d4a1addSreinoud int 261*758ec341Sbjh21 irq_release(int irq, irqhandler_t *handler) 2627d4a1addSreinoud { 2637d4a1addSreinoud int level; 2647d4a1addSreinoud irqhandler_t *irqhand; 2657d4a1addSreinoud irqhandler_t **prehand; 2667d4a1addSreinoud #ifdef IRQSTATS 2677d4a1addSreinoud extern char *_intrnames; 2687d4a1addSreinoud #endif 2697d4a1addSreinoud 2707d4a1addSreinoud /* 2717d4a1addSreinoud * IRQ_INSTRUCT indicates that we should get the irq number 2727d4a1addSreinoud * from the irq structure 2737d4a1addSreinoud */ 2747d4a1addSreinoud if (irq == IRQ_INSTRUCT) 2757d4a1addSreinoud irq = handler->ih_num; 2767d4a1addSreinoud 2777d4a1addSreinoud /* Make sure the irq number is valid */ 2787d4a1addSreinoud if (irq < 0 || irq >= NIRQS) 2797d4a1addSreinoud return(-1); 2807d4a1addSreinoud 2817d4a1addSreinoud /* Locate the handler */ 2827d4a1addSreinoud irqhand = irqhandlers[irq]; 2837d4a1addSreinoud prehand = &irqhandlers[irq]; 2847d4a1addSreinoud 2857d4a1addSreinoud while (irqhand && handler != irqhand) { 2867d4a1addSreinoud prehand = &irqhand->ih_next; 2877d4a1addSreinoud irqhand = irqhand->ih_next; 2887d4a1addSreinoud } 2897d4a1addSreinoud 2907d4a1addSreinoud /* Remove the handler if located */ 2917d4a1addSreinoud if (irqhand) 2927d4a1addSreinoud *prehand = irqhand->ih_next; 2937d4a1addSreinoud else 294*758ec341Sbjh21 return -1; 2957d4a1addSreinoud 2967d4a1addSreinoud /* Now the handler has been removed from the chain mark is as inactive */ 2977d4a1addSreinoud irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE; 2987d4a1addSreinoud 2997d4a1addSreinoud /* Make sure the head of the handler list is active */ 3007d4a1addSreinoud if (irqhandlers[irq]) 3017d4a1addSreinoud irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE; 3027d4a1addSreinoud 3037d4a1addSreinoud #ifdef IRQSTATS 3047d4a1addSreinoud /* Get the interrupt name from the head of the list */ 3057d4a1addSreinoud if (irqhandlers[irq] && irqhandlers[irq]->ih_name) { 3067d4a1addSreinoud char *ptr = _intrnames + (irq * 14); 3077d4a1addSreinoud strcpy(ptr, " "); 3087d4a1addSreinoud strncpy(ptr, irqhandlers[irq]->ih_name, 3097d4a1addSreinoud min(strlen(irqhandlers[irq]->ih_name), 13)); 3107d4a1addSreinoud } else { 3117d4a1addSreinoud char *ptr = _intrnames + (irq * 14); 3127d4a1addSreinoud sprintf(ptr, "irq %2d ", irq); 3137d4a1addSreinoud } 3147d4a1addSreinoud #endif /* IRQSTATS */ 3157d4a1addSreinoud 3167d4a1addSreinoud /* 3177d4a1addSreinoud * Update the irq masks. 3187d4a1addSreinoud * If ih_level is out of range then don't bother to update 3197d4a1addSreinoud * the masks. 3207d4a1addSreinoud */ 3217d4a1addSreinoud if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 3227d4a1addSreinoud irqhandler_t *ptr; 3237d4a1addSreinoud 3247d4a1addSreinoud /* Clean the bit from all the masks */ 3257d4a1addSreinoud for (level = 0; level < IPL_LEVELS; ++level) 3267d4a1addSreinoud irqmasks[level] &= ~(1 << irq); 3277d4a1addSreinoud 3287d4a1addSreinoud /* 3297d4a1addSreinoud * Find the lowest interrupt priority on the irq chain. 3307d4a1addSreinoud * Interrupt is allowable at priorities lower than this. 3317d4a1addSreinoud */ 3327d4a1addSreinoud ptr = irqhandlers[irq]; 3337d4a1addSreinoud if (ptr) { 3347d4a1addSreinoud level = ptr->ih_level - 1; 3357d4a1addSreinoud while (ptr) { 3367d4a1addSreinoud if (ptr->ih_level - 1 < level) 3377d4a1addSreinoud level = ptr->ih_level - 1; 3387d4a1addSreinoud ptr = ptr->ih_next; 3397d4a1addSreinoud } 3407d4a1addSreinoud while (level >= 0) { 3417d4a1addSreinoud irqmasks[level] |= (1 << irq); 3427d4a1addSreinoud --level; 3437d4a1addSreinoud } 3447d4a1addSreinoud } 3457d4a1addSreinoud } 3467d4a1addSreinoud 3477d4a1addSreinoud /* 3487d4a1addSreinoud * Disable the appropriate mask bit if there are no handlers left for 3497d4a1addSreinoud * this IRQ. 3507d4a1addSreinoud */ 3517d4a1addSreinoud if (irqhandlers[irq] == NULL) 3527d4a1addSreinoud disable_irq(irq); 3537d4a1addSreinoud 3547d4a1addSreinoud set_spl_masks(); 3557d4a1addSreinoud 356*758ec341Sbjh21 return 0; 3577d4a1addSreinoud } 3587d4a1addSreinoud 3597d4a1addSreinoud 3607d4a1addSreinoud void * 361*758ec341Sbjh21 intr_claim(int irq, int level, const char *name, int (*ih_func)(void *), 362*758ec341Sbjh21 void *ih_arg) 3637d4a1addSreinoud { 3647d4a1addSreinoud irqhandler_t *ih; 3657d4a1addSreinoud 3667d4a1addSreinoud ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 3677d4a1addSreinoud if (!ih) 3680f09ed48Sprovos panic("intr_claim(): Cannot malloc handler memory"); 3697d4a1addSreinoud 3707d4a1addSreinoud ih->ih_level = level; 3717d4a1addSreinoud ih->ih_name = name; 3727d4a1addSreinoud ih->ih_func = ih_func; 3737d4a1addSreinoud ih->ih_arg = ih_arg; 3747d4a1addSreinoud ih->ih_flags = 0; 3757d4a1addSreinoud 3767d4a1addSreinoud if (irq_claim(irq, ih) != 0) 377*758ec341Sbjh21 return NULL; 378*758ec341Sbjh21 return ih; 3797d4a1addSreinoud } 3807d4a1addSreinoud 3817d4a1addSreinoud 3827d4a1addSreinoud int 383*758ec341Sbjh21 intr_release(void *arg) 3847d4a1addSreinoud { 3857d4a1addSreinoud irqhandler_t *ih = (irqhandler_t *)arg; 3867d4a1addSreinoud 3877d4a1addSreinoud if (irq_release(ih->ih_num, ih) == 0) { 3887d4a1addSreinoud free(ih, M_DEVBUF); 389*758ec341Sbjh21 return 0 ; 3907d4a1addSreinoud } 391*758ec341Sbjh21 return 1; 3927d4a1addSreinoud } 3937d4a1addSreinoud 3947d4a1addSreinoud #if 0 3957d4a1addSreinoud u_int 396*758ec341Sbjh21 disable_interrupts(u_int mask) 3977d4a1addSreinoud { 3987d4a1addSreinoud u_int cpsr; 3997d4a1addSreinoud 4007d4a1addSreinoud cpsr = SetCPSR(mask, mask); 401*758ec341Sbjh21 return cpsr; 4027d4a1addSreinoud } 4037d4a1addSreinoud 4047d4a1addSreinoud 4057d4a1addSreinoud u_int 406*758ec341Sbjh21 restore_interrupts(u_int old_cpsr) 4077d4a1addSreinoud { 4087d4a1addSreinoud int mask = I32_bit | F32_bit; 409*758ec341Sbjh21 410*758ec341Sbjh21 return SetCPSR(mask, old_cpsr & mask); 4117d4a1addSreinoud } 4127d4a1addSreinoud 4137d4a1addSreinoud 4147d4a1addSreinoud u_int 415*758ec341Sbjh21 enable_interrupts(u_int mask) 4167d4a1addSreinoud { 417*758ec341Sbjh21 418*758ec341Sbjh21 return SetCPSR(mask, 0); 4197d4a1addSreinoud } 4207d4a1addSreinoud #endif 4217d4a1addSreinoud 4227d4a1addSreinoud /* 4237d4a1addSreinoud * void disable_irq(int irq) 4247d4a1addSreinoud * 4257d4a1addSreinoud * Disables a specific irq. The irq is removed from the master irq mask 4267d4a1addSreinoud */ 4277d4a1addSreinoud 4287d4a1addSreinoud void 429*758ec341Sbjh21 disable_irq(int irq) 4307d4a1addSreinoud { 4317d4a1addSreinoud u_int oldirqstate; 4327d4a1addSreinoud 4337d4a1addSreinoud oldirqstate = disable_interrupts(I32_bit); 4347d4a1addSreinoud current_mask &= ~(1 << irq); 4357d4a1addSreinoud irq_setmasks(); 4367d4a1addSreinoud restore_interrupts(oldirqstate); 4377d4a1addSreinoud } 4387d4a1addSreinoud 4397d4a1addSreinoud 4407d4a1addSreinoud /* 4417d4a1addSreinoud * void enable_irq(int irq) 4427d4a1addSreinoud * 4437d4a1addSreinoud * Enables a specific irq. The irq is added to the master irq mask 4447d4a1addSreinoud * This routine should be used with caution. A handler should already 4457d4a1addSreinoud * be installed. 4467d4a1addSreinoud */ 4477d4a1addSreinoud 4487d4a1addSreinoud void 449*758ec341Sbjh21 enable_irq(int irq) 4507d4a1addSreinoud { 4517d4a1addSreinoud u_int oldirqstate; 4527d4a1addSreinoud 4537d4a1addSreinoud oldirqstate = disable_interrupts(I32_bit); 4547d4a1addSreinoud current_mask |= (1 << irq); 4557d4a1addSreinoud irq_setmasks(); 4567d4a1addSreinoud restore_interrupts(oldirqstate); 4577d4a1addSreinoud } 4587d4a1addSreinoud 4597d4a1addSreinoud 4607d4a1addSreinoud /* 4617d4a1addSreinoud * void stray_irqhandler(u_int mask) 4627d4a1addSreinoud * 4637d4a1addSreinoud * Handler for stray interrupts. This gets called if a handler cannot be 4647d4a1addSreinoud * found for an interrupt. 4657d4a1addSreinoud */ 4667d4a1addSreinoud 4677d4a1addSreinoud void 468*758ec341Sbjh21 stray_irqhandler(u_int mask) 4697d4a1addSreinoud { 4707d4a1addSreinoud static u_int stray_irqs = 0; 4717d4a1addSreinoud 4727d4a1addSreinoud if (++stray_irqs <= 8) 4737d4a1addSreinoud log(LOG_ERR, "Stray interrupt %08x%s\n", mask, 4747d4a1addSreinoud stray_irqs >= 8 ? ": stopped logging" : ""); 4757d4a1addSreinoud } 476