1 /******************************************************************************* 2 Copyright (C) Marvell International Ltd. and its affiliates 3 4 Developed by Semihalf 5 6 ******************************************************************************** 7 Marvell BSD License 8 9 If you received this File from Marvell, you may opt to use, redistribute and/or 10 modify this File under the following licensing terms. 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 * Redistributions of source code must retain the above copyright notice, 15 this list of conditions and the following disclaimer. 16 17 * Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 21 * Neither the name of Marvell nor the names of its contributors may be 22 used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 26 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 29 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 32 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 36 *******************************************************************************/ 37 38 #ifndef _ARMADAXPREG_H_ 39 #define _ARMADAXPREG_H_ 40 41 #include <arm/marvell/mvsocreg.h> 42 #include <evbarm/marvell/marvellvar.h> 43 44 #define ARMADAXP_UNITID_DDR MVSOC_UNITID_DDR 45 #define ARMADAXP_UNITID_DEVBUS MVSOC_UNITID_DEVBUS 46 #define ARMADAXP_UNITID_MBUS MVSOC_UNITID_MBUS 47 #define ARMADAXP_UNITID_MLMB MVSOC_UNITID_MLMB 48 #define ARMADAXP_UNITID_PEX MVSOC_UNITID_PEX 49 #define ARMADAXP_UNITID_USB 0x5 /* USB registers */ 50 #define ARMADAXP_UNITID_XORE0 0x6 /* Reserved? */ 51 #define ARMADAXP_UNITID_GBE0 0x7 52 #define ARMADAXP_UNITID_GBE2 0x3 53 #define ARMADAXP_UNITID_PEX0 MVSOC_UNITID_PEX 54 #define ARMADAXP_UNITID_PEX1 0x8 55 #define ARMADAXP_UNITID_PEX2 MVSOC_UNITID_PEX 56 #define ARMADAXP_UNITID_PEX3 0x8 57 #define ARMADAXP_UNITID_CRYPT 0x9 58 #define ARMADAXP_UNITID_SATA 0xa 59 #define ARMADAXP_UNITID_BM 0xc 60 #define ARMADAXP_UNITID_PNC 0xc 61 #define ARMADAXP_UNITID_SDIO 0xd /* SDIO registers */ 62 #define ARMADAXP_UNITID_LCD 0xe /* Reserved? */ 63 #define ARMADAXP_UNITID_XORE1 0xf /* Reserved? */ 64 65 #define ARMADAXP_ATTR_PEXx0_MEM 0xe8 66 #define ARMADAXP_ATTR_PEXx0_IO 0xe0 67 #define ARMADAXP_ATTR_PEXx1_MEM 0xd8 68 #define ARMADAXP_ATTR_PEXx1_IO 0xd0 69 #define ARMADAXP_ATTR_PEXx2_MEM 0xb8 70 #define ARMADAXP_ATTR_PEXx2_IO 0xb0 71 #define ARMADAXP_ATTR_PEXx3_MEM 0x78 72 #define ARMADAXP_ATTR_PEXx3_IO 0x70 73 #define ARMADAXP_ATTR_PEX2_MEM 0xf8 74 #define ARMADAXP_ATTR_PEX2_IO 0xf0 75 #define ARMADAXP_ATTR_PEX3_MEM 0xf8 76 #define ARMADAXP_ATTR_PEX3_IO 0xf0 77 78 79 #define ARMADAXP_IRQ_GBE0_TH_RXTX 8 /* GBE0_TH_RXTX_Int */ 80 #define ARMADAXP_IRQ_GBE1_TH_RXTX 10 /* GBE1_TH_RXTX_Int */ 81 #define ARMADAXP_IRQ_GBE2_TH_RXTX 12 /* GBE2_TH_RXTX_Int */ 82 #define ARMADAXP_IRQ_GBE3_TH_RXTX 14 /* GBE3_TH_RXTX_Int */ 83 84 #define ARMADAXP_IRQ_LCD 29 85 #define ARMADAXP_IRQ_SPI 30 86 #define ARMADAXP_IRQ_TWSI0 31 87 #define ARMADAXP_IRQ_TWSI1 32 88 #define ARMADAXP_IRQ_IDMA0 33 /* IDMA Channel 0 */ 89 #define ARMADAXP_IRQ_IDMA1 34 /* IDMA Channel 1 */ 90 #define ARMADAXP_IRQ_IDMA2 35 /* IDMA Channel 2 */ 91 #define ARMADAXP_IRQ_IDMA3 36 /* IDMA Channel 3 */ 92 #define ARMADAXP_IRQ_TIMER0 37 93 #define ARMADAXP_IRQ_TIMER1 38 94 #define ARMADAXP_IRQ_TIMER2 39 95 #define ARMADAXP_IRQ_TIMER3 40 96 #define ARMADAXP_IRQ_UART0 41 97 #define ARMADAXP_IRQ_UART1 42 98 #define ARMADAXP_IRQ_UART2 43 99 #define ARMADAXP_IRQ_UART3 44 100 #if 0 101 #define ARMADAXP_IRQ_USB0 45 102 #define ARMADAXP_IRQ_USB1 46 103 #define ARMADAXP_IRQ_USB2 47 104 #else 105 /* 106 * According to functional specification (MV-S107021-00B.pdf), interrupt number 107 * for USB0_int is 47, in fact this number is 45. Because of that interrupt 108 * number definitions are not equivalent to ArmadaXP functional specification 109 * (MV-S107021-00B.pdf). 110 */ 111 #define ARMADAXP_IRQ_USB0 45 /* USB2 */ 112 #define ARMADAXP_IRQ_USB1 46 /* USB1 */ 113 #define ARMADAXP_IRQ_USB2 47 /* USB0 */ 114 #endif 115 #define ARMADAXP_IRQ_CESA0 48 116 #define ARMADAXP_IRQ_CESA1 49 117 #define ARMADAXP_IRQ_RTC 50 118 #define ARMADAXP_IRQ_XOR0CH0 51 /* XOR0 Ch0 */ 119 #define ARMADAXP_IRQ_XOR0CH1 52 /* XOR0 Ch1 */ 120 #define ARMADAXP_IRQ_BM 53 /* Buffer Management */ 121 #define ARMADAXP_IRQ_SDIO 54 122 #define ARMADAXP_IRQ_SATA0 55 123 #define ARMADAXP_IRQ_TDM 56 124 #define ARMADAXP_IRQ_SATA1 57 125 #define ARMADAXP_IRQ_PEX00 58 /* PCIe Port0.0 INTA/B/C/D */ 126 #define ARMADAXP_IRQ_PEX01 59 /* PCIe Port0.1 INTA/B/C/D */ 127 #define ARMADAXP_IRQ_PEX02 60 /* PCIe Port0.2 INTA/B/C/D */ 128 #define ARMADAXP_IRQ_PEX03 61 /* PCIe Port0.3 INTA/B/C/D */ 129 #define ARMADAXP_IRQ_PEX10 62 /* PCIe Port1.0 INTA/B/C/D */ 130 #define ARMADAXP_IRQ_PEX11 63 /* PCIe Port1.1 INTA/B/C/D */ 131 #define ARMADAXP_IRQ_PEX12 64 /* PCIe Port1.2 INTA/B/C/D */ 132 #define ARMADAXP_IRQ_PEX13 65 /* PCIe Port1.3 INTA/B/C/D */ 133 #define ARMADAXP_IRQ_XOR1CH2 94 /* XOR1 Ch2 */ 134 #define ARMADAXP_IRQ_XOR1CH3 95 /* XOR1 Ch3 */ 135 #define ARMADAXP_IRQ_PEX2 99 /* PCIe Port2 INTA/B/C/D */ 136 #define ARMADAXP_IRQ_PEX3 103 /* PCIe Port3 INTA/B/C/D */ 137 138 139 #define ARMADAXP_MLMB_NWINDOW 19 140 #define ARMADAXP_MLMB_NREMAP 8 141 142 /* 143 * Physical address of integrated peripherals 144 */ 145 146 #undef UNITID2PHYS 147 #define UNITID2PHYS(uid) ((ARMADAXP_UNITID_ ## uid) << 16) 148 149 /* 150 * Real-Time Clock Unit Registers 151 */ 152 #define ARMADAXP_RTC_BASE (MVSOC_DEVBUS_BASE + 0x0300) 153 154 /* 155 * SPI Interface Registers 156 */ 157 #define ARMADAXP_SPI_BASE (MVSOC_DEVBUS_BASE + 0x0600) 158 159 /* 160 * TWSI Interface Registers 161 */ 162 #define ARMADAXP_TWSI1_BASE (MVSOC_DEVBUS_BASE + 0x1100) 163 164 /* 165 * UART Interface Registers 166 */ /* NS16550 compatible */ 167 #define ARMADAXP_COM2_BASE (MVSOC_DEVBUS_BASE + 0x2200) 168 #define ARMADAXP_COM3_BASE (MVSOC_DEVBUS_BASE + 0x2300) 169 170 /* 171 * General Purpose Input/Output Port Registers 172 */ 173 #define ARMADAXP_GPIO0_BASE (MVSOC_DEVBUS_BASE + 0x8100) 174 #define ARMADAXP_GPIO1_BASE (MVSOC_DEVBUS_BASE + 0x8120) 175 #define ARMADAXP_GPIO2_BASE (MVSOC_DEVBUS_BASE + 0x8140) 176 177 /* 178 * Power Management Unit Registers 179 */ /* NS16550 compatible */ 180 #define ARMADAXP_PMU_BASE (MVSOC_DEVBUS_BASE + 0xc000) 181 182 /* 183 * Miscellanseous Register 184 */ 185 #define ARMADAXP_MISC_BASE (MVSOC_DEVBUS_BASE + 0x8200) 186 187 #define ARMADAXP_MISC_PMCGC 0x20 /* PM Clock Gating Control */ 188 #define ARMADAXP_MISC_SAR_LO 0x30 /* Sample At Reset Low */ 189 #define ARMADAXP_MISC_SAR_HI 0x34 /* Sample At Reset High */ 190 #define ARMADAXP_MISC_RSTOUTNMASKR 0x60 /* RSTOUTn Mask Register */ 191 #define ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN (1 << 0) 192 #define ARMADAXP_MISC_SSRR 0x64 /* System Soft Reset Register */ 193 #define ARMADAXP_MISC_SSRR_GLOBALSOFTRST (1 << 0) 194 195 /* Multiprocessor Interrupt Controller Registers */ 196 #define ARMADAXP_MLMB_MPIC_BASE 0x20a00 197 #define ARMADAXP_MLMB_MPIC_CPU_BASE 0x21800 198 #define ARMADAXP_MLMB_MPIC_CTRL 0x0 199 #define ARMADAXP_MLMB_MPIC_SOFT_INT 0x4 200 #define ARMADAXP_MLMB_MPIC_ERR_CAUSE 0x20 201 #define ARMADAXP_MLMB_MPIC_ISE 0x30 202 #define ARMADAXP_MLMB_MPIC_ICE 0x34 203 #define ARMADAXP_MLMB_MPIC_ISCR_BASE 0x100 204 205 #define ARMADAXP_MLMB_MPIC_DOORBELL 0x78 206 #define ARMADAXP_MLMB_MPIC_DOORBELL_MASK 0x7c 207 #define ARMADAXP_MLMB_MPIC_CTP 0xb0 208 #define ARMADAXP_MLMB_MPIC_IIACK 0xb4 209 #define ARMADAXP_MLMB_MPIC_ISM 0xb8 210 #define ARMADAXP_MLMB_MPIC_ICM 0xbc 211 #define ARMADAXP_MLMB_MPIC_ERR_MASK 0xec0 212 213 /* Multiprocessor Interrupt Controller Shifts */ 214 #define MPIC_CTP_SHIFT 28 /* Global priority level field */ 215 #define MPIC_ISCR_SHIFT 24 /* IRQ source priority level field */ 216 217 /* Cache Main Control */ 218 #define ARMADAXP_L2_BASE 0x8000 219 #define ARMADAXP_L2_CTRL 0x100 220 #define ARMADAXP_L2_AUX_CTRL 0x104 221 #define ARMADAXP_L2_CNTR_CTRL 0x200 222 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) 223 #define ARMADAXP_L2_INT_CAUSE 0x220 224 #define ARMADAXP_L2_CFU 0x228 225 #define ARMADAXP_L2_INV_WAY 0x778 226 #define L2_ENABLE (1 << 0) 227 #define L2_WBWT_MODE_MASK (3 << 0) 228 #define L2_REP_STRAT_MASK (3 << 27) 229 #define L2_REP_STRAT_SEMIPLRU (3 << 27) 230 #define L2_ALL_WAYS 0xffffffff 231 232 /* 233 * PCI-Express Interface Registers 234 */ 235 #define ARMADAXP_PEX01_BASE (MVSOC_PEX_BASE + 0x4000) 236 #define ARMADAXP_PEX02_BASE (MVSOC_PEX_BASE + 0x8000) 237 #define ARMADAXP_PEX03_BASE (MVSOC_PEX_BASE + 0xc000) 238 #define ARMADAXP_PEX10_BASE (UNITID2PHYS(PEX1)) 239 #define ARMADAXP_PEX11_BASE (ARMADAXP_PEX10_BASE + 0x4000) 240 #define ARMADAXP_PEX12_BASE (ARMADAXP_PEX10_BASE + 0x8000) 241 #define ARMADAXP_PEX13_BASE (ARMADAXP_PEX10_BASE + 0xc000) 242 #define ARMADAXP_PEX2_BASE (UNITID2PHYS(PEX2) + 0x2000) 243 #define ARMADAXP_PEX3_BASE (UNITID2PHYS(PEX3) + 0x2000) 244 245 /* 246 * USB 2.0 Interface Registers 247 */ 248 #define ARMADAXP_USB_BASE (UNITID2PHYS(USB)) /* 0x50000 */ 249 #define ARMADAXP_USB0_BASE (ARMADAXP_USB_BASE + 0x0000) 250 #define ARMADAXP_USB1_BASE (ARMADAXP_USB_BASE + 0x1000) 251 #define ARMADAXP_USB2_BASE (ARMADAXP_USB_BASE + 0x2000) 252 253 /* 254 * XOR Engine Registers 255 */ 256 #define ARMADAXP_XORE0_BASE (UNITID2PHYS(XORE0)) /* 0x60000 */ 257 #define ARMADAXP_XORE1_BASE (UNITID2PHYS(XORE1)) /* 0xf0000 */ 258 259 /* 260 * Gigabit Ethernet Registers 261 */ 262 #define ARMADAXP_GBE0_BASE (UNITID2PHYS(GBE0)) /* 0x70000 */ 263 #define ARMADAXP_GBE1_BASE (ARMADAXP_GBE0_BASE + 0x4000) 264 #define ARMADAXP_GBE2_BASE (UNITID2PHYS(GBE2)) /* 0x30000 */ 265 #define ARMADAXP_GBE3_BASE (ARMADAXP_GBE2_BASE + 0x4000) 266 267 /* 268 * Precise Time Protocol (PTP) Registers 269 */ 270 #define ARMADAXP_PTP_BASE (UNITID2PHYS(GBE0)) /* 0x7c000 */ 271 272 /* 273 * Cryptographic Engine and Security Accelerator Registers 274 */ 275 #define ARMADAXP_CESA0_BASE (UNITID2PHYS(CRYPT) + 0xd000) /* 0x9d000 */ 276 #define ARMADAXP_CESA1_BASE (UNITID2PHYS(CRYPT) + 0xf000) /* 0x9f000 */ 277 278 /* 279 * Serial-ATA Host Controller (SATAHC) Registers 280 */ 281 #define ARMADAXP_SATAHC_BASE (UNITID2PHYS(SATA)) /* 0xa0000 */ 282 283 /* 284 * Buffer Management Controller Registers 285 */ 286 #define ARMADAXP_BMC_BASE (UNITID2PHYS(BM)) /* 0xc0000 */ 287 288 /* 289 * NAND Flash Controller Version 2.0 Registers 290 */ 291 #define ARMADAXP_NAND_BASE 0xc0000 292 293 /* 294 * PnC Unit Registers 295 */ 296 #define ARMADAXP_PNC_BASE (UNITID2PHYS(PNC)) /* 0xc8000 */ 297 298 /* 299 * SDIO Registers 300 */ 301 #define ARMADAXP_SDIO_BASE (UNITID2PHYS(SDIO) + 0x4000) /* 0xd4000 */ 302 303 /* 304 * Liquid Crystal Display Registers 305 */ 306 #define ARMADAXP_LCD_BASE (UNITID2PHYS(LCD)) /* 0xe0000 */ 307 308 #endif /* _ARMADAXPREG_H_ */ 309