1*59b77be9Sriastradh /* $NetBSD: rk_vop.c,v 1.16 2021/12/20 00:27:17 riastradh Exp $ */
2276fc83aSjmcneill
3276fc83aSjmcneill /*-
4276fc83aSjmcneill * Copyright (c) 2019 Jared D. McNeill <jmcneill@invisible.ca>
5276fc83aSjmcneill * All rights reserved.
6276fc83aSjmcneill *
7276fc83aSjmcneill * Redistribution and use in source and binary forms, with or without
8276fc83aSjmcneill * modification, are permitted provided that the following conditions
9276fc83aSjmcneill * are met:
10276fc83aSjmcneill * 1. Redistributions of source code must retain the above copyright
11276fc83aSjmcneill * notice, this list of conditions and the following disclaimer.
12276fc83aSjmcneill * 2. Redistributions in binary form must reproduce the above copyright
13276fc83aSjmcneill * notice, this list of conditions and the following disclaimer in the
14276fc83aSjmcneill * documentation and/or other materials provided with the distribution.
15276fc83aSjmcneill *
16276fc83aSjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17276fc83aSjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18276fc83aSjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19276fc83aSjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20276fc83aSjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21276fc83aSjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22276fc83aSjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23276fc83aSjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24276fc83aSjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25276fc83aSjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26276fc83aSjmcneill * SUCH DAMAGE.
27276fc83aSjmcneill */
28276fc83aSjmcneill
29276fc83aSjmcneill #include <sys/cdefs.h>
30*59b77be9Sriastradh __KERNEL_RCSID(0, "$NetBSD: rk_vop.c,v 1.16 2021/12/20 00:27:17 riastradh Exp $");
31276fc83aSjmcneill
32276fc83aSjmcneill #include <sys/param.h>
33276fc83aSjmcneill #include <sys/bus.h>
3467b4eb14Sriastradh #include <sys/conf.h>
35276fc83aSjmcneill #include <sys/device.h>
36276fc83aSjmcneill #include <sys/intr.h>
37276fc83aSjmcneill #include <sys/kernel.h>
38276fc83aSjmcneill #include <sys/sysctl.h>
3967b4eb14Sriastradh #include <sys/systm.h>
40276fc83aSjmcneill
41276fc83aSjmcneill #include <dev/fdt/fdt_port.h>
4267b4eb14Sriastradh #include <dev/fdt/fdtvar.h>
43276fc83aSjmcneill
44276fc83aSjmcneill #include <arm/rockchip/rk_drm.h>
45276fc83aSjmcneill
468b06e185Sriastradh #include <drm/drm_atomic.h>
478b06e185Sriastradh #include <drm/drm_atomic_helper.h>
4867b4eb14Sriastradh #include <drm/drm_crtc.h>
4967b4eb14Sriastradh #include <drm/drm_crtc_helper.h>
5067b4eb14Sriastradh #include <drm/drm_drv.h>
5167b4eb14Sriastradh #include <drm/drm_fourcc.h>
5267b4eb14Sriastradh #include <drm/drm_plane_helper.h>
53*59b77be9Sriastradh #include <drm/drm_vblank.h>
5467b4eb14Sriastradh
55276fc83aSjmcneill #define VOP_REG_CFG_DONE 0x0000
56276fc83aSjmcneill #define REG_LOAD_EN __BIT(0)
57276fc83aSjmcneill #define VOP_SYS_CTRL 0x0008
58276fc83aSjmcneill #define VOP_STANDBY_EN __BIT(22)
59276fc83aSjmcneill #define MIPI_OUT_EN __BIT(15)
60276fc83aSjmcneill #define EDP_OUT_EN __BIT(14)
61276fc83aSjmcneill #define HDMI_OUT_EN __BIT(13)
62276fc83aSjmcneill #define RGB_OUT_EN __BIT(12)
63276fc83aSjmcneill #define VOP_DSP_CTRL0 0x0010
64276fc83aSjmcneill #define DSP_OUT_MODE __BITS(3,0)
65276fc83aSjmcneill #define DSP_OUT_MODE_RGB888 0
66276fc83aSjmcneill #define DSP_OUT_MODE_RGBaaa 15
67276fc83aSjmcneill #define VOP_DSP_CTRL1 0x0014
68276fc83aSjmcneill #define VOP_WIN0_CTRL 0x0030
69276fc83aSjmcneill #define WIN0_LB_MODE __BITS(7,5)
70276fc83aSjmcneill #define WIN0_LB_MODE_RGB_3840X2 2
71276fc83aSjmcneill #define WIN0_LB_MODE_RGB_2560X4 3
72276fc83aSjmcneill #define WIN0_LB_MODE_RGB_1920X5 4
73276fc83aSjmcneill #define WIN0_LB_MODE_RGB_1280X8 5
74276fc83aSjmcneill #define WIN0_DATA_FMT __BITS(3,1)
75276fc83aSjmcneill #define WIN0_DATA_FMT_ARGB888 0
76276fc83aSjmcneill #define WIN0_EN __BIT(0)
77276fc83aSjmcneill #define VOP_WIN0_COLOR_KEY 0x0038
78276fc83aSjmcneill #define VOP_WIN0_VIR 0x003c
79276fc83aSjmcneill #define WIN0_VIR_STRIDE __BITS(13,0)
80276fc83aSjmcneill #define VOP_WIN0_YRGB_MST 0x0040
81276fc83aSjmcneill #define VOP_WIN0_ACT_INFO 0x0048
82276fc83aSjmcneill #define WIN0_ACT_HEIGHT __BITS(28,16)
83276fc83aSjmcneill #define WIN0_ACT_WIDTH __BITS(12,0)
84276fc83aSjmcneill #define VOP_WIN0_DSP_INFO 0x004c
85276fc83aSjmcneill #define WIN0_DSP_HEIGHT __BITS(27,16)
86276fc83aSjmcneill #define WIN0_DSP_WIDTH __BITS(11,0)
87276fc83aSjmcneill #define VOP_WIN0_DSP_ST 0x0050
88276fc83aSjmcneill #define WIN0_DSP_YST __BITS(28,16)
89276fc83aSjmcneill #define WIN0_DSP_XST __BITS(12,0)
90276fc83aSjmcneill #define VOP_POST_DSP_HACT_INFO 0x0170
91276fc83aSjmcneill #define DSP_HACT_ST_POST __BITS(28,16)
92276fc83aSjmcneill #define DSP_HACT_END_POST __BITS(12,0)
93276fc83aSjmcneill #define VOP_POST_DSP_VACT_INFO 0x0174
94276fc83aSjmcneill #define DSP_VACT_ST_POST __BITS(28,16)
95276fc83aSjmcneill #define DSP_VACT_END_POST __BITS(12,0)
96276fc83aSjmcneill #define VOP_DSP_HTOTAL_HS_END 0x0188
97ee563e59Sjmcneill #define DSP_HS_END __BITS(28,16)
98ee563e59Sjmcneill #define DSP_HTOTAL __BITS(12,0)
99276fc83aSjmcneill #define VOP_DSP_HACT_ST_END 0x018c
100276fc83aSjmcneill #define DSP_HACT_ST __BITS(28,16)
101276fc83aSjmcneill #define DSP_HACT_END __BITS(12,0)
102276fc83aSjmcneill #define VOP_DSP_VTOTAL_VS_END 0x0190
103ee563e59Sjmcneill #define DSP_VS_END __BITS(28,16)
104ee563e59Sjmcneill #define DSP_VTOTAL __BITS(12,0)
105276fc83aSjmcneill #define VOP_DSP_VACT_ST_END 0x0194
106276fc83aSjmcneill #define DSP_VACT_ST __BITS(28,16)
107276fc83aSjmcneill #define DSP_VACT_END __BITS(12,0)
108*59b77be9Sriastradh #define VOP_INTR_EN0 0x0280
109*59b77be9Sriastradh #define VOP_INTR_CLEAR0 0x0284
110*59b77be9Sriastradh #define VOP_INTR_STATUS0 0x0288
111*59b77be9Sriastradh #define VOP_INTR_RAW_STATUS0 0x028c
112*59b77be9Sriastradh #define VOP_INTR0_DMA_FINISH __BIT(15)
113*59b77be9Sriastradh #define VOP_INTR0_MMU __BIT(14)
114*59b77be9Sriastradh #define VOP_INTR0_DSP_HOLD_VALID __BIT(13)
115*59b77be9Sriastradh #define VOP_INTR0_FS_FIELD __BIT(12)
116*59b77be9Sriastradh #define VOP_INTR0_POST_BUF_EMPTY __BIT(11)
117*59b77be9Sriastradh #define VOP_INTR0_HWC_EMPTY __BIT(10)
118*59b77be9Sriastradh #define VOP_INTR0_WIN3_EMPTY __BIT(9)
119*59b77be9Sriastradh #define VOP_INTR0_WIN2_EMPTY __BIT(8)
120*59b77be9Sriastradh #define VOP_INTR0_WIN1_EMPTY __BIT(7)
121*59b77be9Sriastradh #define VOP_INTR0_WIN0_EMPTY __BIT(6)
122*59b77be9Sriastradh #define VOP_INTR0_BUS_ERROR __BIT(5)
123*59b77be9Sriastradh #define VOP_INTR0_LINE_FLAG1 __BIT(4)
124*59b77be9Sriastradh #define VOP_INTR0_LINE_FLAG0 __BIT(3)
125*59b77be9Sriastradh #define VOP_INTR0_ADDR_SAME __BIT(2)
126*59b77be9Sriastradh #define VOP_INTR0_FS_NEW __BIT(1)
127*59b77be9Sriastradh #define VOP_INTR0_FS __BIT(0)
128276fc83aSjmcneill
129276fc83aSjmcneill /*
130276fc83aSjmcneill * Polarity fields are in different locations depending on SoC and output type,
131276fc83aSjmcneill * but always in the same order.
132276fc83aSjmcneill */
133276fc83aSjmcneill #define DSP_DCLK_POL __BIT(3)
134276fc83aSjmcneill #define DSP_DEN_POL __BIT(2)
135276fc83aSjmcneill #define DSP_VSYNC_POL __BIT(1)
136276fc83aSjmcneill #define DSP_HSYNC_POL __BIT(0)
137276fc83aSjmcneill
138276fc83aSjmcneill enum vop_ep_type {
139276fc83aSjmcneill VOP_EP_MIPI,
140276fc83aSjmcneill VOP_EP_EDP,
141276fc83aSjmcneill VOP_EP_HDMI,
142276fc83aSjmcneill VOP_EP_MIPI1,
143276fc83aSjmcneill VOP_EP_DP,
144276fc83aSjmcneill VOP_NEP
145276fc83aSjmcneill };
146276fc83aSjmcneill
147276fc83aSjmcneill struct rk_vop_softc;
148276fc83aSjmcneill struct rk_vop_config;
149276fc83aSjmcneill
150276fc83aSjmcneill struct rk_vop_crtc {
151276fc83aSjmcneill struct drm_crtc base;
152276fc83aSjmcneill struct rk_vop_softc *sc;
153276fc83aSjmcneill };
154276fc83aSjmcneill
1558b06e185Sriastradh struct rk_vop_plane {
1568b06e185Sriastradh struct drm_plane base;
1578b06e185Sriastradh struct rk_vop_softc *sc;
1588b06e185Sriastradh };
1598b06e185Sriastradh
160276fc83aSjmcneill struct rk_vop_softc {
161276fc83aSjmcneill device_t sc_dev;
162276fc83aSjmcneill bus_space_tag_t sc_bst;
163276fc83aSjmcneill bus_space_handle_t sc_bsh;
164276fc83aSjmcneill int sc_phandle;
165276fc83aSjmcneill
166276fc83aSjmcneill struct clk *sc_dclk;
167276fc83aSjmcneill
1688b06e185Sriastradh struct rk_vop_plane sc_plane;
169276fc83aSjmcneill struct rk_vop_crtc sc_crtc;
170276fc83aSjmcneill
171276fc83aSjmcneill struct fdt_device_ports sc_ports;
172276fc83aSjmcneill
1730717bee5Sthorpej const struct rk_vop_config *sc_conf;
174*59b77be9Sriastradh
175*59b77be9Sriastradh /* vblank */
176*59b77be9Sriastradh void *sc_ih;
177*59b77be9Sriastradh kmutex_t sc_intr_lock;
178*59b77be9Sriastradh struct drm_pending_vblank_event *sc_event;
179276fc83aSjmcneill };
180276fc83aSjmcneill
181276fc83aSjmcneill #define to_rk_vop_crtc(x) container_of(x, struct rk_vop_crtc, base)
1828b06e185Sriastradh #define to_rk_vop_plane(x) container_of(x, struct rk_vop_plane, base)
183276fc83aSjmcneill
184276fc83aSjmcneill #define RD4(sc, reg) \
185276fc83aSjmcneill bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
186276fc83aSjmcneill #define WR4(sc, reg, val) \
187276fc83aSjmcneill bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
188276fc83aSjmcneill
189*59b77be9Sriastradh static void
WR4_MASK(struct rk_vop_softc * sc,bus_size_t reg,uint16_t mask,uint16_t val)190*59b77be9Sriastradh WR4_MASK(struct rk_vop_softc *sc, bus_size_t reg, uint16_t mask, uint16_t val)
191*59b77be9Sriastradh {
192*59b77be9Sriastradh
193*59b77be9Sriastradh KASSERT(val == (mask & val));
194*59b77be9Sriastradh WR4(sc, reg, ((uint32_t)mask << 16) | val);
195*59b77be9Sriastradh }
196*59b77be9Sriastradh
197276fc83aSjmcneill struct rk_vop_config {
198276fc83aSjmcneill const char *descr;
199276fc83aSjmcneill u_int out_mode;
200276fc83aSjmcneill void (*init)(struct rk_vop_softc *);
201276fc83aSjmcneill void (*set_polarity)(struct rk_vop_softc *,
202276fc83aSjmcneill enum vop_ep_type, uint32_t);
203276fc83aSjmcneill };
204276fc83aSjmcneill
2058b06e185Sriastradh static const uint32_t rk_vop_layer_formats[] = {
2068b06e185Sriastradh DRM_FORMAT_ARGB8888,
2078b06e185Sriastradh DRM_FORMAT_XRGB8888,
2088b06e185Sriastradh };
2098b06e185Sriastradh
2108b06e185Sriastradh static const uint64_t rk_vop_layer_modifiers[] = {
2118b06e185Sriastradh DRM_FORMAT_MOD_LINEAR,
2128b06e185Sriastradh DRM_FORMAT_MOD_INVALID
2138b06e185Sriastradh };
2148b06e185Sriastradh
215276fc83aSjmcneill #define RK3399_VOP_MIPI_POL __BITS(31,28)
216276fc83aSjmcneill #define RK3399_VOP_EDP_POL __BITS(27,24)
217276fc83aSjmcneill #define RK3399_VOP_HDMI_POL __BITS(23,20)
218276fc83aSjmcneill #define RK3399_VOP_DP_POL __BITS(19,16)
219276fc83aSjmcneill
220276fc83aSjmcneill #define RK3399_VOP_SYS_CTRL_ENABLE __BIT(11)
221276fc83aSjmcneill
222276fc83aSjmcneill static void
rk3399_vop_set_polarity(struct rk_vop_softc * sc,enum vop_ep_type ep_type,uint32_t pol)223276fc83aSjmcneill rk3399_vop_set_polarity(struct rk_vop_softc *sc, enum vop_ep_type ep_type, uint32_t pol)
224276fc83aSjmcneill {
225276fc83aSjmcneill uint32_t mask, val;
226276fc83aSjmcneill
227276fc83aSjmcneill switch (ep_type) {
228276fc83aSjmcneill case VOP_EP_MIPI:
229276fc83aSjmcneill case VOP_EP_MIPI1:
230276fc83aSjmcneill mask = RK3399_VOP_MIPI_POL;
231276fc83aSjmcneill break;
232276fc83aSjmcneill case VOP_EP_EDP:
233276fc83aSjmcneill mask = RK3399_VOP_EDP_POL;
234276fc83aSjmcneill break;
235276fc83aSjmcneill case VOP_EP_HDMI:
236276fc83aSjmcneill mask = RK3399_VOP_HDMI_POL;
237276fc83aSjmcneill break;
238276fc83aSjmcneill case VOP_EP_DP:
239276fc83aSjmcneill mask = RK3399_VOP_DP_POL;
240276fc83aSjmcneill break;
241276fc83aSjmcneill default:
242276fc83aSjmcneill return;
243276fc83aSjmcneill }
244276fc83aSjmcneill
245276fc83aSjmcneill val = RD4(sc, VOP_DSP_CTRL1);
246276fc83aSjmcneill val &= ~mask;
247276fc83aSjmcneill val |= __SHIFTIN(pol, mask);
248276fc83aSjmcneill WR4(sc, VOP_DSP_CTRL1, val);
249276fc83aSjmcneill }
250276fc83aSjmcneill
251276fc83aSjmcneill static void
rk3399_vop_init(struct rk_vop_softc * sc)252276fc83aSjmcneill rk3399_vop_init(struct rk_vop_softc *sc)
253276fc83aSjmcneill {
254276fc83aSjmcneill uint32_t val;
255276fc83aSjmcneill
256276fc83aSjmcneill val = RD4(sc, VOP_SYS_CTRL);
257276fc83aSjmcneill val |= RK3399_VOP_SYS_CTRL_ENABLE;
258276fc83aSjmcneill WR4(sc, VOP_SYS_CTRL, val);
259276fc83aSjmcneill }
260276fc83aSjmcneill
261276fc83aSjmcneill static const struct rk_vop_config rk3399_vop_lit_config = {
262276fc83aSjmcneill .descr = "RK3399 VOPL",
263276fc83aSjmcneill .out_mode = DSP_OUT_MODE_RGB888,
264276fc83aSjmcneill .init = rk3399_vop_init,
265276fc83aSjmcneill .set_polarity = rk3399_vop_set_polarity,
266276fc83aSjmcneill };
267276fc83aSjmcneill
268276fc83aSjmcneill static const struct rk_vop_config rk3399_vop_big_config = {
269276fc83aSjmcneill .descr = "RK3399 VOPB",
270276fc83aSjmcneill .out_mode = DSP_OUT_MODE_RGBaaa,
271276fc83aSjmcneill .init = rk3399_vop_init,
272276fc83aSjmcneill .set_polarity = rk3399_vop_set_polarity,
273276fc83aSjmcneill };
274276fc83aSjmcneill
2750717bee5Sthorpej static const struct device_compatible_entry compat_data[] = {
2760717bee5Sthorpej { .compat = "rockchip,rk3399-vop-big",
2770717bee5Sthorpej .data = &rk3399_vop_big_config },
2780717bee5Sthorpej { .compat = "rockchip,rk3399-vop-lit",
2790717bee5Sthorpej .data = &rk3399_vop_lit_config },
2800717bee5Sthorpej
281f18cbf47Sthorpej DEVICE_COMPAT_EOL
282276fc83aSjmcneill };
283276fc83aSjmcneill
284276fc83aSjmcneill static int
rk_vop_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)2858b06e185Sriastradh rk_vop_plane_atomic_check(struct drm_plane *plane,
2868b06e185Sriastradh struct drm_plane_state *state)
287276fc83aSjmcneill {
2888b06e185Sriastradh struct drm_crtc_state *crtc_state;
289276fc83aSjmcneill
2908b06e185Sriastradh if (state->crtc == NULL)
291276fc83aSjmcneill return 0;
2928b06e185Sriastradh
2938b06e185Sriastradh crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
2948b06e185Sriastradh if (IS_ERR(crtc_state))
2958b06e185Sriastradh return PTR_ERR(crtc_state);
2968b06e185Sriastradh
2978b06e185Sriastradh return drm_atomic_helper_check_plane_state(state, crtc_state,
2988b06e185Sriastradh DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING,
2998b06e185Sriastradh false, true);
300276fc83aSjmcneill }
301276fc83aSjmcneill
302276fc83aSjmcneill static void
rk_vop_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)3038b06e185Sriastradh rk_vop_plane_atomic_update(struct drm_plane *plane,
3048b06e185Sriastradh struct drm_plane_state *old_state)
305276fc83aSjmcneill {
3068b06e185Sriastradh struct rk_vop_plane *vop_plane = to_rk_vop_plane(plane);
3078b06e185Sriastradh struct rk_vop_softc * const sc = vop_plane->sc;
3088b06e185Sriastradh struct rk_drm_framebuffer *sfb =
3098b06e185Sriastradh to_rk_drm_framebuffer(plane->state->fb);
3108b06e185Sriastradh struct drm_display_mode *mode = &plane->state->crtc->mode;
3118b06e185Sriastradh struct drm_rect *src = &plane->state->src;
3128b06e185Sriastradh struct drm_rect *dst = &plane->state->dst;
3138b06e185Sriastradh uint32_t act_width, act_height, dsp_width, dsp_height;
3148b06e185Sriastradh uint32_t htotal, hsync_start;
3158b06e185Sriastradh uint32_t vtotal, vsync_start;
3168b06e185Sriastradh uint32_t lb_mode;
3178b06e185Sriastradh uint32_t block_h, block_w, x, y, block_start_y, num_hblocks;
3188b06e185Sriastradh uint64_t paddr;
3198b06e185Sriastradh uint32_t val;
3208b06e185Sriastradh
3218b06e185Sriastradh act_width = drm_rect_width(src) >> 16;
3228b06e185Sriastradh act_height = drm_rect_height(src) >> 16;
3238b06e185Sriastradh val = __SHIFTIN(act_width - 1, WIN0_ACT_WIDTH) |
3248b06e185Sriastradh __SHIFTIN(act_height - 1, WIN0_ACT_HEIGHT);
3258b06e185Sriastradh WR4(sc, VOP_WIN0_ACT_INFO, val);
3268b06e185Sriastradh
3278b06e185Sriastradh dsp_width = drm_rect_width(dst);
3288b06e185Sriastradh dsp_height = drm_rect_height(dst);
3298b06e185Sriastradh val = __SHIFTIN(dsp_width - 1, WIN0_DSP_WIDTH) |
3308b06e185Sriastradh __SHIFTIN(dsp_height - 1, WIN0_DSP_HEIGHT);
3318b06e185Sriastradh WR4(sc, VOP_WIN0_DSP_INFO, val);
3328b06e185Sriastradh
3338b06e185Sriastradh htotal = mode->htotal;
3348b06e185Sriastradh hsync_start = mode->hsync_start;
3358b06e185Sriastradh vtotal = mode->vtotal;
3368b06e185Sriastradh vsync_start = mode->vsync_start;
3378b06e185Sriastradh val = __SHIFTIN(dst->x1 + htotal - hsync_start, WIN0_DSP_XST) |
3388b06e185Sriastradh __SHIFTIN(dst->y1 + vtotal - vsync_start, WIN0_DSP_YST);
3398b06e185Sriastradh WR4(sc, VOP_WIN0_DSP_ST, val);
3408b06e185Sriastradh
3418b06e185Sriastradh WR4(sc, VOP_WIN0_COLOR_KEY, 0);
3428b06e185Sriastradh
3438b06e185Sriastradh if (act_width > 2560)
3448b06e185Sriastradh lb_mode = WIN0_LB_MODE_RGB_3840X2;
3458b06e185Sriastradh else if (act_width > 1920)
3468b06e185Sriastradh lb_mode = WIN0_LB_MODE_RGB_2560X4;
3478b06e185Sriastradh else if (act_width > 1280)
3488b06e185Sriastradh lb_mode = WIN0_LB_MODE_RGB_1920X5;
3498b06e185Sriastradh else
3508b06e185Sriastradh lb_mode = WIN0_LB_MODE_RGB_1280X8;
3518b06e185Sriastradh val = __SHIFTIN(lb_mode, WIN0_LB_MODE) |
3528b06e185Sriastradh __SHIFTIN(WIN0_DATA_FMT_ARGB888, WIN0_DATA_FMT) |
3538b06e185Sriastradh WIN0_EN;
3548b06e185Sriastradh WR4(sc, VOP_WIN0_CTRL, val);
3558b06e185Sriastradh
3568b06e185Sriastradh paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr;
3578b06e185Sriastradh paddr += sfb->base.offsets[0];
3588b06e185Sriastradh
3598b06e185Sriastradh block_h = drm_format_info_block_height(sfb->base.format, 0);
3608b06e185Sriastradh block_w = drm_format_info_block_width(sfb->base.format, 0);
3618b06e185Sriastradh x = plane->state->src_x >> 16;
3628b06e185Sriastradh y = plane->state->src_y >> 16;
3638b06e185Sriastradh block_start_y = (y / block_h) * block_h;
3648b06e185Sriastradh num_hblocks = x / block_w;
3658b06e185Sriastradh
3668b06e185Sriastradh paddr += block_start_y * sfb->base.pitches[0];
3678b06e185Sriastradh paddr += sfb->base.format->char_per_block[0] * num_hblocks;
3688b06e185Sriastradh
3698b06e185Sriastradh DRM_DEBUG_KMS("[PLANE:%s] fb=%p paddr=0x%lx\n", plane->name, sfb, paddr);
3708b06e185Sriastradh
3718b06e185Sriastradh KASSERT((paddr & ~0xffffffff) == 0);
3728b06e185Sriastradh
3738b06e185Sriastradh val = __SHIFTIN(sfb->base.pitches[0] / 4, WIN0_VIR_STRIDE);
3748b06e185Sriastradh WR4(sc, VOP_WIN0_VIR, val);
3758b06e185Sriastradh
3768b06e185Sriastradh /* Framebuffer start address */
3778b06e185Sriastradh WR4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr);
378276fc83aSjmcneill }
379276fc83aSjmcneill
3808b06e185Sriastradh static void
rk_vop_plane_atomic_disable(struct drm_plane * plane,struct drm_plane_state * state)381a27a6199Sriastradh rk_vop_plane_atomic_disable(struct drm_plane *plane,
382a27a6199Sriastradh struct drm_plane_state *state)
3838b06e185Sriastradh {
384a27a6199Sriastradh struct rk_vop_plane *vop_plane = to_rk_vop_plane(plane);
385a27a6199Sriastradh struct rk_vop_softc * const sc = vop_plane->sc;
386a27a6199Sriastradh
387a27a6199Sriastradh WR4(sc, VOP_WIN0_CTRL, 0); /* clear WIN0_EN */
3888b06e185Sriastradh }
3898b06e185Sriastradh
3908b06e185Sriastradh static const struct drm_plane_helper_funcs rk_vop_plane_helper_funcs = {
3918b06e185Sriastradh .atomic_check = rk_vop_plane_atomic_check,
3928b06e185Sriastradh .atomic_update = rk_vop_plane_atomic_update,
3938b06e185Sriastradh .atomic_disable = rk_vop_plane_atomic_disable,
3948b06e185Sriastradh #if 0
3958b06e185Sriastradh .prepare_fb = drm_gem_vram_plane_helper_prepare_fb,
3968b06e185Sriastradh .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb,
3978b06e185Sriastradh #endif
3988b06e185Sriastradh };
3998b06e185Sriastradh
4008b06e185Sriastradh static bool
rk_vop_plane_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)401*59b77be9Sriastradh rk_vop_plane_format_mod_supported(struct drm_plane *plane, uint32_t format,
4028b06e185Sriastradh uint64_t modifier)
4038b06e185Sriastradh {
4048b06e185Sriastradh return modifier == DRM_FORMAT_MOD_LINEAR;
4058b06e185Sriastradh }
4068b06e185Sriastradh
4078b06e185Sriastradh static const struct drm_plane_funcs rk_vop_plane_funcs = {
4088b06e185Sriastradh .update_plane = drm_atomic_helper_update_plane,
4098b06e185Sriastradh .disable_plane = drm_atomic_helper_disable_plane,
4108b06e185Sriastradh .destroy = drm_plane_cleanup,
4118b06e185Sriastradh .reset = drm_atomic_helper_plane_reset,
4128b06e185Sriastradh .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
4138b06e185Sriastradh .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
414*59b77be9Sriastradh .format_mod_supported = rk_vop_plane_format_mod_supported,
415276fc83aSjmcneill };
416276fc83aSjmcneill
417276fc83aSjmcneill static void
rk_vop_crtc_dpms(struct drm_crtc * crtc,int mode)418*59b77be9Sriastradh rk_vop_crtc_dpms(struct drm_crtc *crtc, int mode)
419276fc83aSjmcneill {
420ea15afdeSmrg struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
421ea15afdeSmrg struct rk_vop_softc * const sc = mixer_crtc->sc;
422ea15afdeSmrg uint32_t val;
423ea15afdeSmrg
424ea15afdeSmrg val = RD4(sc, VOP_SYS_CTRL);
425ea15afdeSmrg
426ea15afdeSmrg switch (mode) {
427ea15afdeSmrg case DRM_MODE_DPMS_ON:
428ea15afdeSmrg val &= ~VOP_STANDBY_EN;
429ea15afdeSmrg break;
430ea15afdeSmrg case DRM_MODE_DPMS_STANDBY:
431ea15afdeSmrg case DRM_MODE_DPMS_SUSPEND:
432ea15afdeSmrg case DRM_MODE_DPMS_OFF:
433ea15afdeSmrg val |= VOP_STANDBY_EN;
434ea15afdeSmrg break;
435ea15afdeSmrg }
436ea15afdeSmrg
437ea15afdeSmrg WR4(sc, VOP_SYS_CTRL, val);
438ea15afdeSmrg
439ea15afdeSmrg /* Commit settings */
440ea15afdeSmrg WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
441276fc83aSjmcneill }
442276fc83aSjmcneill
4438b06e185Sriastradh static int
rk_vop_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)444*59b77be9Sriastradh rk_vop_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
445276fc83aSjmcneill {
4468b06e185Sriastradh bool enabled = state->plane_mask & drm_plane_mask(crtc->primary);
4478b06e185Sriastradh
4488b06e185Sriastradh if (enabled != state->enable)
4498b06e185Sriastradh return -EINVAL;
4508b06e185Sriastradh
4518b06e185Sriastradh return drm_atomic_add_affected_planes(state->state, crtc);
452276fc83aSjmcneill }
453276fc83aSjmcneill
4548b06e185Sriastradh static void
rk_vop_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * state)455*59b77be9Sriastradh rk_vop_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *state)
456276fc83aSjmcneill {
457276fc83aSjmcneill struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
458276fc83aSjmcneill struct rk_vop_softc * const sc = mixer_crtc->sc;
4598b06e185Sriastradh struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
460276fc83aSjmcneill uint32_t val;
46147dfb5c8Sjakllsch u_int pol;
46247dfb5c8Sjakllsch int connector_type = 0;
46347dfb5c8Sjakllsch struct drm_connector *connector;
464c7fa00edSriastradh struct drm_connector_list_iter conn_iter;
4658b06e185Sriastradh int error;
466276fc83aSjmcneill
467276fc83aSjmcneill const u_int hactive = adjusted_mode->hdisplay;
468276fc83aSjmcneill const u_int hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
469276fc83aSjmcneill const u_int hback_porch = adjusted_mode->htotal - adjusted_mode->hsync_end;
47047dfb5c8Sjakllsch const u_int hfront_porch = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
471276fc83aSjmcneill
472276fc83aSjmcneill const u_int vactive = adjusted_mode->vdisplay;
473276fc83aSjmcneill const u_int vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
474276fc83aSjmcneill const u_int vback_porch = adjusted_mode->vtotal - adjusted_mode->vsync_end;
47547dfb5c8Sjakllsch const u_int vfront_porch = adjusted_mode->vsync_start - adjusted_mode->vdisplay;
476276fc83aSjmcneill
477276fc83aSjmcneill error = clk_set_rate(sc->sc_dclk, adjusted_mode->clock * 1000);
4788b06e185Sriastradh if (error)
479276fc83aSjmcneill DRM_ERROR("couldn't set pixel clock: %d\n", error);
480276fc83aSjmcneill
48147dfb5c8Sjakllsch pol = DSP_DCLK_POL;
48247dfb5c8Sjakllsch if ((adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) != 0)
48347dfb5c8Sjakllsch pol |= DSP_HSYNC_POL;
48447dfb5c8Sjakllsch if ((adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) != 0)
48547dfb5c8Sjakllsch pol |= DSP_VSYNC_POL;
48647dfb5c8Sjakllsch
487c7fa00edSriastradh drm_connector_list_iter_begin(crtc->dev, &conn_iter);
488c7fa00edSriastradh drm_for_each_connector_iter(connector, &conn_iter) {
489c7fa00edSriastradh if (connector->encoder == NULL)
49047dfb5c8Sjakllsch continue;
49147dfb5c8Sjakllsch if (connector->encoder->crtc == crtc) {
49247dfb5c8Sjakllsch connector_type = connector->connector_type;
49347dfb5c8Sjakllsch break;
49447dfb5c8Sjakllsch }
49547dfb5c8Sjakllsch }
496c7fa00edSriastradh drm_connector_list_iter_end(&conn_iter);
49747dfb5c8Sjakllsch
49847dfb5c8Sjakllsch switch (connector_type) {
49947dfb5c8Sjakllsch case DRM_MODE_CONNECTOR_HDMIA:
50047dfb5c8Sjakllsch sc->sc_conf->set_polarity(sc, VOP_EP_HDMI, pol);
50147dfb5c8Sjakllsch break;
50247dfb5c8Sjakllsch case DRM_MODE_CONNECTOR_eDP:
50347dfb5c8Sjakllsch sc->sc_conf->set_polarity(sc, VOP_EP_EDP, pol);
50447dfb5c8Sjakllsch break;
50547dfb5c8Sjakllsch }
50647dfb5c8Sjakllsch
50747dfb5c8Sjakllsch val = RD4(sc, VOP_SYS_CTRL);
50847dfb5c8Sjakllsch val &= ~VOP_STANDBY_EN;
50947dfb5c8Sjakllsch val &= ~(MIPI_OUT_EN|EDP_OUT_EN|HDMI_OUT_EN|RGB_OUT_EN);
51047dfb5c8Sjakllsch
51147dfb5c8Sjakllsch switch (connector_type) {
51247dfb5c8Sjakllsch case DRM_MODE_CONNECTOR_HDMIA:
51347dfb5c8Sjakllsch val |= HDMI_OUT_EN;
51447dfb5c8Sjakllsch break;
51547dfb5c8Sjakllsch case DRM_MODE_CONNECTOR_eDP:
51647dfb5c8Sjakllsch val |= EDP_OUT_EN;
51747dfb5c8Sjakllsch break;
51847dfb5c8Sjakllsch }
51947dfb5c8Sjakllsch WR4(sc, VOP_SYS_CTRL, val);
52047dfb5c8Sjakllsch
52147dfb5c8Sjakllsch val = RD4(sc, VOP_DSP_CTRL0);
52247dfb5c8Sjakllsch val &= ~DSP_OUT_MODE;
52347dfb5c8Sjakllsch val |= __SHIFTIN(sc->sc_conf->out_mode, DSP_OUT_MODE);
52447dfb5c8Sjakllsch WR4(sc, VOP_DSP_CTRL0, val);
52547dfb5c8Sjakllsch
52647dfb5c8Sjakllsch val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST_POST) |
52747dfb5c8Sjakllsch __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END_POST);
52847dfb5c8Sjakllsch WR4(sc, VOP_POST_DSP_HACT_INFO, val);
52947dfb5c8Sjakllsch
53047dfb5c8Sjakllsch val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST) |
53147dfb5c8Sjakllsch __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END);
53247dfb5c8Sjakllsch WR4(sc, VOP_DSP_HACT_ST_END, val);
53347dfb5c8Sjakllsch
53447dfb5c8Sjakllsch val = __SHIFTIN(hsync_len, DSP_HTOTAL) |
53547dfb5c8Sjakllsch __SHIFTIN(hsync_len + hback_porch + hactive + hfront_porch, DSP_HS_END);
53647dfb5c8Sjakllsch WR4(sc, VOP_DSP_HTOTAL_HS_END, val);
53747dfb5c8Sjakllsch
53847dfb5c8Sjakllsch val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST_POST) |
53947dfb5c8Sjakllsch __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END_POST);
54047dfb5c8Sjakllsch WR4(sc, VOP_POST_DSP_VACT_INFO, val);
54147dfb5c8Sjakllsch
54247dfb5c8Sjakllsch val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST) |
54347dfb5c8Sjakllsch __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END);
54447dfb5c8Sjakllsch WR4(sc, VOP_DSP_VACT_ST_END, val);
54547dfb5c8Sjakllsch
54647dfb5c8Sjakllsch val = __SHIFTIN(vsync_len, DSP_VTOTAL) |
54747dfb5c8Sjakllsch __SHIFTIN(vsync_len + vback_porch + vactive + vfront_porch, DSP_VS_END);
54847dfb5c8Sjakllsch WR4(sc, VOP_DSP_VTOTAL_VS_END, val);
549*59b77be9Sriastradh
550*59b77be9Sriastradh drm_crtc_vblank_on(crtc);
551276fc83aSjmcneill }
552276fc83aSjmcneill
553276fc83aSjmcneill static void
rk_vop_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * state)554*59b77be9Sriastradh rk_vop_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *state)
555*59b77be9Sriastradh {
556*59b77be9Sriastradh struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
557*59b77be9Sriastradh struct rk_vop_softc * const sc = mixer_crtc->sc;
558*59b77be9Sriastradh uint32_t val;
559*59b77be9Sriastradh
560*59b77be9Sriastradh drm_crtc_vblank_off(crtc);
561*59b77be9Sriastradh
562*59b77be9Sriastradh val = RD4(sc, VOP_SYS_CTRL);
563*59b77be9Sriastradh val |= VOP_STANDBY_EN;
564*59b77be9Sriastradh WR4(sc, VOP_SYS_CTRL, val);
565*59b77be9Sriastradh
566*59b77be9Sriastradh if (crtc->state->event && !crtc->state->active) {
567*59b77be9Sriastradh spin_lock(&crtc->dev->event_lock);
568*59b77be9Sriastradh drm_crtc_send_vblank_event(crtc, crtc->state->event);
569*59b77be9Sriastradh spin_unlock(&crtc->dev->event_lock);
570*59b77be9Sriastradh
571*59b77be9Sriastradh crtc->state->event = NULL;
572*59b77be9Sriastradh }
573*59b77be9Sriastradh }
574*59b77be9Sriastradh
575*59b77be9Sriastradh static void
rk_vop_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * state)576*59b77be9Sriastradh rk_vop_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state)
577*59b77be9Sriastradh {
578*59b77be9Sriastradh struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
579*59b77be9Sriastradh struct rk_vop_softc * const sc = mixer_crtc->sc;
580*59b77be9Sriastradh int ret;
581*59b77be9Sriastradh
582*59b77be9Sriastradh /* Commit settings */
583*59b77be9Sriastradh WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
584*59b77be9Sriastradh
585*59b77be9Sriastradh /*
586*59b77be9Sriastradh * If caller wants a vblank event, tell the vblank interrupt
587*59b77be9Sriastradh * handler to send it on the next interrupt.
588*59b77be9Sriastradh */
589*59b77be9Sriastradh spin_lock(&crtc->dev->event_lock);
590*59b77be9Sriastradh if (crtc->state->event) {
591*59b77be9Sriastradh if ((ret = drm_crtc_vblank_get_locked(crtc)) != 0)
592*59b77be9Sriastradh aprint_error_dev(sc->sc_dev,
593*59b77be9Sriastradh "drm_crtc_vblank_get: %d\n", ret);
594*59b77be9Sriastradh if (sc->sc_event) /* XXX leaky; KASSERT? */
595*59b77be9Sriastradh aprint_error_dev(sc->sc_dev, "unfinished vblank\n");
596*59b77be9Sriastradh sc->sc_event = crtc->state->event;
597*59b77be9Sriastradh crtc->state->event = NULL;
598*59b77be9Sriastradh }
599*59b77be9Sriastradh spin_unlock(&crtc->dev->event_lock);
600*59b77be9Sriastradh }
601*59b77be9Sriastradh
602*59b77be9Sriastradh static const struct drm_crtc_helper_funcs rk_vop_crtc_helper_funcs = {
603*59b77be9Sriastradh .dpms = rk_vop_crtc_dpms,
604*59b77be9Sriastradh .atomic_check = rk_vop_crtc_atomic_check,
605*59b77be9Sriastradh .atomic_enable = rk_vop_crtc_atomic_enable,
606*59b77be9Sriastradh .atomic_disable = rk_vop_crtc_atomic_disable,
607*59b77be9Sriastradh .atomic_flush = rk_vop_crtc_atomic_flush,
608*59b77be9Sriastradh };
609*59b77be9Sriastradh
610*59b77be9Sriastradh static int
rk_vop_crtc_enable_vblank(struct drm_crtc * crtc)611*59b77be9Sriastradh rk_vop_crtc_enable_vblank(struct drm_crtc *crtc)
612276fc83aSjmcneill {
613276fc83aSjmcneill struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
614276fc83aSjmcneill struct rk_vop_softc * const sc = mixer_crtc->sc;
615276fc83aSjmcneill
616*59b77be9Sriastradh mutex_spin_enter(&sc->sc_intr_lock);
617*59b77be9Sriastradh WR4_MASK(sc, VOP_INTR_CLEAR0, VOP_INTR0_FS_NEW, VOP_INTR0_FS_NEW);
618*59b77be9Sriastradh WR4_MASK(sc, VOP_INTR_EN0, VOP_INTR0_FS_NEW, VOP_INTR0_FS_NEW);
619*59b77be9Sriastradh mutex_spin_exit(&sc->sc_intr_lock);
620*59b77be9Sriastradh
621*59b77be9Sriastradh return 0;
622276fc83aSjmcneill }
623276fc83aSjmcneill
624*59b77be9Sriastradh static void
rk_vop_crtc_disable_vblank(struct drm_crtc * crtc)625*59b77be9Sriastradh rk_vop_crtc_disable_vblank(struct drm_crtc *crtc)
626*59b77be9Sriastradh {
627*59b77be9Sriastradh struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
628*59b77be9Sriastradh struct rk_vop_softc * const sc = mixer_crtc->sc;
629*59b77be9Sriastradh
630*59b77be9Sriastradh mutex_spin_enter(&sc->sc_intr_lock);
631*59b77be9Sriastradh WR4_MASK(sc, VOP_INTR_EN0, VOP_INTR0_FS_NEW, 0);
632*59b77be9Sriastradh mutex_spin_exit(&sc->sc_intr_lock);
633*59b77be9Sriastradh }
6348b06e185Sriastradh
6358b06e185Sriastradh static const struct drm_crtc_funcs rk_vop_crtc_funcs = {
6368b06e185Sriastradh .set_config = drm_atomic_helper_set_config,
6378b06e185Sriastradh .destroy = drm_crtc_cleanup,
6388b06e185Sriastradh .page_flip = drm_atomic_helper_page_flip,
6398b06e185Sriastradh .reset = drm_atomic_helper_crtc_reset,
6408b06e185Sriastradh .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
6418b06e185Sriastradh .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
642*59b77be9Sriastradh .enable_vblank = rk_vop_crtc_enable_vblank,
643*59b77be9Sriastradh .disable_vblank = rk_vop_crtc_disable_vblank,
644276fc83aSjmcneill };
645276fc83aSjmcneill
646276fc83aSjmcneill static int
rk_vop_ep_activate(device_t dev,struct fdt_endpoint * ep,bool activate)647276fc83aSjmcneill rk_vop_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate)
648276fc83aSjmcneill {
649276fc83aSjmcneill struct rk_vop_softc * const sc = device_private(dev);
650276fc83aSjmcneill struct drm_device *ddev;
6518b06e185Sriastradh int error;
652276fc83aSjmcneill
653276fc83aSjmcneill if (!activate)
654276fc83aSjmcneill return EINVAL;
655276fc83aSjmcneill
656276fc83aSjmcneill ddev = rk_drm_port_device(&sc->sc_ports);
657276fc83aSjmcneill if (ddev == NULL) {
658276fc83aSjmcneill DRM_ERROR("couldn't find DRM device\n");
659276fc83aSjmcneill return ENXIO;
660276fc83aSjmcneill }
661276fc83aSjmcneill
6628b06e185Sriastradh if (sc->sc_plane.sc == NULL) {
6638b06e185Sriastradh sc->sc_plane.sc = sc;
6648b06e185Sriastradh
6658b06e185Sriastradh error = drm_universal_plane_init(ddev, &sc->sc_plane.base, 0x3,
6668b06e185Sriastradh &rk_vop_plane_funcs,
6678b06e185Sriastradh rk_vop_layer_formats, __arraycount(rk_vop_layer_formats),
6688b06e185Sriastradh rk_vop_layer_modifiers,
6698b06e185Sriastradh DRM_PLANE_TYPE_PRIMARY,
6708b06e185Sriastradh NULL);
6718b06e185Sriastradh if (error) {
6728b06e185Sriastradh DRM_ERROR("couldn't initialize plane: %d\n", error);
6738b06e185Sriastradh return ENXIO;
6748b06e185Sriastradh }
6758b06e185Sriastradh drm_plane_helper_add(&sc->sc_plane.base, &rk_vop_plane_helper_funcs);
6768b06e185Sriastradh }
6778b06e185Sriastradh
678276fc83aSjmcneill if (sc->sc_crtc.sc == NULL) {
679276fc83aSjmcneill sc->sc_crtc.sc = sc;
680276fc83aSjmcneill
6818b06e185Sriastradh drm_crtc_init_with_planes(ddev, &sc->sc_crtc.base,
6828b06e185Sriastradh &sc->sc_plane.base, NULL, &rk_vop_crtc_funcs, NULL);
683276fc83aSjmcneill drm_crtc_helper_add(&sc->sc_crtc.base, &rk_vop_crtc_helper_funcs);
684276fc83aSjmcneill
685276fc83aSjmcneill aprint_debug_dev(dev, "using CRTC %d for %s\n",
686276fc83aSjmcneill drm_crtc_index(&sc->sc_crtc.base), sc->sc_conf->descr);
687276fc83aSjmcneill }
688276fc83aSjmcneill
689276fc83aSjmcneill const u_int ep_index = fdt_endpoint_index(ep);
69047dfb5c8Sjakllsch if (ep_index >= VOP_NEP) {
6919cd82edaSmrg DRM_ERROR("endpoint index %d out of range\n", ep_index);
6929cd82edaSmrg return ENXIO;
693276fc83aSjmcneill }
694276fc83aSjmcneill
695276fc83aSjmcneill return fdt_endpoint_activate(ep, activate);
696276fc83aSjmcneill }
697276fc83aSjmcneill
698276fc83aSjmcneill static void *
rk_vop_ep_get_data(device_t dev,struct fdt_endpoint * ep)699276fc83aSjmcneill rk_vop_ep_get_data(device_t dev, struct fdt_endpoint *ep)
700276fc83aSjmcneill {
701276fc83aSjmcneill struct rk_vop_softc * const sc = device_private(dev);
702276fc83aSjmcneill
70347dfb5c8Sjakllsch return &sc->sc_crtc.base;
704276fc83aSjmcneill }
705276fc83aSjmcneill
706276fc83aSjmcneill static int
rk_vop_intr(void * cookie)707*59b77be9Sriastradh rk_vop_intr(void *cookie)
708*59b77be9Sriastradh {
709*59b77be9Sriastradh struct rk_vop_softc * const sc = cookie;
710*59b77be9Sriastradh struct drm_crtc *crtc = &sc->sc_crtc.base;
711*59b77be9Sriastradh struct drm_device *ddev;
712*59b77be9Sriastradh uint32_t intr;
713*59b77be9Sriastradh int ours = 0;
714*59b77be9Sriastradh
715*59b77be9Sriastradh mutex_spin_enter(&sc->sc_intr_lock);
716*59b77be9Sriastradh intr = RD4(sc, VOP_INTR_STATUS0);
717*59b77be9Sriastradh WR4_MASK(sc, VOP_INTR_CLEAR0, intr, intr);
718*59b77be9Sriastradh mutex_spin_exit(&sc->sc_intr_lock);
719*59b77be9Sriastradh
720*59b77be9Sriastradh ddev = rk_drm_port_device(&sc->sc_ports);
721*59b77be9Sriastradh KASSERT(ddev);
722*59b77be9Sriastradh
723*59b77be9Sriastradh if (intr & VOP_INTR0_FS_NEW) {
724*59b77be9Sriastradh intr &= ~VOP_INTR0_FS_NEW;
725*59b77be9Sriastradh ours = 1;
726*59b77be9Sriastradh
727*59b77be9Sriastradh /* XXX defer to softint? */
728*59b77be9Sriastradh drm_crtc_handle_vblank(&sc->sc_crtc.base);
729*59b77be9Sriastradh spin_lock(&ddev->event_lock);
730*59b77be9Sriastradh if (sc->sc_event) {
731*59b77be9Sriastradh drm_crtc_send_vblank_event(crtc, sc->sc_event);
732*59b77be9Sriastradh sc->sc_event = NULL;
733*59b77be9Sriastradh drm_crtc_vblank_put(crtc);
734*59b77be9Sriastradh }
735*59b77be9Sriastradh spin_unlock(&ddev->event_lock);
736*59b77be9Sriastradh }
737*59b77be9Sriastradh
738*59b77be9Sriastradh if (intr) {
739*59b77be9Sriastradh aprint_error_dev(sc->sc_dev, "unhandled interrupts: 0x%04x\n",
740*59b77be9Sriastradh intr);
741*59b77be9Sriastradh }
742*59b77be9Sriastradh
743*59b77be9Sriastradh return ours;
744*59b77be9Sriastradh }
745*59b77be9Sriastradh
746*59b77be9Sriastradh static int
rk_vop_match(device_t parent,cfdata_t cf,void * aux)747276fc83aSjmcneill rk_vop_match(device_t parent, cfdata_t cf, void *aux)
748276fc83aSjmcneill {
749276fc83aSjmcneill struct fdt_attach_args * const faa = aux;
750276fc83aSjmcneill
7518e90f9edSthorpej return of_compatible_match(faa->faa_phandle, compat_data);
752276fc83aSjmcneill }
753276fc83aSjmcneill
754276fc83aSjmcneill static void
rk_vop_attach(device_t parent,device_t self,void * aux)755276fc83aSjmcneill rk_vop_attach(device_t parent, device_t self, void *aux)
756276fc83aSjmcneill {
757276fc83aSjmcneill struct rk_vop_softc * const sc = device_private(self);
758276fc83aSjmcneill struct fdt_attach_args * const faa = aux;
759276fc83aSjmcneill const int phandle = faa->faa_phandle;
760*59b77be9Sriastradh char intrstr[128];
761276fc83aSjmcneill const char * const reset_names[] = { "axi", "ahb", "dclk" };
762276fc83aSjmcneill const char * const clock_names[] = { "aclk_vop", "hclk_vop" };
763276fc83aSjmcneill struct fdtbus_reset *rst;
764276fc83aSjmcneill bus_addr_t addr;
765276fc83aSjmcneill bus_size_t size;
766276fc83aSjmcneill u_int n;
767276fc83aSjmcneill
768276fc83aSjmcneill if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
769276fc83aSjmcneill aprint_error(": couldn't get registers\n");
770276fc83aSjmcneill return;
771276fc83aSjmcneill }
772276fc83aSjmcneill
773*59b77be9Sriastradh if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
774*59b77be9Sriastradh aprint_error(": failed to decode interrupt\n");
775*59b77be9Sriastradh return;
776*59b77be9Sriastradh }
777*59b77be9Sriastradh
778276fc83aSjmcneill fdtbus_clock_assign(phandle);
779276fc83aSjmcneill
78099c9ad1eSriastradh /* assert all the reset signals for 20us */
781276fc83aSjmcneill for (n = 0; n < __arraycount(reset_names); n++) {
782276fc83aSjmcneill rst = fdtbus_reset_get(phandle, reset_names[n]);
78399c9ad1eSriastradh if (rst == NULL || fdtbus_reset_assert(rst) != 0) {
78499c9ad1eSriastradh aprint_error(": couldn't assert reset %s\n",
78599c9ad1eSriastradh reset_names[n]);
786276fc83aSjmcneill return;
787276fc83aSjmcneill }
788276fc83aSjmcneill }
78999c9ad1eSriastradh DELAY(10);
79099c9ad1eSriastradh for (n = 0; n < __arraycount(reset_names); n++) {
79199c9ad1eSriastradh rst = fdtbus_reset_get(phandle, reset_names[n]);
79299c9ad1eSriastradh if (rst == NULL || fdtbus_reset_deassert(rst) != 0) {
79399c9ad1eSriastradh aprint_error(": couldn't de-assert reset %s\n",
79499c9ad1eSriastradh reset_names[n]);
79599c9ad1eSriastradh return;
79699c9ad1eSriastradh }
79799c9ad1eSriastradh }
79899c9ad1eSriastradh
799276fc83aSjmcneill for (n = 0; n < __arraycount(clock_names); n++) {
800276fc83aSjmcneill if (fdtbus_clock_enable(phandle, clock_names[n], true) != 0) {
801276fc83aSjmcneill aprint_error(": couldn't enable clock %s\n", clock_names[n]);
802276fc83aSjmcneill return;
803276fc83aSjmcneill }
804276fc83aSjmcneill }
805276fc83aSjmcneill sc->sc_dclk = fdtbus_clock_get(phandle, "dclk_vop");
806276fc83aSjmcneill if (sc->sc_dclk == NULL || clk_enable(sc->sc_dclk) != 0) {
807276fc83aSjmcneill aprint_error(": couldn't enable clock %s\n", "dclk_vop");
808276fc83aSjmcneill return;
809276fc83aSjmcneill }
810276fc83aSjmcneill
811276fc83aSjmcneill sc->sc_dev = self;
812276fc83aSjmcneill sc->sc_bst = faa->faa_bst;
813276fc83aSjmcneill if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
814276fc83aSjmcneill aprint_error(": couldn't map registers\n");
815276fc83aSjmcneill return;
816276fc83aSjmcneill }
817276fc83aSjmcneill sc->sc_phandle = faa->faa_phandle;
8188e90f9edSthorpej sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data;
819276fc83aSjmcneill
820276fc83aSjmcneill aprint_naive("\n");
821276fc83aSjmcneill aprint_normal(": %s\n", sc->sc_conf->descr);
822276fc83aSjmcneill
823276fc83aSjmcneill if (sc->sc_conf->init != NULL)
824276fc83aSjmcneill sc->sc_conf->init(sc);
825276fc83aSjmcneill
826276fc83aSjmcneill sc->sc_ports.dp_ep_activate = rk_vop_ep_activate;
827276fc83aSjmcneill sc->sc_ports.dp_ep_get_data = rk_vop_ep_get_data;
82847dfb5c8Sjakllsch fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_CRTC);
829276fc83aSjmcneill
830276fc83aSjmcneill const int port_phandle = of_find_firstchild_byname(phandle, "port");
831276fc83aSjmcneill if (port_phandle > 0)
832276fc83aSjmcneill rk_drm_register_port(port_phandle, &sc->sc_ports);
833*59b77be9Sriastradh
834*59b77be9Sriastradh mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM);
835*59b77be9Sriastradh sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
836*59b77be9Sriastradh FDT_INTR_MPSAFE, &rk_vop_intr, sc, device_xname(self));
837*59b77be9Sriastradh if (sc->sc_ih == NULL) {
838*59b77be9Sriastradh aprint_error_dev(self, "failed to establish interrupt on %s\n",
839*59b77be9Sriastradh intrstr);
840*59b77be9Sriastradh return;
841*59b77be9Sriastradh }
842*59b77be9Sriastradh aprint_normal_dev(self, "interrupting on %s\n", intrstr);
843276fc83aSjmcneill }
844276fc83aSjmcneill
845276fc83aSjmcneill CFATTACH_DECL_NEW(rk_vop, sizeof(struct rk_vop_softc),
846276fc83aSjmcneill rk_vop_match, rk_vop_attach, NULL, NULL);
847