1*2e42c2b1Smsaitoh /* $NetBSD: i80312var.h,v 1.11 2012/10/14 14:20:57 msaitoh Exp $ */ 220b742fdSthorpej 349951f6dSthorpej /* 4dce44763Sthorpej * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 549951f6dSthorpej * All rights reserved. 649951f6dSthorpej * 749951f6dSthorpej * Written by Jason R. Thorpe for Wasabi Systems, Inc. 849951f6dSthorpej * 949951f6dSthorpej * Redistribution and use in source and binary forms, with or without 1049951f6dSthorpej * modification, are permitted provided that the following conditions 1149951f6dSthorpej * are met: 1249951f6dSthorpej * 1. Redistributions of source code must retain the above copyright 1349951f6dSthorpej * notice, this list of conditions and the following disclaimer. 1449951f6dSthorpej * 2. Redistributions in binary form must reproduce the above copyright 1549951f6dSthorpej * notice, this list of conditions and the following disclaimer in the 1649951f6dSthorpej * documentation and/or other materials provided with the distribution. 1749951f6dSthorpej * 3. All advertising materials mentioning features or use of this software 1849951f6dSthorpej * must display the following acknowledgement: 1949951f6dSthorpej * This product includes software developed for the NetBSD Project by 2049951f6dSthorpej * Wasabi Systems, Inc. 2149951f6dSthorpej * 4. The name of Wasabi Systems, Inc. may not be used to endorse 2249951f6dSthorpej * or promote products derived from this software without specific prior 2349951f6dSthorpej * written permission. 2449951f6dSthorpej * 2549951f6dSthorpej * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 2649951f6dSthorpej * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2749951f6dSthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2849951f6dSthorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 2949951f6dSthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 3049951f6dSthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3149951f6dSthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3249951f6dSthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3349951f6dSthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3449951f6dSthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3549951f6dSthorpej * POSSIBILITY OF SUCH DAMAGE. 3649951f6dSthorpej */ 3749951f6dSthorpej 3849951f6dSthorpej #ifndef _ARM_XSCALE_I80312VAR_H_ 3949951f6dSthorpej #define _ARM_XSCALE_I80312VAR_H_ 4049951f6dSthorpej 41af51edd2Sdyoung #include <sys/bus.h> 42660b98b7Sthorpej 43660b98b7Sthorpej #include <dev/pci/pcivar.h> 44660b98b7Sthorpej 45660b98b7Sthorpej struct i80312_softc { 46*2e42c2b1Smsaitoh device_t sc_dev; /* generic device glue */ 47660b98b7Sthorpej 48660b98b7Sthorpej int sc_is_host; /* indicates if we're a host or 49660b98b7Sthorpej plugged into another host */ 50660b98b7Sthorpej 51660b98b7Sthorpej /* 52660b98b7Sthorpej * This is the bus_space and handle used to access the 53660b98b7Sthorpej * i80312 itself. This is filled in by the board-specific 54660b98b7Sthorpej * front-end. 55660b98b7Sthorpej */ 56660b98b7Sthorpej bus_space_tag_t sc_st; 57660b98b7Sthorpej bus_space_handle_t sc_sh; 58660b98b7Sthorpej 59660b98b7Sthorpej /* Handles for the various subregions. */ 60660b98b7Sthorpej bus_space_handle_t sc_ppb_sh; 61660b98b7Sthorpej bus_space_handle_t sc_atu_sh; 62d1f4bf74Sthorpej bus_space_handle_t sc_mem_sh; 638ae5055eSthorpej bus_space_handle_t sc_intc_sh; 64660b98b7Sthorpej 65660b98b7Sthorpej /* 66660b98b7Sthorpej * Secondary IDSEL Select bits for providing a private 67660b98b7Sthorpej * PCI device space. 68660b98b7Sthorpej */ 69660b98b7Sthorpej uint16_t sc_sisr; 70660b98b7Sthorpej 71660b98b7Sthorpej /* 72660b98b7Sthorpej * We expect the board-specific front-end to have already mapped 73660b98b7Sthorpej * the PCI I/O spaces .. they're only 64K each, and I/O mappings 74660b98b7Sthorpej * tend to be smaller than a page size, so it's generally more 75660b98b7Sthorpej * efficient to map them all into virtual space in one fell swoop. 76660b98b7Sthorpej */ 77660b98b7Sthorpej vaddr_t sc_piow_vaddr; /* primary I/O window vaddr */ 78660b98b7Sthorpej vaddr_t sc_siow_vaddr; /* secondary I/O window vaddr */ 79660b98b7Sthorpej 80660b98b7Sthorpej /* 81660b98b7Sthorpej * Variables that define the Primary Inbound window. The base 82660b98b7Sthorpej * address is configured by a host via BAR #0. The xlate variable 83660b98b7Sthorpej * defines the start of the local address space that it maps to. 84660b98b7Sthorpej * The size variable defines the byte size. 85660b98b7Sthorpej * 86660b98b7Sthorpej * This window is used for incoming PCI memory read/write cycles 87660b98b7Sthorpej * from a host. 88660b98b7Sthorpej * 89660b98b7Sthorpej * ...unless we're a host, in which case we make the Primary 90660b98b7Sthorpej * Inbound window work like the Secondary Inbound window, so 91660b98b7Sthorpej * that PCI devices on that bus can talk to our local RAM. 92660b98b7Sthorpej */ 93660b98b7Sthorpej uint32_t sc_pin_base; 94660b98b7Sthorpej uint32_t sc_pin_xlate; 95660b98b7Sthorpej uint32_t sc_pin_size; 96660b98b7Sthorpej 97660b98b7Sthorpej /* 98660b98b7Sthorpej * Variables that define the Secondary Inbound window. The 99660b98b7Sthorpej * base variable indicates the PCI base address of the window. 100660b98b7Sthorpej * The xlate variable defines the start of the local address 101660b98b7Sthorpej * space that it maps to. The size variable defines the byte 102660b98b7Sthorpej * size. 103660b98b7Sthorpej * 104660b98b7Sthorpej * This window is used for DMA with devices on the secondary bus. 105660b98b7Sthorpej */ 106660b98b7Sthorpej uint32_t sc_sin_base; 107660b98b7Sthorpej uint32_t sc_sin_xlate; 108660b98b7Sthorpej uint32_t sc_sin_size; 109660b98b7Sthorpej 110660b98b7Sthorpej /* 111660b98b7Sthorpej * This is the PCI address that the Primary Outbound Memory 112660b98b7Sthorpej * window maps to. 113660b98b7Sthorpej */ 114660b98b7Sthorpej uint32_t sc_pmemout_base; 115660b98b7Sthorpej uint32_t sc_pmemout_size; 116660b98b7Sthorpej 117660b98b7Sthorpej /* 118660b98b7Sthorpej * This is the PCI address that the Primary Outbound I/O 119660b98b7Sthorpej * window maps to. 120660b98b7Sthorpej */ 121660b98b7Sthorpej uint32_t sc_pioout_base; 122660b98b7Sthorpej uint32_t sc_pioout_size; 123660b98b7Sthorpej 124660b98b7Sthorpej /* 125660b98b7Sthorpej * This is the PCI address that the Secondary Outbound Memory 126660b98b7Sthorpej * window maps to. 127660b98b7Sthorpej */ 128660b98b7Sthorpej uint32_t sc_smemout_base; 129660b98b7Sthorpej uint32_t sc_smemout_size; 130660b98b7Sthorpej 131660b98b7Sthorpej /* 132660b98b7Sthorpej * This is the PCI address that the Secondary Outbound I/O 133660b98b7Sthorpej * window maps to. 134660b98b7Sthorpej */ 135660b98b7Sthorpej uint32_t sc_sioout_base; 136660b98b7Sthorpej uint32_t sc_sioout_size; 137660b98b7Sthorpej 138660b98b7Sthorpej /* 139660b98b7Sthorpej * This defines the private I/O and Memory spaces on the 140660b98b7Sthorpej * Secondary bus. 141660b98b7Sthorpej */ 142660b98b7Sthorpej uint32_t sc_privio_base; 143660b98b7Sthorpej uint32_t sc_privio_size; 144660b98b7Sthorpej uint32_t sc_privmem_base; 145660b98b7Sthorpej uint32_t sc_privmem_size; 146660b98b7Sthorpej 147660b98b7Sthorpej uint8_t sc_sder; /* secondary decode enable register */ 148660b98b7Sthorpej 149660b98b7Sthorpej /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */ 150660b98b7Sthorpej struct bus_space sc_pci_iot; 151660b98b7Sthorpej struct bus_space sc_pci_memt; 152660b98b7Sthorpej struct arm32_bus_dma_tag sc_pci_dmat; 153660b98b7Sthorpej struct arm32_pci_chipset sc_pci_chipset; 1548ae5055eSthorpej 155dce44763Sthorpej /* DMA window info for PCI DMA. */ 156dce44763Sthorpej struct arm32_dma_range sc_pci_dma_range; 157dce44763Sthorpej 1588ae5055eSthorpej /* GPIO state */ 1598ae5055eSthorpej uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */ 1608ae5055eSthorpej uint8_t sc_gpio_val; /* GPIO output pin value */ 161d322684fSthorpej 162d322684fSthorpej /* DMA tag for local devices. */ 163d322684fSthorpej struct arm32_bus_dma_tag sc_local_dmat; 164d322684fSthorpej }; 165d322684fSthorpej 166d322684fSthorpej /* 167d322684fSthorpej * Arguments used to attach IOP built-ins. 168d322684fSthorpej */ 169d322684fSthorpej struct iopxs_attach_args { 170d322684fSthorpej const char *ia_name; /* name of device */ 171d322684fSthorpej bus_space_tag_t ia_st; /* space tag */ 172d322684fSthorpej bus_space_handle_t ia_sh;/* handle of IOP base */ 173d322684fSthorpej bus_dma_tag_t ia_dmat; /* DMA tag */ 174d322684fSthorpej bus_addr_t ia_offset; /* offset of device from IOP base */ 175d322684fSthorpej bus_size_t ia_size; /* size of sub-device */ 176660b98b7Sthorpej }; 177660b98b7Sthorpej 178660b98b7Sthorpej extern struct bus_space i80312_bs_tag; 1798ae5055eSthorpej extern struct i80312_softc *i80312_softc; 180660b98b7Sthorpej 18149951f6dSthorpej void i80312_sdram_bounds(bus_space_tag_t, bus_space_handle_t, 18249951f6dSthorpej paddr_t *, psize_t *); 18349951f6dSthorpej 184660b98b7Sthorpej void i80312_attach(struct i80312_softc *); 185660b98b7Sthorpej 186660b98b7Sthorpej void i80312_bs_init(bus_space_tag_t, void *); 187660b98b7Sthorpej void i80312_io_bs_init(bus_space_tag_t, void *); 188660b98b7Sthorpej void i80312_mem_bs_init(bus_space_tag_t, void *); 189660b98b7Sthorpej 1908ae5055eSthorpej void i80312_gpio_set_direction(uint8_t, uint8_t); 1918ae5055eSthorpej void i80312_gpio_set_val(uint8_t, uint8_t); 1928ae5055eSthorpej uint8_t i80312_gpio_get_val(void); 1938ae5055eSthorpej 194660b98b7Sthorpej void i80312_pci_init(pci_chipset_tag_t, void *); 195660b98b7Sthorpej 19649951f6dSthorpej #endif /* _ARM_XSCALE_I80312VAR_H_ */ 197