1*33109dc9Sthorpej /* $NetBSD: ixp425reg.h,v 1.23 2020/02/12 05:44:26 thorpej Exp $ */ 200eb02e3Sichiro /* 300eb02e3Sichiro * Copyright (c) 2003 400eb02e3Sichiro * Ichiro FUKUHARA <ichiro@ichiro.org>. 500eb02e3Sichiro * All rights reserved. 600eb02e3Sichiro * 700eb02e3Sichiro * Redistribution and use in source and binary forms, with or without 800eb02e3Sichiro * modification, are permitted provided that the following conditions 900eb02e3Sichiro * are met: 1000eb02e3Sichiro * 1. Redistributions of source code must retain the above copyright 1100eb02e3Sichiro * notice, this list of conditions and the following disclaimer. 1200eb02e3Sichiro * 2. Redistributions in binary form must reproduce the above copyright 1300eb02e3Sichiro * notice, this list of conditions and the following disclaimer in the 1400eb02e3Sichiro * documentation and/or other materials provided with the distribution. 1500eb02e3Sichiro * 1600eb02e3Sichiro * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 1700eb02e3Sichiro * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1800eb02e3Sichiro * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1900eb02e3Sichiro * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 2000eb02e3Sichiro * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2100eb02e3Sichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2200eb02e3Sichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2300eb02e3Sichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2400eb02e3Sichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2500eb02e3Sichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2600eb02e3Sichiro * SUCH DAMAGE. 2700eb02e3Sichiro */ 2800eb02e3Sichiro 2900eb02e3Sichiro #ifndef _IXP425REG_H_ 3000eb02e3Sichiro #define _IXP425REG_H_ 3100eb02e3Sichiro 3200eb02e3Sichiro /* 3300eb02e3Sichiro * Physical memory map for the Intel IXP425 3400eb02e3Sichiro */ 3500eb02e3Sichiro /* 3600eb02e3Sichiro * CC00 00FF --------------------------- 3700eb02e3Sichiro * SDRAM Configuration Registers 3800eb02e3Sichiro * CC00 0000 --------------------------- 3900eb02e3Sichiro * 4000eb02e3Sichiro * C800 BFFF --------------------------- 4100eb02e3Sichiro * System and Peripheral Registers 4200eb02e3Sichiro * C800 0000 --------------------------- 4300eb02e3Sichiro * Expansion Bus Configuration Registers 4400eb02e3Sichiro * C400 0000 --------------------------- 4500eb02e3Sichiro * PCI Configuration and Status Registers 4600eb02e3Sichiro * C000 0000 --------------------------- 4700eb02e3Sichiro * 4800eb02e3Sichiro * 6400 0000 --------------------------- 4900eb02e3Sichiro * Queue manager 5000eb02e3Sichiro * 6000 0000 --------------------------- 5100eb02e3Sichiro * Expansion Bus Data 5200eb02e3Sichiro * 5000 0000 --------------------------- 5300eb02e3Sichiro * PCI Data 5400eb02e3Sichiro * 4800 0000 --------------------------- 5500eb02e3Sichiro * 5600eb02e3Sichiro * 4000 0000 --------------------------- 57*33109dc9Sthorpej * SDRAM (alias) 58*33109dc9Sthorpej * 3000 0000 --------------------------- 59*33109dc9Sthorpej * SDRAM (alias) 60*33109dc9Sthorpej * 2000 0000 --------------------------- 61*33109dc9Sthorpej * SDRAM (alias) 6200eb02e3Sichiro * 1000 0000 --------------------------- 63*33109dc9Sthorpej * SDRAM 64*33109dc9Sthorpej * 0000 0000 --------------------------- 6500eb02e3Sichiro */ 6600eb02e3Sichiro 6700eb02e3Sichiro /* 6800eb02e3Sichiro * Virtual memory map for the Intel IXP425 integrated devices 6900eb02e3Sichiro */ 7000eb02e3Sichiro /* 7100eb02e3Sichiro * FFFF FFFF --------------------------- 7200eb02e3Sichiro * 73c2415a0dSscw * FC00 0000 --------------------------- 74c2415a0dSscw * PCI Data (memory space) 75c2415a0dSscw * F800 0000 --------------------------- 76c2415a0dSscw * 772107fae8Sscw * F020 1000 --------------------------- 78c2415a0dSscw * SDRAM Controller 792107fae8Sscw * F020 0000 --------------------------- 802107fae8Sscw * 8100eb02e3Sichiro * F001 2000 --------------------------- 8200eb02e3Sichiro * PCI Configuration and Status Registers 8300eb02e3Sichiro * F001 1000 --------------------------- 8400eb02e3Sichiro * Expansion bus Configuration Registers 8500eb02e3Sichiro * F001 0000 --------------------------- 8600eb02e3Sichiro * System and Peripheral Registers 8700eb02e3Sichiro * VA F000 0000 = PA C800 0000 (SIZE 0x10000) 8800eb02e3Sichiro * F000 0000 --------------------------- 8900eb02e3Sichiro * 9000eb02e3Sichiro * 0000 0000 --------------------------- 9100eb02e3Sichiro * 9200eb02e3Sichiro */ 9300eb02e3Sichiro 9400eb02e3Sichiro /* Physical/Virtual address for I/O space */ 9500eb02e3Sichiro 9600eb02e3Sichiro #define IXP425_IO_VBASE 0xf0000000UL 9700eb02e3Sichiro #define IXP425_IO_HWBASE 0xc8000000UL 9800eb02e3Sichiro #define IXP425_IO_SIZE 0x00010000UL 9900eb02e3Sichiro 10000eb02e3Sichiro /* Offset */ 10100eb02e3Sichiro 10200eb02e3Sichiro #define IXP425_UART0_OFFSET 0x00000000UL 10300eb02e3Sichiro #define IXP425_UART1_OFFSET 0x00001000UL 10400eb02e3Sichiro #define IXP425_PMC_OFFSET 0x00002000UL 10500eb02e3Sichiro #define IXP425_INTR_OFFSET 0x00003000UL 10600eb02e3Sichiro #define IXP425_GPIO_OFFSET 0x00004000UL 10700eb02e3Sichiro #define IXP425_TIMER_OFFSET 0x00005000UL 108bdea1361Sscw #define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */ 109bdea1361Sscw #define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */ 110bdea1361Sscw #define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */ 11100eb02e3Sichiro #define IXP425_MAC_A_OFFSET 0x00009000UL 11200eb02e3Sichiro #define IXP425_MAC_B_OFFSET 0x0000a000UL 11300eb02e3Sichiro #define IXP425_USB_OFFSET 0x0000b000UL 11400eb02e3Sichiro 11500eb02e3Sichiro #define IXP425_REG_SIZE 0x1000 11600eb02e3Sichiro 11700eb02e3Sichiro /* 11800eb02e3Sichiro * UART 11900eb02e3Sichiro * UART0 0xc8000000 12000eb02e3Sichiro * UART1 0xc8001000 12100eb02e3Sichiro * 12200eb02e3Sichiro */ 12300eb02e3Sichiro /* I/O space */ 12400eb02e3Sichiro #define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) 12500eb02e3Sichiro #define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) 12600eb02e3Sichiro 12700eb02e3Sichiro #define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) 128745355a8Sichiro /* 0xf0000000 */ 12900eb02e3Sichiro #define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) 130745355a8Sichiro /* 0xf0001000 */ 13100eb02e3Sichiro 132fb2c5211Sscw #define IXP425_UART_FREQ 14745600 13300eb02e3Sichiro 134fb2c5211Sscw /*#define IXP4XX_COM_NPORTS 8*/ 13500eb02e3Sichiro 13600eb02e3Sichiro /* 13700eb02e3Sichiro * Timers 13800eb02e3Sichiro * 13900eb02e3Sichiro */ 140fb2c5211Sscw #define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET) 1415801c731Sscw #define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET) 14200eb02e3Sichiro 1435801c731Sscw #define IXP425_OST_TS 0x0000 14400eb02e3Sichiro #define IXP425_OST_TIM0 0x0004 14500eb02e3Sichiro #define IXP425_OST_TIM1 0x000C 14600eb02e3Sichiro 14700eb02e3Sichiro #define IXP425_OST_TIM0_RELOAD 0x0008 14800eb02e3Sichiro #define IXP425_OST_TIM1_RELOAD 0x0010 14900eb02e3Sichiro #define TIMERRELOAD_MASK 0xFFFFFFFC 15000eb02e3Sichiro #define OST_ONESHOT_EN (1U << 1) 15100eb02e3Sichiro #define OST_TIMER_EN (1U << 0) 15200eb02e3Sichiro 15300eb02e3Sichiro #define IXP425_OST_STATUS 0x0020 15400eb02e3Sichiro #define OST_WARM_RESET (1U << 4) 15500eb02e3Sichiro #define OST_WDOG_INT (1U << 3) 15600eb02e3Sichiro #define OST_TS_INT (1U << 2) 15700eb02e3Sichiro #define OST_TIM1_INT (1U << 1) 15800eb02e3Sichiro #define OST_TIM0_INT (1U << 0) 15900eb02e3Sichiro 160bdea1361Sscw #define IXP425_OST_WDOG_HWBASE (IXP425_TIMER_HWBASE + 0x14) 161bdea1361Sscw #define IXP425_OST_WDOG_VBASE (IXP425_TIMER_VBASE + 0x14) 162bdea1361Sscw #define IXP425_OST_WDOG_SIZE 0x0c 163bdea1361Sscw #define IXP425_OST_WDOG 0x0000 164bdea1361Sscw #define IXP425_OST_WDOG_ENAB 0x0004 165bdea1361Sscw #define IXP425_OST_WDOG_KEY 0x0008 1660df10200Sscw #define OST_WDOG_KEY_MAJICK 0x482e 1670df10200Sscw #define OST_WDOG_ENAB_RST_ENA (1u << 0) 1680df10200Sscw #define OST_WDOG_ENAB_INT_ENA (1u << 1) 1690df10200Sscw #define OST_WDOG_ENAB_CNT_ENA (1u << 2) 1700df10200Sscw 17100eb02e3Sichiro /* 17200eb02e3Sichiro * Interrupt Controller Unit. 173745355a8Sichiro * PA 0xc8003000 17400eb02e3Sichiro */ 17500eb02e3Sichiro 17600eb02e3Sichiro #define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET 17700eb02e3Sichiro #define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET 178745355a8Sichiro /* 0xf0003000 */ 17900eb02e3Sichiro #define IXP425_IRQ_SIZE 0x00000020UL 18000eb02e3Sichiro 18100eb02e3Sichiro #define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) 18200eb02e3Sichiro #define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) 18300eb02e3Sichiro #define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) 18400eb02e3Sichiro #define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) 18500eb02e3Sichiro #define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) 18600eb02e3Sichiro #define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) 18700eb02e3Sichiro #define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) 18800eb02e3Sichiro #define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) 18900eb02e3Sichiro 19000eb02e3Sichiro #define IXP425_INT_SW1 31 /* SW Interrupt 1 */ 19100eb02e3Sichiro #define IXP425_INT_SW0 30 /* SW Interrupt 0 */ 19200eb02e3Sichiro #define IXP425_INT_GPIO_12 29 /* GPIO 12 */ 19300eb02e3Sichiro #define IXP425_INT_GPIO_11 28 /* GPIO 11 */ 19400eb02e3Sichiro #define IXP425_INT_GPIO_10 27 /* GPIO 11 */ 19500eb02e3Sichiro #define IXP425_INT_GPIO_9 26 /* GPIO 9 */ 19600eb02e3Sichiro #define IXP425_INT_GPIO_8 25 /* GPIO 8 */ 19700eb02e3Sichiro #define IXP425_INT_GPIO_7 24 /* GPIO 7 */ 19800eb02e3Sichiro #define IXP425_INT_GPIO_6 23 /* GPIO 6 */ 19900eb02e3Sichiro #define IXP425_INT_GPIO_5 22 /* GPIO 5 */ 20000eb02e3Sichiro #define IXP425_INT_GPIO_4 21 /* GPIO 4 */ 20100eb02e3Sichiro #define IXP425_INT_GPIO_3 20 /* GPIO 3 */ 20200eb02e3Sichiro #define IXP425_INT_GPIO_2 19 /* GPIO 2 */ 203bedffd53Sichiro #define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */ 204bedffd53Sichiro #define IXP425_INT_AHB_PMU 17 /* AHB PMU */ 20500eb02e3Sichiro #define IXP425_INT_WDOG 16 /* Watchdog Timer */ 206bedffd53Sichiro #define IXP425_INT_UART0 15 /* HighSpeed UART */ 20700eb02e3Sichiro #define IXP425_INT_STAMP 14 /* Timestamp Timer */ 208bedffd53Sichiro #define IXP425_INT_UART1 13 /* Console UART */ 20900eb02e3Sichiro #define IXP425_INT_USB 12 /* USB */ 21000eb02e3Sichiro #define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ 21100eb02e3Sichiro #define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ 21200eb02e3Sichiro #define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ 21300eb02e3Sichiro #define IXP425_INT_PCIINT 8 /* PCI Interrupt */ 21400eb02e3Sichiro #define IXP425_INT_GPIO_1 7 /* GPIO 1 */ 21500eb02e3Sichiro #define IXP425_INT_GPIO_0 6 /* GPIO 0 */ 21600eb02e3Sichiro #define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ 21700eb02e3Sichiro #define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ 21800eb02e3Sichiro #define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ 219bdea1361Sscw #define IXP425_INT_NPE_C 2 /* Ethernet NPE C */ 220bdea1361Sscw #define IXP425_INT_NPE_B 1 /* Ethernet NPE B */ 221bdea1361Sscw #define IXP425_INT_NPE_A 0 /* NPE A */ 22200eb02e3Sichiro 22300eb02e3Sichiro /* 22400eb02e3Sichiro * software interrupt 22500eb02e3Sichiro */ 22600eb02e3Sichiro #define IXP425_INT_bit31 31 22700eb02e3Sichiro #define IXP425_INT_bit30 30 228a402937cSscw #define IXP425_INT_bit14 14 229a402937cSscw #define IXP425_INT_bit11 11 23000eb02e3Sichiro 23100eb02e3Sichiro #define IXP425_INT_HWMASK (0xffffffff & \ 23200eb02e3Sichiro ~((1 << IXP425_INT_bit31) | \ 23300eb02e3Sichiro (1 << IXP425_INT_bit30) | \ 234a402937cSscw (1 << IXP425_INT_bit14) | \ 235a402937cSscw (1 << IXP425_INT_bit11))) 236fb2c5211Sscw #define IXP425_INT_GPIOMASK (0x3ff800c0u) 23700eb02e3Sichiro 23800eb02e3Sichiro /* 239663ccee1Sichiro * GPIO 240663ccee1Sichiro */ 241663ccee1Sichiro #define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET 242663ccee1Sichiro #define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET 243663ccee1Sichiro /* 0xf0004000 */ 244663ccee1Sichiro #define IXP425_GPIO_SIZE 0x00000020UL 245663ccee1Sichiro 246663ccee1Sichiro #define IXP425_GPIO_GPOUTR 0x00 247663ccee1Sichiro #define IXP425_GPIO_GPOER 0x04 248663ccee1Sichiro #define IXP425_GPIO_GPINR 0x08 249663ccee1Sichiro #define IXP425_GPIO_GPISR 0x0c 250663ccee1Sichiro #define IXP425_GPIO_GPIT1R 0x10 251663ccee1Sichiro #define IXP425_GPIO_GPIT2R 0x14 252663ccee1Sichiro #define IXP425_GPIO_GPCLKR 0x18 253663ccee1Sichiro # define GPCLKR_MUX14 (1U << 8) 254663ccee1Sichiro # define GPCLKR_CLK0TC_SHIFT 4 255663ccee1Sichiro # define GPCLKR_CLK0DC_SHIFT 0 256663ccee1Sichiro 257663ccee1Sichiro /* GPIO Output */ 258663ccee1Sichiro #define GPOUT_ON 0x1 259663ccee1Sichiro #define GPOUT_OFF 0x0 260663ccee1Sichiro 261663ccee1Sichiro /* GPIO direction */ 262663ccee1Sichiro #define GPOER_INPUT 0x1 263663ccee1Sichiro #define GPOER_OUTPUT 0x0 264663ccee1Sichiro 265fb2c5211Sscw /* GPIO Type bits */ 266fb2c5211Sscw #define GPIO_TYPE_ACT_HIGH 0x0 267fb2c5211Sscw #define GPIO_TYPE_ACT_LOW 0x1 268fb2c5211Sscw #define GPIO_TYPE_EDG_RISING 0x2 269fb2c5211Sscw #define GPIO_TYPE_EDG_FALLING 0x3 270fb2c5211Sscw #define GPIO_TYPE_TRANSITIONAL 0x4 271fb2c5211Sscw #define GPIO_TYPE_MASK 0x7 272fb2c5211Sscw #define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3)) 273fb2c5211Sscw #define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R) 274fb2c5211Sscw 275663ccee1Sichiro /* 27600eb02e3Sichiro * Expansion Bus 27700eb02e3Sichiro */ 27800eb02e3Sichiro #define IXP425_EXP_HWBASE 0xc4000000UL 27900eb02e3Sichiro #define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE) 280745355a8Sichiro /* 0xf0010000 */ 281745355a8Sichiro #define IXP425_EXP_SIZE IXP425_REG_SIZE /* 0x1000 */ 28200eb02e3Sichiro 28300eb02e3Sichiro /* offset */ 28400eb02e3Sichiro #define EXP_TIMING_CS0_OFFSET 0x0000 28500eb02e3Sichiro #define EXP_TIMING_CS1_OFFSET 0x0004 28600eb02e3Sichiro #define EXP_TIMING_CS2_OFFSET 0x0008 28700eb02e3Sichiro #define EXP_TIMING_CS3_OFFSET 0x000c 28800eb02e3Sichiro #define EXP_TIMING_CS4_OFFSET 0x0010 28900eb02e3Sichiro #define EXP_TIMING_CS5_OFFSET 0x0014 29000eb02e3Sichiro #define EXP_TIMING_CS6_OFFSET 0x0018 29100eb02e3Sichiro #define EXP_TIMING_CS7_OFFSET 0x001c 2920df10200Sscw #define EXP_CNFG0_OFFSET 0x0020 2930df10200Sscw #define EXP_CNFG1_OFFSET 0x0024 294bdea1361Sscw #define EXP_FCTRL_OFFSET 0x0028 29500eb02e3Sichiro 29600eb02e3Sichiro #define IXP425_EXP_RECOVERY_SHIFT 16 29700eb02e3Sichiro #define IXP425_EXP_HOLD_SHIFT 20 29800eb02e3Sichiro #define IXP425_EXP_STROBE_SHIFT 22 29900eb02e3Sichiro #define IXP425_EXP_SETUP_SHIFT 26 30000eb02e3Sichiro #define IXP425_EXP_ADDR_SHIFT 28 30100eb02e3Sichiro #define IXP425_EXP_CS_EN (1U << 31) 30200eb02e3Sichiro 30300eb02e3Sichiro #define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) 30400eb02e3Sichiro #define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) 30500eb02e3Sichiro #define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) 30600eb02e3Sichiro #define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 3070c9cb92aSichiro #define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) 30800eb02e3Sichiro 30900eb02e3Sichiro // EXP_CSn bits 31000eb02e3Sichiro #define EXP_BYTE_EN (1 << 0) 31100eb02e3Sichiro #define EXP_WR_EN (1 << 1) 31200eb02e3Sichiro #define EXP_SPLT_EN (1 << 3) 31300eb02e3Sichiro #define EXP_MUX_EN (1 << 4) 31400eb02e3Sichiro #define EXP_HRDY_POL (1 << 5) 31500eb02e3Sichiro #define EXP_BYTE_RD16 (1 << 6) 31600eb02e3Sichiro #define EXP_SZ_512 (0 << 10) 31700eb02e3Sichiro #define EXP_SZ_1K (1 << 10) 31800eb02e3Sichiro #define EXP_SZ_2K (2 << 10) 31900eb02e3Sichiro #define EXP_SZ_4K (3 << 10) 32000eb02e3Sichiro #define EXP_SZ_8K (4 << 10) 32100eb02e3Sichiro #define EXP_SZ_16K (5 << 10) 32200eb02e3Sichiro #define EXP_SZ_32K (6 << 10) 32300eb02e3Sichiro #define EXP_SZ_64K (7 << 10) 32400eb02e3Sichiro #define EXP_SZ_128K (8 << 10) 32500eb02e3Sichiro #define EXP_SZ_256K (9 << 10) 32600eb02e3Sichiro #define EXP_SZ_512K (10 << 10) 32700eb02e3Sichiro #define EXP_SZ_1M (11 << 10) 32800eb02e3Sichiro #define EXP_SZ_2M (12 << 10) 32900eb02e3Sichiro #define EXP_SZ_4M (13 << 10) 33000eb02e3Sichiro #define EXP_SZ_8M (14 << 10) 33100eb02e3Sichiro #define EXP_SZ_16M (15 << 10) 33200eb02e3Sichiro #define EXP_CYC_INTEL (0 << 14) 33300eb02e3Sichiro #define EXP_CYC_MOTO (1 << 14) 33400eb02e3Sichiro #define EXP_CYC_HPI (2 << 14) 33500eb02e3Sichiro 33600eb02e3Sichiro // EXP_CNFG0 bits 33700eb02e3Sichiro #define EXP_CNFG0_8BIT (1 << 0) 33800eb02e3Sichiro #define EXP_CNFG0_PCI_HOST (1 << 1) 33900eb02e3Sichiro #define EXP_CNFG0_PCI_ARB (1 << 2) 34000eb02e3Sichiro #define EXP_CNFG0_PCI_66MHZ (1 << 4) 34100eb02e3Sichiro #define EXP_CNFG0_MEM_MAP (1 << 31) 34200eb02e3Sichiro 34300eb02e3Sichiro // EXP_CNFG1 bits 34400eb02e3Sichiro #define EXP_CNFG1_SW_INT0 (1 << 0) 34500eb02e3Sichiro #define EXP_CNFG1_SW_INT1 (1 << 1) 34600eb02e3Sichiro 34700eb02e3Sichiro /* 34800eb02e3Sichiro * PCI 34900eb02e3Sichiro */ 35000eb02e3Sichiro #define IXP425_PCI_HWBASE 0xc0000000 35100eb02e3Sichiro #define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE) 352745355a8Sichiro /* 0xf0011000 */ 35300eb02e3Sichiro #define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */ 35400eb02e3Sichiro 35546192ffbSichiro /* 356745355a8Sichiro * Mapping registers of IXP425 PCI Configuration 357745355a8Sichiro */ 358745355a8Sichiro /* PCI_ID_REG 0x00 */ 359745355a8Sichiro /* PCI_COMMAND_STATUS_REG 0x04 */ 360745355a8Sichiro /* PCI_CLASS_REG 0x08 */ 361745355a8Sichiro /* PCI_BHLC_REG 0x0c */ 362745355a8Sichiro #define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */ 363745355a8Sichiro #define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */ 364745355a8Sichiro #define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */ 365745355a8Sichiro #define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */ 366745355a8Sichiro #define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */ 367745355a8Sichiro #define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */ 368745355a8Sichiro /* PCI_SUBSYS_ID_REG 0x2c */ 369745355a8Sichiro /* PCI_INTERRUPT_REG 0x3c */ 370745355a8Sichiro #define PCI_RTOTTO 0x40 371745355a8Sichiro 372663ccee1Sichiro /* PCI Controller CSR Base Address */ 373663ccee1Sichiro #define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE 374663ccee1Sichiro 375663ccee1Sichiro /* PCI Memory Space */ 376c2415a0dSscw #define IXP425_PCI_MEM_HWBASE 0x48000000UL 377c2415a0dSscw #define IXP425_PCI_MEM_VBASE 0xf8000000UL 378663ccee1Sichiro #define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */ 379663ccee1Sichiro 380663ccee1Sichiro /* PCI I/O Space */ 381fb2c5211Sscw #define IXP425_PCI_IO_HWBASE 0x00000000UL 382663ccee1Sichiro #define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 383663ccee1Sichiro 384745355a8Sichiro /* PCI Controller Configuration Offset */ 385745355a8Sichiro #define PCI_NP_AD 0x00 386745355a8Sichiro #define PCI_NP_CBE 0x04 387663ccee1Sichiro # define NP_CBE_SHIFT 4 388745355a8Sichiro #define PCI_NP_WDATA 0x08 389745355a8Sichiro #define PCI_NP_RDATA 0x0c 390745355a8Sichiro #define PCI_CRP_AD_CBE 0x10 391745355a8Sichiro #define PCI_CRP_AD_WDATA 0x14 392745355a8Sichiro #define PCI_CRP_AD_RDATA 0x18 393745355a8Sichiro #define PCI_CSR 0x1c 394663ccee1Sichiro # define CSR_PRST (1U << 16) 395663ccee1Sichiro # define CSR_IC (1U << 15) 396663ccee1Sichiro # define CSR_ABE (1U << 4) 397663ccee1Sichiro # define CSR_PDS (1U << 3) 398663ccee1Sichiro # define CSR_ADS (1U << 2) 399fb2c5211Sscw # define CSR_HOST (1U << 0) 400745355a8Sichiro #define PCI_ISR 0x20 401663ccee1Sichiro # define ISR_AHBE (1U << 3) 402663ccee1Sichiro # define ISR_PPE (1U << 2) 403663ccee1Sichiro # define ISR_PFE (1U << 1) 404663ccee1Sichiro # define ISR_PSE (1U << 0) 405745355a8Sichiro #define PCI_INTEN 0x24 406745355a8Sichiro #define PCI_DMACTRL 0x28 407745355a8Sichiro #define PCI_AHBMEMBASE 0x2c 408745355a8Sichiro #define PCI_AHBIOBASE 0x30 409745355a8Sichiro #define PCI_PCIMEMBASE 0x34 410745355a8Sichiro #define PCI_AHBDOORBELL 0x38 411745355a8Sichiro #define PCI_PCIDOORBELL 0x3c 412745355a8Sichiro #define PCI_ATPDMA0_AHBADDR 0x40 413745355a8Sichiro #define PCI_ATPDMA0_PCIADDR 0x44 414745355a8Sichiro #define PCI_ATPDMA0_LENGTH 0x48 415745355a8Sichiro #define PCI_ATPDMA1_AHBADDR 0x4c 416745355a8Sichiro #define PCI_ATPDMA1_PCIADDR 0x50 417745355a8Sichiro #define PCI_ATPDMA1_LENGTH 0x54 418745355a8Sichiro #define PCI_PTADMA0_AHBADDR 0x58 419745355a8Sichiro #define PCI_PTADMA0_PCIADDR 0x5c 420745355a8Sichiro #define PCI_PTADMA0_LENGTH 0x60 421745355a8Sichiro #define PCI_PTADMA1_AHBADDR 0x64 422745355a8Sichiro #define PCI_PTADMA1_PCIADDR 0x68 423745355a8Sichiro #define PCI_PTADMA1_LENGTH 0x6c 424745355a8Sichiro 425663ccee1Sichiro /* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */ 426663ccee1Sichiro #define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/ 427663ccee1Sichiro #define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/ 428663ccee1Sichiro #define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */ 429663ccee1Sichiro #define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */ 430663ccee1Sichiro #define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */ 431663ccee1Sichiro #define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */ 432663ccee1Sichiro #define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */ 433663ccee1Sichiro #define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */ 434745355a8Sichiro 435fb2c5211Sscw /* PCI byte enables */ 436fb2c5211Sscw #define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0) 437fb2c5211Sscw #define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0) 438fb2c5211Sscw #define BE_32BIT(a) 0x00 439fb2c5211Sscw 440fb2c5211Sscw /* PCI byte selects */ 441c4425234Sskrll #define READ_8BIT(v,a) ((uint8_t)((v) >> (((a) & 3) * 8))) 442c4425234Sskrll #define READ_16BIT(v,a) ((uint16_t)((v) >> (((a) & 2) * 8))) 443c4425234Sskrll #define WRITE_8BIT(v,a) (((uint32_t)(v)) << (((a) & 3) * 8)) 444c4425234Sskrll #define WRITE_16BIT(v,a) (((uint32_t)(v)) << (((a) & 2) * 8)) 445fb2c5211Sscw 446663ccee1Sichiro /* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */ 447fb2c5211Sscw #define COMMAND_CRP_READ 0x00 448663ccee1Sichiro #define COMMAND_CRP_WRITE (1U << 16) 449fb2c5211Sscw 450745355a8Sichiro /* 451c2cac1cbSichiro * SDRAM Configuration Register 452c2cac1cbSichiro */ 453c2cac1cbSichiro #define IXP425_MCU_HWBASE 0xcc000000UL 4542107fae8Sscw #define IXP425_MCU_VBASE 0xf0200000UL 45540db825eSscw #define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */ 456c2cac1cbSichiro #define MCU_SDR_CONFIG 0x00 45740db825eSscw #define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7) 45840db825eSscw #define MCU_SDR_CONFIG_64MBIT (1u << 5) 459c2cac1cbSichiro #define MCU_SDR_REFRESH 0x04 460c2cac1cbSichiro #define MCU_SDR_IR 0x08 461c2cac1cbSichiro 462c2cac1cbSichiro /* 46346192ffbSichiro * Performance Monitoring Unit (CP14) 46446192ffbSichiro * 46546192ffbSichiro * CP14.0.1 Performance Monitor Control Register(PMNC) 46646192ffbSichiro * CP14.1.1 Clock Counter(CCNT) 46746192ffbSichiro * CP14.4.1 Interrupt Enable Register(INTEN) 46846192ffbSichiro * CP14.5.1 Overflow Flag Register(FLAG) 46946192ffbSichiro * CP14.8.1 Event Selection Register(EVTSEL) 47046192ffbSichiro * CP14.0.2 Performance Counter Register 0(PMN0) 47146192ffbSichiro * CP14.1.2 Performance Counter Register 0(PMN1) 47246192ffbSichiro * CP14.2.2 Performance Counter Register 0(PMN2) 47346192ffbSichiro * CP14.3.2 Performance Counter Register 0(PMN3) 47446192ffbSichiro */ 47546192ffbSichiro 47646192ffbSichiro #define PMNC_E 0x00000001 /* enable all counters */ 47746192ffbSichiro #define PMNC_P 0x00000002 /* reset all PMNs to 0 */ 47846192ffbSichiro #define PMNC_C 0x00000004 /* clock counter reset */ 47946192ffbSichiro #define PMNC_D 0x00000008 /* clock counter / 64 */ 48046192ffbSichiro 48146192ffbSichiro #define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ 48246192ffbSichiro #define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ 48346192ffbSichiro #define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ 48446192ffbSichiro #define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ 48546192ffbSichiro #define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ 48646192ffbSichiro 48746192ffbSichiro #define FLAG_CC_IF 0x00000001 /* clock counter overflow */ 48846192ffbSichiro #define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ 48946192ffbSichiro #define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ 49046192ffbSichiro #define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ 49146192ffbSichiro #define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ 49246192ffbSichiro 49346192ffbSichiro #define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ 49446192ffbSichiro #define PMNC_EVCNT0_SHIFT 0 49546192ffbSichiro #define PMNC_EVCNT1_SHIFT 8 49646192ffbSichiro #define PMNC_EVCNT2_SHIFT 16 49746192ffbSichiro #define PMNC_EVCNT3_SHIFT 24 49846192ffbSichiro 499bdea1361Sscw 500bdea1361Sscw /* 501bdea1361Sscw * Queue Manager 502bdea1361Sscw */ 503bdea1361Sscw #define IXP425_QMGR_HWBASE 0x60000000UL 504bdea1361Sscw #define IXP425_QMGR_VBASE (IXP425_PCI_VBASE + IXP425_PCI_SIZE) 505bdea1361Sscw #define IXP425_QMGR_SIZE 0x4000 506bdea1361Sscw 507bdea1361Sscw /* 508bdea1361Sscw * Network Processing Engines (NPE's) and associated Ethernet MAC's. 509bdea1361Sscw */ 510bdea1361Sscw #define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET) 511bdea1361Sscw #define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET) 512bdea1361Sscw #define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */ 513bdea1361Sscw 514bdea1361Sscw #define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET) 515bdea1361Sscw #define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET) 516bdea1361Sscw #define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */ 517bdea1361Sscw 518bdea1361Sscw #define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET) 519bdea1361Sscw #define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET) 520bdea1361Sscw #define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */ 521bdea1361Sscw 522bdea1361Sscw #define IXP425_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_A_OFFSET) 523bdea1361Sscw #define IXP425_MAC_A_VBASE (IXP425_IO_VBASE + IXP425_MAC_A_OFFSET) 524bdea1361Sscw #define IXP425_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */ 525bdea1361Sscw 526bdea1361Sscw #define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET) 527bdea1361Sscw #define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET) 528bdea1361Sscw #define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */ 529bdea1361Sscw 53000eb02e3Sichiro #endif /* _IXP425REG_H_ */ 531