xref: /netbsd/sys/arch/bebox/pci/pci_machdep.c (revision c0f06f05)
1*c0f06f05Snonaka /*	$NetBSD: pci_machdep.c,v 1.22 2016/10/19 00:08:41 nonaka Exp $	*/
2fe3d055dSsakamoto 
3fe3d055dSsakamoto /*
4fe3d055dSsakamoto  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
56d3d8a13Smycroft  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
6fe3d055dSsakamoto  *
7fe3d055dSsakamoto  * Redistribution and use in source and binary forms, with or without
8fe3d055dSsakamoto  * modification, are permitted provided that the following conditions
9fe3d055dSsakamoto  * are met:
10fe3d055dSsakamoto  * 1. Redistributions of source code must retain the above copyright
11fe3d055dSsakamoto  *    notice, this list of conditions and the following disclaimer.
12fe3d055dSsakamoto  * 2. Redistributions in binary form must reproduce the above copyright
13fe3d055dSsakamoto  *    notice, this list of conditions and the following disclaimer in the
14fe3d055dSsakamoto  *    documentation and/or other materials provided with the distribution.
15fe3d055dSsakamoto  * 3. All advertising materials mentioning features or use of this software
16fe3d055dSsakamoto  *    must display the following acknowledgement:
176d3d8a13Smycroft  *	This product includes software developed by Charles M. Hannum.
18fe3d055dSsakamoto  * 4. The name of the author may not be used to endorse or promote products
19fe3d055dSsakamoto  *    derived from this software without specific prior written permission.
20fe3d055dSsakamoto  *
21fe3d055dSsakamoto  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22fe3d055dSsakamoto  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23fe3d055dSsakamoto  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24fe3d055dSsakamoto  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25fe3d055dSsakamoto  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26fe3d055dSsakamoto  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27fe3d055dSsakamoto  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28fe3d055dSsakamoto  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29fe3d055dSsakamoto  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30fe3d055dSsakamoto  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31fe3d055dSsakamoto  */
32fe3d055dSsakamoto 
33fe3d055dSsakamoto /*
34fe3d055dSsakamoto  * Machine-specific functions for PCI autoconfiguration.
35fe3d055dSsakamoto  *
36fe3d055dSsakamoto  * On PCs, there are two methods of generating PCI configuration cycles.
37fe3d055dSsakamoto  * We try to detect the appropriate mechanism for this machine and set
38fe3d055dSsakamoto  * up a few function pointers to access the correct method directly.
39fe3d055dSsakamoto  */
40fe3d055dSsakamoto 
41e803bea7Slukem #include <sys/cdefs.h>
42*c0f06f05Snonaka __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.22 2016/10/19 00:08:41 nonaka Exp $");
43e803bea7Slukem 
44fe3d055dSsakamoto #include <sys/types.h>
45fe3d055dSsakamoto #include <sys/param.h>
46fe3d055dSsakamoto #include <sys/time.h>
47fe3d055dSsakamoto #include <sys/systm.h>
48fe3d055dSsakamoto #include <sys/errno.h>
49fe3d055dSsakamoto #include <sys/device.h>
50fe3d055dSsakamoto 
51ca5133d3Smrg #include <uvm/uvm_extern.h>
52fe3d055dSsakamoto 
53daf8279eSmatt #define _POWERPC_BUS_DMA_PRIVATE
54af51edd2Sdyoung #include <sys/bus.h>
55fe3d055dSsakamoto #include <machine/intr.h>
56fe3d055dSsakamoto 
57d974db0aSgarbled #include <powerpc/pio.h>
58d974db0aSgarbled 
59fe3d055dSsakamoto #include <dev/isa/isavar.h>
60fe3d055dSsakamoto #include <dev/pci/pcivar.h>
61fe3d055dSsakamoto #include <dev/pci/pcireg.h>
62d974db0aSgarbled #include <dev/pci/pcidevs.h>
63fe3d055dSsakamoto 
64d974db0aSgarbled #include <machine/pci_machdep.h>
65fe3d055dSsakamoto 
66d974db0aSgarbled extern struct genppc_pci_chipset *genppc_pct;
6789a374bfSbriggs 
68d974db0aSgarbled #define	PCI_MODE1_ADDRESS_REG	(PREP_BUS_SPACE_IO + 0xcf8)
69d974db0aSgarbled #define	PCI_MODE1_DATA_REG	(PREP_BUS_SPACE_IO + 0xcfc)
70d974db0aSgarbled 
71fe3d055dSsakamoto void
bebox_pci_get_chipset_tag(pci_chipset_tag_t pc)72d974db0aSgarbled bebox_pci_get_chipset_tag(pci_chipset_tag_t pc)
73fe3d055dSsakamoto {
74d974db0aSgarbled 	pc->pc_conf_v = (void *)pc;
75fe3d055dSsakamoto 
76d974db0aSgarbled 	pc->pc_attach_hook = genppc_pci_indirect_attach_hook;
77d974db0aSgarbled 	pc->pc_bus_maxdevs = genppc_pci_bus_maxdevs;
78d974db0aSgarbled 	pc->pc_make_tag = genppc_pci_indirect_make_tag;
79d974db0aSgarbled 	pc->pc_conf_read = genppc_pci_indirect_conf_read;
80d974db0aSgarbled 	pc->pc_conf_write = genppc_pci_indirect_conf_write;
81fe3d055dSsakamoto 
82d974db0aSgarbled 	pc->pc_intr_v = (void *)pc;
83fe3d055dSsakamoto 
84d974db0aSgarbled 	pc->pc_intr_map = genppc_pci_intr_map;
85d974db0aSgarbled 	pc->pc_intr_string = genppc_pci_intr_string;
86d974db0aSgarbled 	pc->pc_intr_evcnt = genppc_pci_intr_evcnt;
87d974db0aSgarbled 	pc->pc_intr_establish = genppc_pci_intr_establish;
88d974db0aSgarbled 	pc->pc_intr_disestablish = genppc_pci_intr_disestablish;
899835a3ebSmatt 	pc->pc_intr_setattr = genppc_pci_intr_setattr;
90*c0f06f05Snonaka 	pc->pc_intr_type = genppc_pci_intr_type;
91*c0f06f05Snonaka 	pc->pc_intr_alloc = genppc_pci_intr_alloc;
92*c0f06f05Snonaka 	pc->pc_intr_release = genppc_pci_intr_release;
93*c0f06f05Snonaka 	pc->pc_intx_alloc = genppc_pci_intx_alloc;
94*c0f06f05Snonaka 
95*c0f06f05Snonaka 	pc->pc_msi_v = (void *)pc;
96*c0f06f05Snonaka 	genppc_pci_chipset_msi_init(pc);
97*c0f06f05Snonaka 
98*c0f06f05Snonaka 	pc->pc_msix_v = (void *)pc;
99*c0f06f05Snonaka 	genppc_pci_chipset_msix_init(pc);
100fe3d055dSsakamoto 
101d974db0aSgarbled 	pc->pc_conf_interrupt = bebox_pci_conf_interrupt;
102d974db0aSgarbled 	pc->pc_decompose_tag = genppc_pci_indirect_decompose_tag;
103d974db0aSgarbled 	pc->pc_conf_hook = genppc_pci_conf_hook;
104fe3d055dSsakamoto 
1057a31608fSmatt 	pc->pc_addr = mapiodev(PCI_MODE1_ADDRESS_REG, 4, false);
1067a31608fSmatt 	pc->pc_data = mapiodev(PCI_MODE1_DATA_REG, 4, false);
107d974db0aSgarbled 	pc->pc_bus = 0;
108d974db0aSgarbled 	pc->pc_node = 0;
109d974db0aSgarbled 	pc->pc_memt = 0;
110d974db0aSgarbled 	pc->pc_iot = 0;
111fe3d055dSsakamoto }
112fe3d055dSsakamoto 
113fe3d055dSsakamoto void
bebox_pci_conf_interrupt(void * v,int bus,int dev,int pin,int swiz,int * iline)1149835a3ebSmatt bebox_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
1159835a3ebSmatt     int *iline)
11689a374bfSbriggs {
117a8675850Skiyohara 
118a8675850Skiyohara 	if (bus == 0) {
119a8675850Skiyohara 		switch (dev) {
120a8675850Skiyohara 		case 12: /*       SCSI is bit 10, mapped to IRQ 26 */
121a8675850Skiyohara 		case 13: /* PCI slot 1 is bit 11, mapped to IRQ 27 */
122a8675850Skiyohara 		case 14: /* PCI slot 2 is bit 12, mapped to IRQ 28 */
123a8675850Skiyohara 		case 15: /* PCI slot 3 is bit 13, mapped to IRQ 29 */
124a8675850Skiyohara #define  BEBOX_PCIBUS0_DEV2LINE(d)	((d) + 14)
125a8675850Skiyohara 			*iline = BEBOX_PCIBUS0_DEV2LINE(dev);
126a8675850Skiyohara 		}
127a8675850Skiyohara 	} else
12884b65541Skiyohara #define  BEBOX_PCIBUS_SWIZ2LINE(s)	((s) + 14)
12984b65541Skiyohara 		*iline = BEBOX_PCIBUS_SWIZ2LINE(swiz);
130fe3d055dSsakamoto }
131