1/* $NetBSD: intmmu.S,v 1.9 2005/06/03 15:56:49 rearnsha Exp $ */ 2 3/* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include "assym.h" 33#include <machine/asm.h> 34#include <arm/armreg.h> 35#include <arm/arm32/pte.h> 36 37 .section .start,"ax",%progbits 38 39ASENTRY_NP(integrator_start) 40 mov r6, #0x16000000 /* UART0 Physical base*/ 41#ifdef VERBOSE_INIT_ARM 42 mov r3, #'A' 43 str r3, [r6] /* Let the world know we are alive */ 44#endif 45/* 46 * Check that the processor has a CP15. Some core modules do not. 47 * We can tell by reading CM_PROC. If it is zero, then we're OK, otherwise 48 * let the user know why we've died. 49 */ 50 mov r7, #0x10000000 51 ldr r3, [r7, #4] 52 cmp r3, #0 53 bne Lno_cp15 54/* 55 * Now read CP15 and check what sort of core we have. We need to know 56 * if it has an MMU. There's no simple test for this, but the following 57 * hack should be sufficient for all currently supported CM boards: 58 * - Check that the product code has a '2' or '3' in bits 8-11 59 */ 60 mrc p15, 0, r3, c0, c0, 0 61 and r0, r3, #0x00000f00 62 teq r0, #0x00000200 /* ARM 920, 1020, 1026, etc */ 63 teqne r0, #0x00000300 /* ARM 1136 */ 64 bne Lno_mmu 65 66/* 67 * At this time the MMU is off. 68 * We build up an initial memory map at 0x8000 that we can use to get 69 * the kernel running from the top of memory. All mappings in this table 70 * use L1 section maps. 71 */ 72 73/* 74 * Set Virtual == Physical 75 */ 76 mov r3, #(L1_S_AP(AP_KRW)) 77 add r3, r3, #(L1_TYPE_S) 78 mov r2, #0x100000 /* advance by 1MB */ 79 mov r1, #0x8000 /* page table start */ 80 mov r0, #0x1000 /* page table size */ 81 82Lflat: 83 str r3, [r1], #0x0004 84 add r3, r3, r2 85 subs r0, r0, #1 86 bgt Lflat 87 88/* 89 * Map VA 0xc0000000->0xc03fffff to PA 0x00000000->0x003fffff 90 */ 91 mov r3, #(L1_S_AP(AP_KRW)) 92 add r3, r3, #(L1_TYPE_S) 93 mov r1, #0x8000 /* page table start */ 94 add r1, r1, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 95# add r1, r1, #(0x001 * 4) /* offset to 0xc01xxxxx */ 96 mov r0, #63 97Lkern: 98 str r3, [r1], #0x0004 /* 0xc000000-0xc03fffff */ 99 add r3, r3, r2 100 subs r0, r0, #1 101 bgt Lkern 102/* 103 * Mapping the peripheral register region (0x10000000->0x1fffffff) linearly 104 * would require 256MB of virtual memory (as much space as the entire kernel 105 * virtual space). So we map the first 1M of each 16MB sub-space into the 106 * region VA 0xfd000000->0xfdffffff; this should map enough of the peripheral 107 * space to at least get us up and running. 108 */ 109 mov r3, #(L1_S_AP(AP_KRW)) 110 add r3, r3, #L1_TYPE_S 111 add r3, r3, #0x10000000 /* Peripherals base */ 112 mov r1, #0x8000 /* page table start */ 113 add r1, r1, #(0xfd0 * 4) 114 mov r2, #0x01000000 /* 16MB increment. */ 115 mov r0, #16 116Lperiph: 117 str r3, [r1], #4 /* 0xfd000000-0xfdffffff */ 118 add r3, r3, r2 119 subs r0, r0, #1 120 bgt Lperiph 121 122/* 123 * We now have our page table ready, so load it up and light the blue 124 * touch paper. 125 */ 126 127 /* set the location of the L1 page table */ 128 mov r1, #0x8000 129 mcr p15, 0, r1, c2, c0, 0 130 131 /* Flush the old TLBs (just in case) */ 132 mcr p15, 0, r1, c8, c7, 0 133 /* And the caches */ 134 mov r0, #0 135 mcr p15, 0, r1, c7, c6, 0 136 137#ifdef VERBOSE_INIT_ARM 138 mov r2, #'B' 139 strb r2, [r6] 140#endif 141 142 /* Set the Domain Access register. Very important! */ 143 mov r1, #1 144 mcr p15, 0, r1, c3, c0, 0 145 146 /* 147 * set mmu bit (don't set anything else for now, we don't know 148 * what sort of CPU we have yet. 149 */ 150 mov r1, #CPU_CONTROL_MMU_ENABLE 151 152/* 153 * This is where it might all start to go wrong if the CPU fitted to your 154 * integrator does not have an MMU. 155 */ 156 /* fetch current control state */ 157 mrc p15, 0, r2, c1, c0, 0 158 orr r2, r2, r1 159 160 /* set new control state */ 161 mcr p15, 0, r2, c1, c0, 0 162 163 mov r0, r0 164 mov r0, r0 165 mov r0, r0 166 167#ifdef VERBOSE_INIT_ARM 168 /* emit a char. Uart is now at 0xfd600000 */ 169 mov r6, #0xfd000000 170 add r6, r6, #0x00600000 171 mov r2, #'C' 172 strb r2, [r6] 173#endif 174 175 /* jump to kernel space */ 176 mov r0, #0x0200 177 178 /* Switch to kernel VM and really set the ball rolling. */ 179 ldr pc, Lstart 180 181Lstart: .long start 182 183Lmsg: 184 ldrb r2, [r0], #1 185 cmp r2, #0 186 strneb r2, [r6] 187Lwait: 188 ldrb r3, [r6, #0x18] 189 tst r3, #0x80 190 beq Lwait 191 cmp r2, #0 192 bne Lmsg 193 /* We're toast! */ 194 b . 195 196Lno_cp15: 197 adr r0, Lcp15msg 198 b Lmsg 199Lno_mmu: 200 adr r0, Lmmumsg 201 b Lmsg 202 203Lcp15msg: 204 .ascii "Core has no cp15\r\n\0" 205Lmmumsg: 206 .ascii "Core has no MMU\r\n\0" 207